LTC2385IUH-16#PBF - ANALOG DEVICES

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

TYPICAL APPLICATION

FEATURES DESCRIPTION

16-Bit, 5Msps SAR ADC

The LTC

2385-16 is a low noise, high speed, 16-bit 5Msps

successive approximation register (SAR) ADC ideally

suited for a wide range of applications. The combination

of excellent linearity and wide dynamic range makes the

LTC2385-16 ideal for high speed imaging and instru-

mentation applications. No-latency operation provides a

unique solution for high speed control loop applications.

The very low distortion at high input frequencies enables

communications applications requiring wide dynamic

range and significant signal bandwidth.

To support high speed operation while minimizing the

number of data lines, the LTC2385-16 features a serial

LVDS digital interface. The LVDS interface has one-lane

and two-lane output modes, allowing the user to optimize

the interface data rate for each application.

FFT, fSMPL = 5Msps, fIN = 2kHz

APPLICATIONS

n 5Msps Throughput Rate

n No Pipeline Delay, No Cycle Latency

n 93.8dB SNR (Typ) at fIN = 1MHz

n 101dB SFDR (Typ) at fIN = 1MHz

n Nyquist Sampling Up to 2.5MHz Input

n Guaranteed 16-Bit, No Missing Codes

n ±0.5LSB INL (Max)

n 8.192VP-P Differential Inputs

n 5V and 2.5V Supplies

n Internal 20ppm/°C (Max) Reference

n Serial LVDS Interface

n 78mW Power Dissipation

n 32-Pin (5mm × 5mm) QFN Package

n High Speed Data Acquisition

n Imaging

n Communications

n Control Loops

n Instrumentation

n ATE

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 7705765, 8232905, 8810443. Other patents are pending.

SNR = 94.0dB

THD = –117dB

SINAD = 93.9dB

SFDR = 119dB

FREQUENCY (MHz)

0.5

1.5

2.5

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

238516 TA02

SAMPLE

CLOCK

10µF

0.1µF

2.5V5V

0.1µF0.1µF

CLK

DCO

LVDS

INTERFACE

238516 TA01

IN–

IN+

680pF

24.9Ω

GNDREFINREFBUF REFGND

LTC2385-16

VCM

680pF TWOLANES

TESTPAT

CNV

VDD

2.5V

0.1µF

VDDL OVDD

–

4.096V

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ..................................................6V

Supply Voltage (VDDL, OVDD) ................................... 2.8V

Analog Input Voltage (Note 3)

IN+, IN– .........................(GND – 0.3V) to (VDD + 0.3V)

REFBUF .........................(GND – 0.3V) to (VDD + 0.3V)

REFIN (Note 4) ...........................(GND – 0.3V) to 2.8V

Digital Input Voltage (Note 3)

PD, TESTPAT ............. (GND – 0.3V) to (OVDD + 0.3V)

CLK+, CLK– ................ (GND – 0.3V) to (OVDD + 0.3V)

TWOLANES, CNV+,

CNV– ...........................(GND – 0.3V) to (VDDL + 0.3V)

Power Dissipation .............................................. 500mW

Operating Temperature Range

LTC2385C ................................................ 0°C to 70°C

LTC2385I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

GND

31 30 29 28 27 26 25

9 10 11 12

TOP VIEW

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

13 14 15 16

1GND

IN+

IN–

GND

REFGND

REFBUF

CLK+

CLK–

GND

DCO

–

DA+

DA–

VCM

VDDL

GND

CNV+

CNV–

GND

TWOLANES

REFIN

GND

VDD

TESTPAT

DB–

DB+

TJMAX = 125°C, θJA = 34°C/W

EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 5)

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2385CUH-16#PBF LTC2385CUH-16#TRPBF 238516 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C

LTC2385IUH-16#PBF LTC2385IUH-16#TRPBF 238516 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN+Absolute Input Range (IN+) (Note 6) l–0.1 VREFBUF + 0.1 V

VIN–Absolute Input Range (IN–) (Note 6) l–0.1 VREFBUF + 0.1 V

VIN+ – VIN–Input Differential Voltage Range VIN+ – VIN–l–VREFBUF VREFBUF V

VINCM Common Mode Input Range (VIN+ + VIN–)/2 lVREFBUF/2 – 0.1 VREFBUF/2 VREFBUF/2 + 0.1 V

IIN Analog Input DC Leakage Current l–1 1 μA

CIN Analog Input Capacitance Sample Mode

Hold Mode

CMRR Input Common Mode Rejection Ratio fIN = 1MHz 75 dB

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

CONVERTER CHARACTERISTICS

DYNAMIC ACCURACY

INTERNAL REFERENCE CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 5)

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 5, 10)

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution l16 Bits

No Missing Codes l16 Bits

Transition Noise 0.35 LSBRMS

INL Integral Linearity Error REFBUF = 4.096V (Notes 7, 9) l–0.5 ±0.15 0.5 LSB

DNL Differential Linearity Error l–0.6 ±0.06 0.6 LSB

ZSE Zero-Scale Error (Note 8) l–2.5 ±0.4 2.5 LSB

Zero-Scale Error Drift 0.005 LSB/°C

FSE Full-Scale Error REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)

REFIN = 2.048V (REFIN Overdriven) (Note 8)

–5

–40

±1.3

±7

LSB

Full-Scale Error Drift REFBUF = 4.096V (REFBUF Overdriven) (Note 9)

REFIN = 2.048V (REFIN Overdriven)

±0.1

±1.5

ppm/°C

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SINAD Signal-to-(Noise + Distortion) Ratio fIN = 2kHz

fIN = 1MHz

91.5

91.2

93.9

93.2

SNR Signal-to-Noise Ratio fIN = 2kHz

fIN = 1MHz

91.6

91.4

93.8

THD Total Harmonic Distortion

(First Five Harmonics)

fIN = 2kHz

fIN = 1MHz

–117

–100

–108

–97

SFDR Spurious Free Dynamic Range fIN = 2kHz

fIN = 1MHz

107

119

101

–3dB Input Bandwidth 200 MHz

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFIN Internal Reference Output Voltage IOUT = 0μA 2.043 2.048 2.053 V

VREFIN Temperature Coefficient (Note 11) l±5 ±20 ppm/°C

REFIN Output Impedance 15 kΩ

VREFIN Line Regulation VDD = 4.75V to 5.25V 0.3 mV/V

REFIN Input Voltage Range (REFIN Overdriven) (Note 6) l2.008 2.048 2.088 V

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

REFERENCE BUFFER CHARACTERISTICS

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)

POWER REQUIREMENTS

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VREFBUF Reference Buffer Output Voltage VREFIN = 2.048V l4.090 4.096 4.102 V

REFBUF Input Voltage Range (REFBUF Overdriven) (Notes 6, 9) l4.016 4.096 4.176 V

IREFBUF REFBUF Load Current VREFBUF = 4.096V (REFBUF Overdriven) (Notes 9, 12)

VREFBUF = 4.096V, Sleep Mode (REFBUF Overdriven) (Note 9)

l0.9

0.5

1.1 mA

VCM Common Mode Output VREFBUF = 4.096V, IOUT = 0μA 2.028 2.048 2.068 V

VCM Output Impedance –1mA < IOUT < 1mA l15 Ω

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PD, TESTPAT, TWOLANES

VIH High Level Input Voltage VDDL = OVDD = 2.5V l1.7 V

VIL Low Level Input Voltage VDDL = OVDD = 2.5V l0.6 V

IIN Digital Input Current VIN = 0V to 2.5V l–10 10 μA

CIN Digital Input Capacitance 3 pF

CNV+, Single-Ended Convert Start Mode (CNV– Tied to GND)

VIH High Level Input Voltage VDDL = 2.5V l1.7 V

VIL Low Level Input Voltage VDDL = 2.5V l0.6 V

CIN Digital Input Capacitance 2 pF

CNV+/CNV–, Differential Convert Start Mode

VID Differential Input Voltage (Note 13) l175 350 650 mV

VICM Common Mode Input Voltage l0.8 1.25 1.7 V

CLK+/CLK– (LVDS Clock Input)

VID Differential Input Voltage (Note 13) l175 350 650 mV

VICM Common Mode Input Voltage l0.8 1.25 1.7 V

DCO+/DCO–, DA+/DA–, DB+/DB– (LVDS Outputs)

VOD Differential Output Voltage 100Ω Differential Load l247 350 454 mV

VOS Common Mode Output Voltage 100Ω Differential Load l1.125 1.25 1.375 V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Supply Voltage (Note 6) l4.75 5 5.25 V

VDDL Supply Voltage (Note 6) l2.375 2.5 2.625 V

OVDD Supply Voltage (Note 6) l2.375 2.5 2.625 V

IVDD

IVDDL

IOVDD

IPOWERDOWN

Supply Current

Power-Down Mode Current

5Msps Sample Rate

Power-Down Mode (IVDD)

Power-Down Mode (IVDDL + IOVDD)

17.1

8.1

3.8

19.6

9.6

250

μA

PDPower Dissipation

Power-Down Mode

5Msps Sample Rate

Power-Down Mode (IVDD + IVDDL + IOVDD)

725

μW

IDIFFCNV Increase in IVDDL with Differential CNV Mode Enabled (No Increase During Power-Down) 2.1 mA

ITWOLANE Increase in IOVDD with Tw o -Lane Mode Enabled (No Increase During Power-Down) 3.6 mA

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

ADC TIMING CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above VDD,

VDDL or OVDD, they will be clamped by internal diodes. This product can

handle input currents up to 100mA below ground or above VDD, VDDL or

OVDD without latchup.

Note 4: When this pin voltage is taken below ground, it will be clamped by

an internal diode. When this pin voltage is taken above VDDL, it is clamped

by a diode in series with a 2k resistor. This product can handle input

currents up to 100mA below ground without latchup.

Note 5: VDD = 5V, VDDL = 2.5V, OVDD = 2.5V, fSMPL = 5MHz,

REFIN=2.048V, single-ended CNV, one-lane output mode unless

otherwise noted.

Note 6: Recommended operating conditions.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSMPL Sampling Frequency l0.02 5 Msps

tCONV CNV↑ to Output Data Ready l88 94 101 ns

tACQ Acquisition Time tCYC – 67 ns

tCYC Time Between Conversions l200 50,000 ns

tCNVH CNV High Time (Note 13) l5 ns

tCNVL CNV Low Time (Note 13) l8 ns

tFIRSTCLK CNV↑ to First CLK↑ from the Same Conversion (Note 13) l104 ns

tLASTCLK CNV↑ to Last CLK↓ from the Previous

Conversion

(Note 13) l83 ns

tCLKH CLK High Time l1.25 ns

tCLKL CLK Low Time l1.25 ns

tCLKDCO CLK to DCO Delay (Note 13) l0.7 1.3 2.3 ns

tCLKD CLK to DA/DB Delay (Note 13) l0.7 1.3 2.3 ns

tSKEW DCO to DA/DB skew tCLKD – tCLKDCO (Note 13) l–200 0 200 ps

tAP Sampling Delay Time (Note 13) 0 ns

tJITTER Sampling Delay Jitter (Note 13) 0.25 psRMS

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Zero-scale error is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 0000 and 1111

1111 1111 1111. Full-scale error is the worst-case deviation of the first

and last code transitions from ideal and includes the effect of offset error.

Note 9: When REFBUF is overdriven, the internal reference buffer must be

turned off by setting REFIN = 0V.

Note 10: All specifications in dB are referred to a full-scale ±VREFBUF

differential input.

Note 11: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

Note 12: fSMPL = 5MHz, IREFBUF varies linearly with sample rate.

Note 13: Guaranteed by design, not subject to test.

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

TYPICAL PERFORMANCE CHARACTERISTICS

32k Point FFT fSMPL = 5Msps,

fIN = 2kHz

32k Point FFT fSMPL = 5Msps,

fIN = 100kHz

32k Point FFT fSMPL = 5Msps,

fIN = 1MHz SNR, SINAD vs Input Frequency

THD vs Input Frequency

and Amplitude

Integral Nonlinearity vs

Output Code (LSB)

Differential Nonlinearity vs

Output Code

DC Histogram

TA = 25°C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V,

REFIN = 2.048V, fSMPL = 5Msps, unless otherwise noted.

Integral Nonlinearity

vs Output Code (ppm)

OUTPUT CODE

16384

32768

49152

65536

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

INL ERROR (LSB)

238516 G01a

OUTPUT CODE

16384

32768

49152

65536

–6.0

–4.5

–3.0

–1.5

1.5

3.0

4.5

6.0

INL ERROR (ppm)

238516 G01b

OUTPUT CODE

16384

32768

49152

65536

–0.5

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

0.5

DNL ERROR (LSB)

238516 G02

σ = 0.35

OUTPUT CODE

N–3

N–2

N–1

N+1

N+2

N+3

25000

50000

75000

100000

125000

150000

175000

200000

225000

COUNT

238516 G03

SNR = 94.0dB

THD = –117dB

SINAD = 93.9dB

SFDR = 119dB

FREQUENCY (MHz)

0.5

1.5

2.5

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

238516 G04

SNR = 94.0dB

THD = –115dB

SINAD = 93.9dB

SFDR = 117dB

FREQUENCY (MHz)

0.5

1.5

2.5

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

238516 G05

SNR = 93.8dB

THD = –100dB

SINAD = 93.2dB

SFDR = 101dB

FREQUENCY (MHz)

0.5

1.5

2.5

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

238516 G06

SNR

SINAD

FREQUENCY (MHz)

0.01

0.1

SNR, SINAD (dBFS)

238516 G08

–1dBFS

–3dBFS

–6dBFS

–10dBFS

FREQUENCY (MHz)

0.01

0.1

–140

–130

–120

–110

–100

–90

–80

–70

THD (dBFS)

238516 G09

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

TYPICAL PERFORMANCE CHARACTERISTICS

SNR, SINAD vs Temperature,

fIN = 2kHz, –1dBFS

THD, Harmonics vs Temperature,

fIN = 2kHz, –1dBFS INL/DNL vs Temperature

Full-Scale Error vs Temperature,

REFBUF = 4.096V

SFDR vs Input Level, fIN = 2kHz SFDR vs Input Level, fIN = 1MHz

TA = 25°C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V,

REFIN = 2.048V, fSMPL = 5Msps, unless otherwise noted.

dBFS

dBc

INPUT LEVEL (dBFS)

–70

–60

–50

–40

–30

–20

–10

100

110

120

130

140

150

SFDR (dBFS, dBc)

238516 G10

dBFS

dBc

INPUT LEVEL (dBFS)

–70

–60

–50

–40

–30

–20

–10

100

110

120

130

140

150

SFDR (dBFS, dBc)

238516 G11

SNR

SINAD

TEMPERATURE (°C)

–40

–20

SNR, SINAD (dBFS)

238516 G12

THD

2ND

3RD

TEMPERATURE (°C)

–40

–20

–125

–120

–115

–110

–105

THD, HARMONICS (dBFS)

238516 G13

MAX INL

MAX DNL

MIN DNL

MIN INL

TEMPERATURE (°C)

–40

–20

–0.4

–0.3

–0.2

–0.1

0.1

0.2

0.3

0.4

INL/DNL ERROR (LSB)

238516 G14

+ FS

– FS

TEMPERATURE (°C)

–40

–20

–1.5

–1.0

–0.5

0.5

1.0

1.5

FULL-SCALE ERROR (LSB)

238516 G15

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

TA = 25°C, VDD = 5V, VDDL = 2.5V, OVDD = 2.5V,

REFIN = 2.048V, fSMPL = 5Msps, unless otherwise noted.

Analog Input Current

vs Differential Input Voltage

Internal Reference Output

vs Temperature

IN–

IN+

SMPL

= 5Msps

DIFFERENTIAL INPUT (V)

–4.096

–2.048

2.048

4.096

–0.50

–0.25

0.25

0.50

ANALOG INPUT CURRENT (mA)

238516 G19

THREE TYPICAL UNITS

TEMPERATURE (°C)

–40

–20

2.047

2.048

2.049

2.050

REFERENCE OUTPUT (V)

238516 G20

TYPICAL PERFORMANCE CHARACTERISTICS

Zero-Scale Error vs Temperature Supply Current vs Temperature

TEMPERATURE (°C)

–40

–20

–1.5

–1.0

–0.5

0.5

1.0

1.5

ZERO–SCALE ERROR (LSB)

238516 G16

VDDL

VDD

OVDD

TEMPERATURE (°C)

–40

–20

SUPPLY CURRENT (mA)

238516 G17

Supply Current vs Sample Rate

VDDL

VDD

OVDD

SAMPLE RATE (MHz)

SUPPLY CURRENT (mA)

238516 G18

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

PIN FUNCTIONS

GND (Pins 1, 4, 10, 21, 26, 29 ): Ground. Connect to a

solid ground plane in the PCB underneath the ADC.

IN+, IN– (Pins 2, 3): Positive and Negative Differential

Analog Inputs. The inputs must be driven differentially

and 180° out of phase, with a common mode voltage of

2.048V. The differential input range is ±4.096V (each input

pin swings from 0V to 4.096V.)

REFGND (Pins 5, 6): Reference Ground. The two pins

should be shorted together and connected to the refer-

ence bypass capacitor with a short, wide trace. In ad-

dition, connect the pins to the exposed pad (Pin 33). A

suggested layout is shown in the ADC Reference section

of the data sheet.

REFBUF (Pins 7, 8): Internal Reference Buffer Output.

The output voltage of the internal 2× gain reference buffer,

nominally 4.096V, is provided on this pin. The two pins

should be shorted together and bypassed to REFGND with

a 10µF (X7R, 0805 size) ceramic capacitor. If the internal

buffer is not required, tie REFIN to GND to power down

the buffer and connect an external 4.096V reference to

REFBUF.

REFIN (Pin 9): Internal Reference Output/Reference Buffer

Input. The output voltage of the internal reference, nomi-

nally 2.048V, is output on this pin. An external reference

can be applied to REFIN if a more accurate reference is

required. For increased filtering of reference noise, bypass

this pin to GND using a 0.1µF or larger ceramic capacitor.

If the internal reference buffer is not used, tie REFIN to

GND to power down the buffer and connect an external

buffered reference to REFBUF.

VDD (Pins 11, 12): 5V Analog Power Supply. The range

of VDD is 4.75V to 5.25V. The two pins should be shorted

together and bypassed to GND with 0.1μF and 10μF ce-

ramic capacitors.

PD (Pin 13): Digital input that enables power-down mode.

When PD is low, the LTC2385 enters power-down mode,

and all circuitry (including the LVDS interface) is shut

down. When PD is high, the part operates normally. Logic

levels are determined by OVDD.

TESTPAT (Pin 14): Digital input that forces the LVDS data

outputs to be a test pattern. When TESTPAT is high, the

digital outputs are a test pattern. When TESTPAT is low,

the digital outputs are the ADC conversion result. Logic

levels are determined by OVDD.

DB–/DB+, DA–/DA+ (Pins 15/16, 17/18): Serial LVDS

Data Outputs. In one-lane output mode, DB–/DB+ are not

used and their LVDS driver is disabled to reduce power

consumption.

DCO–/DCO+ (Pins 19/20): LVDS Data Clock Output. This

is an echoed version of CLK–/CLK+ that can be used to

latch the data outputs.

OVDD (Pin 22): 2.5V Output Power Supply. The range of

OVDD is 2.375V to 2.625V. Bypass to GND with a 0.1μF

ceramic capacitor.

CLK–/CLK+ (Pins 23/24): LVDS Clock Input. This is an

externally applied clock that serially shifts out the conver-

sion result.

TWOLANES (Pin 25): Digital input that enables two-lane

output mode. When TWOLANES is high (two-lane output

mode), the ADC outputs two bits at a time on DA–/DA+

and DB–/DB+. When TWOLANES is low (one-lane output

mode), the ADC outputs one bit at a time on DA–/DA+, and

DB–/DB+ are disabled. Logic levels are determined by VDDL.

CNV–/CNV+ (Pins 27/28): Conversion Start LVDS Input.

A rising edge on CNV+ puts the internal sample-and-hold

into the hold mode and starts a conversion cycle. CNV+

can also be driven with a 2.5V CMOS signal if CNV– is

tied to GND.

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

PIN FUNCTIONS

VDDL (Pins 30, 31): 2.5V Analog Power Supply. The

range of VDDL is 2.375V to 2.625V. The two pins should

be shorted together and bypassed to GND with 0.1μF and

10μF ceramic capacitors.

VCM (Pin 32): Common Mode Output. VCM, nominally

2.048V, can be used to set the common mode of the ana-

log inputs. Bypass to GND with a 0.1μF ceramic capacitor

close to the pin. If VCM is not used, the bypass capacitor

is not necessary as long as the parasitic capacitance on

the VCM pin is under 10pF.

Exposed Pad (Pin 33): The exposed pad on the bottom

of the package. Connect to the ground plane of the PCB

using multiple vias.

FUNCTIONAL BLOCK DIAGRAM

SERIAL

LVDS

INTERFACE

CLK

DCO

238516 BD

IN–

IN+

VDD VDDL OVDD

VCM

REFGND REFBUF REFINGND

CONTROL

LOGIC

CNV

TWOLANES

TESTPAT

–

16-BIT, 5Msps ADC

0.5

22.048V

REFERENCE

15k

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

TIMING DIAGRAM

tAP

tCNVH

ANALOG

INPUT

CNV–

CNV+

D15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

OUTPUT DATA FROM SAMPLE N

LOGIC 0 D15 14 13 12 11 10 D9 D8 D7 D6

LOGIC 0 D6 D5 D4 D3 D2 D1 D0

OUTPUT DATA FROM SAMPLE N+1 OUTPUT DATA FROM SAMPLE N–1

SAMPLE N

SAMPLE N+1

CLK+

CLK–

DCO+

DCO–

DA+

DA–

INPUT ACQUISITION INPUT ACQUISITION

tACQ

tCYC

12345678

tLASTCLK

tFIRSTCLK

tCONV

238516 TD01

One-Lane Output Mode

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

TIMING DIAGRAM

tAP

tCNVH

ANALOG

INPUT

CNV–

CNV+

D15 13 11 D9 D7 D5 D3 D1LOGIC 0 D15 13 11 D9 D7LOGIC 0 13 11 D9 D7 D5 D3 D1

SAMPLE N

SAMPLE N+1

CLK+

CLK–

DCO+

DCO–

DA+

DA–

INPUT ACQUISITION INPUT ACQUISITION

tACQ

tCYC

1234

tLASTCLK

tFIRSTCLK

tCONV

D14 12 10 D8 D6 D4 D2 D0LOGIC 0 D14 12 10 D8 D6LOGIC 0 12 10 D8 D6 D4 D2 D0

OUTPUT DATA FROM SAMPLE N OUTPUT DATA FROM SAMPLE N+1

238516 TD02

OUTPUT DATA FROM SAMPLE N–1

DB+

DB–

Tw o -Lane Output Mode

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

TIMING DIAGRAM

APPLICATIONS INFORMATION

Data Output Timing

CLKH

tCLKDCO

CLK+

CLK–

DCO

–

DA+

DA–

tCLKDCO

tCLKD tCLKD

CLKL

238516 TD03

DB+

DB–

OVERVIEW

The LTC2385-16 is a low noise, high speed, 16-bit succes-

sive approximation register (SAR) ADC. Operating from 5V

and 2.5V supplies, the LTC2385-16 has a fully differential

±4.096V input range, making it ideal for applications that

require a wide dynamic range. The LTC2385-16 achieves

±0.5 LSB INL (maximum), no missing codes at 16-bits

and 94dB SNR (typical).

The LTC2385-16 includes a precision internal 2.048V

reference, with a guaranteed 0.25% initial accuracy and

a ±20ppm/°C (maximum) temperature coefficient, as well

as an internal reference buffer. The LTC2385-16 also has

a high speed serial LVDS interface that can output one

or two bits at a time. The fast 5Msps throughput with no

pipeline latency makes the LTC2385-16 ideally suited for

a wide variety of high speed applications. The LTC2385-16

dissipates only 78mW at 5Msps and has a power-down

mode to reduce the power consumption to 10μW during

inactive periods.

CONVERTER OPERATION

The LTC2385-16 operates in two phases. During the ac-

quisition phase, the sample capacitors are connected to

the analog input pins IN+ and IN– to sample the differential

analog input voltage. A rising edge on the CNV pin initiates

a conversion. During the conversion phase, the ADC is

sequenced through a successive approximation algorithm,

comparing the sampled input with binary-weighted frac-

tions of the reference voltage (e.g. VREFBUF/2, VREFBUF/4

… VREFBUF/65536) using a differential comparator. At the

end of conversion, control logic prepares the 16-bit digital

output code for serial transfer.

TRANSFER FUNCTION

The LTC2385-16 digitizes the full-scale voltage of 2×

REFBUF into 216 levels, resulting in an LSB size of 125μV

with REFBUF = 4.096V. The output data is in two’s comple-

ment format. The ideal transfer function is shown in Figure

1. The ideal offset binary transfer function can be obtained

from the two’s complement transfer function by inverting

the most significant bit (MSB) of each output code.

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

APPLICATIONS INFORMATION

ANALOG INPUTS

The LTC2385-16 has a fully differential ±4.096V input

range. The IN+ and IN– pins should be driven 180 degrees

out-of-phase with respect to each other, centered around

a common mode voltage (IN+ + IN–)/2 that is restricted

to (VREFBUF/2 ± 0.1V). The ADC samples and digitizes the

voltage difference between the two analog input pins (IN+

− IN–), and any unwanted signal that is common to both

inputs is reduced by the common mode rejection ratio

(CMRR) of the ADC. The analog inputs can be modeled

by the equivalent circuit shown in Figure 2. The diodes

and 10Ω resistors at the input provide ESD and overdrive

protection. In the acquisition phase, each input sees ap-

proximately 18pF (CSAMPLE) from the sampling capacitor

in series with 28Ω (RON) from the on-resistance of the

sampling switch. CPAR is a lumped capacitance on the

order of 2pF formed primarily of diode junctions.

The inputs draw a small current spike while charging the

CSAMPLE capacitors during acquisition. This current spike is

consistent and does not depend on the previously sampled

input voltage. During conversion and power-down, the

analog inputs draw only a small leakage current.

Input Drive Circuits

A low impedance source can directly drive the high im-

pedance inputs of the LTC2385-16 without gain error. A

high impedance source should be buffered to minimize

settling time during acquisition and to optimize the dis-

tortion performance of the ADC. Minimizing settling time

is important even for DC signals because the ADC inputs

draw a current spike when entering acquisition.

For best performance, a buffer amplifier should be used

to drive the analog inputs of the LTC2385-16. The ampli-

fier provides low output impedance enabling fast settling

of the analog signal during the acquisition phase. It also

provides isolation between the signal source and the current

spike drawn by the ADC inputs when entering acquisition.

The LTC2385-16 is optimized for pulsed inputs that are fully

settled when sampled, or dynamic signals up to 7.5MHz.

Input signals that change faster than 300mV/ns when they

are sampled are not recommended. This is equivalent to

an 8VP-P sine wave at 12MHz.

Input Filtering

The noise and distortion of the buffer amplifier and other

supporting circuitry must be considered since they add

to the ADC noise and distortion. A buffer amplifier with

low noise density must be selected to minimize SNR

degradation. A filter network should be placed between

the buffer output and ADC input to both minimize the

noise contribution of the buffer and reduce disturbances

reflected into the buffer from ADC sampling transients. A

simple one-pole lowpass RC filter is sufficient for many

applications. It is important that the RC time constant of

this filter be small enough to allow the analog inputs to

settle within the ADC acquisition time (tACQ), as insufficient

settling can limit INL and THD performance.

High quality capacitors and resistors should be used in

the RC filters since these components can add distortion.

Figure 1. LTC2385-16 Transfer Function

Figure 2. Equivalent Circuit for the Differential Analog

Inputs of the LTC2385-16

INPUT VOLTAGE (V)

OUTPUT CODE (TWO’S COMPLEMENT)

–1

LSB

238516 F01

011...111

011...110

000...001

000...000

100...000

100...001

111...110

LSB

BIPOLAR

ZERO

111...111

FSR/2 – 1LSB–FSR/2

FSR = +FS – –FS

1LSB = FSR/65536

+10Ω

CPAR

2pF

CSAMPLE

18pF

238516 F02

–

BIAS

VOLTAGE

10Ω

CPAR

2pF

CSAMPLE

18pF

VDD

28Ω

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

APPLICATIONS INFORMATION

NPO type dielectric capacitors have excellent linearity.

Carbon surface mount resistors can generate distortion

from self-heating and from damage that may occur during

soldering. Metal film surface mount resistors are much

less susceptible to both problems.

Figure 3 shows a typical input drive circuit with an RC

filter. The optimal values for R and C are application spe-

cific and may require experimentation. Setting R = 24.9Ω

gives good performance over a wide range of conditions.

The analog inputs may be modeled as a switched capacitor

load on the drive circuit. A drive circuit may rely partially on

attenuating switched-capacitor current spikes with small

filter capacitors placed directly at the ADC inputs and par-

tially on the driver amplifier having sufficient bandwidth to

recover from the residual disturbance. Amplifiers optimized

for DC performance may not have sufficient bandwidth

to fully recover at the ADC’s maximum conversion rate,

which can produce nonlinearity and other errors. Coupling

filter circuits may be classified in two broad categories:

Fully Settled – This case is characterized by filter time

constants and an overall settling time that are consider-

ably shorter than the sample period. When acquisition

begins, the coupling filter is disturbed. For a typical first

order RC filter, the disturbance will look like an initial step

with an exponential decay. The amplifier will have its own

response to the disturbance, which may include ringing. If

the input settles completely (to within the accuracy of the

LTC2385-16), the disturbance will not contribute any error.

Partially Settled – In this case, the beginning of acquisition

causes a disturbance of the coupling filter, which then

begins to settle out towards the nominal input voltage.

However, acquisition ends (and the conversion begins)

before the input settles to its final value. This generally

produces a gain error, but as long as the settling is linear,

no distortion is produced. The coupling filter’s response

is affected by the amplifier’s output impedance and other

parameters. A linear settling response to fast switched-

capacitor current spikes can NOT always be assumed for

precision, low bandwidth amplifiers. The coupling filter

serves to attenuate the current spikes’ high-frequency

energy before it reaches the amplifier.

ADC REFERENCE

The internal reference circuitry of the LTC2385-16 is shown

in Figure 5. There is a low noise, low drift (20ppm/°C),

bandgap reference connected to REFIN (Pin 9). An internal

reference buffer gains the REFIN voltage by 2× to 4.096V

at REFBUF (Pins 7, 8). The voltage difference between

REFBUF and REFGND determines the full-scale input range

of the ADC. The reference and reference buffer can also

be externally driven if desired.

Figure 3. Typical Input Drive Circuit

Figure 4. Suggested Range of CFILT Values vs Sample Rate

The value for CFILT involves a trade-off: larger values give

better noise, and smaller values give better full-scale error.

Figure 4 shows a range of capacitor values to consider as

a starting point based on the sample rate.

MAX VALUE (LOWER NOISE)

MIN VALUE (LOWER FULL–SCALE ERROR)

SAMPLE RATE (Msps)

2.5

3.5

4.5

250

500

750

1000

1250

1500

1750

2000

2250

2500

FILT

(pF)

238516 F04

Input Currents

One of the biggest challenges in coupling an amplifier to

the LTC2385-16 is in dealing with current spikes drawn

by analog inputs at the start of each acquisition phase.

24.9Ω

FILT

4.096V

IN+

IN–

LTC2385-16

–

238516 F03

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

APPLICATIONS INFORMATION

Figure 7. Suggested REFBUF Bypass Capacitor Layout

Figure 8. Using the LTC6655-2.048 as an External Reference

Internal Reference with Internal Reference Buffer

To use the internal reference and internal reference buf-

fer, bypass REFIN to GND with a 0.1μF ceramic capacitor

(Figure 6). Bypass REFBUF to REFGND with a single 10μF

(X7R, 0805 size) ceramic capacitor. The REFBUF capacitor

should be as close as possible to the LTC2385-16 package

to minimize wiring inductance. Do not place this capaci-

tor on the opposite side of the board. Adding a second,

smaller capacitor in parallel with the 10μF may degrade

performance and is not recommended.

shown in Figure 8. Linear Technology offers a portfolio of

high performance references designed to meet the needs

of many applications. With its small size, low power, and

high accuracy, the LTC6655-2.048 is well suited for use

with the LTC2385-16 when overdriving the internal ref-

erence. The LTC6655-2.048 offers 0.025% (max) initial

accuracy and 2ppm/°C (max) temperature coefficient for

high precision applications. Bypassing the LTC6655-2.048

with a 2.7μF to 10μF ceramic capacitor close to the REFIN

pin is recommended.

238516 F08

REFGND

REFBUF

REFIN

2.7µF LTC2385-16

REFGND

REFBUF

10µF

VIN

LTC6655-2.048

GND

SHDN

VOUT_F

VOUT_S

0.1µF

Figure 6. Configuration for Using the Internal Reference

Figure 5. LTC2385-16 Internal Reference Circuitry

238516 F05

2.048V

REFERENCE

ADC

CORE

REFGND

REFBUF

REFIN

15k

LTC2385-16

2×

238516 F06

REFGND

REFBUF

REFIN

0.1µF

LTC2385-16

REFGND

REFBUF

10µF

238516 F07

9 10 11 12

Figure 7 shows a suggested layout for the REFBUF capaci-

tor. The capacitor should be connected to REFBUF and

REFGND through short, wide traces. REFGND should also

be connected with a wide trace to the grounded exposed

pad (Pin 33).

External Reference with Internal Reference Buffer

If more accuracy and/or lower drift is desired, REFIN can

be directly overdriven by an external 2.048V reference as

External Reference Buffer

The internal reference buffer can also be overdriven with

an external 4.096V reference at REFBUF as shown in

Figure 9. To do so, REFIN must be grounded to disable

the reference buffer. The external reference must have a

fast transient response and be able to drive the 0.5mA

to 0.9mA load at the REFBUF pin. The LTC6655-4.096 is

recommended when overdriving REFBUF.

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

APPLICATIONS INFORMATION

Figure 10. 32k Point FFT of the LTC2385-

16, fSMPL = 5Msps, fIN = 2kHz

Common Mode Output

The VCM pin is an output that provides one-half the voltage

present on the REFBUF pin. This voltage can be used to

set the common mode of a differential amplifier driving the

analog inputs. Bypass VCM to GND with a 0.1μF ceramic

capacitor. If VCM is not used it can be left floating, but the

parasitic capacitance on the pin needs to be under 10pF.

The VCM output has 1/f noise which for most driver circuits

will be removed by the ADC common mode rejection ratio.

VCM is not recommended for single-ended to differential

circuits that pass the VCM noise to only one ADC input.

DYNAMIC PERFORMANCE

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2385-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

to frequencies from above DC and below half the sampling

frequency. Figure 10 shows that the LTC2385-16 achieves

a typical SINAD of 93.9dB at a 5MHz sampling rate with

a 2kHz input.

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 10 shows

that the LTC2385-16 achieves a typical SNR of 94dB at a

5MHz sampling rate with a 2kHz input.

Total Harmonic Distortion (THD)

Total Harmonic Distortion (THD) is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (fSMPL/2).

THD is expressed as:

THD=20log V22+V32+V42+…+ Vn2

where V1 is the RMS amplitude of the fundamental

frequency and V2 through Vn are the amplitudes of the

second through nth harmonics. Figure 10 shows that the

LTC2385-16 achieves a typical THD of –117dB at a 5MHz

sampling rate with a 2kHz input.

POWER CONSIDERATIONS

The LTC2385-16 requires three power supplies: VDD (5V),

VDDL (2.5V), and OVDD (2.5V). Bypass VDD to GND with

a 0.1µF ceramic capacitor close to the pair of pins and a

SNR = 94.0dB

THD = –117dB

SINAD = 93.9dB

SFDR = 119dB

FREQUENCY (MHz)

0.5

1.5

2.5

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

238516 F10

Figure 9. Overdriving REFBUF Using the LTC6655-4.096

238516 F09

REFGND

REFBUF

REFIN

LTC2385-16

REFGND

REFBUF

10µF

VIN

LTC6655-4.096

GND

SHDN

VOUT_F

VOUT_S

0.1µF

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

APPLICATIONS INFORMATION

10µF ceramic capacitor in parallel. Bypass VDDL to GND

with a 0.1µF ceramic capacitor close to the pair of pins

and a 10µF ceramic capacitor in parallel. OVDD can come

from the same source as VDDL but it should be isolated

by a ferrite bead and have its own 0.1μF bypass capacitor.

Power Supply Sequencing

The LTC2385-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2385-16

has a power-on-reset (POR) circuit that will reset the

LTC2385-16 at initial power-up or whenever VDD or VDDL

drops well below their minimum values. Once the supply

voltage re-enters the nominal supply voltage range, the

POR will reinitialize the ADC.

Power-Down Mode

When PD is pulled low, LTC2385-16 enters power-down

mode. In this state, all internal functions, including the

reference and LVDS outputs, are turned off and subsequent

conversion requests are ignored. The power consumption

drops to a typical value of 10µW. This mode can be used

if the LTC2385-16 is inactive for a long period of time and

the user wants to minimize power dissipation.

The amount of time required to recover from power-down

mode depends on how REFBUF is configured. When using

the internal reference buffer with a 10µF bypass capacitor,

the ADC will stabilize after 20ms. If REFBUF is externally

driven, the recovery time can be significantly less.

TIMING AND CONTROL

CNV Timing

The LTC2385-16 conversion is controlled by the CNV+ and

CNV– inputs. CNV+/CNV– can be driven directly with an

LVDS signal. Alternatively, CNV+ can be driven with a 0V

to 2.5V CMOS signal when CNV– is tied to GND. A rising

edge on CNV+ will sample the analog inputs and start a

conversion. The pulse width of CNV+ should meet the

tCNVH and tCNVL specifications in the timing table.

After the LTC2385-16 is powered on, or exits power-down

mode, conversion data is invalid for the first two conver-

sion cycles. Subsequent results are accurate as long as

the time between conversions meets the tCYC specification.

If the analog input signal has not completely settled when

it is sampled, the ADC noise performance will be affected

by jitter on the rising edge of CNV+. In this case the rising

edge of CNV+ should be driven by a clean low jitter signal.

Note that the ADC is less sensitive to jitter on the falling

edge of CNV+.

In applications that are insensitive to jitter, CNV can be

driven directly from an FPGA.

Internal Conversion Clock

The LTC2385-16 has an internal clock that is trimmed

to achieve a maximum conversion time of 101ns. With a

typical acquisition time of 133ns, throughput performance

of 5Msps is guaranteed.

DIGITAL INTERFACE

The LTC2385-16 has a serial LVDS digital interface that

is easy to connect to an FPGA. Three LVDS pairs are re-

quired: CLK±, DCO±, and DA±. A fourth LVDS pair, DB±,

is optional (Figure 11).

Figure 11. Digital Output Interface to an FPGA

238516 F11

LTC2385-16

OPTIONAL

FPGA

100Ω

CLK+

CLK–

–

100Ω

DCO+

DCO–

–

100Ω

DA+

DA–

100Ω

DB+

DB–

–

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

APPLICATIONS INFORMATION

The LVDS signals should be routed on the PC board as

100Ω differential transmission lines and terminated at the

receiver with 100Ω resistors.

A conversion is started by the rising edge of CNV+. When

the conversion is complete, the most-significant data bit

is output on DA±. Data is then ready to be shifted out by

applying a burst of eight clock pulses to the CLK± input.

The data on DA± is updated by every edge of CLK±. An

echoed version of CLK± is output on DCO±. The edges of

DA± and DCO± are aligned, so DCO± can be used to latch

DA± in the FPGA. The timing of a single conversion is

shown in Figure 12.

Data must be clocked out after the current conversion is

complete, and before the next conversion finishes. The valid

time window for clocking out data is shown in Figure 13.

Note that it is allowed to be still clocking out data when

the next conversion begins.

Tw o -Lane Output Mode

At high sample rates the required LVDS interface data rate

can reach >200Mbps. Most FPGAs can support this, but

if a lower data rate is desired, the two-lane output mode

can be used. When the TWOLANES input pin is tied high,

the optional LVDS output DB± is enabled, and data is out-

put two bits at a time on DA± and DB±. Enabling the DB±

output increases the supply current from OVDD by about

3.6mA. In two-lane mode, four clock pulses are required

for CLK± (see Timing Diagrams).

Output Test Patterns

To allow in-circuit testing of the digital interface to the

ADC, there is a test mode that forces the ADC data outputs

to known values:

One-Lane Mode: 1010 0000 0111 1111

Tw o -Lane Mode: 1100 1100 0011 1111

The test pattern is enabled when the TESTPAT pin is

brought high.

BOARD LAYOUT

The LTC2385-16 requires a printed circuit board with a

clean unbroken ground plane. A multilayer board with an

internal ground plane in the first layer beneath the ADC is

recommended. Layout for the printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

Figure 12. Timing Diagram for a Single Conversion in One-Lane Mode

tCONV

238516 F12

CNV

D15 14 13 12 11 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CLK

DCO

1 2 3 4 5 6 7 8

MSB LSB

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

Figure 13. Valid Time Window for Clocking Out Data

tFIRSTCLK tLASTCLK

238516 F13

CNV

CLK

1 2 3 4 5 6 7 8

TIME WINDOW FOR CLOCKING OUT CONVERSION N

CONVERSION N CONVERSION N+1

APPLICATIONS INFORMATION

to run any digital track alongside an analog signal track

or underneath the ADC.

High quality ceramic bypass capacitors should be used

at the VDD, VDDL, OVDD, VCM, REFIN, and REFBUF pins.

Bypass capacitors must be located as close to the pins as

possible. Size 0402 ceramic capacitors are recommended

(except for REFBUF). The traces connecting the pins and

bypass capacitors must be kept short and should be made

as wide as possible.

Of particular importance is the capacitor between REFBUF

and REFGND, which should be a 10μF (X7R, 0805 size)

ceramic capacitor. This capacitor should be on the same

side of the circuit board as the ADC, and as close to the

device as possible. Adding a second, smaller capacitor in

parallel with the 10μF may degrade performance and is

not recommended.

The analog inputs, convert start, and digital outputs should

not be routed next to each other. Ground fill and grounded

vias should be used as barriers to isolate these signals

from each other.

Exposed Package Pad

For good electrical and thermal performance, the exposed

pad on the bottom of the package must be soldered to a

large grounded pad on the PC board. This pad should be

connected to the internal ground planes by an array of vias.

Mechanical Stress Shift

The mechanical stress of mounting a part to a board can

cause subtle changes to the SNR and internal voltage

reference. The best soldering method is to use IR reflow

or convection soldering with a controlled temperature

profile. Hand soldering with a heat gun or a soldering iron

is not recommended.

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2385-16#packaging for the most recent package drawings.

5.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

3.50 REF

(4-SIDES)

3.45 ±0.10

0.75 ±0.05 R = 0.115

TYP

0.25 ±0.05

(UH32) QFN 0406 REV D

0.50 BSC

0.200 REF

0.00 – 0.05

0.70 ±0.05

3.50 REF

(4 SIDES)

4.10 ±0.05

5.50

±0.05

0.25 ±0.05

PACKAGE OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

3.45 ±0.05

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

LTC2385-16

238516f

For more information www.linear.com/LTC2385-16

LT 0316 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2385-16

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

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LTC2271 16-Bit, 20Msps Serial Dual ADC 84.1dB SNR, 99dB SFDR, 92mW per Channel

References

LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package

Amplifiers

LT6200/LT6201 Single/Dual 165MHz Op-Amp 0.95nV/√Hz, Low Distortion

LT6236/LT6237 Single/Dual 215MHz Op-Amp 1.1nV/√Hz, Low Distortion

Low Power Input Drive Circuit for Signals up to 200kHz

Input Drive Circuit with Low Distortion up to 1MHz 32k Point FFT, fSMPL = 5Msps,

fIN = 50kHz

32k Point FFT, fSMPL = 5Msps,

fIN = 50kHz

24.9Ω

680pF

0.1µF

10µF

0.1µF

4.096V

IN+

IN–

LTC2385-16

1/2 LT6201

< 1MHz

DDL

2.5V

CLK

DCO

TWOLANES

TESTPAT

CNV

REFBUF

REFGND

REFIN

LVDS

INTERFACE

5MHz

SAMPLE

CLOCK

238516 TA03

–

SNR = 94.3dB

THD = –117dB

SINAD = 94.3dB

SFDR = 119dB

FREQUENCY (MHz)

0.5

1.5

2.5

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

238516 TA04

SNR = 94.3dB

THD = –115dB

SINAD = 94.3dB

SFDR = 117dB

FREQUENCY (MHz)

0.5

1.5

2.5

–160

–140

–120

–100

–80

–60

–40

–20

AMPLITUDE (dBFS)

238516 TA06

24.9Ω

680pF

4.096V

IN+

IN–

LTC2385-16

1/2 LT6237

< 200kHz

1/2 LT6237

7.5V

–2.5V

–

238516 TA05