Product Specification PE4308 75 RF Digital Attenuator 5-bit, 31 dB, DC - 4.0 GHz Product Description The PE4308 is a high linearity, 5-bit RF Digital Step Attenuator (DSA) covering 31 dB attenuation range in 1dB steps, and is pin compatible with the PE430x series. This 75-ohm RF DSA provides both parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4308 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE4308 is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Features * Attenuation: 1 dB steps to 31 dB * Flexible parallel and serial programming interfaces * Latched or direct mode * Unique power-up state selection * Positive CMOS control logic * High attenuation accuracy and linearity over temperature and frequency * Very low power consumption * Single-supply operation * 75 impedance * Pin compatible with PE430x series * Packaged in a 20 Lead 4x4 mm QFN Figure 2. Package Type 20 Lead 4x4 mm QFN Switched Attenuator Array RF Input RF Output Parallel Control 5 Serial Control 3 Power-Up Control 2 Control Logic Interface Table 1. Electrical Specifications @ +25C, VDD = 3.0 V Parameter Test Conditions Frequency Operation Frequency Insertion Loss Any Bit or Bit Combination 1 dB Compression3,4 Input IP31,2,4 Two-tone inputs up to +18 dBm Return Loss Switching Speed Notes: 1. 2. 3. 4. Typical DC 2 Attenuation Accuracy Minimum Maximum Units 2000 MHz DC 1.2 GHz - 1.4 1.95 dB DC 1.2 GHz - - (0.2 + 4% of atten setting) Not to Exceed +0.4 dB dB dB 1 MHz 1.2 GHz 30 34 - dBm 1 MHz 1.2 GHz - 52 - dBm DC 1.2 GHz 10 13 - dB - - 1 s 50% control to 0.5 dB of final value Device Linearity will begin to degrade below 1 MHz See figures on Pages 4 to 6 for data across frequency. Note Absolute Maximum in Table 3. Measured in a 50 system. Document No. 70-0162-04 www.psemi.com (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE4308 Product Specification Figure 14. Pin Configuration (Top View) N/C C1 GND C2 C4 20 19 18 17 16 Symbol 1 VDD Pin Name Max Units VDD Power supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD+ 0.3 V -65 150 C TST Storage temperature range 14 RF2 PIN Input power (50) +30 dBm 13 P/S 500 V 12 Vss/GND ESD voltage (Human Body Model) 11 GND Table 2. Pin Descriptions Pin No. Min C8 10 5 Parameter/Conditions 15 GND LE Exposed Solder Pad 9 4 VDD Clock 8 3 PUP2 Data 7 2 6 RF1 20-lead QFN 4x4mm PUP1 C16 Table 3. Absolute Maximum Ratings VESD Table 4. Operating Ranges Parameter C16 Attenuation control bit, 16dB (Note 4). Digital Input Leakage RF1 RF port (Note 1). Input Power 3 Data Serial interface data input (Note 4). 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2). 6 VDD Power supply pin. 7 PUP1 Power-up selection bit. 8 PUP2 Power-up selection bit. Power supply pin. VDD GND Ground connection. 11 GND Ground connection. 12 Vss/GND Negative supply voltage or GND connection (Note 3) 13 P/S Parallel/Serial mode select. 14 RF2 RF port (Note 1). 15 C8 Attenuation control bit, 8 dB. 16 C4 Attenuation control bit, 4 dB. 17 C2 Attenuation control bit, 2 dB. 18 GND Ground connection. 19 C1 Attenuation control bit, 1 dB. 20 N/C No connect Paddle GND Ground for proper operation Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor. 2: Latch Enable (LE) has an internal 100 kresistor to VDD. 3: Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator. 4. Place a 10 kresistor in series, as close to pin as possible to avoid frequency resonance. See "Resistor on Pin 1 & 3" paragraph (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 Units 2.7 3.0 3.3 V 100 A 0.7xVDD Digital Input Low 2 9 Max IDD Power Supply Current 1 10 Typ VDD Power Supply Voltage Digital Input High Description Min Temperature range -40 V 0.3xVDD V 1 A +24 dBm 85 C Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up. Switching Frequency The PE4308 has a maximum 25 kHz switching rate. Resistor on Pin 1 & 3 A 10 k resistor on the inputs to Pin 1 & 3 (see Figure 5) will eliminate package resonance between the RF input pin and the two digital inputs. Specified attenuation error versus frequency performance is dependent upon this condition. Document No. 70-0162-04 UltraCMOSTM RFIC Solutions PE4308 Product Specification Figure 4. Evaluation Board Layout Evaluation Kit The Digital Attenuator Evaluation Kit was designed to ease customer evaluation of the PE4308 DSA. Peregrine Specification 101/0112 J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and -VDD. If use of the internal negative voltage generator is desired, then connect -VDD (black banana plug) to ground. If an external -VDD is desired, then apply -3 V. J1 should be connected to the LPT1 port of a PC with the supplied control cable. The evaluation software is written to operate the DSA in serial mode, so switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Note: Jumper J6 supplies power to the evaluation board support circuits. To evaluate the power up options, first disconnect the control cable from the evaluation board. The control cable must be removed to prevent the PC port from biasing the control pins. During power up with P/S=1 high and LE=1, the default power-up signal attenuation is set to the value present on the five control bits on the five parallel data inputs (C1 to C16). This allows any one of the 32 attenuation settings to be specified as the power-up state. During power up with P/S=0 high and LE=0, the control bits are automatically set to one of four possible values presented through the PUP interface. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in the Table 6. Figure 5. Evaluation Board Schematic Peregrine Specification 102/0142 Pin 20 is open and can be connected to any bias. Note: Resistors on pins 1 and 3 are required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency. Document No. 70-0162-04 www.psemi.com (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE4308 Product Specification Typical Performance Data (25C, VDD = 3.0 V unless otherwise noted) Figure 7. Attenuation at Major steps Figure 6. Insertion Loss (Zo=75 ohms) 0 35 31dB 30 -1 Attenuation (dB) Insertion Loss (dB) 25 -2 -3 20 16dB 15 2dB 10 -4 4dB 5 -5 0 0 500 1000 1500 2000 0 500 RF Frequency (MHz) 1500 2000 Figure 9. Output Return Loss at Major Attenuation Steps (Zo=75 ohms) 0 -10 -10 Output Return Loss (dB) 0 -20 8dB -30 1000 RF Frequency (MHz) Figure 8. Input Return Loss at Major Attenuation Steps (Zo=75 ohms) Input Return Loss (dB) 1dB 8dB 16dB -20 -30 31dB -40 -40 -50 -50 0 500 1000 1500 RF Frequency (MHz) (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 2000 0 500 1000 1500 2000 RF Frequency (MHz) Document No. 70-0162-04 UltraCMOSTM RFIC Solutions PE4308 Product Specification Typical Performance Data (25C, VDD = 3.0 V unless otherwise noted) Figure 11. Attenuation Error Vs. Attenuation Setting Figure 10. Attenuation Error Vs. Frequency 0.4 0.5 2dB 0.2 8dB Attenuation Error (dB) Attenuation Error (dB) 0 -0.5 10MHz, -40C 16dB -1 31dB 10MHz, 25C 0 10MHz, 85C -0.2 -0.4 -1.5 -0.6 -0.8 -2 0 500 1000 1500 0 2000 5 10 15 20 25 30 35 Attenuation Setting (dB) RF Frequency (MHz) Figure 12. Attenuation Error Vs. Attenuation Setting Figure 13. Attenuation Error Vs. Attenuation Setting 0.4 0.4 0.2 0.2 Attenuation Error (dB) Attenuation Error (dB) 500MHz, -40C 0 500MHz, 25C -0.2 500MHz, 85C -0.4 0 -0.2 1GHz, -40C -0.4 1GHz, 25C -0.6 -0.6 1GHz, 85C -0.8 -0.8 0 5 10 15 20 25 30 0 35 5 10 15 20 25 30 35 Attenuation Setting (dB) Attenuation Setting (dB) Note: Positive attenuation error indicates higher attenuation than target value Document No. 70-0162-04 www.psemi.com (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 PE4308 Product Specification Typical Performance Data (25C, VDD = 3.0 V unless otherwise noted) Figure 15. Input 1 dB Compression (Zo=50 ohms) 0.4 40 0.2 35 30 0 -0.2 -0.4 1.2GHz, -40C 1.2GHz, 25C -0.6 1dB Compression (dBm) Attenuation Error (dB) Figure 14. Attenuation Error vs. Attenuation Setting -0.8 1.2GHz, 85C -1 25 20 15 10 5 0 0 5 10 15 20 25 30 35 Attenuation Setting (dB) 0 500 1000 1500 2000 RF Frequency (MHz) Figure 16. Input IP3 (Zo=50 ohms) 60 55 50 IIP3 (dBm) 45 40 35 30 25 20 0 500 1000 1500 2000 RF Frequency (MHz) Note: Positive attenuation error indicates higher attenuation than target value (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 Document No. 70-0162-04 UltraCMOSTM RFIC Solutions PE4308 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4308. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 19 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 19) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Table 5. Truth Table P/S C16 C8 C4 C2 C1 Attenuation State 0 0 0 0 0 0 Reference Loss 0 0 0 0 0 1 1 dB 0 0 0 0 1 0 2 dB 0 0 0 1 0 0 4 dB 0 0 1 0 0 0 8 dB 0 1 0 0 0 0 16 dB 0 1 1 1 1 1 31 dB Note: Not all 32 possible combinations of C1-C16 are shown. Serial Interface The PE4308's serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. The latch is controlled by three CMOScompatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be Document No. 70-0162-04 www.psemi.com serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The stop bit (B0) of the data should always be low to prevent an unknown state in the device. The timing for this operation is defined by Figure 17 (Serial Interface Timing Diagram) and Table 8 (Serial Interface AC Characteristics). Power-up Control Settings The PE4308 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/ S=1), the five control bits and a stop bit are set to whatever data is present on the five parallel data inputs (C1 to C16). This allows any one of the 32 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/ S=0) with LE=0, the control bits are automatically set to one of four possible values. These four values are selected by the two power-up control bits, PUP1 and PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode). Table 6. Power-Up Truth Table, Parallel Interface Mode P/S LE PUP2 PUP1 Attenuation State 0 0 0 0 Reference Loss 0 0 0 1 8 dB 0 0 1 0 16 dB 0 0 1 1 0 Note: 1 X X 31 dB Defined by C1-C16 Power up with LE=1 provides normal parallel operation with C1-C16, and PUP1 and PUP2 are not active. (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PE4308 Product Specification Table 7. 5-Bit Attenuator Serial Programming Register Map Figure 17. Serial Interface Timing Diagram LE Clock B5 B4 B3 B2 B1 B0 C16 C8 C4 C2 C1 0 MSB (first in) Data MSB LSB (last in) LSB tSDSUP tLESUP tSDHLD tLEPW Note: The stop bit (B0) must always be low to prevent the attenuator from entering an unknown state. Figure 18. Parallel Interface Timing Diagram LE Parallel Data C16:C1 tPDSUP tLEPW tPDHLD Table 8. Serial Interface AC Characteristics Table 9. Parallel Interface AC Characteristics VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol Parameter Min Max Unit 10 MHz fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns tSDSUP Serial data set-up time before clock rising edge 10 ns tSDHLD Serial data hold time after clock falling edge 10 ns Note: Symbol Parameter Min Max Unit tLEPW LE minimum pulse width 10 ns tPDSUP Data set-up time before rising edge of LE 10 ns tPDHLD Data hold time after falling edge of LE 10 ns fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70-0162-04 UltraCMOSTM RFIC Solutions PE4308 Product Specification Figure 19. Package Drawing 4.00 INDEX AREA 2.00 X 2.00 2.00 4.00 2.00 -B- 0.25 C 0.80 -A- 0.10 C 0.08 C SEATING PLANE -C- 0.20 REF 0.50 TYP 0.55 2.00 TYP 0.020 EXPOSED PAD & TERMINAL PADS 2.00 1.00 0.435 1.00 10 2.00 11 4.00 0.435 0.18 6 5 0.18 1 15 20 DETAIL A EXPOSED PAD 16 DETAIL A 2 0.23 1 0.10 C A B 1. Dimension applies to metallized terminal and is measured between 0.25 and 0.30 from terminal tip. 2. Coplanarity applies to the exposed heat sink slug as well as the terminals. 3. Dimensions are in millimeters. Document No. 70-0162-04 www.psemi.com (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE4308 Product Specification Figure 20. Marking Specifications 4308 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number Figure 21. Tape and Reel Drawing Table 10. Ordering Information Order Code Part Marking Description Package Shipping Method 4308-01 4308 PE4308-20MLP 4x4mm-75A 20-lead 4x4 mm QFN 75 units / Tube 4308-02 4308 PE4308-20MLP 4x4mm-3000C 20-lead 4x4 mm QFN 3000 units / T&R 4308-00 PE4308-EK PE4308-20MLP 4x4mm-EK Evaluation Kit 1 / Box 4308-51 4308 PE4308G-20MLP 4x4mm-75A Green 20-lead 4x4 mm QFN 75 units / Tube 4308-52 4308 PE4308G-20MLP 4x4mm-3000C Green 20-lead 4x4 mm QFN 3000 units / T&R (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 Document No. 70-0162-04 UltraCMOSTM RFIC Solutions PE4308 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corporation Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor, Korea Peregrine Semiconductor Europe #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Batiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 South Asia Pacific Space and Defense Products Peregrine Semiconductor, China Americas: Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0162-04 www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. (c)2003-2006 Peregrine Semiconductor Corp. All rights reserved. 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