December 2011 Doc ID 16891 Rev 26 1/44
1
M24C64-DF
M24C64-W M24C64-R M24C64-F
64 Kbit serial I²C bus EEPROM
Features
■Compatible with all I2C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■Memory array:
– 64 Kb (8 Kbytes) of EEPROM
– Page size: 32 bytes
– Additional Write lockable Page (M24C64-
DF)
■Write
– Byte Write within 5 ms
– Page Write within 5 ms
■Single supply voltage:
– M24C64-W: 2.5 V to 5.5 V
– M24C64-R: 1.8 V to 5.5 V
– M24C64-xF: 1.7 V
■Random and Sequential Read modes
■Write protect of the whole memory array
■Enhanced ESD/Latch-Up protection
■More than 1 million Write cycles
■More than 40-year data retention
■Packages
– RoHS-compliant and halogen-free
(ECOPACK2®)
– PDIP8 package: RoHS-compliant
(ECOPACK1®)
PDIP8 (BN)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MB)
WLCSP5 (CS)
www.st.com
Contents M24C64-DF, M24C64-W, M24C64-R, M24C64-F
2/44 Doc ID 16891 Rev 26
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9 Write Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . 17
4.10 Lock Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . . . 18
4.12 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.15 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Contents
Doc ID 16891 Rev 26 3/44
4.16 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.17 Read Identification Page (M24C64-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.18 Read the lock status (M24C64-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
List of tables M24C64-DF, M24C64-W, M24C64-R, M24C64-F
4/44 Doc ID 16891 Rev 26
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. DC characteristics (M24xxx-W - device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 33
Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 35
Table 22. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 23. WLCSP-R 5-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . . 37
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
M24C64-DF, M24C64-W, M24C64-R, M24C64-F List of figures
Doc ID 16891 Rev 26 5/44
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. WLCSP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus
parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 33
Figure 16. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 34
Figure 17. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19. WLCSP-R 5-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . . 37
Description M24C64-DF, M24C64-W, M24C64-R, M24C64-F
6/44 Doc ID 16891 Rev 26
1 Description
The M24C64-W operates with a supply voltage range of 2.5 V/5.5 V, the M24C64-R
operates with a supply voltage range of 1.8 V/5.5 V and the M24C64-F, M24C64-DF devices
operate with a supply voltage range of 1.7 V/5.5 V.
The M24C64-DF offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in read only mode.
Figure 1. Logic diagram
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Description
Doc ID 16891 Rev 26 7/44
Figure 2. 8-pin package connections
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3. WLCSP connections (top view)
Note: Inputs E2, E1, E0 are internally connected to (001). Please refer to Section 2.3 for further
explanations.
Caution: As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
Table 1. Signal names
Signal name Function Direction
E2, E1, E0 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC Write Control Input
VCC Supply voltage
VSS Ground
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Signal description M24C64-DF, M24C64-W, M24C64-R, M24C64-F
8/44 Doc ID 16891 Rev 26
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how
the value of the pull-up resistor can be calculated).
2.3 Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code as shown in Figure 4. When not connected (left
floating), these inputs are read as low (0). For the WLCSP package, the (E2,E1,E0) inputs
are internally connected to (0,0,1).
Figure 4. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven high, device select and Address bytes are
acknowledged, Data bytes are not acknowledged.
Ai12806
VCC
M24xxx
VSS
Ei
VCC
M24xxx
VSS
Ei
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Signal description
Doc ID 16891 Rev 26 9/44
2.5 VSS ground
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Ta b l e 7 , Ta b le 8 and
Ta bl e 9 ). In order to secure a stable DC supply voltage, it is recommended to decouple the
VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Ta bl e 7 , Ta b le 8 and Ta b le 9 . The rise time must not vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Ta bl e 8 and Ta bl e 9 ). Until VCC
passes over the POR threshold, the device is reset and in Standby Power mode.
In a similar way, during power-down (continuous decay of VCC), as soon as VCC drops below
the POR threshold voltage, the device is reset and stops responding to any instruction sent
to it.
2.6.4 Power-down conditions
During power-down (continuous decay of VCC), the device must be in Standby Power mode
(mode reached after decoding a Stop condition, assuming that there is no internal Write
cycle in progress).
Signal description M24C64-DF, M24C64-W, M24C64-R, M24C64-F
10/44 Doc ID 16891 Rev 26
Figure 5. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus)
Figure 6. I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus
parasitic capacitance (Cbus)
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Signal description
Doc ID 16891 Rev 26 11/44
Figure 7. I2C bus protocol
Table 2. Device select code
Device type identifier(1)
1. The most significant bit, b7, is sent first.
Chip Enable address(2)(3)
2. E2, E1 and E0 are compared against the respective external pins on the memory device.
3. For the WLCSP package, the (E2,E1,E0) inputs are internally connected to (0,0,1).
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select code1010E2E1E0RW
Table 3. Address most significant byte
b15 b14 b13 b12 b11 b10 b9 b8
Table 4. Address least significant byte
b7 b6 b5 b4 b3 b2 b1 b0
SCL
SDA
SCL
SDA
SDA
Start
Condition
SDA
Input
SDA
Change
AI00792B
Stop
Condition
123 789
MSB ACK
Start
Condition
SCL 123 789
MSB ACK
Stop
Condition
Memory organization M24C64-DF, M24C64-W, M24C64-R, M24C64-F
12/44 Doc ID 16891 Rev 26
3 Memory organization
The memory is organized as shown in Figure 8.
Figure 8. Block diagram
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation
Doc ID 16891 Rev 26 13/44
4 Device operation
The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
4.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
4.4 Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F
14/44 Doc ID 16891 Rev 26
4.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Ta b l e 3 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is
1010b. Up to eight memory devices can be connected on a single I2C bus(a). Each one is
given a unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select
code is received, the device only responds if the Chip Enable Address is the same as the
value on the Chip Enable (E2, E1, E0) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
a. Only one M24C64 in WLCSP package can be connected on the I²C bus (see Figure 4).
Table 5. Operating modes
Mode RW bit WC(1)
1. X = VIH or VIL.
Bytes Initial sequence
Current Address
Read 1 X 1 Start, device select, RW = 1
Random Address
Read
0X 1Start, device select, RW = 0, Address
1 X reStart, device select, RW = 1
Sequential Read 1 X ≥ 1 Similar to Current or Random Address
Read
Byte Write 0 VIL 1 Start, device select, RW = 0
Page Write 0 VIL ≤ 32 Start, device select, RW = 0
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation
Doc ID 16891 Rev 26 15/44
Figure 9. Write mode sequences with WC = 1 (data write inhibited)
Stop
Start
Byte Write Dev select Byte address Byte address Data in
WC
Start
Page Write Dev select Byte address Byte address Data in 1
WC
Data in 2
AI01120d
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK ACK ACK NO ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK NO ACK
Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F
16/44 Doc ID 16891 Rev 26
4.6 Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 10, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data Byte.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Ta bl e 3 ) is sent first, followed by the Least Significant Byte (Ta b l e 4 ). Bits b15 to b0
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 9.
4.7 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 10.
4.8 Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b12-b5) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation
Doc ID 16891 Rev 26 17/44
Figure 10. Write mode sequences with WC = 0 (data write enabled)
4.9 Write Identification Page (M24C64-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. The Identification Page is written by issuing an
Write Identification Page instruction. This instruction uses the same protocol and format as
Page Write (into memory array), except for the following differences:
●Device type identifier = 1011b
●MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A4/A0 define the byte address inside the Identification Page.
If the Identification Page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
Stop
Start
Byte Write Dev Select Byte address Byte address Data in
WC
Start
Page Write Dev Select Byte address Byte address Data in 1
WC
Data in 2
AI01106d
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F
18/44 Doc ID 16891 Rev 26
4.10 Lock Identification Page (M24C64-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification Page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
●Device type identifier = 1011b
●Address bit A10 must be ‘1’; all other address bits are don't care
●The data byte must be equal to the binary value xxxx xx1x, where x is don't care
If the Identification Page is locked, the data bytes transferred during the Lock Identification
Page instruction are not acknowledged (NoAck).
4.11 ECC (Error Correction Code) and Write cycling
The M24C64 devices identified with the process letter A or K offer an ECC (Error Correction
Code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC.
As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read
operation, the ECC detects it and replaces it by the correct value. The read reliability is
therefore much improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by word (4 bytes) at address 4*N
(where N is an integer) in order to benefit from the larger amount of Write cycles.
The M24C64 devices are qualified as 1 million (1,000,000) Write cycles, using a cycling
routine that writes to the device by multiples of 4-byte words.
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation
Doc ID 16891 Rev 26 19/44
Figure 11. Write cycle polling flowchart using ACK
4.12 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Ta bl e 1 7 , but the typical time is shorter. To make use of this, a polling sequence can
be used by the bus master.
The sequence, as shown in Figure 11, is:
1. Initial condition: a Write cycle is in progress.
2. Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Write cycle
in progress
AI01847d
Next
operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
Returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write operation
Device select
with RW = 1
Send address
and receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO Start
condition
Continue the
Write operation
Continue the
Random Read operation
Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F
20/44 Doc ID 16891 Rev 26
Figure 12. Read mode sequences
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
Start
Dev select * Byte address Byte address
Start
Dev select Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Dev select Data out
Random
Address
Read
Stop
Start
Dev select * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev select * Byte address Byte address
Sequential
Random
Read
Start
Dev select * Data out 1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation
Doc ID 16891 Rev 26 21/44
4.13 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
4.14 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 12) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
4.15 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 12, without acknowledging the Byte.
4.16 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 12.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory
address 00h.
4.17 Read Identification Page (M24C64-D)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the Identification Page from location 10d, the
number of bytes should be less than or equal to 22, as the ID page boundary is 32 bytes).
Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F
22/44 Doc ID 16891 Rev 26
4.18 Read the lock status (M24C64-D)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that:
●Start: the truncated command is not executed because the Start condition resets the
device internal logic,
●Stop: the device is then set back into Standby mode by the Stop condition.
4.19 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Initial delivery state
Doc ID 16891 Rev 26 23/44
5 Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
6 Maximum rating
Stressing the device outside the ratings listed in Ta b l e 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TAAmbient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD
Lead temperature during soldering see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
PDIP-specific lead temperature during soldering 260(2)
2. TLEAD max must not be applied for more than 10 s.
°C
VIO Input or output range –0.50 6.5 V
IOL DC output current (SDA = 0) - 5 mA
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic pulse (human body model)(3)
3. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with JEDEC
Std JESD22-A114, C1=100pF, R1=1500Ω, R2=500Ω)
- 4000 V
DC and AC parameters M24C64-DF, M24C64-W, M24C64-R, M24C64-F
24/44 Doc ID 16891 Rev 26
7 DC and AC parameters
Figure 13. AC test measurement I/O waveform
Table 7. Operating conditions (M24xxx-W)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TA
Ambient operating temperature (device grade 6) –40 85 °C
Ambient operating temperature (device grade 3) –40 125 °C
fCOperating clock frequency - 1 MHz
Table 8. Operating conditions (M24xxx-R)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.8 5.5 V
TAAmbient operating temperature –40 85 °C
fCOperating clock frequency - 1 MHz
Table 9. Operating conditions (M24xxx-F)
Symbol Parameter Min. Max. Unit
VCC Supply voltage 1.7 5.5 V
TAAmbient operating temperature –40 85 °C
fCOperating clock frequency - 400(1)
1. fCmax is 1 MHz under certain conditions, see Table 16, note 1.
kHz
Table 10. AC test measurement conditions
Symbol Parameter Min. Max. Unit
Cbus Load capacitance 100 pF
SCL input rise/fall time, SDA input fall time 50 ns
Input voltage levels 0.2VCC to 0.8VCC V
Input and output timing reference levels 0.3VCC to 0.7VCC V
MS19844V1
0.7VCC
0.3VCC
0.8VCC
0.2VCC
Input voltage levels Input and output
timing reference
levels
M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC and AC parameters
Doc ID 16891 Rev 26 25/44
Note: This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please refer to AN2014.
Table 11. Input parameters
Symbol Parameter(1)
1. Characterized value, not tested in production.
Test condition Min. Max. Unit
CIN Input capacitance (SDA) 8 pF
CIN Input capacitance (other pins) 6 pF
ZL(2)
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Input impedance
(E2, E1, E0, WC) VIN < 0.3VCC 30 kΩ
ZH(2) Input impedance
(E2, E1, E0, WC) VIN > 0.7VCC 500 kΩ
Table 12. Memory cell characteristics
Symbol Parameter Test condition Min. Max. Unit
Ncycle Endurance TA = 25°C, 1.8 V < Vcc < 5.5 V 1,000,000 - Write cycle
DC and AC parameters M24C64-DF, M24C64-W, M24C64-R, M24C64-F
26/44 Doc ID 16891 Rev 26
Table 13. DC characteristics (M24xxx-W, device grade 6)
Symbol Parameter Test conditions (see Ta ble 7 and
Table 1 0 )Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, E2, E1,
E0)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
± 2 µA
ICC Supply current (Read)
2.5 V < VCC < 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns) 2mA
2.5 V < VCC < 5.5 V, fc = 1 MHz(1)
(rise/fall time < 50 ns)
1. Only for devices operating at fC max = 1 MHz (see Table 18)
2.5 mA
ICC0 Supply current (Write) During tW, 2.5 V < VCC < 5.5 V 5(2)
2. Characterized value, not tested in production.
mA
ICC1
Standby supply
current
Device not selected(3), VIN = VSS or
VCC, VCC = 2.5 V
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
2µA
Device not selected(3), VIN = VSS or
VCC, VCC = 5.5 V 5(4)
4. The new M24C64-W devices (identified by the process letter K) offer ICC1 = 3µA (max)
µA
VIL
Input low voltage
(SCL, SDA, WC) –0.45 0.3VCC V
VIH
Input high voltage
(SCL, SDA) 0.7VCC 6.5
V
Input high voltage
(WC, E2, E1, E0) 0.7VCC VCC+0.6
VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V 0.4 V
M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC and AC parameters
Doc ID 16891 Rev 26 27/44
Table 14. DC characteristics (M24xxx-W - device grade 3)
Symbol Parameter Test conditions (in addition to those
in Ta b le 7 and Tab le 1 0)Min. Max. Unit
ILI
Input leakage current
(SCL, SDA, E2, E1,
E0)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
± 2 µA
ICC Supply current (Read) fc = 400 kHz 2 mA
ICC0 Supply current (Write) During tW5(1)
1. Characterized value, not tested in production.
mA
ICC1
Standby supply
current
Device not selected(2), VIN = VSS or
VCC
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
10 µA
VIL
Input low voltage
(SCL, SDA, WC) –0.45 0.3VCC V
VIH
Input high voltage
(SCL, SDA) 0.7VCC 6.5 V
Input high voltage
(WC, E2, E1, E0) 0.7VCC VCC+0.6 V
VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V 0.4 V
DC and AC parameters M24C64-DF, M24C64-W, M24C64-R, M24C64-F
28/44 Doc ID 16891 Rev 26
Table 15. DC characteristics (M24xxx-R - device grade 6)
Symbol Parameter
Test conditions(1) (in addition
to those in Tabl e 8 and
Table 1 0 )
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
Min. Max. Unit
ILI
Input leakage current
(E1, E2, SCL, SDA)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
± 2 µA
ICC Supply current (Read)
VCC = 1.8 V, fc= 400 kHz 0.8 mA
fc= 1 MHz(2)
2. Only for devices operating at fC max = 1 MHz (see Table 18).
2.5 mA
ICC0 Supply current (Write) During tW, 1.8 V < VCC < 2.5 V 3(3)
3. Characterized value, not tested in production.
mA
ICC1 Standby supply current Device not selected(4),
VIN = VSS or VCC, VCC = 1.8 V
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
1µA
VIL
Input low voltage
(SCL, SDA, WC) 1.8 V ≤ V
CC < 2.5 V –0.45 0.25 VCC V
VIH
Input high voltage
(SCL, SDA) 1.8 V ≤ V
CC < 2.5 V 0.75VCC 6.5 V
Input high voltage
(WC, E2, E1, E0) 1.8 V ≤ V
CC < 2.5 V 0.75VCC VCC+0.6 V
VOL Output low voltage IOL = 1 mA, VCC = 1.8 V 0.2 V
M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC and AC parameters
Doc ID 16891 Rev 26 29/44
Table 16. DC characteristics (M24xxx-F)
Symbol Parameter
Test conditions(1) (in addition
to those in Tab l e 9 and
Tab l e 1 0 )
1. If the application uses the voltage range F device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
Min. Max. Unit
ILI
Input leakage current
(E1, E2, SCL, SDA)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO Output leakage current SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
± 2 µA
ICC Supply current (Read)
VCC = 1.7 V, fc= 400 kHz 0.8 mA
fc= 1 MHz(2)
2. Only for devices operating at fC max = 1 MHz (see Table 18).
2.5 mA
ICC0 Supply current (Write) During tW, 1.7 V < VCC < 2.5 V 3(3)
3. Characterized value, not tested in production.
mA
ICC1 Standby supply current Device not selected(4),
VIN = VSS or VCC, VCC = 1.7 V
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
1µA
VIL
Input low voltage
(SCL, SDA, WC) 1.7 V ≤ V
CC < 2.5 V –0.45 0.25 VCC V
VIH
Input high voltage
(SCL, SDA) 1.7 V ≤ V
CC < 2.5 V 0.75VCC 6.5 V
Input high voltage
(WC, E2, E1, E0) 1.7 V ≤ V
CC < 2.5 V 0.75VCC VCC+0.6 V
VOL Output low voltage IOL = 1 mA, VCC = 1.7 V 0.2 V
DC and AC parameters M24C64-DF, M24C64-W, M24C64-R, M24C64-F
30/44 Doc ID 16891 Rev 26
Table 17. 400 kHz AC characteristics
Symbol Alt. Parameter(1)
1. Test conditions (in addition to those in Table 7, Table 8, Ta bl e 9 and Table 10).
Min. Max. Unit
fCfSCL Clock frequency - 400 kHz
tCHCL tHIGH Clock pulse width high 600 - ns
tCLCH tLOW Clock pulse width low 1300 ns
tQL1QL2(2)
2. Characterized value, not tested in production.
tFSDA (out) fall time 20(3)
3. With CL = 10 pF.
120 ns
tXH1XH2 tRInput signal rise time (4)
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC< 400 kHz.
(4) ns
tXL1XL2 tFInput signal fall time (4) (4) ns
tDXCX tSU:DAT Data in set up time 100 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX tDH Data out hold time 100(5)
5. The new M24C64 device (identified by the process letter K) offers tCLQX = 100 ns (min) and tCLQV = 100 ns
(min), while the current device offers tCLQX = 200 ns (min) and tCLQV = 200 ns (min). Both series offer a
safe margin compared to the I2C specification which recommends tCLQV = 0 ns (min).
-ns
tCLQV(6)(7)
6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 5.
tAA Clock low to next data valid (access time) 100(5) 900 ns
tCHDL tSU:STA Start condition setup time 600 - ns
tDLCL tHD:STA Start condition hold time 600 - ns
tCHDH tSU:STO Stop condition set up time 600 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 1300 - ns
tWLDL(8)(2)
8. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(9)(2)
9. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Write time - 5 ms
tNS(2) Pulse width ignored (input filter on SCL and
SDA) - single glitch -80
(10)
10. The current M24C64 device offers tNS=100 ns (max), the new M24C64 device (identified by the process
letter K) offers tNS=80 ns (max). Both products offer a safe margin compared to the 50 ns minimum value
recommended by the I2C specification.
ns
M24C64-DF, M24C64-W, M24C64-R, M24C64-F DC and AC parameters
Doc ID 16891 Rev 26 31/44
Table 18. 1 MHz AC characteristics(1)
1. Only M24C64 and M24C64-D devices identified by the process letter K are qualified at 1 MHz.
Symbol Alt. Parameter(2)
2. Test conditions (in addition to those in Table 7, Table 8, Ta bl e 9 and Table 10).
Min. Max. Unit
fCfSCL Clock frequency 0 1 MHz
tCHCL tHIGH Clock pulse width high 260 - ns
tCLCH tLOW Clock pulse width low 400 - ns
tXH1XH2 tRInput signal rise time (3)
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC< 400 kHz, or less than 120 ns when fC<1MHz.
(3) ns
tXL1XL2 tFInput signal fall time (3) (3) ns
tQL1QL2(8) tFSDA (out) fall time - 120 ns
tDXCX tSU:DAT Data in setup time 50 - ns
tCLDX tHD:DAT Data in hold time 0 - ns
tCLQX tDH Data out hold time 100 - ns
tCLQV(4)(5)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 6.
tAA Clock low to next data valid (access time) 450 ns
tCHDL tSU:STA Start condition setup time 250 - ns
tDLCL tHD:STA Start condition hold time 250 - ns
tCHDH tSU:STO Stop condition setup time 250 - ns
tDHDL tBUF
Time between Stop condition and next Start
condition 500 - ns
tWLDL(6)(8)
6. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition) 0 - µs
tDHWH(7)(8)
7. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition) 1 - µs
tWtWR Write time - 5 ms
tNS(8)
8. Characterized only, not tested in production.
Pulse width ignored (input filter on SCL and
SDA) -80ns
DC and AC parameters M24C64-DF, M24C64-W, M24C64-R, M24C64-F
32/44 Doc ID 16891 Rev 26
Figure 14. AC waveforms
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Package mechanical data
Doc ID 16891 Rev 26 33/44
8 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 15. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline
1. Drawing is not to scale.
Table 19. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.2098
A1 0.38 0.0150
A2 3.30 2.92 4.95 0.1299 0.1150 0.1949
b 0.46 0.36 0.56 0.0181 0.0142 0.0220
b2 1.52 1.14 1.78 0.0598 0.0449 0.0701
c 0.25 0.20 0.36 0.0098 0.0079 0.0142
D 9.27 9.02 10.16 0.3650 0.3551 0.4000
E 7.87 7.62 8.26 0.3098 0.3000 0.3252
E1 6.35 6.10 7.11 0.2500 0.2402 0.2799
e2.54––0.1000––
eA 7.62 – – 0.3000 – –
eB 10.92 0.4299
L 3.30 2.92 3.81 0.1299 0.1150 0.1500
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
Package mechanical data M24C64-DF, M24C64-W, M24C64-R, M24C64-F
34/44 Doc ID 16891 Rev 26
Figure 16. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
1. Drawing is not to scale.
Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 1.75 0.0689
A1 0.10 0.25 0.0039 0.0098
A2 1.25 0.0492
b 0.28 0.48 0.0110 0.0189
c 0.17 0.23 0.0067 0.0091
ccc 0.10 0.0039
D 4.90 4.80 5.00 0.1929 0.1890 0.1969
E 6.00 5.80 6.20 0.2362 0.2283 0.2441
E1 3.90 3.80 4.00 0.1535 0.1496 0.1575
e1.27– –0.0500– –
h 0.25 0.50
k 0°8° 0°8°
L 0.40 1.27 0.0157 0.0500
L1 1.04 0.0410
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Package mechanical data
Doc ID 16891 Rev 26 35/44
Figure 17. TSSOP8 – 8 lead thin shrink small outline, package outline
1. Drawing is not to scale.
Table 21. TSSOP8 – 8 lead thin shrink small outline, package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
Package mechanical data M24C64-DF, M24C64-W, M24C64-R, M24C64-F
36/44 Doc ID 16891 Rev 26
Figure 18. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline
1. Drawing is not to scale.
2. The central pad (E2 × D2 area in the above illustration) is internally pulled to VSS. It must not be allowed to
be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 22. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 0.550 0.450 0.600 0.0217 0.0177 0.0236
A1 0.020 0.000 0.050 0.0008 0.0000 0.0020
b 0.250 0.200 0.300 0.0098 0.0079 0.0118
D 2.000 1.900 2.100 0.0787 0.0748 0.0827
D2 (rev MB) 1.600 1.500 1.700 0.0630 0.0591 0.0669
D2 (rev MC) 1.200 1.600 0.0472 0.0630
E 3.000 2.900 3.100 0.1181 0.1142 0.1220
E2 (rev MB) 0.200 0.100 0.300 0.0079 0.0039 0.0118
E2 (rev MC) 1.200 1.600 0.0472 0.0630
e 0.500 0.0197
K 0.300 0.0118
L 0.300 0.500 0.0118 0.0197
L1 0.150 0.0059
L3 0.300 0.0118
eee(2)
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
0.080 0.0031
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M24C64-DF, M24C64-W, M24C64-R, M24C64-F Package mechanical data
Doc ID 16891 Rev 26 37/44
Figure 19. WLCSP-R 5-bump wafer-length chip-scale package outline
1. Drawing is not to scale.
2. The index on the wafer back side (circle) is above the index of the bump side (triangle/arrow).
Table 23. WLCSP-R 5-bump wafer-length chip-scale package mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to four decimal digits.
Typ Min Max Typ Min Max
A 0.545 0.490 0.600 0.0215 0.0193 0.0236
A1 0.190 0.0075
A2 0.355 0.0140
b(2)
2. Dimension measured at the maximum bump diameter parallel to primary datum Z.
0.270 0.0106
D 0.959 1.074 0.0378 0.0423
E 1.073 1.168 0.0422 0.0460
e 0.693 0.0273
e1 0.400 0.0157
e2 0.3465 0.0136
F 0.280 0.0110
G 0.190 0.0075
N (number of terminals) 5 5
aaa 0.110 0.0043
eee 0.060 0.0024
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Part numbering M24C64-DF, M24C64-W, M24C64-R, M24C64-F
38/44 Doc ID 16891 Rev 26
9 Part numbering
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 24. Ordering information scheme
Example: M24C64-D W MN 6 T P /P
Device type
M24 = I2C serial access EEPROM
Device function
C64 = 64 Kbit (8192 x 8)
Device family
Blank: Without Identification page
-D: With additional Identification page
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
Package
BN = PDIP8(1)
1. ECOPACK1® (RoHS-compliant).
MN = SO8 (150 mil width)(2)
2. ECOPACK2® (RoHS-compliant and halogen-free).
DW = TSSOP8 (169 mil width)(2)
MB or MC = UFDFPN8 (MLP8)
CS = WLCSP-R
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
5 = Consumer: device tested with standard test flow over –20 to 85°C
3 = Device tested with high reliability certified flow(3) automotive
temperature range (-40 to 125 °C)
3. ST strongly recommends the use of Automotive Grade devices for use in an automotive environment. The
high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest
ST sales office for a copy.
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(4)
4. Process letter is used only for device grade 3 and WLCSP packages.
P = F6DP26% Chartered
K = F8H process
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Revision history
Doc ID 16891 Rev 26 39/44
10 Revision history
Table 25. Document revision history
Date Revision Changes
22-Dec-1999 2.3 TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,
PackageMechData).
28-Jun-2000 2.4 TSSOP8 package data corrected
31-Oct-2000 2.5
References to Temperature Range 3 removed from Ordering Information
Voltage range -S added, and range -R removed from text and tables
throughout.
20-Apr-2001 2.6
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data
updated
16-Jan-2002 2.7
Test condition for ILI made more precise, and value of ILI for E2-E0 and
WC added
-R voltage range added
02-Aug-2002 2.8
Document reformatted using new template.
TSSOP8 (3x3mm² body size) package (MSOP8) added.
5ms write time offered for 5V and 2.5V devices
04-Feb-2003 2.9 SO8W package removed. -S voltage range removed
27-May-2003 2.10 TSSOP8 (3x3mm² body size) package (MSOP8) removed
22-Oct-2003 3.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to -0.45V.
01-Jun-2004 4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices.
Device Grade clarified
04-Nov-2004 5.0
Product List summary table added. Device Grade 3 added. 4.5-5.5V
range is Not for New Design. Some minor wording changes. AEC-Q100-
002 compliance. tNS(max) changed. VIL(min) is the same on all input
pins of the device. ZWCL changed.
05-Jan-2005 6.0 UFDFPN8 package added. Small text changes.
Revision history M24C64-DF, M24C64-W, M24C64-R, M24C64-F
40/44 Doc ID 16891 Rev 26
29-Jun-2006 7
Document converted to new ST template.
M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.
M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.
Section 2.3: Chip Enable (E2, E1, E0) and Section 2.4: Write Control
(WC) modified, Section 2.6: Supply voltage (VCC) added and replaces
Power On Reset: VCC Lock-Out Write Protect section.
TA added, Note 1 updated and TLEAD specified for PDIP packages in
Table 6: Absolute maximum ratings.
ICC0 added, ICC voltage conditions changed and ICC1 specified over the
whole voltage range in Table 24: DC characteristics (M24xxx-W, device
grade 6).
ICC0 added, ICC frequency conditions changed and ICC1 specified over
the whole voltage range in Table 26: DC characteristics (M24xxx-R -
device grade 6).
tW modified in Table 28: AC characteristics.
SO8N package specifications updated (see Figure 16 and Ta bl e 2 0).
Device grade 5 added, B and P Process letters added to Ta bl e 2 4 :
Ordering information scheme. Small text changes.
03-Jul-2006 8
ICC1 modified in Table 24: DC characteristics (M24xxx-W, device grade
6).
Note 1 added to Table 27: DC characteristics (M24xxx-F) and table title
modified.
17-Oct-2006 9
UFDFPN8 package specifications updated (see Ta b le 2 1 ). M24128-BW-
and M24128-BR part numbers added.
Generic part number corrected in Features on page 1.
ICC0 corrected in Ta b le 2 5 and Ta bl e 2 4 .
Packages are ECOPACK® compliant.
27-Apr-2007 10
Available packages and temperature ranges by product specified in
Ta bl e 2 2 , Ta b l e 2 4 and Tab l e 2 5 .
Notes modified below Table 23: Input parameters.
VIH max modified in DC characteristics tables (see Ta b l e 2 4 , Ta b l e 2 5 ,
Ta bl e 2 6 and Ta b l e 2 7 ).
C process code added to Table 24: Ordering information scheme.
For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007
on, tW will be 5 ms (see Table 28: AC characteristics.
27-Nov-2007 11
Small text changes. Section 2.5: VSS ground and Section 4.9: ECC
(error correction code) and write cycling added.
VIL and VIH modified in Table 26: DC characteristics (M24xxx-R - device
grade 6).
JEDEC standard reference updated below Table 6: Absolute maximum
ratings.
Package mechanical data inch values calculated from mm and rounded
to 4 decimal digits (see Section 8: Package mechanical data).
Table 25. Document revision history (continued)
Date Revision Changes
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Revision history
Doc ID 16891 Rev 26 41/44
18-Dec-2007 12
Added Section 2.6.2: Power-up conditions, updated Section 2.6.3:
Device reset, and Section 2.6.4: Power-down conditions in Section 2.6:
Supply voltage (VCC).
Updated Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value
versus bus parasitic capacitance (Cbus).
Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6,
respectively, in Section 4.9: ECC (error correction code) and write
cycling.
Added temperature grade 6 in Table 21: Operating conditions (M24xxx-
F).
Updated test conditions for ILO and VLO in Table 24: DC characteristics
(M24xxx-W, device grade 6), Table 25: DC characteristics (M24xxx-W,
device grade 3), and Table 26: DC characteristics (M24xxx-R - device
grade 6).
Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V ≤
VCC < 2.5 V and 2.5 V ≤ VCC < 5.5 V in Table 27: DC characteristics
(M24xxx-F).
Updated Table 28: AC characteristics, and Table 17: AC characteristics
(M24xxx-F).
Updated Figure 14: AC waveforms.
Added M24128-BF in Table 25: Available M24C32 products (package,
voltage range, temperature grade).
Process B removed fromTable 24: Ordering information scheme.
30-May-2008 13
Small text changes.
C Process option and Blank Plating technology option removed from
Table 24: Ordering information scheme.
15-Jul-2008 14
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 8: Package
mechanical data). Section 4.9: ECC (error correction code) and write
cycling updated.
16-Sep-2008 15
IOL added to Table 6: Absolute maximum ratings.
Table 24: Available M24C32 products (package, voltage range,
temperature grade) and Table 25: Available M24C32 products (package,
voltage range, temperature grade) updated.
05-Jan-2009 16
I2C modes supported specified in Features on page 1.
Note removed from Table 27: DC characteristics (M24xxx-F). Small text
changes.
Table 25. Document revision history (continued)
Date Revision Changes
Revision history M24C64-DF, M24C64-W, M24C64-R, M24C64-F
42/44 Doc ID 16891 Rev 26
10-Dec-2009 17
32 and 128 Kbit densities removed.
ECOPACK status of packages specified on page 1 and in Ta bl e 2 4:
Ordering information scheme.
Section 2.6.2: Power-up conditions updated.
Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) updated. ECC section removed.
tNS modified in Table 23: Input parameters.
ICC1 and VIH updated in Table 24: DC characteristics (M24xxx-W, device
grade 6), Table 25: DC characteristics (M24xxx-W, device grade 3),
Table 26: DC characteristics (M24xxx-R - device grade 6) and Tab l e 27 :
DC characteristics (M24xxx-F). Note added to Table 26: DC
characteristics (M24xxx-R - device grade 6).
Table 28: AC characteristics modified.
Figure 14: AC waveforms modified.
Note added below Figure 18: UFDFPN8 (MLP8) – 8-lead ultra thin fine
pitch dual flat package no lead 2 × 3mm, package outline.
Small text changes.
05-Feb-2010 18 Number of bytes changed for Page Write in Table 5: Operating modes.
15-Sep-2010 19
Updated tables (process letter K) under Section 6:
–Ta b le 6 : ESD HBM passes 3000 V
Updated tables (process letter K) under Section 7:
–Ta b l e 1 8 (1MHz AC) inserted,
–Ta b l e 1 7 , Ta b l e 1 8 : Tclqv(min) = 100 ns
–Ta b l e 1 7 , Ta b l e 1 8 : tNS = 80 ns
16-Nov-2010 20
Added M24C64-DF device.
Updated Features, Section 1: Description, Section 4: Device operation.
Changed title of Figure 2: 8-pin package connections.
Updated Table 10: AC test measurement conditions.
Replaced Figure 18: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual
flat package no lead 2 × 3mm, package outline and Table 21: UFDFPN8
(MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm,
data.
Added Table 29: M24C32-D product (package, voltage range,
temperature grade).
08-Dec-2010 21
Added WLCSP in Features and Figure 4: WLCSP connections (top
view).
Updated Table 22: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat
package no lead 2 x 3 mm, data.
Updated Table 26: Available M24C32 products (package, voltage range,
temperature grade) and Table 29: M24C32-D product (package, voltage
range, temperature grade).
14-Mar-2011 22
Updated information concerning E2, E1, E0 for the WLCSP package:
– note under Figure 3: WLCSP connections (top view)
– comment under Figure 4: Device select code
– note (3) under Table 2: Device select code
Table 25. Document revision history (continued)
Date Revision Changes
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Revision history
Doc ID 16891 Rev 26 43/44
07-Apr-2011 23 Updated MLP8 package data and Section 9: Part numbering.
Added footnote (a) in Section 4.5: Memory addressing.
18-May-2011 24
Updated:
–Figure 3: WLCSP connections (top view)
–Table 6: Absolute maximum ratings
–Small text changes
Added:
–Figure 12: Memory cell characteristics
08-Sep-2011 25
Updated:
–Table 22: UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat
package no lead 2 x 3 mm, data
–Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
–Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value
versus bus parasitic capacitance (Cbus).
Added tWLDL and tDHWH in:
–Table 17: 400 kHz AC characteristics
–Table 18: 1 MHz AC characteristics
–Figure 14: AC waveforms
Minor text changes.
16-Dec-2011 26 Updated A dimension in Table 23: WLCSP-R 5-bump wafer-length chip-
scale package mechanical data.
Table 25. Document revision history (continued)
Date Revision Changes
M24C64-DF, M24C64-W, M24C64-R, M24C64-F
44/44 Doc ID 16891 Rev 26
Please Read Carefully:
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