LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-
LVDS FANOUT BUFFER
ICS889832
IDT™ / ICS™ LVDS FANOUT BUFFER 1 ICS889832AK REV. A OCTOBER 21, 2008
GENERAL DESCRIPTION
The ICS889832 is a high speed 1-to-4 Differential-
to-LVDS Fanout Buffer and is a member of the
HiPerClockS™ family of high performance clock
solutions from IDT. The ICS889832 is optimized
for high speed and very low output skew, making
it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The
internally terminated differential input and VREF_AC pin allow
other differential signal families such as LVPECL, LVDS, and
SSTL to be easily interfaced to the input with minimal use of
external components. The device also has an output enable
pin which may be useful for system test and debug purposes.
The ICS889832 is packaged in a small 3mm x 3mm 16-pin
VFQFN package which makes it ideal for use in space-
constrained applications.
FEATURES
•Four differential LVDS outputs
•IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, SSTL
•50Ω internal input termination to VT
•Output frequency: >2GHz
•Output skew: 25ps (maximum)
•Part-to-part skew: 200ps (maximum)
•Additive phase jitter, RMS: <0.2ps (typical)
•Propagation delay: 510ps (maximum)
•2.5V operating supply
•-40°C to 85°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM PIN ASSIGNMENT
HiPerClockS™
ICS
IN
VT
nIN
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
VREF_AC ICS889832
16-Lead VFQFN
3mm x 3mm x 0.925 package body
K Package
Top View
Q1
nQ1
Q2
nQ2
IN
VT
VREF_AC
nIN
Q3
nQ3
V DD
EN
nQ0
Q0
VDD
GND
1
2
3
4
12
11
10
9
5 6 7 8
16 15 14 13
50Ω
50Ω
DQ
EN
IDT™ / ICS™ LVDS FANOUT BUFFER 2 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
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R
PULLUP
rotsiseRpulluPtupnI 73kΩ
rebmuNemaNepyTnoitpircseD
2,11Qn,1QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
4,32Qn,2QtuptuO.slevelecafr
etniSDVL.riaptuptuolaitnereffiD
6,53Qn,3QtuptuO.slevelecafretniSDVL.riaptuptuolaitnereffiD
41,7V
DD
rewoP.snipylppusevitisoP
8NEtupnIpulluP
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tupnI.stupni
NItanoitisnartWOLtxenehtnoHGIHoglliwstuptuo
Vsidlohserht
DD
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egdegnillafehtnodekcolcsihctallanretniehT.gnitaolftfel
nehwHGIH
.slevelecafretniSOMCVL/LTTVL.NIlangistupniehtfo
9NIntupnI05.tupnikcolclaitnereffidgnitrevnI ΩVotno
itanimrettupnilanretni
T
.
01V
CA_FER
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T
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T
.
31DNGrewoP.dnuorgylppusrewoP
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:ETON
pulluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
IDT™ / ICS™ LVDS FANOUT BUFFER 3 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 3A. CONTROL INPUT FUNCTION TABLE
TABLE 3B. TRUTH TABLE
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NE3Q:0Q3Qn:0Qn
0WOL;delbasiDHGIH;delbasiD
1delbanEdelbanE
delbanerodelbasiderastuptuokcolceht,sehct
iwsNEretfA
ninwohssaegdekcolctupnignillafagniwollof
rugiF
e
.1
FIGURE 1. EN TIMING DIAGRAM
EN
nIN
IN
nQx
Qx
stupnIstuptuO
NINInNE3Q:0Q3Qn:0Qn
01101
10 1 10
XX00
)1ETON(
1
)1ETON(
.)NI(langistupniehtfonoitisnartevitagentxennO:1ETON
←→ t
PD
t
S
t
H
V
OUT
Swing
V
DD
/2V
DD
/2
V
IN
IDT™ / ICS™ LVDS FANOUT BUFFER 4 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, IO (LVDS)
Continuous Current 10mA
Surge Current 15mA
Input Current, IN, nIN ±50mA
VT Current, IVT ±100mA
Input Sink/Source, IREF_AC ± 0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 88.5°C/W (0 mps)
(Junction-to-Ambient)
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C
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DD
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I
DD
tnerruCylppuSrewoP 021Am
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
egatloVhgiHtupnI 7.1V
DD
3.0+V
V
LI
egatloVwoLtupnI 07.0V
I
HI
tnerruChgiHtupnINEV
DD
V=
NI
V526.2=5Aµ
I
LI
tnerruCwoLtupnINEV
DD
V,V526.2=
NI
V0=051-Aµ
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R
NI
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HI
51.0-V
V
NI
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V
CA_FER
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DD
24.1-V
DD
73.1-V
DD
23.1-V
V
NI_FFID
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IDT™ / ICS™ LVDS FANOUT BUFFER 5 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C
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F
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t
S
emiTputeSelbanEkcolCNIn,NIotNE003sp
t
H
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.stniopssorclaitnereffidehtta
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V
DO
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V
DO
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V
SO
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ΔV
SO
V
SO
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IDT™ / ICS™ LVDS FANOUT BUFFER 6 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 200MHz
(12kHz to 20MHz) = <0.2ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k 10k 100k 1M 10M 100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB PHASE NOISE dBc/HZ
IDT™ / ICS™ LVDS FANOUT BUFFER 7 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME PROPAGATION DELAY
GND
nIN
VDD
IN
SCOPE
Qx
nQx
LVDS
2.5V±5%
POWER SUPPLY
+–
Float GND
t
sk(pp)
t
sk(o)
nQx
Qx
nQy
Qy
PA RT 1
PA RT 2
nQx
Qx
nQy
Qy
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
OD
tPD
nIN
Q0:Q3
nQ0:nQ3
IN
V
IH
Cross Points
V
IN
V
IL
VDD
IDT™ / ICS™ LVDS FANOUT BUFFER 8 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
SETUP & HOLD TIME
t
HOLD
t
SET-UP
nIN
IN
EN
V
IN
, V
OUT
400mV
(typical)
V
DIFF_IN
, V
DIFF_OUT
800mV
(typical)
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
OFFSET VOLTAGE SETUP
➤
➤
➤
100
out
out
LVDS
DC Input VOD/Δ VOD
VDD
out
out
LVDS
DC Input
➤
➤
➤
V
OS
/Δ V
OS
V
DD
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT™ / ICS™ LVDS FANOUT BUFFER 9 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
APPLICATION INFORMATION
LVPECL INPUT WITH BUILT-IN 50ΩΩ
ΩΩ
Ω T ERMINATIONS INTERFACE
The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL,
LVHSTL, CML, SSTL and other differential signals. Both VSWING
and VOH must meet the VPP and VCMR input requirements.
Figures
1A to 1f
show interface examples for the HiPerClockS IN/nIN
input with built-in 50Ω terminations driven by the most common
driver types. The input interfaces suggested here are examples
only. If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50ΩΩ
ΩΩ
Ω
DRIVEN BY AN LVDS DRIVER
FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50ΩΩ
ΩΩ
Ω
DRIVEN BY AN LVPECL DRIVER
IN
nIN
VT
2.5V
LVDS
3.3V or 2.5V
Zo = 50 Ohm
Zo = 50 Ohm
Receiver
With
Built-In
50 Ohm
Zo = 50 Ohm
Receiver
With
Built-In
50 Ohm
Zo = 50 Ohm
IN
nIN
VT
2.5V2.5V
R1
18
2.5V LVPECL
FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50ΩΩ
ΩΩ
Ω
FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50ΩΩ
ΩΩ
Ω
DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50ΩΩ
ΩΩ
Ω
DRIVEN BY A CML DRIVER WITH
BUILT-IN 50ΩΩ
ΩΩ
Ω PULLUP
Zo = 50 Ohm
2.5V
Zo = 50 Ohm
IN
nIN
VT
Receiver
With
Built-In
50 Ohm
2.5V
CML - Open Collector
IN
nIN
VT
Receiver
With
Built-In
50 Ohm
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
CML - Built-in 50 Ohm Pull-up
2.5V
FIGURE 1F. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50ΩΩ
ΩΩ
Ω
DRIVEN BY A 3.3V CML DRIVER WITH
BUILT-IN PULLUP
2.5V
3.3V
Receiver with Built-In 50Ω
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
IN
VT
nIN
REF_AC
50 Ohm
50 Ohm
3.3V LVPECL
R5
100 - 200 Ohm
R5
100 - 200 Ohm
2.5V
3.3V
Receiver with Built-In 50Ω
Zo = 50 Ohm
Zo = 50 Ohm
C1
C2
IN
VT
nIN
REF_AC
50 Ohm
50 Ohm
3.3V CML with
Built-In Pullup
IDT™ / ICS™ LVDS FANOUT BUFFER 10 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
OUTPUTS:
LVDS Outputs
All unused LVDS outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
2.5V LVDS DRIVER T ERMINATION
Figure 2
shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
2.5V
100 Ohm Differential Transmission Line
2.5V
LVDS_Driv er
R1
100
+
-
100ΩΩ
ΩΩ
Ω Differential Transmission Line
transmission line environment. For buffer with multiple LDVS
driver, it is recommended to terminate the unused outputs.
IDT™ / ICS™ LVDS FANOUT BUFFER 11 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
FIGURE 3. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
VFQFN EPAD THERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in
Figure 3.
The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”)
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the
Surface Mount Assembly
of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
THERMAL VIA
LAND PATTERN
SOLDER PIN
SOLDER
PIN PADPIN PAD
PIN
GROUND PLANE
EXPOSED HEAT SLUG
(GROUND PAD)
IDT™ / ICS™ LVDS FANOUT BUFFER 12 ICS889832AK REV. A OCTOBER 21, 2008
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS889832.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS889832 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
•Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 120mA = 315mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 88.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.315W * 88.5°C/W = 112.9°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 16-PIN VFQFN, FORCED CONVECTION
θθ
θθ
θJA vs. 0 Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 88.5°C/W 77.3°C/W 69.4°C/W
IDT™ / ICS™ LVDS FANOUT BUFFER 13 ICS889832AK REV. A OCTOBER 21, 2008
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LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS889832 is: 206
Pin compatible with SY89832U
TABLE 7. θ
JAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
θθ
θθ
θJA vs. 0 Air Flow (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 88.5°C/W 77.3°C/W 69.4°C/W
IDT™ / ICS™ LVDS FANOUT BUFFER 14 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
Reference Document: JEDEC Publication 95, MO-220
NOITAIRAVCEDEJ
SRETEMILLIMNISNOISNEMIDLLA
LOBMYSMUMINIMMUMIXAM
N61
A08.00.1
1A 050.0
3A ecnerefeR52.0
b81.003.0
eCIS
AB05.0
N
D
4
N
E
4
D0.3
2D 0.18.1
E0.3
2E 0.18.1
L03.005.0
Top View
Index
A
rea
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singulation
A
0. 08 C
C
A3
A1
Seating Plan
e
E2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N& N
Odd
1
2
e
2
(Typ.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Thermal
Base
N
OR
DE
DDE
DE
E
IDT™ / ICS™ LVDS FANOUT BUFFER 15 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
TABLE 9. ORDERING INFORMATION
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FLKA238988 LA23NFQFV"eerF-daeL"daeL61ebutC°58otC°04-
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IDT™ / ICS™ LVDS FANOUT BUFFER 16 ICS889832AK REV. A OCTOBER 21, 2008
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
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4
11
21
31
41
51
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80/03/1
ICS889832
LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
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