ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS889832 is a high speed 1-to-4 DifferentialICS to-LVDS Fanout Buffer and is a member of the HiPerClockSTM HiPerClockSTM family of high performance clock solutions from IDT. The ICS889832 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF _AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889832 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in spaceconstrained applications. * Four differential LVDS outputs * IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, SSTL * 50 internal input termination to VT * Output frequency: >2GHz * Output skew: 25ps (maximum) * Part-to-part skew: 200ps (maximum) * Additive phase jitter, RMS: <0.2ps (typical) * Propagation delay: 510ps (maximum) * 2.5V operating supply * -40C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 16 15 14 13 12 IN nQ0 nQ1 2 11 VT Q2 3 10 VREF_AC nQ2 4 Q2 EN 7 8 nIN ICS889832 nQ2 D 6 EN 50 nIN 9 5 VDD nQ1 nQ3 50 VREF_AC GND Q1 1 Q1 VT VDD Q0 Q3 IN Q0 PIN ASSIGNMENT nQ0 BLOCK DIAGRAM 16-Lead VFQFN 3mm x 3mm x 0.925 package body K Package Top View Q Q3 nQ3 IDT TM / ICSTM LVDS FANOUT BUFFER 1 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q1, nQ1 Output Type Description 3, 4 Q2, nQ2 Output Differential output pair. LVDS interface levels. 5, 6 Q3, nQ3 Output Differential output pair. LVDS interface levels. 7, 14 VDD Power 8 EN Input 9 nIN Input Positive supply pins. Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VDD/2V. Includes a 37k pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels. Inver ting differential clock input. 50 internal input termination to VT. 10 VREF_AC Output Differential output pair. LVDS interface levels. Pullup Reference voltage for AC-coupled applications. 11 VT Input Termination input. 12 IN Input Non-inver ting differential clock input. 50 internal input termination to VT. 13 GND Power Power supply ground. 15, 16 Q0, nQ0 Output Differential output pair. LVDS interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLUP Input Pullup Resistor IDT TM / ICSTM LVDS FANOUT BUFFER Test Conditions Minimum Typical 37 2 Maximum Units k ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Input Outputs EN Q0:Q3 nQ0:nQ3 0 Disabled; LOW Disabled; HIGH 1 Enabled Enabled After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. EN VDD/2 VDD/2 tS tH nIN IN nQx VIN tPD VOUT Swing Qx FIGURE 1. EN TIMING DIAGRAM TABLE 3B. TRUTH TABLE Inputs IN nI N Outputs EN Q0:Q3 nQ0:nQ3 0 1 1 0 1 1 0 1 1 0 X X 0 0(NOTE1) 1(NOTE1) NOTE 1: On next negative transition of the input signal (IN). IDT TM / ICSTM LVDS FANOUT BUFFER 3 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute 4.6V Maximum Ratings may cause permanent damage to the Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA those listed in the DC Characteristics or AC Characteristics is not Input Current, IN, nIN 50mA tended periods may affect product reliability. VT Current, IVT 100mA Input Sink/Source, IREF_AC 0.5mA Operating Temperature Range, TA -40C to +85C Storage Temperature, TSTG -65C to 150C Package Thermal Impedance, JA 88.5C/W (0 mps) device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond implied. Exposure to absolute maximum rating conditions for ex- (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 120 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current EN VDD = VIN = 2.625V IIL Input Low Current EN VDD = 2.625V, VIN = 0V Minimum Typical Maximum Units 1.7 VDD + 0.3 V 0 0.7 V 5 A -150 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C Symbol Parameter RIN Differential Input Resistance (IN, nIN) Test Conditions Minimum Typical Maximum Units IN-to-VT 40 50 60 VIH Input High Voltage (IN, nIN) 1.2 VDD V VIL Input Low Voltage (IN, nIN) 0 VIH - 0.15 V VIN Input Voltage Swing 0.15 2.8 V VREF_AC Reference Voltage VDIFF_IN Differential Input Voltage Swing IIN Input Current; NOTE 1 VDD - 1.42 0.3 (IN, nIN) VDD - 1.37 VDD - 1.32 V 3.4 V 35 mA NOTE 1: Guaranteed by design. IDT TM / ICSTM LVDS FANOUT BUFFER 4 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 0.3 0.4 0.5 mV 50 mV 1 1.25 1.5 V 50 mV Maximum Units TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 5%; TA = -40C TO 85C Symbol Parameter fMAX Maximum Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 t PD t sk(o) t sk(pp) t jit Condition Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Minimum Typical >2 275 Integration Range: 12kHz - 20MHz 390 GHz 510 ps 25 ps 200 ps <0.2 ps tR/tF Output Rise/Fall Time tS Clock Enable Setup Time EN to IN, nIN 300 ps tH Clock Enable Hold Time EN to IN, nIN 300 ps 20% to 80% 70 150 235 ps All parameters are measured at 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT TM / ICSTM LVDS FANOUT BUFFER 5 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz 0 -10 Additive Phase Jitter @ 200MHz (12kHz to 20MHz) = <0.2ps (typical) -20 -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT TM / ICSTM LVDS FANOUT BUFFER 6 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD SCOPE Qx VDD 2.5V5% POWER SUPPLY + Float GND - nIN LVDS V Cross Points IN V IH IN nQx V IL GND OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nIN 80% 80% IN VOD Clock Outputs 20% 20% tR nQ0:nQ3 tF Q0:Q3 tPD OUTPUT RISE/FALL TIME IDT TM / ICSTM LVDS FANOUT BUFFER PROPAGATION DELAY 7 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER nIN IN t HOLD EN VDIFF_IN, VDIFF_OUT 800mV (typical) t SET-UP SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING SETUP & HOLD TIME VDD VDD 100 out VOD/ VOD LVDS out DC Input LVDS out DC Input VIN, VOUT 400mV (typical) out VOS/ VOS DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT TM / ICSTM LVDS FANOUT BUFFER OFFSET VOLTAGE SETUP 8 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER APPLICATION INFORMATION TERMINATIONS INTERFACE LVPECL INPUT WITH BUILT-IN 50 The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 1A to 1f show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven by the most common 3.3V or 2.5V driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN Receiver With Built-In 50 Ohm LVDS Receiver With Built-In 50 Ohm 2.5V LVPECL R1 18 FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER 2.5V VT Zo = 50 Ohm nIN FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN CML - Open Collector VT Zo = 50 Ohm nIN Receiver With Built-In 50 Ohm CML - Built-in 50 Ohm Pull-up Receiver With Built-In 50 Ohm FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH PULLUP BUILT-IN 50 FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER 2.5V 2.5V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 3.3V CML with Built-In Pullup IN Zo = 50 Ohm C1 IN 50 Ohm 50 Ohm VT Zo = 50 Ohm C2 VT 50 Ohm Zo = 50 Ohm nIN R5 100 - 200 Ohm REF_AC Receiver with Built-In 50 Receiver with Built-In 50 FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 IDT TM / ICSTM LVDS FANOUT BUFFER 50 Ohm nIN REF_AC R5 100 - 200 Ohm C2 FIGURE 1F. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A 3.3V CML DRIVER WITH BUILT-IN PULLUP 9 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVDS Outputs All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 2.5V LVDS DRIVER TERMINATION transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. Figure 2 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Line Differential 100 Differential Transmission Transmission Line FIGURE 2. TYPICAL LVDS DRIVER TERMINATION IDT TM / ICSTM LVDS FANOUT BUFFER 10 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER VFQFN EPAD THERMAL RELEASE PATH are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/ slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/ Electrically Enhance Leadfame Base Package, Amkor Technology. In order to maximize both the removal of heat from the package and the electrical perfor mance, a land patter n must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 3. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 3. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH -SIDE VIEW (DRAWING NOT TO SCALE) IDT TM / ICSTM LVDS FANOUT BUFFER 11 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS889832. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS889832 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. * Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 120mA = 315mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 88.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.315W * 88.5C/W = 112.9C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 16-PIN VFQFN, FORCED CONVECTION JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT TM / ICSTM LVDS FANOUT BUFFER 12 0 1 2.5 88.5C/W 77.3C/W 69.4C/W ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN JA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 88.5C/W 77.3C/W 69.4C/W TRANSISTOR COUNT The transistor count for ICS889832 is: 206 Pin compatible with SY89832U IDT TM / ICSTM LVDS FANOUT BUFFER 13 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN (Ref.) Seating Plane (R ef.) A1 Index Area ND & NE Even (ND-1)x e L A3 N N 1 Anvil Singula tion e (Typ.) 2 If ND & NE are Even 2 OR E2 (NE -1)x e (Re f.) E2 2 Top View b A (Ref.) D e ND & NE Odd 0. 08 Chamfer 4x 0.6 x 0.6 max OPTIONAL C D2 2 Thermal Base D2 C TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM 16 N A 0.80 A1 0 1.0 0.05 0.25 Reference A3 b MAXIMUM 0.18 0.30 e 0.50 BASIC ND 4 NE 4 D 3.0 D2 1.0 1.8 3.0 E E2 1.0 1.8 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT TM / ICSTM LVDS FANOUT BUFFER 14 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number 889832AK Marking Package Shipping Packaging Temperature 832A 16 Lead VFQFN tube -40C to 85C 889832AKT 832A 16 Lead VFQFN 2500 tape & reel -40C to 85C 889832AKLF 32AL 16 Lead "Lead-Free" VFQFN tube -40C to 85C 889832AKLFT 32AL 16 Lead "Lead-Free" VFQFN 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM LVDS FANOUT BUFFER 15 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER REVISION HISTORY SHEET Rev A A Table T8 T9 T6 T7 T9 Page 13 14 4 11 12 13 14 15 Description of Change Package Dimensions - corrected D2/E2 mimimum from 0.25mm to 1.0mm. Ordering Information table - added lead-free marking. Absolute Maximum Ratings - updated Package Thermal Impedance. Updated VFQFN Thermal Release Path section. Updated Thermal Resistance Table and Junction Temperature calculation. Updated Reliability Information. Updated Package Outline. Corrected Lead-Free Par t/Order Number. IDT TM / ICSTM LVDS FANOUT BUFFER 16 Date 1/22/07 1/30/08 ICS889832AK REV. A OCTOBER 21, 2008 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Japan Asia Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) NIPPON IDT KK Sanbancho Tokyu Bld. 7F, 8-1 Sanbancho Chiyoda-ku, Tokyo 102-0075 +81 3 3221 9822 +81 3 3221 9824 (fax) Integrated Device Technology IDT (S) Pte. Ltd. 1 Kallang Sector, #07-01/06 Kolam Ayer Industrial Park Singapore 349276 +65 6 744 3356 +65 6 744 1764 (fax) IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 +44 (0) 1372 378851 (fax) (c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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