Dual 1:5 Differential Clock/Data Fanout Buffe
r
FastEdge™ Series
CY2PP3210
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-07508 Rev.*C Revised July 28, 2004
Features
• Dual sets of five ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 500 ps propagation delay (typical)
• 0.8 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.2 GHz max. toggle frequency)
• PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%
with VEE = 0V
• ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5%
with VCC = 0V
• Industrial temperature range: –40°C to 85°C
• 32-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6210
Functional Description
The CY2PP3210 is a low-skew, low propagation delay dual
1-to-5 differential fanout buffer targeted to meet the require-
ments of high-performance clock and data distribution applica-
tions. The device is implemented on SiGe technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to 1.5
GHz.
The device features two differential input paths that are differ-
ential internally. The CY2PP3210 may function not only as a
differential clock buffer but also as a signal-level translator and
fanout distributing a single-ended signal. An external bias pin,
VBB, is provided for this purpose. In such an application, the
VBB pin should be connected to either one of the CLKA# or
CLKB# inputs and bypassed to ground via a 0.01-µF capacitor.
Traditionally, in ECL, it is used to provide the reference level
to a receiving single-ended input that might have a differential
bias point.
Since the CY2PP3210 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP3210 delivers consistent performance
over various platforms.
Block Diagram Pin Configuration
CY2PP3210
VCC
QA0
QA0#
QA1
QA1#
QA2
QA2#
VCC
VCC
QB4#
QB4
QB3#
QB3
QB2#
QB2
VCC
QA3
QA3#
QA4
QA4#
QB0
QB0#
QB1
QB1#
VCC
NC
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
QB0
QB0#
QB1
QB1#
QB3
QB3#
QB4
QB4#
QB2
QB2#
CLKB
CLKB#
VCC
QA0
QA0#
QA1
QA1#
QA2
QA2#
QA3
QA3#
QA4
QA4#
CLKA
CLKA#
VCC
VBB
VEE
VEE
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 2 of 9
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP3210. The agency name and relevant specification is
listed below in Ta b l e 2 .
Pin Definitions[1, 2, 3]
Pin Name I/O[1] Type Description
2NCNo connect.
3 CLKA, I,PD ECL/PECL ECL/PECL Differential Input Clocks.
4 CLKA# I,PD/PU ECL/PECL ECL/PECL Differential Input Clocks.
5 VBB[3] OBiasReference Voltage Output.
6 CLKB, I,PD ECL/PECL ECL/PECL Differential Input Clocks.
7 CLKB# I,PD/PU ECL/PECL ECL/PECL Differential Input Clocks.
8 VEE[2] –PWR Power Negative Supply.
1,9,16,25,32 VCC +PWR Power Positive Supply.
31,29,27,24,22 QA(0:4) O ECL/PECL True output
30,28,26,23,21 QA#(0:4) O ECL/PECL Complement output
20,18,15,13,11 QB(0:4) O ECL/PECL True output
19,17,14,12,10 QB#(0:4) O ECL/PECL Complement output
Table 1.
Agency Name Specification
JEDEC JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec 883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), VEE is either –3.3V or –2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode),
VEE is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC)
and are between VCC and VEE.
3. VBB is available for use for single-ended bias mode for |3.3V| supplies (not |2.5V|).
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 3 of 9
Absolute Maximum Ratings
Parameter Description Condition Min. Max. Unit
VCC Positive Supply Voltage Non-Functional –0.3 4.6 V
VEE Negative Supply Voltage Non-Functional -4.6 0.3 V
TSTemperature, Storage Non-Functional –65 +150 °C
TJTemperature, Junction Non-Functional 150 °C
ESDhESD Protection Human Body Model 2000 V
MSL Moisture Sensitivity Level 3 N.A.
Gate Count Total Number of Used Gates Assembled Die 50 gates
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter Description Condition Min. Max. Unit
IBB Output Reference Current Relative to VBB – |200| uA
LUILatch Up Immunity Functional, typical 100 mA
TATemperature, Operating Ambient Functional –40 +85 °C
ØJc Dissipation, Junction to Case Functional 29[4] °C/W
ØJa Dissipation, Junction to Ambient Functional 76[4] °C/W
IEE Maximum Quiescent Supply Current VEE pin[5] –130mA
CIN Input pin capacitance – 3 pF
LIN Pin Inductance 1nH
VIN Input Voltage Relative to VCC[6] –0.3 VCC + 0.3 V
VTT Output Termination Voltage Relative to VCC[6] VCC – 2 V
VOUT Output Voltage Relative to VCC[6] –0.3 VCC + 0.3 V
IIN Input Current[7] VIN = VIL, or VIN = VIH l150l uA
PECL DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VCC Operating Voltage 2.5V ± 5%, VEE = 0.0V
3.3V ± 5%, VEE = 0.0V
2.375
3.135
2.625
3.465
V
V
VCMR Differential Cross Point Voltage[8] Differential operation 1.2 VCC V
VOH Output High Voltage IOH = –30 mA[9] VCC – 1.25 VCC – 0.7 V
VOL Output Low Voltage
VCC = 3.3V ± 5%
VCC = 2.5V ± 5%
IOL = –5 mA[9]
VCC – 1.995
VCC –1.995
VCC – 1.5
VCC – 1.3
V
V
VIH Input Voltage, High Single-ended operation VCC – 1.165 VCC – 0.880 [10] V
VIL Input Voltage, Low Single-ended operation VCC – 1.945 [10] VCC – 1.625 V
VBB[3] Output Reference Voltage Relative to VCC[6] VCC – 1.620 VCC – 1.220 V
Notes:
4. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
5. Power Calculation: VCC * IEE +0.5 (IOH + IOL) (VOH – VOL) (number of differential outputs used); IEE does not include current going off chip.
6. where VCC is 3.3V±5% or 2.5V±5%
7. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
8. Refer to Figure 1
9. Equivalent to a termination of 50Ω to VTT. IOHMIN=(VOHMIN-VTT)/50; IOHMAX=(VOHMAX-VTT)/50; IOLMIN=(VOLMIN-VTT)/50; IOLMAX=(VOLMAX-VTT)/50;
10. VIL will operate down to VEE; VIH will operate up to VCC
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 4 of 9
Timing Definitions
Notes:
11. 50% duty cycle; standard load; differential operation
12. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
ECL DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VEE Negative Power Supply –2.5V ± 5%, VCC = 0.0V
–3.3V ± 5%, VCC = 0.0V
–2.625
–3.465
–2.375
–3.135
V
VCMR Differential cross point voltage[8] Differential operation VEE + 1.2 0V V
VOH Output High Voltage IOH = –30 mA[9] –1.25 –0.7 V
VOL Output Low Voltage
VEE = –3.3V ± 5%
VEE = –2.5V ± 5%
IOL = –5 mA[9]
–1.995
–1.995
–1.5
–1.3
V
VIH Input Voltage, High Single-ended operation –1.165 –0.880 [10] V
VIL Input Voltage, Low Single-ended operation –1.945 [10] –1.625 V
VBB[3] Output Reference Voltage – 1.620 – 1.220 V
AC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VPP Differential Input Voltage[8] Differential operation 0.1 1.3 V
FCLK Input Frequency 50% duty cycle Standard load 1.5 GHz
TPD Propagation Delay CLKA or CLKB to
Output pair
660 MHz [11] 280 750 ps
Vo Output Voltage (peak-to-peak; see
Figure 2) < 1 GHz 0.375
–
V
VCMRO Output Common Voltage Range (typ.) VCC – 1.425 V
tsk(0) Output-to-output Skew 660 MHz [11], See Figure 3 – 50 ps
tsk(PP) Part-to-Part Output Skew 660 MHz [11] –150ps
TPER Output Period Jitter (rms)[12] 660 MHz [11] –0.8ps
tsk(P) Output Pulse Skew[13] 660 MHz [11], See Figure 3 – 50 ps
TR,TFOutput Rise/Fall Time (see Figure 2) 660 MHz 50% duty cycle
Differential 20% to 80%
0.08 0.3 ns
VIH
VIL
VCMRVPP
VCMR Min = VEE + 1.2
VPP range
0.1V - 1.3V
VCMR Max = VCC
VCC
VEE
Figure 1. PECL/ECL Input Waveform Definitions
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 5 of 9
Test Configuration
Standard test load using a differential pulse generator and
differential measurement instrument.
tr, tf,
20-80% VO
Figure 2. ECL/LVPECL Output
Figure 3. Propagation Delay (TPD), output pulse skew (|tPLH-tPHL|), and output-to-output skew (tSK(O))
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
VO
VPP
TPD
In p u t
Clock
Output
Clock
Another
Output
Clock
TPLH,
TPHL
tS K (O )
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
VTT
RT = 50 ohm
Zo = 50 ohm
VTT
5"
5"
VTT
RT = 50 ohm
DUT
CY2PP3210 RT = 50 ohm
RT = 50 ohm
Figure 4. CY2PP318 AC Test Reference
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 6 of 9
Applications Information
Termination Examples
VTT
Zo = 50 ohm
VTT
5"
5"
CY2PP3210
RT = 50 ohm
RT = 50 ohm
VCC
VEE
Figure 5. Standard LVPECL – PECL Output Termination
VTT
Zo = 50 ohm
VTT
5"
5"
CY2PP3210
RT = 50 ohm
RT = 50 ohm
VCC
VEE
VBB (3.3V)
Fi
g
ure 6. Drivin
g
a PECL/ECL Sin
g
le-ended In
p
ut
3.3V
Zo = 50 ohm
3.3V
5"
5"
CY2PP3210
120 ohm
120 ohm
VCC =3.3V
VEE = 0V
LVDS
51 ohm
(2 places)
33 ohm
(2 places)
LVPECL to
LVDS
Figure 7. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Sig-
naling (LVDS) Interface
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 7 of 9
Figure 8. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000
Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards
and supplies.
VCC
VDD-2
YX
Z
One output is shown for clarity
Ordering Information
Part Number Package Type Product Flow
CY2PP3210AI 32-pin TQFP Industrial, –40° to 85°C
CY2PP3210AIT 32-pin TQFP – Tape and Reel Industrial, –40° to 85°C
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Drawing and Dimension
FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
Dimensions are in mm
FastEdge™ Series
CY2PP3210
Document #: 38-07508 Rev.*C Page 9 of 9
Document History Page
Document Title: CY2PP3210 FastEdge™ Series Dual 1:5 Differential Clock/Data Fanout Buffer
Document Number: 38-07508
REV. ECN NO.
Issue
Date
Orig. of
Change Description of Change
** 122396 02/12/03 RGL New Data Sheet
*A 125458 04/17/03 RGL Corrected pins 26 to 31 from Q2#, Q2, Q1#, Q1, Q0#, Q0 to QA2#, QA2,
QA1#, QA1,QA0#, QA0 in the Pin Configuration diagram
Changed pins 9, 16, 25, 32 from VCC to VCCO
Changed the title to FastEdge™ Series Dual 1:5 Differential Clock/Data
Fanout Buffer
*B 229370 See ECN RGL Supplied data to all the TBD’s to match the device
*C 247616 See ECN RGL/GGK Changed VOH and VOL to match the Char Data
