mes 1 59C | 1/12/13 Features Low Voltage and Standard Voltage Operation 5.0 V (Vcc = 4.5 V to 5.5 V) 3.0 V (Voc = 2.7 V to 5.5 V) User Selectable Internal Organization 1K: 128x8or64x 16 2K: 256 x 8 or 128 x 16 4K: 512 x 8 or 256 x 16 Four-Wire Serial Interface Self-Timed Write Cycle (10 ms Max) e High Reliability Endurance: 100,000 Cycles Data Retention: 100 Years 8-Pin PDIP and JEDEC SOIC Packages Description The ATS9C 11/12/13 provides 1024/2048/4096 bits of serial E*PROM (Electrically Eragable Programmable Read Only Memory) organized as 64/128/256 words of 16 bits each, wherithe ORG Pin is connected to Vcc and 128/256/512 words of 8 bits each when it is tied 19 grour The device is optimized for use in many industrial and commercial applications saving 8-pin PDIP and 8-pin JEDEC and SOIC packages. The AT59C 11/12/13 is enabled through the Chip Select pin (CS), a serial interface consisting of Data Input (DI), Data Output (DO), ag receiving a READ instruction at DI, the address is decoded and jhe on the data output pin DO, the WRITE cycle is completely self cycle is required before WRITE. The WRITE cycle is only eital ERASE/WRITE ENABLE state. Ready/Busy status cai programming operation by polling the Ready/Busy pin. Atmels E7PROMs are designed and tested for applications 7% Devices in this family are guaranteed for 100,000 ERASE/WR retention, The ATS9C 11/12/13 is available in 50V+ + 10% atl 2.7 V to 5.5 V versions. Data retention is specified to be greater than, 400 years. a 4- ware Upon ed out erially vec. RDY/BUSY ORG CLK Serial Data Clock GND DI Seriaf fata Input po Serial Data Output GND Ground Vcc Power Supply wo i vcc ORG Internal Organization 4 RDY/BUSY RDY/BUSY | Status Output i ORG J GND 8-Pin SOIC 8 or 256 x 16) Preliminary 2-31AImE} Absolute Maximum Ratings* Block Diagram vec GND Operating Temperature................... -55C to +125C } } Storage Temperature... -65C to +150C MEMORY ARRAY ORG +] i2e2see12x8 [omy ADDRESS Voltage on Any Pin eantzevee x 16 with Respect to Ground .................. -1.0Vto+7.0V Maximum Operating Voltage ............. cee 6.25 V 1 REGISTER DC Output Current... eee eee eeeeeteeeeeeeee 5.0mA MODE BUFFER cS --]---: OECODE LoGic *NOTICE: Stresses beyond those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. CLOCK | This is a stress rating only and functional operation of the CLK *_ GENERATOR po device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended Note: periods may affect device reliability. 1 ADY/BUSY . When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organiza- tion is selected. If the ORG pin is left unconnected, then an in- ternal pullup device will select the x 16 organization. D.C. Characteristics Applicable over recommended operating range from: Tai = -40C to +85C, Vcc = +2.7 V to +5.5 V, Tac = 0C to + 70C, Vcc = +2.7 V to +5.5 V (unless otherwise noted) Symbol Parameter Test Condition Min Max Units Operating Current _ CLK = 1.0 MHz") 2 lect CMOS Input Levels S=Y' CLK =0.5MHz"") 2 mA Operating Current _ CLK = 1.0 MHz!) 3 lece TTL Input Levels CS=VIH, GLK = 0.5 MHz") 3 mA CLK = 1.0 MHz!) 100 lecs Standby Current CS=0V CLK =05 Mie) 100 HA lie Input Leakage Vin = 0 V to Voc . pA lou Output Leakage Vin = 0 V to Voc art ne pA View Input Low Voltage 0.8 Vint Input High Voltage 45V<Vec <5.5V 2 V ViL2 Input Low Voltage -0.1 0.6 Ving Input High Voltage 2-7 VS Voc: $5.5 V 2 VCC +1 v Vout Output Low Voltage 45VsVec <5.5V V Output High Voltage [OL = 2.1 mA 0.4 V OHI put Hig 9@ lon = -400 pA 2.4 v VoL2 Output Low Voltage 2.7 Vv sVec < 5.5V VoH Output High Voltage [OL = 10 HA 02 V OH2 put rig 9 lon = -10 WA Voc - 0.2 V Note: 1. Devices operate at 1.0 MHz at VCC = 5.0 V + 10% at commercial temperature. All low voltage and industrial parts operate at 0.5 MHz. 2-32 AT59C11/12/1 3 memeees AT 59C 11/12/13 A.C. Characteristics Applicable over recommended operating range from Ta = -40C to + 85C, Vcc = +2.7 V to +5.5 V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol Parameter Test Condition Min Max Units feLk CLK Clock Frequency 05 MHz . Note 1 500 ickH CLK High Time Note 2 500 ns . Note 1 250 tcKL CLK Low Time Note 2 500 ns . . Note 3 250 tes Minimum CS Low Time Note 4 500 ns tess CS Setup Time Relative to CLK 10 ns tois DI Setup Time Relative to CLK oo ns tcsH CS Hold Time Relative to CLK 0 ns toi Di Hold Time Relative to CLK 4 ns 500 tpo Output Delay AC Test 1000 ns trap CS to Status Valid AC Test 500 ns 1000 an AC Test 100 tez CS to DO in High Impedance CS = Vi. 200 ns two Write Cycle Time 10 ms Number of Data Typical Endurance Changes per Bit 100,000 Cycles Notes: 1. The CLK frequency specification for Commercial parts specifies a minimum CLK clock period of 1 pis, therefore in an CLK clock cycle tcxH + tcKL must be greater than or equal to 2 ps. For example if tc, = 250 ns then the minimum tckH = 750 ns in order to meet the CLK frequency specification. 2. The CLK frequency specification for extended Temperature parts specifies a minimum CLK clock period of 2 [1s, therefore Pin Capacitance Applicable over recommended operating range from Ta = 25C, f = 1.0 MHz, Vcc = +5.0 V (unless otherwise noted) in an CLK clock cycle tckH + tcKL must be greater than or equal to 2 Us. For example, if the tckt = 500 ns then the minimum tckH = 1.5 pts in order to meet the CLK frequency specifica- tion. . For Commercial parts CS must be brought tow for a minimum of 250 ns (tcs} between consecutive instruction cycles. . For Extended Temperature parts CS must be brought low for a minimum of 500 ns (tcs) between consecutive instruction cycles, Test Conditions Max Units Conditions Cout Output Capacitance (DO) 5 pF VouT = 0 V Cin input Capacitance (CS, CLK, Dl, RDY/BUSY) 5 pF Vin =0V Note: 1. This parameter is characterized and is not 100% tested. ANNEL 2-33 EyAIMEL Functional Description The AT59C1 1/12/13 are accessed via a simple and versatile 4- wire serial communication interface. Device operation is con- trolled by 6 instructions issued by the host processor. A valid instruction consists of a Start Bit (logic 1) followed by the ap- propriate Op Code and the desired memory Address location. READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the in- struction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock CLK. It should be noted that a dummy bit (logic 0) precedes the 8- or 16-bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming in- structions can be carried out. Please note that once in the Erase/Write Enable state, programming remains enabled until an Erase/Write Disable (EWDS) instruction is executed or Vcc power is removed from the part. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle starts after the last bit of data is received at serial data input pin DI. The Instruction Set for the AT59C11 Ready/Busy status of the AT59C 11/12/13 can be determined by polling the RDY/BUSY pin. A logic 0 at DO indicates that programming is still in progress. A logic 1 indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic 1" state and is primarily used for testing purposes. The Ready/Busy status of the ATS9C11/12/13 can be determined by polling the RDY/BUSY pin. The ERAL instruction is valid only at Vcc = 5.0 V+ 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The Ready/Busy status of the ATS9C11/12/13 can be determined by polling the RDY/BUSY pin. The WRAL instruction is valid only at Vcc = 5.0 V + 10%. ERASE/WRITE DISABLE (EWDS): To protect against ac- cidental data disturb, the Erase/Write Disable (EWDS) instruc- tion disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS in- structions and can be executed at any time. Op Address Data Instruction SB Code x8 x 16 x8 x16 | Comments Reads data stored in memory, at READ 1 10XX As-Ao As-Ao specified address. Write enable must precede all EWEN 1 0011 0000000 000000 ramming modes. WRITE 1 X1XX Ag-Ao As-Ao | D7-Do D45-Do ites memory location Erases all memory locations. Valid ERAL 1 0010 0000000 000000 only at Vcc = 4.5 V0 5.5 V. WRAL 1 0001 } 0000000 000000 | D7-Do Di5-Do| Minoo AEVIGRBY, EWDS 1 0000 | 0000000 000000 Disables a programming 2-34 AT59C11/12/13 mmmes AT59C 1 1/12/13 Instruction Set for the AT59C12 and AT59C13 Op Address Data Instruction SB Code x8 x16 x8 x16 | Comments _ Reads data stored in memory, at READ 1 10XX As-Ao A7-Ao specified address. Write enable must precede all EWEN 1 0011 000000000 00000000 programming modes. WRITE 1 X1XX | Ag-Aa Ar-Aa | D7-Do Dis-Do | Writes memory location Erases all memory locations. Valid ERAL 1 0010 | 000000000 00000000 only at Vcc = 4.5 V to 5.5 V. Writes ali memory locations. Valid WRAL 1 0001 | 000000000 00000000 D7-Do D15-Do | when Vcc = 5.0 V + 10% and Disable Register cleared. Disabies all programming EWDS 1 0000 | 000000000 00000000 instructions. Timing Diagrams Synchronous Data Timing Vin NI cS oy, 1 ps? K toss toKn tox. jw tosu cu MH | | Vit : V tos <ete toi 1 yp X xX le ep P tpp ez po (READ) O# Vo. e BD cz Von STATUS VALIO RDYBUSY y K a Note: 1. This is the minimum CLK period. Organization Key for Timing Diagrams Density 1K Density 2K Density 4K vO x8 x16 x8 x16 x8 x 16 AN Ag As As Az As A7 DN D7 D15 D7 D15 D? D1i5ANE} Timing Diagrams (Continued) READ Timing os _/ SN 4 po HIGH-Z - ) + OA WRITE Timing dL ft cs . "RRA RR RDY/BUSY HIGH-Z EWEN/EWDS Timing cs / \ Di Jo of * \ 0 0 0 09 0 0 0 ENABLE = 11 DISABLE = 00 2-36 AT59C11/12/13AT59C11/12/13 Timing Diagrams (Continued) ERAL Timing cs _/ ERED RDY/BUSY 4 WRAL Timing ey RDY/BUSY 7 hem two AHEL 2s1ANMEL Ordering Information two loc fMAX (ms) (mA) (kHz) Ordering Code Package Operation Range 10 3.0 1000 AT59C11-10PC (-2.7) 8P3 Commercial AT59C11-10SC (-2.7) 8S1 (0C to 70C) AT59C11-10P! (-2.7) 8P3 Industrial AT59C11-10SI (-2.7) 8S1 (-40C to 85C) AT59C11-10PM 8P3 Military (-55C to 125C) 10 3.0 1000 AT59C-12-10PC (-2.7) BP3 Commercial AT59C12-10SC (-2.7) 8S1 (0C to 70C) AT59C12-10PI (-2.7) 8P3 Industrial AT59C12-10SI (-2.7) 8S1 (-40C to 85C) AT59C12-10PM 8P3 Military (-55C to 125C) 10 3.0 1000 AT59C13-10PC (-2.7) 8P3 Commercial AT59C13-10SC (-2.7) 8S1 (0C to 70C) AT59C13-10PI {-2.7) 8P3 Industrial AT59C 13-1051 (-2.7) 8St (-40C to 85C) AT59C13-10PM 8P3 Military (-55C to 125C) Package Type 8P3 8 Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8 Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options Blank Standard Device (4.5 V to 5.5 V) 2.7 Low Voltage (2.7 V to 5.5 V) 2-38 AT59C11/12/13 meueenenee