HSMP-389x Series, HSMP-489x Series
Surface Mount RF PIN Switch Diodes
Data Sheet
Features
• Unique Congurations in Surface Mount Packages
– Add Flexibility
– Save Board Space
– Reduce Cost
• Switching
– Low Capacitance
– Low Resistance at Low Current
• Low Failure in Time (FIT) Rate[1]
• Matched Diodes for Consistent Performance
• Better Thermal Conductivity for Higher Power
Dissipation
• Lead-free
Note:
1. For more information see the Surface Mount PIN Reliability Data
Sheet.
Description/Applications
The HSMP-389x series is optimized for switching appli-
cations where low resistance at low current and low ca-
pacitance are required. The HSMP-489x series products
feature ultra low parasitic inductance. These products
are specically designed for use at frequencies which
are much higher than the upper limit for conventional
PIN diodes.
Pin Connections and Package Marking
Notes:
1. Package marking provides orientation, identication, and date
code.
2. See “Electrical Specications” for appropriate package marking.
GUx
1
2
3
6
5
4
2
Package Lead Code
Identication,
SOT-23/143
(Top View)
Package Lead Code Identication,
SOT-323
(Top View)
Package Lead Code Identication,
SOT-363
(Top View)
Absolute Maximum Ratings[1] TC = +25°C
Symbol Parameter Unit SOT-23/143 SOT-323/363
If Forward Current (1 µs Pulse) Amp 1 1
PIV Peak Inverse Voltage V 100 100
Tj Junction Temperature °C 150 150
Tstg Storage Temperature °C -65 to 150 -65 to 150
θjc Thermal Resistance[2] °C/W 500 150
ESD WARNING:
Handling Precautions Should Be Taken To Avoid Static Discharge.
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the device.
2. TC = +25°C, where TC is dened to be the temperature at the package pins where contact is made to the circuit board.
SERIES–
SHUNT PAIR
LOW
INDUCTANCE
SINGLE
T
UNCONNECTED
TRIO
L
1 2 3
6 5 4
1 2 3
6 5 4
1 2 3
6 5 4
U
HIGH
FREQUENCY
SERIES
V
1 2 3
6 5 4
DUAL SWITCH
MODEL
R
1 2 3
6 5 4
COMMON
CATHODE
F
COMMON
ANODE
E
SERIES
C
SINGLE
B
DUAL ANODE
489B
COMMON
CATHODE
#4
COMMON
ANODE
#3
SERIES
#2
SINGLE
#0
UNCONNECTED
PAIR
#5
DUAL ANODE
4890
RING
QUAD
#7
1
3
2
4
UNDER DEVELOPMENT
3
Electrical Specications, TC = 25°C, each diode
Package Minimum Maximum Maximum
Part Number Marking Lead Breakdown Series Resistance Total Capacitance
HSMP- Code Code Conguration Voltage VBR (V) RS (ý) CT (pF)
3890 G0[1] 0 Single 100 2.5 0.30
3892 G2[1] 2 Series
3893 G3[1] 3 Common Anode
3894 G4[1] 4 Common Cathode
3895 G5[1] 5 Unconnected Pair
389B G0[2] B Single
389C G2[2] C Series
389E G3[2] E Common Anode
389F G4[2] F Common Cathode
389L GL[2] L Unconnected Trio
389R S[2] R Dual Switch Mode
389T Z[2] T Low Inductance Single
389U GU[2] U Series-Shunt Pair
389V GV[2] V High Frequency Series Pair
Test Conditions VR = VBR IF = 5 mA VR = 5 V
Measure f = 100 MHz f = 1 MHz
IR 10 µA
Notes:
1. Package marking code is white.
2. Package is laser marked.
High Frequency (Low Inductance, 500 MHz– 3 GHz) PIN Diodes
Minimum Maximum Typical Maximum Typical
Part Package Breakdown Series Total Total Total
Number Marking Voltage Resistance Capacitance Capacitance Inductance
HSMP- Code[1] Conguration VBR (V) RS (ý) C T (pF) CT (pF) LT (nH)
489x GA Dual Anode 100 2.5 0.33 0.375 1.0
Test Conditions VR = VBR IF = 5 mA f = 1 MHz VR = 5 V f=500 MHz–
Measure VR = 5 V f = 1 MHz 3 GHz
IR 10 µA
Note:
1. SOT-23 package marking code is white; SOT-323 is laser marked.
Typical Parameters at TC = 25°C
Part Number Series Resistance Carrier Lifetime Total Capacitance
HSMP- RS (ý) τ (ns) C T (pF)
389x 3.8 200 0.20 @ 5V
Test Conditions IF = 1 mA IF = 10 mA
f = 100 MHz IR = 6 mA
4
HSMP-389x Series Typical Performance, TC = 25°C, each diode
Typical Applications for Multiple Diode Products
Figure 6. HSMP-389L used in a SP3T Switch.
Figure 7. HSMP-389L Unconnected Trio used in a Dual Voltage, High Isolation
Switch.
1
123
4
05 6
b1 b2 b3
2
3
1
1 1
RF in RF out
2
2
3
4 5 6
1
0
0
2
+V
–V
“ON”
“OFF”
Figure 1. Total RF Resistance at 25 C vs.
Forward Bias Current.
100
10
1
0.1
RF RESISTANCE (OHMS)
IF – FORWARD BIAS CURRENT (mA)
0.01 0.1 1 10 100
120
115
110
105
100
95
90
85
1 10 30
IF – FORWARD BIAS CURRENT (mA)
Figure 3. 2nd Harmonic Input Intercept
Point vs. Forward Bias Current.
INPUT INTERCEPT POINT (dBm)
Diode Mounted as a
Series Attenuator in a
50 Ohm Microstrip and
Tested at 123 MHz
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20 0 4 8 12 16 20
VR – REVERSE VOLTAGE (V)
TOTAL CAPACITANCE (pF)
1 MHz
1 GHz
Figure 2. Capacitance vs. Reverse
Voltage.
200
160
120
80
40
0
10 2015 25 30
Trr – REVERSE RECOVERY TIME (nS)
FORWARD CURRENT (mA)
Figure 4. Typical Reverse Recovery Time
vs. Reverse Voltage.
VR = –2V
VR = –5V
VR = –10V
100
10
1
0.1
0.01 0 0.2 0.4 0.6 0.8 1.0 1.2
IF – FORWARD CURRENT (mA)
VF – FORWARD VOLTAGE (V)
Figure 5. Forward Current vs. Forward
Voltage.
125 C 25 C –50 C
5
Typical Applications for Multiple Diode Products (continued)
Figure 11. HSMP-389V Series/Shunt Pair used in a 1.8 GHz
Transmit/Receive Switch.
Figure 10. HSMP-389U Series/Shunt Pair used in a 900 MHz
Transmit/Receive Switch.
Figure 8. HSMP-389L Unconnected Trio used in a Positive Voltage,
High Isolation Switch.
Figure 9. HSMP-389T used in a Low Inductance Shunt
Mounted Switch.
RF in RF out
1
+V
0
2
0
+V
“ON”
“OFF”
456
1
1 1
2
2
3
λ
4
Rcvr
Xmtr
Bias Ant
PA
bias
HSMP-389U
LNA
λ
4
Rcvr
Bias
Xmtr
HSMP-389V
Antenna
λ
4
λ
4
Rcvr
Xmtr
Bias Ant
C C
6
Typical Applications for Multiple Diode Products (continued)
RF COMMON
RF COMMON
RF 1
BIAS 1 BIAS BIAS
RF 2
BIAS 2
Figure 12. Simple SPDT Switch, Using Only Positive Current.
RF COMMON
RF 1 RF 2
BIAS
Figure 14. Switch Using Both Positive and Negative Bias Current. Figure 15. Very High Isolation SPDT Switch, Dual Bias.
Figure 13. High Isolation SPDT Switch, Dual Bias.
RF 2
RF 1
RF COMMON
RF 2
RF 1
BIAS
7
Equivalent Circuit Model
HSMP-389x Chip*
Typical Applications for HSMP-489x Low Inductance Series
Microstrip Series Connection for HSMP-489x Series
In order to take full advantage of the low inductance
of the HSMP-489x series when using them in series ap-
plications, both lead 1 and lead 2 should be connected
together, as shown in Figure 17.
Co-Planar Waveguide Shunt Connection for HSMP-489x Series
Co-Planar waveguide, with ground on the top side of
the printed circuit board, is shown in Figure 20. Since
it eliminates the need for via holes to ground, it oers
lower shunt parasitic inductance and higher maximum
attenuation when compared to a microstrip circuit.
A SPICE model is not available for PIN diodes as SPICE
does not provide for a key PIN diode characteristic, car-
rier lifetime.
1 2
3
Figure 16. Internal Connections.
HSMP-489x
Figure 17. Circuit Layout.
50 OHM MICROSTRIP LINES
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
Figure 18. Circuit Layout.
0.3 nH
0.3 nH
0.3 pF
1.5 nH 1.5 nH
Figure 19. Equivalent Circuit.
Figure 20. Circuit Layout.
Co-Planar Waveguide
Groundplane
Center Conductor
Groundplane
0.12 pF*
* Measured at -20 V
0.5 Ω
Rj
Rs
Cj
Rj = 20 Ω
I0.9
RT = 0.5 + Rj
CT = CP + Cj
I = Forward Bias Current in mA
* See AN1124 for package models
Figure 21. Equivalent Circuit.
0.3 pF
0.75 nH
Figure 16. Internal Connections.
Figure 17. Circuit Layout.
Microstrip Shunt Connections for HSMP-489x Series
In Figure 18, the center conductor of the microstrip line
is interrupted and leads 1 and 2 of the HSMP-489x diode
are placed across the resulting gap. This forces the 1.5
nH lead inductance of leads 1 and 2 to appear as part of
a low pass lter, reducing the shunt parasitic inductance
and increasing the maximum available attenuation. The
0.3 nH of shunt inductance external to the diode is cre-
ated by the via holes, and is a good estimate for 0.032"
thick material.
Figure 18. Circuit Layout.
Figure 19. Equivalent Circuit.
Figure 20. Circuit Layout.
Figure 21. Equivalent Circuit.
8
Assembly Information
0.026
0.075
0.016
0.035
Figure 22. PCB Pad Layout, SOT-363.
(dimensions in inches).
0.026
0.035
0.07
0.016
Figure 23. PCB Pad Layout, SOT-323.
(dimensions in inches).
0.037
0.95
0.037
0.95
0.079
2.0
0.031
0.8
DIMENSIONS IN inches
mm
0.035
0.9
SOT-23 Footprint
Figure 24. PCB Pad Layout, SOT-23.
DIMENSIONS IN
inches
mm
0.075
1.9 0.071
1.8
0.112
2.85
0.079
2
0.033
0.85
0.041
1.05
0.108
2.75
0.033
0.85
0.047
1.2
0.031
0.8
0.033
0.85
Figure 25. PCB Pad Layout, SOT-143.
9
Lead-Free Reow Prole Recommendation (IPC/JEDEC J-STD-020C)
Reow Parameter Lead-Free Assembly
Average ramp-up rate (Liquidus Temperature (TS(max) to Peak) 3°C/ second max
Preheat Temperature Min (TS(min)) 150°C
Temperature Max (TS(max)) 200°C
Time (min to max) (tS) 60-180 seconds
Ts(max) to TL Ramp-up Rate 3°C/second max
Time maintained above: Temperature (TL) 217°C
Time (tL) 60-150 seconds
Peak Temperature (TP) 260 +0/-5°C
Time within 5 °C of actual Peak temperature (tP) 20-40 seconds
Ramp-down Rate 6°C/second max
Time 25 °C to Peak Temperature 8 minutes max
Note 1: All temperatures refer to topside of the package, measured on the package body surface
25
Time
Temperature
Tp
T
L
tp
t
L
t 25°C to Peak
Ramp-up
ts
Ts
min
Ramp-down
Preheat
Critical Zone
T
L
to Tp
Ts
max
Figure 26. Surface Mount Assembly Prole.
SMT Assembly
Reliable assembly of surface mount components is a
complex process that involves many material, process,
and equipment factors, including: method of heating
(e.g., IR or vapor phase reow, wave soldering, etc.) cir-
cuit board material, conductor thickness and pattern,
type of solder alloy, and the thermal conductivity and
thermal mass of components. Components with a low
mass, such as the SOT package, will reach solder reow
temperatures faster than those with a greater mass.
Avago Technologies’ diodes have been qualied to the
time-temperature prole shown in Figure 26. This prole
is representative of an IR reow type of surface mount
assembly process.
After ramping up from room temperature, the circuit
board with components attached to it (held in place
with solder paste) passes through one or more preheat
zones. The preheat zones increase the temperature of
the board and components to prevent thermal shock
and begin evaporating solvents from the solder paste.
The reow zone briey elevates the temperature su-
ciently to produce a reow of the solder.
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to compo-
nents due to thermal shock. The maximum temperature
in the reow zone (TMAX) should not exceed 260°C.
These parameters are typical for a surface mount assem-
bly process for Avago Technologies diodes. As a general
guideline, the circuit board and components should be
exposed only to the minimum temperatures and times
necessary to achieve a uniform reow of solder.
10
e
B
e2
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.79
0.000
0.30
0.08
2.73
1.15
0.89
1.78
0.45
2.10
0.45
MAX.
1.20
0.100
0.54
0.20
3.13
1.50
1.02
2.04
0.60
2.70
0.69
SYMBOL
A
A1
B
C
D
E1
e
e1
e2
E
L
eB
e2
B1
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.79
0.013
0.36
0.76
0.086
2.80
1.20
0.89
1.78
0.45
2.10
0.45
MAX.
1.097
0.10
0.54
0.92
0.152
3.06
1.40
1.02
2.04
0.60
2.65
0.69
SYMBOL
A
A1
B
B1
C
D
E1
e
e1
e2
E
L
e
B
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.80
0.00
0.15
0.08
1.80
1.10
1.80
0.26
MAX.
1.00
0.10
0.40
0.25
2.25
1.40
2.40
0.46
SYMBOL
A
A1
B
C
D
E1
e
e1
E
L
1.30 typical
0.65 typical
E
HE
D
e
A1
b
A
A2
DIMENSIONS (mm)
MIN.
1.15
1.80
1.80
0.80
0.80
0.00
0.15
0.08
0.10
MAX.
1.35
2.25
2.40
1.10
1.00
0.10
0.30
0.25
0.46
SYMBOL
E
D
HE
A
A2
A1
e
b
c
L
0.650 BCS
L
c
Package Dimensions
Outline 23 (SOT-23)
Outline 143 (SOT-143) Outline SOT-363 (SC-70 6 Lead)
Outline SOT-323 (SC-70 3 Lead)
11
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL
Note: "AB" represents package marking code.
"C" re
p
resents date code.
END VIE
W
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
Note: "AB" represents package marking code.
"C" represents date code.
END VIE
W
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
END VIE
W
8 mm
4 mm
TOP VIEW
Note: "AB" represents package marking code.
"C" represents date code.
ABC ABC ABC ABC
Option Descriptions
-BLKG = Bulk, 100 pcs. per antistatic bag
-TR1G = Tape and Reel, 3000 devices per 7" reel
-TR2G = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated
Placement.”
Device Orientation
For Outline SOT-143
For Outlines SOT-23, -323
For Outline SOT-363
Ordering Information
Specify part number followed by option. For example:
HSMP - 389x - xxx
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
Package Characteristics
Lead Material Copper (SOT-323/363); Alloy 42 (SOT-23/143)
Lead Finish Tin 100%
Maximum Soldering Temperature 260°C for 5 seconds
Minimum Lead Strength 2 pounds pull
Typical Package Inductance 2 nH
Typical Package Capacitance 0.08 pF (opposite leads)
12
Tape Dimensions and Product Orientation
For Outline SOT-143
For Outline SOT-23
9 MAX
A
0
P
P
0
D
P
2
E
F
W
D
1
Ko 8 MAX
B
0
13.5 MAX
t1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
3.15
±
0.10
2.77
±
0.10
1.22
±
0.10
4.00
±
0.10
1.00 + 0.05
0.124
±
0.004
0.109
±
0.004
0.048
±
0.004
0.157
±
0.004
0.039
±
0.002
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.50 + 0.10
4.00
±
0.10
1.75
±
0.10
0.059 + 0.004
0.157
±
0.004
0.069
±
0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 – 0.10
0.229
±
0.013
0.315 + 0.012 – 0.004
0.009 0.0005
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50
±
0.05
2.00
±
0.05
0.138
±
0.002
0.079
±
0.002
DISTANCE
BETWEEN
CENTERLINE
W
F
E
P
2
P
0
D
P
D
1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
3.19
±
0.10
2.80
±
0.10
1.31
±
0.10
4.00
±
0.10
1.00 + 0.25
0.126
±
0.004
0.110
±
0.004
0.052
±
0.004
0.157
±
0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.50 + 0.10
4.00
±
0.10
1.75
±
0.10
0.059 + 0.004
0.157
±
0.004
0.069
±
0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 – 0.10
0.254
±
0.013
0.315+ 0.012 – 0.004
0.0100 0.0005
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50
±
0.05
2.00
±
0.05
0.138
±
0.002
0.079
±
0.002
DISTANCE
A
0
9
°
MAX 9
°
MAX
t
1
B
0
K
0
Tape Dimensions and Product Orientation
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-0486EN
AV02-0813EN - June 2, 2009
For Outlines SOT-323, -363
P
P
0
P
2
F
W
C
D
1
D
E
A
0
An
t
1
(CARRIER TAPE THICKNESS) T
t
(COVER TAPE THICKNESS)
An
B
0
K
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
2.40
±
0.10
2.40
±
0.10
1.20
±
0.10
4.00
±
0.10
1.00 + 0.25
0.094
±
0.004
0.094
±
0.004
0.047
±
0.004
0.157
±
0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.55
±
0.05
4.00
±
0.10
1.75
±
0.10
0.061
±
0.002
0.157
±
0.004
0.069
±
0.004
PERFORATION
WIDTH
THICKNESS
W
t
1
8.00
±
0.30
0.254
±
0.02
0.315
±
0.012
0.0100
±
0.0008
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50
±
0.05
2.00
±
0.05
0.138
±
0.002
0.079
±
0.002
DISTANCE
FOR SOT-323 (SC70-3 LEAD) An 8
°
C MAX
FOR SOT-363 (SC70-6 LEAD) 10
°
C MAX
ANGLE
WIDTH
TAPE THICKNESS
C
T
t
5.4
±
0.10
0.062
±
0.001
0.205
±
0.004
0.0025
±
0.00004
COVER TAPE