RDA5802E SINGLE-CHIP BROADCAST FM RADIO TUNER 1 Rev.1.7-Jun.2009 General Description The RDA5802E (RDA5802 Enhanced) is a single-chip broadcast FM stereo radio tuner with fully integrated synthesizer, IF selectivity and MPX decoder. The tuner uses the CMOS process, support multi-interface and require the least external component. The package size is 4X4mm and is completely adjustment-free. All these make it very suitable for portable devices. The RDA5802E has a powerful low-IF digital audio processor, this make it have optimum sound quality with varying reception conditions. The RDA5802E can be tuned to the worldwide frequency band. Figure 1-1. RDA5802E Top View 1.1 Features l CMOS single-chip fully-integrated FM tuner l Low power consumption l l Total current consumption lower than 22mA at 3.0V Programmable de-emphasis (50/75 s) Receive signal strength indicator (RSSI) power supply l Bass boost Support worldwide frequency band l Volume control O 65 -108 MHz l I2S digital output interface Digital low-IF tuner l Line-level analog output voltage O Image-reject down-converter l 32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz O High performance A/D converter O IF selectivity performed internally l 2-wire and 3-wire serial control bus interface Fully integrated digital frequency synthesizer l Directly support 32 resistance loading O Fully integrated on-chip RF and IF VCO l Integrated LDO regulator O Fully integrated on-chip loop filter l Autonomous search tuning l Support 32.768KHz crystal oscillator l Digital auto gain control (AGC) l High cut l l O l O Digital adaptive noise cancellation O Mono/stereo switch O Soft mute Reference clock O l 1.2 1.8 to 5.5 V operation voltage 4X4mm 24 pin QFN package Applications l Cellular handsets l MP3, MP4 players l Portable radiosPDAs, Notebook Copyright (c) RDA Microelectronics Inc. 2006. All rights are reserved. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 2 Table of Contents 1 General Description.................................................................................................................................... 1 1.1 Features ......................................................................................................................................... 1 1.2 Applications .................................................................................................................................... 1 2 3 Table of Contents ........................................................................................................................................ 2 Functional Description ............................................................................................................................... 3 3.1 FM Receiver ................................................................................................................................. 3 3.2 Synthesizer.................................................................................................................................... 3 3.3 Power Supply................................................................................................................................ 3 3.4 RESET and Control Interface select ............................................................................................. 4 3.5 Control Interface ........................................................................................................................... 4 3.6 I2S Audio Data Interface ............................................................................................................... 4 3.7 GPIO Outputs ............................................................................................................................... 4 Electrical Characteristics ........................................................................................................................... 5 Receiver Characteristics............................................................................................................................. 6 Serial Interface............................................................................................................................................ 7 6.1 Three-wire Interface Timing ......................................................................................................... 7 6.2 I2C Interface Timing ..................................................................................................................... 8 Register Definition ...................................................................................................................................... 9 Pins Description ........................................................................................................................................ 13 Application Diagram ................................................................................................................................ 15 9.1 Audio Loading Resistance Larger than 32 & TCXO Application: .......................................... 15 9.1.1 Bill of Materials: ......................................................................................................................... 15 9.2 Audio Loading Resistance Lower than 32 & DCXO Application: .......................................... 16 9.2.1 Bill of Materials: ......................................................................................................................... 16 Package Physical Dimension.................................................................................................................... 17 PCB Land Pattern .................................................................................................................................... 18 Change List................................................................................................................................................ 21 Notes....................................................................................................................................................... 21 RDA5802E RDA5802 .................................................................................................................. 22 Contact Information ................................................................................................................................. 23 4 5 6 7 8 9 10 11 12 13 14 15 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 2 of 23 RDA Microelectronics, Inc. 3 RDA5802E FM Tuner V1.7 Functional Description Figure 3-1. RDA5802E FM Tuner Block Diagram 3.1 FM Receiver The receiver uses a digital low-IF architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduces complexity, and integrates a low noise amplifier (LNA) supporting the FM broadcast band (65 to 108MHz), a quadrature image-reject mixer, a programmable gain control (PGA), a high resolution analog-to-digital converters (ADCs), an audio DSP and a highfidelity digital-to-analog converters (DACs). The LNA has differential input ports (LNAP and LNAN) and supports any input port by set according registers bits (LNA_PORT_SEL[1:0]). It default input common mode voltage is GND. The limiter prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The quadrature mixer down converts the LNA output differential RF signal to low-IF, it also has image-reject function. The PGA amplifies the mixer output IF signal and then digitized with ADCs. The DSP core finishes the channel selection, FM demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise. The DACs convert digital audio signal to analog and change the volume at same time. The DACs has low-pass feature and -3dB frequency is about 30 KHz. 3.2 Synthesizer The frequency synthesizer generates the local oscillator signal which divide to quadrature, then be used to downconvert the RF input to a constant low intermediate frequency (IF). The synthesizer reference clock is 32.768 KHz. The synthesizer frequency is defined by bits CHAN[9:0] with the range from 65MHz to 108MHz. 3.3 Power Supply The RDA5802E integrated one LDO which supplies power to the chip. The external supply The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 3 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 voltage range is 1.8-5.5 V. 3.4 RESET and Control Interface select The RDA5802E is RESET itself When VIO is Power up. And also support soft reset by trigger 02H BIT1 from 0 to 1. The control interface is select by MODE Pin. The MODE Pin is low ,I2C Interface is select. The MODE Pin is set to VIO, SPI Interface is select. 3.5 Control Interface The RDA5802E supports three- wire and I2C control interface. User could select either of them to program the chip. The three-wire interface is a standard SPI interface. It includes three pins: SEN, SCLK and SDIO. Each register write is 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit). RDA5802E samples command byte and data at posedge of SCLK. Each register read is also 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (MSB is the first bit) from RDA5802E. The turn around cycle between command byte from MCU and data from RDA5802E is a half cycle. RDA5802E samples command byte at posedge of SCLK, and output data also at posedge of SCLK. 2 transfer, MCU programs registers from register 0x02h high byte, then register 0x02h low byte, then register 0x03h high byte, till the last register. RDA5802E always gives out ACK after every byte, and MCU gives out STOP condition when register programming is finished. For read transfer, after command byte from MCU, RDA5802E sends out register 0x0Ah high byte, then register 0x0Ah low byte, then register 0x0Bh high byte, till receives NACK from MCU. MCU gives out ACK for data bytes besides last data byte. MCU gives out NACK for last data byte, and then RDA5802E will return the bus to MCU, and MCU will give out STOP condition. Details refer to RDA5802E Programming Guide. 3.6 I2S Audio Data Interface The RDA5802E supports I2S (Inter_IC Sound Bus) audio interface. The interface is fully compliant with I2S bus specification. When setting I2SEN bit high, RDA5802E will output SCK, WS, SD signals from GPIO3, GPIO1, GPIO2 as I2S master and transmitter, the sample rate is 48Kbps 44.1kbps,32kbps..... RDA5802E also support as I2S slaver mode and transmitter, the sample rate is less than 100kbps. Details refer to RDA5802E Programming Guide. 3.7 GPIO Outputs 2 The I C interface is compliant to I C Bus Specification 2.1. It includes two pins: SCLK and SDIO. A I2C interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip address (0010000b) and a R/W bit. The ACK (or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes is read out from RDA5802E. There is no visible 2 2 register address in I C interface transfers. The I C interface has a fixed start register address (0x02h for write transfer and 0x0Ah for read transfer), and an internal incremental address counter. If register address meets the end of register file, 0x3Ah, register address will wrap back to 0x00h. For write The RDA5802E has three GPIOs. The function of GPIOs could programmed with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0] and I2SEN. If I2SEN is set to low, GPIO pins could be programmed to output low or high or high-Z, or be programmed to output interrupt and stereo indicator with bits GPIO1[1:0], GPIO2[1:0], GPIO3[1:0]. GPIO2 could be programmed to output a low interrupt (interrupt will be generated only with interrupt enable bit STCIEN is set to high) when seek/tune process completes. GPIO3 could be programmed to output stereo indicator bit ST. Constant low, high or high-Z functionality is available regardless of the state of VA and VD supplies or the ENABLE bit. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 4 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 SCK LEFT CHANNEL WS RIGHT CHANNEL 1 SCK SD 1 SCK MSB LSB MSB LSB Figure 3-2. I2S Digital Audio Format 4 Electrical Characteristics Table 4-1 SYMBOL DC Electrical Specification (Recommended Operation Conditions): DESCRIPTION MIN TYP MAX UNIT AVDD Analog Supply Voltage 1.8 3.3 5.5 V DVDD Digital Supply Voltage 1.8 3.3 5.5 V VIO Interface Supply Voltage 1.5 - 3.6 V Tamb Ambient Temperature -20 27 +70 VIL CMOS Low Level Input Voltage 0 0.3*DVDD V VIH CMOS High Level Input Voltage 0.7*VDD DVDD V VTH CMOS Threshold Voltage Table 4-2 SYMBOL 0.5*VDD V DC Electrical Specification (Absolute Maximum Ratings): DESCRIPTION MIN TYP MAX UNIT VIO Interface Supply Voltage -0.5 +4 V Tamb Ambient Temperature IIN -40 +90 C (1) -10 +10 mA (1) -0.3 VIO+0.3 V -20 dBm Input Current VIN Input Voltage Vlna LNA FM Input Level Notes: 1. For Pin: SCLK, SDIO, SEN, MODE Table 4-3 Power Consumption Specification (VDD = 1.8 to 5.5 V, TA = -25 to 85 , unless otherwise specified) SYMBOL DESCRIPTION CONDITION TYP UNIT IA Analog Supply Current ENABLE=1 18 mA ID Digital Supply Current ENABLE=1 3 mA IVIO Interface Supply Current SCLK and RCLK inactive 90 A IAPD Analog Powerdown Current ENABLE=0 2 A IDPD Digital Powerdown Current ENABLE=0 2 A IVIO Interface Powerdown Current ENABLE=0 10 A The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 5 of 23 RDA Microelectronics, Inc. 5 RDA5802E FM Tuner V1.7 Receiver Characteristics Table 5-1 Receiver Characteristics (VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) SYMBOL PARAMETER CONDITIONS MIN BAND=00 TYP MAX UNIT 87 108 MHz BAND=01 76 91 MHz BAND=10 76 108 MHz BAND=11 65 76 MHz 1.5 V EMF General specifications Fin Vrf Rin Cin IP3in am S200 FM Input Frequency Sensitivity 1,2,3 (S+N)/N=26dB LNA Input Resistance 1 7 LNA Input Capacitance 150 7 2 4 Input IP3 1,2 AM Suppression Adjacent Channel Selectivity AGCD=1 80 m=0.3 40 200KHz 45 4 - 6 pF - dBV - dB - dB Left and Right Audio VAFL; VAFR Frequency Output Voltage Volume [3:0] =1111 200 mV (Pins LOUT and ROUT) (S+N)/N SCS THD AOI RL Maximum Signal Plus Noise 1,2,3,5 to Noise Ratio Stereo Channel Separation 55 60 - dB 35 - - dB 0.03 0.05 % 0.1 dB - Audio Total Harmonic 1,3,6 Distortion Audio Output L/R Imbalance Audio Output Loading Resistance Single-ended 32 - Pins LNAN, LNAP, LOUT, ROUT and NC(22,23) Vcom_rfin Vcom Vcom_nc Pins LNAN and LNAP Input V 0 Common Mode Voltage Audio Output Common 8 Mode Voltage 0.95 1. Pins NC (22, 23) Common Floating Mode Voltage 1.05 V V ! The NC(22, 23) pins SHOULD BE left floating. Notes: 1. Fin=65 to 108MHz; Fmod=1KHz; de-emphasis=75s; MONO=1; L=R unless noted otherwise; 2. f=22.5KHz; 3. BAF = 300Hz to 15KHz, RBW <=10Hz; 4. |f2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz; 5. PRF=60dB UV; 6. f=75KHz. 7. Measured at VEMF = 1 m V, f RF = 65 to 108MHz 8. At LOUT and ROUT pins The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 6 of 23 RDA Microelectronics, Inc. 6 6.1 RDA5802E FM Tuner V1.7 Serial Interface Three-wire Interface Timing Table 6-1 Three-wire Interface Timing Characteristics (VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT SCLK Cycle Time tCLK SCLK Rise Time tR 50 ns SCLK Fall Time tF 50 ns SCLK High Time tHI 10 ns SCLK Low Time tLO 10 ns SDIO Input, SEN to SCLK Setup ts 10 - - ns SDIO Input, to SCLK Hold th 10 - - ns 35 ns SCLK to SDIO Output Valid tcdv Read 2 - 10 ns SEN to SDIO Output High Z tsdz Read 2 - 10 ns 5 pF Digital Input Pin Capacitance Figure 6-1. Three-wire Interface Write Timing Diagram Figure 6-2. Three-wire Interface Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 7 of 23 RDA Microelectronics, Inc. 6.2 RDA5802E FM Tuner V1.7 I2C Interface Timing Table 6-2 I2C Interface Timing Characteristics (VDD = 2.7 to 5.5 V, TA = -25 to 85 C, unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT SCLK Frequency fscl 0 - 400 KHz SCLK High Time thigh 0.6 - - s SCLK Low Time tlow 1.3 - - s Setup Time for START Condition tsu:sta 0.6 - - s Hold Time for START Condition thd:sta 0.6 - - s Setup Time for STOP Condition tsu:sto 0.6 - - s SDIO Input to SCLK Setup tsu:dat 100 - - ns SDIO Input to SCLK Hold thd:dat 0 - 900 ns STOP to START Time tbuf 1.3 - - s SDIO Output Fall Time tf:out 20+0.1Cb - 250 ns tr:in / tf:in 20+0.1Cb - 300 ns Input Spike Suppression tsp - - 50 ns SCLK, SDIO Capacitive Loading Cb - - 50 pF 5 pF SDIO Input, SCLK Rise/Fall Time Digital Input Pin Capacitance 2 Figure 6-3. I C Interface Write Timing Diagram 2 Figure 6-4. I C Interface Read Timing Diagram The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 8 of 23 RDA Microelectronics, Inc. 7 RDA5802E FM Tuner V1.7 Register Definition REG BITS 00H 15:8 CHIPID[7:0] NAME Chip ID. FUNCTION 0x58 DEFAULT 02H 15 DHIZ Audio Output High-Z Disable. 0 14 DMUTE Mute Disable. 0 = High impedance; 1 = Normal operation 0 0 = Mute; 1 = Normal operation 13 MONO 0 Mono Select. 0 = Stereo; 1 = Force mono 12 BASS Bass Boost. 10 CLK_DIRECT_MODE Reference clk (32.768K,12M,...) 0 0 = Disabled; 1 = Bass boost enabled direct input 0 mode. 0=clk_buffer mode; 1=clk directly input mode 9 SEEKUP Seek Up. 0 0 = Seek down; 1 = Seek up 8 SEEK Seek. 0 0 = Disable stop seek; 1 = Enable Seek begins in the direction specified by SEEKUP and ends when a channel is found with RSSI level above SEEKTH[5:0], or the entire band has been searched. The SEEK bit is set low and the STC bit is set high when the seek operation completes. 7 SKMODE Seek Mode 0 0 = wrap at the upper or lower band limit and continue seeking 1 = stop seeking at the upper or lower band limit 6:4 CLK_MODE[2:0] 000=32.768kHz 000 001=12Mhz 101=24Mhz 010=13Mhz 110=26Mhz 011=19.2Mhz 111=38.4Mhz 1 SOFT_RESET Soft reset. 0 If 0, not reset; If 1, reset. 0 ENABLE Power Up Enable. 0 0 = Disabled; 1 = Enabled 03H 15:6 CHAN[9:0] Channel Select. 0x00 BAND = 0 Frequency = Channel Spacing (kHz) x CHAN+ 87.0 MHz BAND = 1or 2 Frequency = The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 9 of 23 RDA Microelectronics, Inc. REG BITS RDA5802E FM Tuner V1.7 NAME FUNCTION DEFAULT Channel Spacing (kHz) x CHAN + 76.0 MHz BAND = 3 Frequency = Channel Spacing (kHz) x CHAN + 65.0 MHz CHAN is updated after a seek operation. 4 TUNE Tune 0 0 = Disable 1 = Enable The tune operation begins when the TUNE bit is set high. The STC bit is set high when the tune operation completes. The tune bit is reset to low automatically when the tune operation completes.. 3:2 BAND[1:0] Band Select. 00 00 = 87-108 MHz (US/Europe) 01 = 76-91 MHz (Japan) 10 = 76-108 MHz (world wide) 11 = 65 -76 MHz East Europe 1:0 SPACE[1:0] Channel Spacing. 00 00 = 100 kHz 01 = 200 kHz 10 = 50kHz 04H 14 STCIEN Seek/Tune Complete Interrupt Enable. 0 0 = Disable Interrupt 1 = Enable Interrupt Setting STCIEN = 1 will generate a low pulse on GPIO2 when the interrupt occurs. 11 DE De-emphasis. 0 0 = 75 s; 1 = 50 s 9 SOFTMUTE_EN If 1, softmute enable 1 8 AFCD AFC disable. 0 If 0, afc work; If 1, afc disabled. 6 I2S_ENABLED I2S bus enable 0 If 0, disabled; If 1, enabled. 5:4 GPIO3[1:0] General Purpose I/O 3. 00 00 = High impedance 01 = Mono/Stereo indicator (ST) 10 = Low 11 = High 3:2 GPIO2[1:0] General Purpose I/O 2. 00 00 = High impedance 01 = Interrupt (INT) 10 = Low 11 = High 1:0 GPIO1[1:0] General Purpose I/O 1. 00 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 10 of 23 RDA Microelectronics, Inc. REG BITS RDA5802E FM Tuner V1.7 NAME FUNCTION DEFAULT 00 = High impedance 01 = Reserved 10 = Low 11 = High 05H 15 INT _MODE 1 If 0, generate 5ms interrupt; If 1, interrupt last until read reg0CH action occurs. 14:8 SEEKTH[6:0] Seek Threshold. RSSI scale is logarithmic. 7:6 LNA_PORT_SEL[1:0] LNA input port selection bit: 0001000 0000000 = min RSSI 10 00: no input 01: LNAN 10: LNAP 11: dual port input 5:4 LNA_ICSEL_BIT[1:0] 10 Lna working current bit: 00=1.8mA 01=2.1mA 10=2.5mA 11=3.0mA 3:0 VOLUME[3:0] 1111 DAC Gain Control Bits (Volume). 0000=min; 1111=max Volume scale is logarithmic 06H 12 I2s_mode_select 0 If 0, master mode; If 1, slave mode. 7:4 I2s_ws_cnt[4:0] Only valid in master mode 4'b1000: 4'b0111: 4'b0110: 4'b0101: 4'b0100: 4'b0011: 4'b0010: 4'b0001: WS_STEP_48; WS_STEP=44.1kbps; WS_STEP=32kbps; WS_STEP=24kbps; WS_STEP=22.05kbps; WS_STEP=16kbps; WS_STEP=12kbps; WS_STEP=11.025kbps; 0000 4'b0000: WS_STEP=8kbps; 0AH 14 STC 0 Seek/Tune Complete. 0 = Not complete 1 = Complete The seek/tune complete flag is set when the seek or tune operation completes. 13 SF 0 Seek Fail. 0 = Seek successful; 1 = Seek failure The seek fail flag is set when the seek operation fails to find a channel with an RSSI level greater than SEEKTH[5:0]. 10 ST 1 Stereo Indicator. 0 = Mono; 1 = Stereo Stereo indication is available on GPIO3 by setting GPIO1[1:0] =01. 9:0 READCHAN[9:0] 8'h00 Read Channel. BAND = 0 Frequency = Channel Spacing (kHz) x READCHAN[9:0]+ 87.0 MHz BAND = 1 or 2 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 11 of 23 RDA Microelectronics, Inc. REG BITS RDA5802E FM Tuner V1.7 NAME FUNCTION Frequency = Channel Spacing DEFAULT (kHz) x (kHz) x READCHAN[9:0]+ 76.0 MHz BAND = 3 Frequency = Channel Spacing READCHAN[9:0]+ 65.0 MHz READCHAN[9:0] is updated after a tune or seek operation. 0BH 15:9 RSSI[6:0] RSSI. 0 000000 = min 111111 = max RSSI scale is logarithmic. 8 FM TRUE 1 = the current channel is a station 0 0 = the current channel is not a station 7 FM_READY 1=ready 0 0=not ready The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 12 of 23 RDA Microelectronics, Inc. NC NC GPIO1 GPIO2 GPIO3 Pins Description GND 24 23 22 21 20 19 GND 1 18 AVDD LNAN 2 17 GND RFGND 3 16 LOUT LNAP 4 15 ROUT GND 5 14 GND GND 6 13 DVDD GND PAD 9 10 11 RCLK 12 VIO 8 SDIO MODE 7 SCLK RDA5802E SEN 8 RDA5802E FM Tuner V1.7 Figure 8-1. RDA5802E Top View Table 8-1 RDA5802E Pins Description SYMBOL GND LNAN,LNAP RFGND MODE SEN SCLK SDIO RCLK VIO AVDD ROUT,LOUT DVDD GPIO1,GPIO2,GPIO3 NC PIN DESCRIPTION 1,5,6,14,17,24 Ground. Connect to ground plane on PCB LNA input port. For single-ended input, LNAN should 2,4 be connected to RFGND 3 LNA ground. Connect to ground plane on PCB Control Interface select The MODE Pin is low ,I2C Interface is select. 7 The MODE Pin is set to VIO, SPI Interface is select. 8 9 10 11 12 18 15,16 14 19,20,21 22,23 Latch enable (active low) input for serial control bus Clock input for serial control bus Data input/output for serial control bus 32.768KHz crystal oscillator and reference clock input Power supply for I/O Power supply for analog section Right/Left audio output Power supply for digital section General purpose input/output No Connect The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 13 of 23 RDA Microelectronics, Inc. Table 8-2 RDA5802E FM Tuner V1.7 Internal Pin Configuration SYMBOL PIN LNAN/LNAP 2/4 RCLK 11 DESCRIPTION 47K Sin SDIO\SCLK SCLK/SDIO 9/10 Sout MN1 GPIO1/GPIO2/GPIO3 19/20/21 The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 14 of 23 RDA Microelectronics, Inc. 9 RDA5802E FM Tuner V1.7 Application Diagram 9.1 Audio Loading Resistance Larger than 32 & TCXO Application: Notes: 1. J1: Common 32 Resistance Headphone; 2. U1: RDA5802E Chip; 19 3. V1: Analog and Digital Power Supply (1.8~5.5V); 4. FM Choke (L3 and C3) for Audio Common and LNA Input Common; 5. Pins NC(22, 23), Should be Leaved Floating; 6.Set MODE to select control interface(GND--I2C,VIO--SPI); 7 6. Place C6 Close to AVDD pin. Figure 9-1. RDA5802E FM Tuner Application Diagram (TCXO Application) 9.1.1 Bill of Materials: COMPONENT U1 VALUE RDA5802E J1 DESCRIPTION Broadcast FM Radio Tuner SUPPLIER RDA Common 32 Resistance Headphone C2 100pF Couple CAP Murata L3/C3 100nH/24pF LC Chock for LNA Input Murata C4,C5 125F Audio AC Couple Capacitors Murata C6 24nF Power Supply Bypass Capacitor Murata F1/F2 1.5K@100MHz FM Band Ferrite Murata The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 15 of 23 RDA Microelectronics, Inc. 9.2 RDA5802E FM Tuner V1.7 Audio Loading Resistance Lower than 32 & DCXO Application: Notes: F1 1.5K@100MHz C4 125uF 1. J1: Common 32 Resistance J1 F2 1.5K@100MHz C5 125uF Headphone 2. U1: RDA5802E Chip L3 100nH 3. V1: Analog and Digital Power Supply (1.8~5.5V) C3 24pF 5. Pins NC(22, 23),Should be V1 1 Leaved Floating; 6.Set MODE to select control C6 24nF interface(GND--I2C,VIO--SPI); 7. Place C6 Close to AVDD pin 13 SCLK SDIO VIO Figure 9-2. RDA5802E FM Tuner Application Diagram (32.768K crystal,I2C bus mode) 9.2.1 Bill of Materials: COMPONENT U1 VALUE RDA5802E J1 DESCRIPTION Broadcast FM Radio Tuner SUPPLIER RDA Audio Amplifier C4/C5 125uF Audio AC Couple Capacitors Murata L3/C3 100nH/24pF LC Chock for LNA Input Murata C6 24nF Power Supply Bypass Capacitor Murata F1/F2 1.5K@100MHz FM Band Ferrite Murata The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 16 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 10 Package Physical Dimension Figure 10-1 illustrates the package details for the RDA5802E. The package is lead-free and RoHS-compliant. MIN D NOM MAX 4.00 BSC E 4.00 BSC D2 2.60 2.70 2.80 E2 2.60 2.70 2.80 e 0.50 BSC L 0.30 0.40 0.50 b 0.18 0.25 0.30 A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.20 ref Figure 10-2. 24-Pin 4x4 Quad Flat No-Lead (QFN) The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 17 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 11 PCB Land Pattern Figure 18.Classification Reflow Profile Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average Ramp-Up Rate 3 oC/second max. 3 oC/second max. -Temperature Min (Tsmin) 100 oC 150 oC -Temperature Max (Tsmax) 100 oC 200 oC -Time (tsmin to tsmax) 60-120 seconds 60-180 seconds -Temperature (TL) 183 oC 217oC -Time (tL) 60-150seconds 60-150 seconds Peak /Classification Temperature(Tp) See Table-II See Table-III Time within 5 oC of actual Peak Temperature (tp) 10-30 seconds 20-40 seconds Ramp-Down Rate 6 oC/second max. 6 oC/seconds max. Time 25 oC to Peak Temperature 6 minutes max. 8 minutes max. (TSmax to Tp) Preheat Time maintained above: Table-I Classification Reflow Profiles The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 18 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 Volume mm3 Volume mm3 <350 350 2.5mm 240 + 0/-5 o C 225 + 0/-5 o C 2.5mm 225 + 0/-5 o C 225 + 0/-5 o C Package Thickness Table - II SnPb Eutectic Process - Package Peak Reflow Temperatures Package Volume mm3 Volume mm3 Volume mm3 Thickness 350 350-2000 2000 1.6mm 260 + 0 o C * 260 + 0 o C * 260 + 0 o C * 1.6mm - 2.5mm 260 + 0 o C * 250 + 0 o C * 245 + 0 o C * 2.5mm 250 + 0 o C * 245 + 0 o C * 245 + 0 o C * *Tolerance : The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature(this mean Peak reflow temperature + 0 o C. For example 260+ 0 o C ) at the rated MSL Level. Table - III Pb-free Process - Package Classification Reflow Temperatures Note 1: All temperature refer topside of the package. Measured on the package body surface. Note 2: The profiling tolerance is + 0 capability)whatever o C, - X o C (based on machine variation is required to control the profile process but at no time will it exceed - 5 o C. The producer assures process compatibility at the peak reflow profile temperatures defined in Table -III. Note 3: Package volume excludes external terminals(balls, bumps, lands, leads) and/or non integral heat sinks. Note 4: The maximum component temperature reached during reflow depends on package the thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD package may sill exist. Note 5: Components intended for use in a "lead-free" assembly process shall be evaluated using the "lead free" classification temperatures and profiles defined in Table-I II III whether or not lead free. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 19 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 RoHS Compliant The product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE), and are therefore considered RoHS compliant. ESD Sensitivity Integrated circuits are ESD sensitive and can be damaged by static electricity. Proper ESD techniques should be used when handling these devices. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 20 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 12 Change List REV V1.0 DATE 2009-03-03 AUTHER ChunZhao CHANGE DESCRIPTION Original Draft. 13 Notes 1: VIO 7 8 SCLK SDIO 9 10 7 MODE SEN SEN SCLK SCLK SDIO SDIO I2C 8 9 10 MODE SEN SCLK SDIO SPI The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 21 of 23 RDA Microelectronics, Inc. 14 RDA5802E FM Tuner V1.7 RDA5802E RDA5802 15802E 0x0Ch58030x0Dh5804 58005802 5802E; 2FM 4 LNAP 2 LNAN 5802E 3 5802E I2C 001000000100011100000 4RCLK 32.768K PCB 32.768K 5LNAN & LANP 0 0 MP3 100pF ESD I2C SNR SEN RDS I2C 32K 5802E 5000V sclk 250mV 1.85.5V (1.8~2V ) 57dB -109dBm 21.5mA 5802 5802 32K 0x02h bit<10> 1 5802 2000V sclk 200mV 2.7~5.5V 54dB -107dBm 20mA 32K The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 22 of 23 RDA Microelectronics, Inc. RDA5802E FM Tuner V1.7 15 Contact Information RDA Microelectronics (Shanghai), Inc. Suite 1108 Block A, e-Wing Center, 113 Zhichun Road Haidian District, Beijing Tel: 86-10-62635360 Fax: 86-10-82612663 Postal Code: 100086 Suite 302 Building 2, 690 Bibo Road Pudong District, Shanghai Tel: 86-21-50271108 Fax: 86-21-50271099 Postal Code: 201203 Copyright (c) RDA Microelectronics Inc. 2006. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 23 of 23