18-Bit, 2.5 LSB INL, 100 kSPS SAR ADC
AD7678
Rev. A
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FEATURES
18-bit resolution with no missing codes
No pipeline delay (SAR architecture)
Differential input range: ±VREF (VREF up to 5 V)
Throughput: 100 kSPS
INL: ±2.5 LSB max (±9.5 ppm of full scale)
Dynamic range: 103 dB typ (VREF = 5 V)
S/(N+D): 100 dB typ @ 2 kHz (VREF = 5 V)
Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
On-board reference buffer
Single 5 V supply operation
Power dissipation: 18 mW @ 100 kSPS
180 μW @ 1 kSPS
48-lead LQFP or 48-lead LFCSP package
Pin-to-pin compatible upgrade of AD7674/AD7676/AD7679
APPLICATIONS
CT scanners
High dynamic data acquisition
Geophone and hydrophone sensors
- replacement (low power, multichannel)
Instrumentation
Spectrum analysis
Medical instruments
GENERAL DESCRIPTION
The AD7678 is an 18-bit, 100 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates on a
single 5 V power supply. The part contains a high speed 18-bit
sampling ADC, an internal conversion clock, an internal
reference buffer, error correction circuits, and both serial and
parallel system interface ports.
The part is available in 48-lead LQFP or 48-lead LFCSP
packages with operation specified from –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
SWITCHED
CAP DAC
18
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7678
D[17:0]
BUSY
RD
CS
MODE0
OGND
OVDD
DGNDDVDD
AVDD
AGND
REF REFGND
IN+
IN–
PD
RESET
SERIAL
PORT
PARALLEL
INTERFACE
CNVST
PDBUF
REFBUFIN
MODE1
03084–0–001
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
Type/kSPS 100–250 500–570
800–
1000
Pseudo-
Differential
AD7651
AD7660/AD7661
AD7650/AD7652
AD7664/AD7666
AD7653
AD7667
True Bipolar AD7663 AD7665 AD7671
True
Differential
AD7675 AD7676 AD7677
18-Bit AD7678 AD7679 AD7674
Multichannel/
Simultaneous
AD7654
AD7655
PRODUCT HIGHLIGHTS
1. High Resolution, Fast Throughput.
The AD7678 is a 100 kSPS, charge redistribution, 18-bit
SAR ADC (no latency).
2. Excellent Accuracy.
The AD7678 has a maximum integral nonlinearity of
2.5 LSB with no missing 18-bit codes.
3. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 2-wire serial
interface arrangement compatible with both 3 V and
5 V logic.
AD7678
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Specifications ..................................................................................... 3
Timing Specifications ....................................................................... 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Definition of Specifications ........................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information ........................................................................ 15
Converter Operation .................................................................. 15
Typical Connection Diagram ................................................... 17
Power Dissipation versus Throughput .................................... 19
Conversion Control .................................................................... 19
Digital Interface .......................................................................... 20
Parallel Interface ......................................................................... 20
Serial Interface ............................................................................ 20
Master Serial Interface ............................................................... 21
Slave Serial Interface .................................................................. 22
Microprocessor Interfacing ....................................................... 24
Application Hints ........................................................................... 25
Layout .......................................................................................... 25
Evaluating the AD7678’s Performance .................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/09—Rev. 0 to Rev. A
Removed Endnote 3 from DC Accuracy; Zero Error, TMIN to
TMAX Parameter; Table 2 ................................................................... 3
Changes to Endnote 3, Table 2 ........................................................ 4
Moved ESD Caution ......................................................................... 7
Changes to Figure 4 and Table 6 ..................................................... 8
Changes to Evaluating the AD7678’s Performance Section ...... 25
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
8/03—Revision 0: Initial Version
AD7678
Rev. A | Page 3 of 28
SPECIFICATIONS
Table 2. –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter Conditions Min Typ Max Unit
RESOLUTION 18 Bits
ANALOG INPUT
Voltage Range VIN+ – VIN– –VREF +VREF V
Operating Input Voltage VIN+, VIN– to AGND –0.1 AVDD + 0.1 V
Analog Input CMRR fIN = 100 kHz 65 dB
Input Current 100 kSPS Throughput 4 μA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle 10 μs
Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –2.5 +2.5 LSB2
Differential Linearity Error –1 +1.75 LSB
No Missing Codes 18 Bits
Transition Noise VREF = 5 V 0.7 LSB
Zero Error, TMIN to TMAX –40 ±40 LSB
Zero Error Temperature Drift ±0.5 ppm/°C
Gain Error, TMIN to TMAX3 –0.048 See Note 3 +0.048 % of FSR
Gain Error Temperature Drift ±1.6 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±4 LSB
AC ACCURACY
Signal-to-Noise fIN = 2 kHz, VREF = 5 V 101 dB4
VREF = 4.096 V 98 100 dB
fIN = 10 kHz, VREF = 4.096 V 99.5 dB
fIN = 45 kHz, VREF = 4.096 V 98 dB
Dynamic Range VIN+ = VIN– = VREF/2 = 2.5 V 103 dB
Spurious-Free Dynamic Range fIN = 2 kHz 120 dB
fIN = 10 kHz 117 dB
fIN = 45 kHz 110 dB
Total Harmonic Distortion fIN = 2 kHz –118 dB
fIN = 10 kHz –115 dB
fIN = 45 kHz –110 dB
Signal-to-(Noise + Distortion) fIN = 2 kHz 100 dB
fIN = 2 kHz, –60 dB Input 41 dB
–3 dB Input Bandwidth 900 kHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 8.5 μs
Overvoltage Recovery 8.5 μs
REFERENCE
External Reference Voltage Range REF 3 4.096 AVDD + 0.1 V
REF Voltage with Reference Buffer REFBUFIN = 2.5 V 4.05 4.096 4.15 V
Reference Buffer Input Voltage Range REFBUFIN 1.8 2.5 2.6 V
REFBUFIN Input Current –1 +1 μA
REF Current Drain 100 kSPS Throughput 42 μA
AD7678
Rev. A | Page 4 of 28
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 μA
IIH –1 +1 μA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL I
SINK = 1.6 mA 0.4 V
VOH I
SOURCE = –500 μA OVDD – 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 DVDD + 0.37 V
Operating Current 100 kSPS Throughput
AVDD PDBUF High 2.6 mA
DVDD8 1 mA
OVDD8 40 μA
PDBUF High @ 100 kSPS 18 26 mW
PDBUF High @ 1 kSPS 180 μW
PDBUF Low @ 100 kSPS 31 mW
TEMPERATURE RANGE9
Specified Performance TMIN to TMAX –40 +85 °C
1 See the Analog Inputs section.
2 LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 μV.
3 See the Definition of Specifications section. The nominal gain error is not centered at zero and is −0.029% of FSR. This specification is the deviation from this nominal
value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used.
4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5 Data format parallel or serial 18-bit.
6 Conversion results are available immediately after completed conversion.
7 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
8 Tested in Parallel Reading mode.
9 Contact factory for extended temperature range.
AD7678
Rev. A | Page 5 of 28
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter Symbol Min Typ Max Unit
Refer to Figure 27 and Figure 28
Convert Pulse Width t1 10 ns
Time between Conversions t2 10 μs
CNVST LOW to BUSY HIGH Delay t3 35 ns
BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.5 μs
Aperture Delay t5 2 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time t7 1.5 μs
Acquisition Time t8 8.5 μs
RESET Pulsewidth t9 10 ns
Refer to Figure 29, Figure 30, and Figure 31 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay t10 1.5 μs
Data Valid to BUSY LOW Delay t11 20 ns
Bus Access Request to Data Valid t12 45 ns
Bus Relinquish Time t13 5 15 ns
Refer to Figure 33 and Figure 34 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay t14 10 ns
CS LOW to Internal SCLK Valid Delay t15 10 ns
CS LOW to SDOUT Delay t16 10 ns
CNVST LOW to SYNC Delay t17 525 ns
SYNC Asserted to SCLK First Edge Delay2 t
18 3 ns
Internal SCLK Period2 t
19 25 40 ns
Internal SCLK HIGH2 t
20 12 ns
Internal SCLK LOW2 t
21 7 ns
SDOUT Valid Setup Time2 t
22 4 ns
SDOUT Valid Hold Time2 t
23 2 ns
SCLK Last Edge to SYNC Delay2 t
24 3 ns
CS HIGH to SYNC HI-Z t25 10 ns
CS HIGH to Internal SCLK HI-Z t26 10 ns
CS HIGH to SDOUT HI-Z t27 10 ns
BUSY HIGH in Master Serial Read after Convert2 t
28 See Table 4
CNVST LOW to SYNC Asserted Delay t29 1.5 μs
SYNC Deasserted to BUSY LOW Delay t30 25 ns
Refer to Figure 35 and Figure 36 (Slave Serial Interface Modes)
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 3 18 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK HIGH t36 10 ns
External SCLK LOW t37 10 ns
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
AD7678
Rev. A | Page 6 of 28
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0 0 1 1
Unit
DIVSCLK[0] Symbol 0 1 0 1
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 60 120 240 ns
Internal SCLK Period Maximum t19 40 80 160 320 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns
Busy High Width Maximum t28 2.25 3 4.5 7.5 μs
AD7678
Rev. A | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7678 Absolute Maximum Ratings1
Parameter Rating
Analog Inputs
IN+2, IN–2, REF, REFBUFIN, REFGND
to AGND
AVDD + 0.3 V to
AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD –0.3 V to +7 V
Digital Inputs –0.3 V to DVDD + 0.3 V
Internal Power Dissipation3 700 mW
Internal Power Dissipation4 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) 300°C
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those
indicated in the operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
2See Analog Inputs section.
3Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W,
θJC = 30°C/W.
4 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W.
TO OUTPUT
PIN C
L
60pF
1
500AI
OH
1.6mA I
OL
1.4V
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINEDWITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
1
03084–0–002
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
0.8V 2V
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
03084–0–003
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
AD7678
Rev. A | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AV DD
MODE0
MODE1
D0/OB/2C
NC
NC
D1/A0
D2/A1
D3
D4/DIVSCLK[0]
BUSY
D17
D16
D15
AD7678
D5/DIVSCLK[1] D14
PDBUF
AVDD
REFBUFIN
NC
AGND
IN+
NC
NC
NC
IN–
REFGND
REF
D6/EXT/INT
D7/INVSYNC
D8/INVSCLK
D9/RDC/SDIN
OGND
OVDD
DVDD
DGND
D10/SDOUT
D11/SCLK
D12/SYNC
D13/RDERROR
03084-004
NOTES
1. NC = NO CO NNE C T.
2
. T HE E X P OSED P AD IS I NTERNAL LY CO NNE CTED T O AGND. T HIS
CONNECTION IS NOT REQUIRED TO MEET THE ELECT RICA
L
PERF ORMANCES ; HOWE V E R, F OR INCREAS E D RE LIABILITY O
F
THE SOLDER JO INT S, IT IS RECOMM E NDED THAT THE PAD BE
SOLDERED TO THE ANALOG GROUND OF THE S Y STEM .
Figure 4. 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48) Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 44 AGND P Analog Power Ground Pin.
2, 47 AVDD P Input Analog Power Pins. Nominally 5 V.
3 MODE0 DI Data Output Interface Mode Selection.
4 MODE1 DI Data Output Interface Mode Selection:
Interface MODE # MODE1 MODE0 Description
0 0 0 18-Bit Interface
1 0 1 16-Bit Interface
2 1 0 Byte Interface
3 1 1 Serial Interface
5 D0/OB/2C DI/O When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the
data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos
complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is
inverted, resulting in a twos complement output from its internal shift register.
6, 7,
40–42,
45
NC No Connect.
8 D1/A0 DI/O
When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all
other modes, this input pin controls the form in which data is output, as shown in Table 7.
9 D2/A1 DI/O
When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output
bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.
10 D3 DO
In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin
is always an output, regardless of the interface mode.
11, 12 D[4:5]or
DIVSCLK[0:1]
DI/O In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after
convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock
that clocks the data output. In other serial modes, these pins are not used.
AD7678
Rev. A | Page 9 of 28
Pin No. Mnemonic Type1 Description
13 D6
or EXT/INT
DI/O In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.
14 D7
or INVSYNC
DI/O In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15 D8
or INVSCLK
DI/O In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave modes.
16 D9
or RDC/SDIN
DI/O In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH,
RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the
read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D10
or SDOUT
DO In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7678 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial
mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is
valid on the next rising edge.
22 D11
or SCLK
DI/O In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus.
When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
23 D12
or SYNC
DO In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while SDOUT output is valid.
24 D13
or RDERROR
DO In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus.
In MODE = 3 (serial mode) and when EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28 D[14:17] DO Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.
29 BUSY DO
Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground.
31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
33 RESET DI
Reset Input. When set to a logic HIGH, reset the AD7678. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
AD7678
Rev. A | Page 10 of 28
Pin No. Mnemonic Type1 Description
34 PD DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
35 CNVST DI Start Conversion. If CNVST is held HIGH when the acquisition phase (t8) is complete, the next falling
edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. If CNVST
is held LOW when the acquisition phase is complete, the internal sample/hold is put into the hold
state and a conversion is started immediately.
36 AGND P Must Be Tied to Analog Ground.
37 REF AI
Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on this pin
if the internal reference buffer is not used. Should be decoupled effectively with or without the
internal buffer.
38 REFGND AI Reference Input Analog Ground.
39 IN– AI Differential Negative Analog Input.
43 IN+ AI Differential Positive Analog Input.
46 REFBUFIN AI
Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V
typically when 2.5 V is applied on this pin.
48 PDBUF DI
Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched
off.
49
(EPAD)
Exposed Pad
(EPAD)
The exposed pad is internally connected to AGND. This connection is not required to meet the
electrical performances; however, for increased reliability of the solder joints, it is recommended that
the pad be soldered to the analog ground of the system.
1AI = Analog Input; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
Table 7. Data Bus Interface Definitions
MODE MODE1 MODE0 D0/OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description
0 0 0 R[0] R[1] R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 18-Bit Parallel
1 0 1 OB/2C A0:0 R[2] R[3] R[4:9] R[10:11] R[12:15] R[16:17] 16-Bit High Word
1 0 1 OB/2C A0:1 R[0] R[1] All Zeros 16-Bit Low Word
2 1 0 OB/2C A0:0 A1:0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit HIGH Byte
2 1 0 OB/2C A0:0 A1:1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit MID Byte
2 1 0 OB/2C A0:1 A1:0 All Hi-Z R[0:1] All Zeros 8-Bit LOW Byte
2 1 0 OB/2C A0:1 A1:1 All Hi-Z All Zeros R[0:1] 8-Bit LOW Byte
3 1 1 OB/2C All Hi-Z Serial Interface Serial Interface
R[0:17] is the 18-bit ADC value stored in its output register.
AD7678
Rev. A | Page 11 of 28
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal –full scale
(–4.095991 V for the ±4.096 V range). The last transition (from
111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (4.095977 V for the
±4.096 V range). The gain error is the deviation of the differ-
ence between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) from the actual voltage producing the
midscale output code.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input, and is expressed in bits. It is related to S/(N+D) by the
following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the AD7678 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
AD7678
Rev. A | Page 12 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
2.5
0 65536 131072 196608 262144
INL-LSB (18-Bit)
1.5
1.0
0
–2.5
0.5
–0.5
03084-0-005
–1.5
2.0
–2.0
–1.0
Figure 5. Integral Nonlinearity vs. Code
CODE IN HEX
70000
20015
COUNTS
60000
40000
20000
0
30000
10000
50000
20016 20017 20018 200192001A2001B2001C2001D2001E
V
REF
= 5V
03084-0-006
032
5919
60158 59966
3931 42
000
Figure 6. Histogram of 131,072 Conversions of a
DC Input at the Code Transition
FREQUENCY (kHz)
0
0 5 10 50
AMPLITUDE (dB of Full Scale)
–40
–60
–100
–180
–80
–120
03084-0-012
–140
–20
–160
15 20 25 30 35 40 45
f
S
= 100kSPS
f
IN
= 11kHz
V
REF
= 4.096V
SNR = 99.6dB
THD = –116dB
SFDR = 116.2dB
S/(N+D) = 99.5dB
Figure 7. FFT (11 kHz Tone)
CODE
2.0
0 65536 131072 196608 26214
4
DNL-LSB (18-Bit)
1.5
1.0
0
–1.0
0.5
–0.5
03084-0-008
Figure 8. Differential Nonlinearity vs. Code
CODE IN HEX
90000
2001B
COUNTS
60000
40000
20000
0
30000
10000
50000
2001C 2001D 2001E 2001F 20020 20021 20022 20023
V
REF
= 5V
70000
80000
03084-0-009
0 522
21862
83610
23000
1053 1
00
Figure 9. Histogram of 131,072 Conversions of a
DC Input at the Code Center
FREQUENCY (kHz)
102
0
SNR AND S/[N+D] (dB)
100
98
94
96
10 40 50
03084-0-015
ENOB
S/(N+D)
SNR
16.6
16.4
16.0
16.2
15.8
ENOB (Bits)
20 30
Figure 10. SNR, S/(N+D), and ENOB vs. Frequency
AD7678
Rev. A | Page 13 of 28
FREQUENCY (kHz)
–80
0
THD, HARMONICS (dB)
–90
–120
–150
–140
–100
10 40 50
03084-0-016
–110
–130
THD
THIRD
HARMONIC SECOND
HARMONIC
20 30
Figure 11. THD and Harmonics vs. Frequency
INPUT LEVEL (dB)
–60
SNR REFERRED TO FULL SCALE (dB)
101
98
100
03084-0-017
99
SNR
–50 0–10–20–30–40
104
102
103
V
REF
= 4.096V
S/(N+D)
Figure 12. SNR and S/(N+D) vs. Input Level
–55
SNR, S/[N+D] (dB)
99
97
03084-0-018
100
98
–35 12585655–15
101 SNR
ENOB
14.5
15.0
15.5
16.5
16.0
S/(N+D)
25 45 105
TEMPERATURE (C)
Figure 13. SNR, S/(N+D), and ENOB vs. Temperature
TEMPERATURE (C)
–55
THD, HARMONICS (dB)
–120
–140
03084-0-019
–110
–130
–35 12585655–15
–100
25 45 105
THIRD
HARMONIC
SECOND
HARMONIC
THD
Figure 14. THD and Harmonics vs. Temperature
SAMPLING RATE (SPS)
10000
OPERATING CURRENT (
A)
0.001
1000
100
0.1
0.01
100k10k1k1001 10
AVDD
03084-0-020
DVDD
OVDD
10
1
Figure 15. Operating Current vs. Sampling Rate
TEMPERATURE (
C)
1000
–55
POWER-DOWN OPERATING CURRENTS (nA)
800
0
400
200
600
125
DVDD
–35–155 25456585105
AVDD
OVDD
03084-0-021
Figure 16. Power-Down Operating Currents vs. Temperature
AD7678
Rev. A | Page 14 of 28
TEMPERATURE (
C)
–55
ZERO ERROR, GAIN ERROR (LSB)
–30
–50
03083-0-022
–40
–35 12585655–15
50
25 45 105
–10
10
–20
0
20
30
40
GAIN ERROR
ZERO ERROR
Figure 17. Zero Error and Gain Error vs. Temperature
C
L
(pF)
0
t
12
DELAY (ns)
10
0
03084-0-024
20015050
50
100
30
20
40 OVDD = 2.7V @ 85°C
OVDD = 5V @ 85°C
OVDD = 5V @ 25°C
OVDD = 2.7V @ 25°C
Figure 18. Typical Delay vs. Load Capacitance CL
AD7678
Rev. A | Page 15 of 28
CIRCUIT INFORMATION
IN+
REF
REFGND
IN–
MSB 4C 2C C C LSB SW+ SWITCHES
CONTROL
262,144C 131,072C
MSB
4C 2C C C LSB SW–
BUSY
OUTPUT
CODE
CNVST
CONTROL
LOGIC
COMP
262,144C 131,072C
03084–0–025
Figure 19. ADC Simplified Schematic
The AD7678 is a very fast, low power, single-supply, precise
18-bit analog-to-digital converter (ADC) using successive
approximation architecture.
The AD7678’s linearity and dynamic range are similar or better
than many - ADCs. With the advantages of its successive
architecture, which ease multiplexing and reduce power with
throughput, it can be advantageous in applications that
normally use - ADCs.
The AD7678 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7678 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP, or a tiny 48-lead LFCSP package that offers space
savings and allows for flexible configurations as either a serial
or parallel interface. The AD7678 is pin-to-pin compatible with
the AD7674, AD7676, and AD7679.
CONVERTER OPERATION
The AD7678 is a successive approximation ADC based on a
charge redistribution DAC. Figure 19 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW–.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN– inputs. When the
acquisition phase is complete and the CNVST input goes low, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW– are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the REFGND input. Therefore, the differential voltage between
the IN+ and IN– inputs captured at the end of the acquisition
phase is applied to the comparator inputs, causing the
comparator to become unbalanced. By switching each element
of the capacitor array between REFGND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4...VREF/262144). The control logic toggles these
switches, starting with the MSB first, to bring the comparator
back into a balanced condition. After completing this process,
the control logic generates the ADC output code and brings the
BUSY output low.
AD7678
Rev. A | Page 16 of 28
Transfer Functions
Except in 18-bit interface mode, the AD7678 offers straight
binary and twos complement output coding when using OB/2C.
See Figure 20 and Table 8 for the ideal transfer characteristic.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB–FS
–FS + 0.5 LSB
ADC CODE (Straight Binary)
03084-0-026
Figure 20. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 4.096 V
Straight
Binary
(Hex)
Twos
Complement
(Hex)
FSR –1 LSB 4.095962 V 3FFFF1 1FFFF1
FSR – 2 LSB 4.095924 V 3FFFE 1FFFE
Midscale +
1 LSB
31.25 μV 20001 00001
Midscale 0 V 20000 00000
Midscale –
1 LSB
–31.25 μV 1FFFF 3FFFF
–FSR + 1 LSB -4.095962 V 00001 20001
–FSR -4.096 V 000002 200002
1 This is also the code for overrange analog input (VIN+ – VIN–
above VREF – VREFGND).
2 This is also the code for underrange analog input (VIN+ – VIN–
below –VREF + VREFGND).
AVDD AGND DGND DVDD OVDD OGND
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
2.5V REF
NOTE 1
REFBUFIN
20
CLOCK
AD7678
C/P/DSP
SERIAL PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
DVDD
OB/2C
PDBUF
DVDD
50k
100nF
1M
IN+
ANALOG INPUT+
C
C
U1
NOTE 4
50
AD8021
–
+
NOTE 3
NOTE 5
ADR421
10F100nF
+10F 100nF
+100nF +10F
IN–
ANALOG INPUT–
C
C
U2
NOTE 4
50
AD8021
–
+
100nF
10F
MODE1
MODE0
NOTE 2
C
REF
REF
REFGND
03084-0-027
NOTES
1. SEE VOLTAGE REFERENCE SECTION.
2. C
REF
is 10F CERAMIC CAPACITOR OR LOW ESR TANTALUM. CERAMIC SIZE
1206 PANASONIC ECJ-3xB0J106 IS RECOMMENDED. SEE VOLTAGE REFERENCE SECTION.
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. OPTION, SEE POWER SUPPLY SECTION.
Figure 21. Typical Connection Diagram (Internal Reference Buffer, Serial Interface)
AD7678
Rev. A | Page 17 of 28
TYPICAL CONNECTION DIAGRAM
Figure 21 shows a typical connection diagram for the AD7678.
Different circuitry shown on this diagram is optional and is
discussed later in this data sheet.
Analog Inputs
Figure 22 shows a simplified analog input section of the
AD7678. The diodes shown in Figure 22 provide ESD protec-
tion for the inputs. Care must be taken to ensure that the analog
input signal never exceeds the absolute ratings on these inputs.
This will cause these diodes to become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 120 mA max. This condition could eventually occur
when the input buffer’s U1 or U2 supplies are different from
AVDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.
IN+
IN–
AGND
AVDD
R+ = 3k
C
S
C
S
R– = 3k
03084-0-028
Figure 22. Simplified Analog Input
This analog input structure is a true differential structure. By
using these differential inputs, signals common to both inputs
are rejected as shown in Figure 23, which represents typical
CMRR over frequency.
FREQUECY (kHz)
80
CMRR (dB)
75
50 100 1000 10000110
70
65
60
55
03084-0-029
Figure 23. Analog Input CMRR vs. Frequency
During the acquisition phase for ac signals, the AD7678 behaves
like a 1-pole RC filter consisting of the equivalent resistance,
R+, R–, and CS. Resistors R+ and R– are typically 3 k and are
lumped components made up of a serial resistor and the on
resistance of the switches. CS is typically 60 pF and mainly
consists of the ADC sampling capacitor. This 1-pole filter with a
–3 dB cutoff frequency of 900 kHz typ reduces any undesirable
aliasing effect and limits the noise coming from the inputs.
Because the input impedance of the AD7678 is very high, the
part can be driven directly by a low impedance source without
gain error.
Driver Amplifier Choice
Although the AD7678 is easy to drive, the driver amplifier
needs to meet the following requirements:
The driver amplifier and the AD7678 analog input circuit
have to be able to settle for a full-scale step of the capacitor
array at an 18-bit level (0.0004%). In the amplifier’s data
sheet, settling at 0.1% or 0.01% is more commonly
specified. This could differ significantly from the settling
time at an 18-bit level and, therefore, should be verified
prior to driver selection. The tiny op amp AD8021, which
combines ultralow noise and high gain-bandwidth, meets
this settling time requirement.
The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7678. The noise
coming from the driver is filtered by the AD7678 analog
input circuit 1-pole low-pass filter made by R+, R–, and CS.
The SNR degradation due to the amplifier is
2
)(625
25
log20
N
3dB–
LOSS
Ne
f
SNR
where:
f–3dB is the –3 dB input bandwidth in MHz of the AD7678
(0.9 MHz).
N is the noise factor of the amplifiers (1 if in buffer
configuration).
eN is the equivalent input noise voltage of each op amp in
nV/Hz.
For instance, for a driver with an equivalent input noise of
6 nV/Hz (e.g., AD8610) configured as a buffer, thus with
a noise gain of +1, the SNR degrades by only 0.65 dB.
The driver needs to have a THD performance suitable to
that of the AD7678.
AD7678
Rev. A | Page 18 of 28
The AD8021 meets these requirements and is usually appropri-
ate for almost all applications. The AD8021 needs a 10 pF
external compensation capacitor, which should have good
linearity as an NPO ceramic or mica type.
The AD8022 could be used if a dual version is needed and gain
of 1 is present. The AD829 is an alternative in applications
where high frequency (above 100 kHz) performance is not
required. In gain of 1 applications, it requires an 82 pF
compensation capacitor. The AD8610 is another option when
low bias current is needed in low frequency applications.
Single-to-Differential Driver
For applications using unipolar analog signals, a single-ended-
to-differential driver will allow for a differential input into the
part. The schematic is shown in Figure 24. When provided an
input signal of 0 to VREF, this configuration will produce a
differential ±VREF with midscale at VREF/2.
If the application can tolerate more noise, the AD8138
differential driver can be used.
U2
8.25k
2.5V
AD8021
590
AD7678
IN+
IN– REF
U1
ANALOG INPUT
(UNIPOLAR
0V TO 4.096V) 10pF
AD8021
590
10pF 10
F
100nF
1.82k
REFBUFIN
03084-0-030
Figure 24. Single-Ended-to-Differential Driver Circuit
(Internal Reference Buffer Used)
Voltage Reference
The AD7678 allows the use of an external voltage reference with
or without the internal reference buffer.
Using the internal reference buffer is recommended when
sharing a common reference voltage between multiple ADCs is
desired.
However, the advantages of using the external reference voltage
directly are
The SNR and dynamic range improvement (about 1.7 dB)
resulting from the use of a reference voltage very close to
the supply (5 V) instead of a typical 4.096 V reference
when the internal buffer is used.
The power saving when the internal reference buffer is
powered down (PDBUF HIGH).
To use the internal reference buffer, PDBUF should be LOW. A
2.5 V reference voltage applied on the REFBUFIN input will
result in a 4.096 V reference on the REF pin.
In both cases, the voltage reference input REF has a dynamic
input impedance and therefore requires an efficient decoupling
between REF and REFGND inputs. The decoupling consists of
a low ESR 47 μF tantalum capacitor connected to the REF and
REFGND inputs with minimum parasitic inductance.
Care should also be taken with the reference temperature
coefficient of the voltage reference, which directly affects the
full-scale accuracy if this parameter matters. For instance, a
±4 ppm/°C temperature coefficient of the reference changes the
full scale by ±1 LSB/°C.
Power Supply
The AD7678 uses three sets of power supply pins: an analog 5 V
supply (AVDD), a digital 5 V core supply (DVDD), and a digital
output interface supply (OVDD). The OVDD supply defines
the output logic level and allows direct interface with any logic
working between 2.7 V and DVDD + 0.3 V. To reduce the
number of supplies needed, the digital core (DVDD) can be
supplied through a simple RC filter from the analog supply, as
shown in Figure 21. The AD7678 is independent of power
supply sequencing once OVDD does not exceed DVDD by
more than 0.3 V, and is therefore free from supply voltage
induced latch-up. Additionally, it is very insensitive to power
supply variations over a wide frequency range, as shown in
Figure 25.
FREQUECY (kHz)
65
PSRR (dB)
40 100 1000 10000110
60
55
50
45
03084-0-031
Figure 25. PSRR vs. Frequency
AD7678
Rev. A | Page 19 of 28
POWER DISSIPATION VERSUS THROUGHPUT
The AD7678 automatically reduces its power consumption at
the end of each conversion phase. During the acquisition phase,
the operating currents are very low, which allows for a signifi-
cant power savings when the conversion rate is reduced, as
shown in Figure 26. This feature makes the AD7678 ideal for
very low power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be
driven close to the power rails (DVDD and DGND), and
OVDD should not exceed DVDD by more than 0.3 V.
SAMPLING RATE (SPS)
POWER DISSIPATION (mW)
100000
10000
1000
100
10
1
0.1 100
k
10k1k1001 10
PDBUF HIGH
03084-0-032
Figure 26. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 27 shows the detailed timing diagrams of the conversion
process. The AD7678 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the
conversion is complete. The CNVST signal operates
independently of the CS and RD signals.
CNVST
t
1
t
2
MODE ACQUIRE CONVERT ACQUIRE CONVERT
t
7
t
8
BUSY
t
4
t
3
t
5
t
6
03084-0-033
Figure 27. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels with minimum
overshoot and undershoot or ringing.
For other applications, conversions can be automatically
initiated. If CNVST is held low when BUSY is low, the AD7678
controls the acquisition phase and then automatically initiates a
new conversion. By keeping CNVST low, the AD7678 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up, CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7678 could sometimes
run slightly faster than the guaranteed limits of 100 kSPS.
t
9
RESET
DATA
BUS
BUSY
CNVST
t
8
03084-0-034
Figure 28. RESET Timing
AD7678
Rev. A | Page 20 of 28
DIGITAL INTERFACE
The AD7678 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7678 digital interface also accommodates both 3 V and 5 V
logic by simply connecting the AD7678’s OVDD supply pin to
the host system interface digital supply. Finally, by using the
OB/2C input pin in any mode except 18-bit interface mode,
both twos complement and straight binary coding can be used.
The two signals, CS and RD, control the interface. When at least
one of these signals is high, the interface outputs are in high
impedance. Usually, CS allows the selection of each AD7678 in
multicircuit applications, and is held low in a single AD7678
design. RD is generally used to enable the conversion result on
the data bus.
CNVST
BUSY
DATA
BUS
CS = RD = 0
PREVIOUS CONVERSION DATA NEW DATA
t
1
t
10
t
4
t
3
t
11
03084-0-035
Figure 29. Master Parallel Data Timing for Reading (Continuous Read)
PARALLEL INTERFACE
The AD7678 is configured to use the parallel interface with an
18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The
data can be read either after each conversion, which is during
the next acquisition phase, or during the following conversion,
as shown in Figure 30 and Figure 31, respectively. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion phase.
This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry. Refer to Table 7 for a detailed description
of the different options available.
DATA
BUS
t
12
t
13
BUSY
CS
RD
CURRENT
CONVERSION
03084-0-036
Figure 30. Slave Parallel Data Timing for Reading (Read after Convert)
CS = 0
CNVST,
RD
t
1
PREVIOUS
CONVERSION
DATA
BUS
t
12
t
13
BUSY t
4
t
3
03084-0-037
Figure 31. Slave Parallel Data Timing for Reading (Read during Convert)
CS
RD
A0, A1
PINS D[15:8]
PINS D[7:0] HI-Z
HI-Z HIGH BYTE LOW BYTE
LOW BYTE HIGH BYTE HI-Z
HI-Z
t
12
t
12
t
13
03084-0-038
Figure 32. 8-Bit and 16-Bit Parallel Interface
SERIAL INTERFACE
The AD7678 is configured to use the serial interface when
MODE0 and MODE1 are held high. The AD7678 outputs 18
bits of data, MSB first, on the SDOUT pin. This data is
synchronized with the 18 clock pulses provided on the SCLK
pin. The output data is valid on both the rising and falling edge
of the data clock.
AD7678
Rev. A | Page 21 of 28
MASTER SERIAL INTERFACE
Internal Clock
The AD7678 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7678 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. Depending on the
RDC/SDIN input, the data can be read after each conversion or
during the following conversion. Figure 33 and Figure 34 show
the detailed timing diagrams of these two modes.
Usually, because the AD7678 is used with a fast throughput, the
mode master read during conversion is the most recommended
serial mode.
In Read during Conversion mode, the serial clock and data
toggle at appropriate instants, minimizing potential
feedthrough between digital activity and critical conversion
decisions.
In Read after Conversion mode, it should be noted that unlike
in other modes, the BUSY signal returns low after the 18 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
123 161718
D17 D16 D2 D1 D0X
EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
14
t
20
t
15
t
16
t
22
t
23
t
29
t
28
t
18
t
19
t
21
t
30
t
25
t
24
t
26
t
27
03084-0-039
Figure 33. Master Serial Data Timing for Reading (Read after Convert)
AD7678
Rev. A | Page 22 of 28
RDC/SDIN = 1 INVSCLK = INVSYNC = 0
D17 D16 D2 D1 D0X
123 161718
BUSY
SYNC
SCLK
S
DOUT
CS, RD
CNVST
t
3
t
1
t
17
t
14
t
15
t
19
t
20
t
21
t
16
t
22
t
23
t
24
t
27
t
26
t
25
t
18
EXT/INT = 0
03084-0-040
Figure 34. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
SLAVE SERIAL INTERFACE
External Clock
The AD7678 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read
the data. The external serial clock is gated by CS. When CS and
RD are both low, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally high or normally low when
inactive. Figure 35 and Figure 36 show the detailed timing
diagrams of these methods.
While the AD7678 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7678 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is recom-
mended that when an external clock is being provided, it is a
discontinuous clock that only toggles when BUSY is low or,
more importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read after
Conversion
This mode is the most recommended of the serial slave modes.
Figure 35 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both CS and
RD are low. Data is shifted out MSB first with 18 clock pulses,
and is valid on both the rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process. Also,
data can be read at speeds up to 40 MHz, accommodating both
slow digital host interface and the fastest serial reading.
Finally, in this mode only, the AD7678 provides a daisy-chain
feature using the RDC/SDIN input pin to cascade multiple
converters together. This feature is useful for reducing
component count and wiring connections when desired (for
instance, in isolated multiconverter applications).
An example of the concatenation of two devices is shown in
Figure 37. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite the one used to
shift out data on SDOUT. Thus, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
AD7678
Rev. A | Page 23 of 28
SCLK
SDOUT D17 D16 D1 D0D15
X17 X16 X15 X1 X0 Y17 Y16
BUSY
SDIN
INVSCLK = 0
X17 X16X
123 1617181920
EXT/INT = 1 RD = 0
t
35
t
36
t
37
t
31
t
32
t
34
t
16
t
33
CS
03084-0-041
Figure 35. Slave Serial Data Timing for Reading (Read after Convert)
SDOUT
SCLK
D1 D0X D17 D16 D15
123 161718
BUSY
INVSCLK = 0
EXT/INT = 1 RD = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
3
CS
CNVST
03084-0-042
Figure 36. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
AD7678
Rev. A | Page 24 of 28
BUSY BUSY
AD7678
#2 (UPSTREAM)
AD7678
#1 (DOWNSTREAM)
RDC/SDIN SDOUT
CNVST
CS
SCLK
RDC/SDIN SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
03084-0-043
Figure 37. Two AD7678s in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 36 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done,
RDERROR is pulsed high and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy-
chain feature in this mode, and the RDC/SDIN input should
always be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been
initiated.
MICROPROCESSOR INTERFACING
The AD7678 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7678 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7678 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of the
AD7678 with an SPI equipped DSP, the ADSP-219x.
SPI Interface (ADSP-219x)
Figure 38 shows an interface diagram between the AD7678 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7678 acts as a slave device, and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command could be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process could be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-219x is configured for master
mode (MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase
bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI control register (SPICLTx). It should be noted
that to meet all timing requirements, the SPI clock should be
limited to 17 Mbits/s, which allow it to read an ADC result in
about 1.1 μs.
AD7678*
ADSP-219x*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
03084-0-044
Figure 38. Interfacing the AD7678 to an SPI Interface
AD7678
Rev. A | Page 25 of 28
APPLICATION HINTS
LAYOUT
The AD7678 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The printed circuit board that houses the AD7678 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. Digital and
analog ground planes should be joined in only one place,
preferably underneath the AD7678, or at least as close to the
AD7678 as possible. If the AD7678 is in a system where
multiple devices require analog-to-digital ground connections,
the connection should still be made at one point only, a star
ground point that should be established as close to the AD7678
as possible.
The user should avoid running digital lines under the device,
because these will couple noise onto the die. The analog ground
plane should be allowed to run under the AD7678 to avoid
noise coupling. Fast switching signals like CNVST or clocks
should be shielded with digital ground to avoid radiating noise
to other sections of the board, and should never run near
analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other. This will reduce
the effect of feedthrough through the board. The power supply
lines to the AD7678 should use as large a trace as possible to
provide low impedance paths and reduce the effect of glitches
on the power supply lines. Good decoupling is also important
to lower the supply’s impedance presented to the AD7678 and
to reduce the magnitude of the supply spikes. Decoupling
ceramic capacitors, typically 100 nF, should be placed close to
and ideally right up against each power supply pin (AVDD,
DVDD, and OVDD) and their corresponding ground pins.
Additionally, low ESR 10 μF capacitors should be located near
the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7678 can be a separate supply or
can come from the analog supply, AVDD, or the digital
interface supply, OVDD. When the system digital supply is
noisy or when fast switching digital signals are present, and if
no separate supply is available, the user should connect the
DVDD digital supply to the analog supply AVDD through an
RC filter (see Figure 21), and connect the system supply to the
interface digital supply OVDD and the remaining digital
circuitry. When DVDD is powered from the system supply, it is
useful to insert a bead to further reduce high frequency spikes.
The AD7678 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage and
should be a low impedance return to the reference because it
carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground plane
depending on the configuration. OGND is connected to the
digital system ground.
The layout of the decoupling of the reference voltage is
important. The decoupling capacitor should be close to the
ADC and should be connected with short and large traces to
minimize parasitic inductances.
EVALUATING THE AD7678’S PERFORMANCE
The evaluation board for the AD7678 allows a quick means to
measure both dc (histograms and time domain) and ac (time
and frequency domain) performances of the converter. The
EVAL-AD7678CBZ is an evaluation board package that includes
a fully assembled and tested evaluation board, documentation,
and software. The accompanying software requires the use of a
capture board that must be ordered seperately from the evalua-
tion board (see the Ordering Guide for information). The
evaluation board can also be used in a standalone configuration
and does not use the software when in this mode. Refer to the
EVAL-AD76XXEDZ and EVAL-AD76XXCBZ data sheets
available from www.analog.com for evaluation board details.
Two types of data capture boards can be used with the EVAL-
AD7678CBZ:
USB based (EVAL-CED1Z recommended)
Parallel port based (EVAL-CONTROL BRD3Z not
recommended because many newer PCs do not include
parallel ports any longer)
The recommended board layout for the AD7678 is outlined in
the evaluation board data sheet.
AD7678
Rev. A | Page 26 of 28
OUTLINE DIMENSIONS
COMP LI ANT TO JE DE C S TANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12 13 25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD P ITCH
1.60
MAX
0.75
0.60
0.45
VIEW A
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
RO TATE D 9 0° CCW
SEATING
PLANE
7°
3.5°
0°
0.15
0.05
9.20
9.00 S Q
8.80
7.20
7.00 SQ
6.80
051706-A
Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW 6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° M AX
0.20 REF
0.80 M A X
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 M A X
0.02 NOM
0.60 M A X
0.60 MA X PI N 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COM PLI ANT T O JEDEC S TANDARDS MO-220-V KKD- 2
080108-A
FO R P ROPER CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATIO N AND
FUNCT I O N DES CRI PT I O NS
SECTIO N OF THIS DATA SHEE T.
Figure 40. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7678ASTZ1 –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD7678ASTZRL1 –40°C to +85°C 48-Lead Low Profile Quad Flat Package [LQFP] ST-48
AD7678ACPZ1 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
AD7678ACPZRL1 –40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
EVAL-AD7678CBZ2 Evaluation Board
EVAL-CONTROL BRD2Z1, 3 Parallel Port Capture Board, 32k RAM
EVAL-CONTROL BRD3Z1, 3 Parallel Port Capture Board, 128k RAM
EVAL-CED1Z1, 3 USB Data Capture Board
1 Z = RoHS Compliant Part.
2This board can be used as a standalone evaluation board or in conjunction with the a capture board for evaluation/demonstration purposes.
3These capture board allow the PC to control and communicate with all Analog Devices evaluation boards ending in ED for EVAL-CED1Z and CB for EVAL-CONTROL
BRDxZ (x = 2, 3).
AD7678
Rev. A | Page 27 of 28
NOTES
AD7678
Rev. A | Page 28 of 28
NOTES
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
D03084-0-6/09(A)
