71M6511/71M6511H Demo Board User's Manual 71M6511/71M6511H Demo Board USER'S MANUAL 6/19/2007 11:13 AM Revision 5.4 TERIDIAN Semiconductor Corporation 6440 Oak Canyon Rd., suite 100 Irvine, CA 92618-5201 Phone: (714) 508-8800 Fax: (714) 508-8878 http://www.teridian.com/ meter.support@teridian.com Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 1 of 115 71M6511/71M6511H Demo Board User's Manual TERIDIAN Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company's warranty detailed in the TERIDIAN Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Page: 2 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 71M6511 Single-Phase Energy Meter IC DEMO BOARD USER'S MANUAL Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 3 of 115 71M6511/71M6511H Demo Board User's Manual Table of Contents 1 GETTING STARTED ........................................................................................................................................ 9 1.1 General............................................................................................................................................................. 9 1.2 Safety and ESD Notes..................................................................................................................................... 9 1.3 Demo Kit Contents ........................................................................................................................................ 10 1.4 Demo Board Versions................................................................................................................................... 10 1.5 Compatibility ................................................................................................................................................. 10 1.6 Suggested Equipment and Test Tools not Included.................................................................................. 11 1.7 Demo Board Test Setup................................................................................................................................ 11 1.7.1 Power Supply Setup................................................................................................................................. 14 1.7.2 Cable for Serial Connection (Debug Board) ............................................................................................. 14 1.7.3 Checking Operation ................................................................................................................................. 15 1.7.4 Serial Connection Setup........................................................................................................................... 15 1.8 Using the Demo Board.................................................................................................................................. 16 1.8.1 Serial Command Language...................................................................................................................... 16 1.8.2 Using the Demo Board for Energy Measurements ................................................................................... 25 1.8.3 Using the Demo Board in CT Mode ......................................................................................................... 25 1.8.4 Adjusting the Demo Board to Different Current Transformers.................................................................. 25 1.8.5 Adjusting the Kh Factor for the Demo Board............................................................................................ 26 1.8.6 Using the Demo Board in Current Shunt Mode ........................................................................................ 26 1.8.7 Adjusting the Demo Board to Different Voltage Dividers .......................................................................... 29 1.9 Calibration Parameters ................................................................................................................................. 30 1.9.1 General Calibration Procedure................................................................................................................. 30 1.9.2 Calibration Macro File .............................................................................................................................. 31 1.9.3 Updating the 6511_demo.hex file............................................................................................................. 32 1.9.4 Updating Calibration Data in flash Memory without using the ICE ........................................................... 32 1.9.5 Automatic GAINS Calibration ................................................................................................................... 32 1.9.6 Loading the 6511_demo.hex file into the Demo Board............................................................................. 33 1.9.7 The Programming Interface of the 71M6511/6511H ................................................................................ 34 1.10 Demo Code................................................................................................................................................. 35 1.10.1 Demo Code Description........................................................................................................................ 35 1.10.2 Demo Code MPU Parameters .............................................................................................................. 36 1.10.3 Useful CLI Commands Involving the MPU and CE............................................................................... 43 2 APPLICATION INFORMATION ...................................................................................................................... 45 2.1 Calibration Theory......................................................................................................................................... 45 2.1.1 Calibration with Three Measurements...................................................................................................... 45 2.1.2 Calibration with Five Measurements ........................................................................................................ 47 2.2 Calibration Procedures................................................................................................................................. 48 2.2.1 Calibration Procedure with Three Measurements .................................................................................... 49 2.2.2 Calibration Procedure with Five Measurements ....................................................................................... 50 2.2.3 Calibration Spreadsheets ......................................................................................................................... 50 2.2.4 Compensating for Non-Linearities ............................................................................................................ 52 2.2.5 Calibrating Meters with Combined CT and Shunt Resistor ...................................................................... 53 Page: 4 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 2.3 Power Saving Measures ............................................................................................................................... 57 2.4 Schematic Information.................................................................................................................................. 58 2.4.1 Components for the V1 Pin ...................................................................................................................... 58 2.4.2 Reset Circuit............................................................................................................................................. 58 2.4.3 Oscillator .................................................................................................................................................. 59 2.4.4 EEPROM ................................................................................................................................................. 59 2.4.5 LCD.......................................................................................................................................................... 60 2.4.6 Optical Interface ....................................................................................................................................... 61 2.4.7 Connecting the RX Pin ............................................................................................................................. 62 2.5 Testing the Demo Board............................................................................................................................... 64 2.5.1 Functional Meter Test .............................................................................................................................. 64 2.5.2 EEPROM ................................................................................................................................................. 65 2.5.3 RTC.......................................................................................................................................................... 66 2.5.4 Hardware Watchdog Timer ...................................................................................................................... 66 2.5.5 LCD.......................................................................................................................................................... 66 2.6 TERIDIAN Application Notes ........................................................................................................................ 68 3 HARDWARE DESCRIPTION.......................................................................................................................... 69 3.1 4-Layer Board Description: Jumpers, Switches, Test Points.................................................................... 69 3.2 2-Layer Board Description: Jumpers, Switches, Test Points.................................................................... 73 3.3 Board Hardware Specifications (4-Layer) ................................................................................................... 77 3.4 Board Hardware Specifications (2-Layer) ................................................................................................... 78 4 DEMO BOARD ELECTRICAL SECTION ....................................................................................................... 79 4.1 71M6511 4-Layer Demo Board Electrical Schematic.................................................................................. 80 4.2 71M6511 2-Layer Demo Board with Capacitive Power Supply - Electrical Schematic............................ 83 4.3 71M6511 2-Layer Demo Board with Transformer - Electrical Schematics ............................................... 86 4.4 71M6511 4-Layer Demo Board Bill of Material ............................................................................................ 89 4.5 BOM for 71M6511 2-Layer Demo Board (Capacitive Power Supply) ........................................................ 90 4.6 BOM for 71M6511 2-Layer Demo Board (Transformer Power Supply) ..................................................... 91 4.7 71M6511 4-Layer Demo Board PCB Layout ................................................................................................ 93 4.8 PCB Layout for the 71M6511 2-Layer Demo Board (Capacitive Power Supply) ...................................... 99 4.9 PCB Layout for the 71M6511 2-Layer Demo Board (transformer Power Supply) .................................. 104 4.10 Debug Board Bill of Material................................................................................................................... 108 4.11 Debug Board Schematics ....................................................................................................................... 109 4.12 Debug Board PCB Layout ....................................................................................................................... 110 4.13 TERIDIAN 71M6511/6511H Pin-Out Information.................................................................................... 113 Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 5 of 115 71M6511/71M6511H Demo Board User's Manual List of Figures Figure 1-1: Demo Board Versions. 4-layer (left), 2-layer (right).................................................................................... 10 Figure 1-2: 4-Layer Demo Board: Basic Connections .................................................................................................. 11 Figure 1-3: 2-Layer Demo Board: Basic Connections .................................................................................................. 12 Figure 1-4: 2-Layer Demo Board: Ribbon Cable Connections ..................................................................................... 12 Figure 1-5: The TERIDIAN 6511 Demo Board with Debug Board Block Diagram (CT Configuration) ......................... 13 Figure 1-6: Hyperterminal Sample Window with Disconnect Button............................................................................. 15 Figure 1-7: Port Speed/Handshake Setup (left) and Port Bit Setup (right) ................................................................... 16 Figure 1-8: Command Line Interface Help Display....................................................................................................... 17 Figure 1-9: Current Shunt Operation Mode (Shown for the 6511 2-Layer PCB) .......................................................... 28 Figure 1-10: Current Shunt Top-Level Schematics (Shown for the 2-Layer Board) ..................................................... 29 Figure 1-11: Typical Calibration Macro file................................................................................................................... 31 Figure 1-12: Emulator Window Showing Reset and Erase Buttons.............................................................................. 33 Figure 1-13: Emulator Window Showing Erased Flash Memory and File Load Menu.................................................. 34 Figure 2-1: Watt Meter with Gain and Phase Errors.................................................................................................... 45 Figure 2-2: Phase Angle Definitions............................................................................................................................. 49 Figure 2-3: Calibration Spreadsheet for Three Measurements .................................................................................... 51 Figure 2-4: Calibration Spreadsheet for Five Measurements ....................................................................................... 51 Figure 2-5: Non-Linearity Caused by Quantification Noise........................................................................................... 52 Figure 2-6: 71M6511 with Shunt and CT ..................................................................................................................... 53 Figure 2-7: Voltage Divider for V1 ................................................................................................................................ 58 Figure 2-8: External Components for RESETZ ............................................................................................................ 58 Figure 2-9: Oscillator Circuit......................................................................................................................................... 59 Figure 2-10: EEPROM Circuit ...................................................................................................................................... 59 Figure 2-11: LCD Connections..................................................................................................................................... 60 Figure 2-12: LCD Boost and LCD Control Registers.................................................................................................... 60 Figure 2-13: Optical Interface Block Diagram .............................................................................................................. 61 Figure 2-14: Optical Port Circuitry on the 4-Layer Demo Board ................................................................................... 61 Figure 2-15: Optical Port Circuitry on the 2-Layer Demo Board ................................................................................... 62 Figure 2-16: Internal Diode Clamp on the RX Pin ........................................................................................................ 62 Figure 2-17: Resistor Network for RX .......................................................................................................................... 63 Figure 2-18: Meter with Calibration System ................................................................................................................. 64 Figure 2-19: Calibration System Screen ...................................................................................................................... 65 Figure 3-1: 71M6511 4-Layer Demo Board: Board Description ................................................................................... 72 Figure 3-2: D6511T4A8 Two-Layer Demo Board with Capacitive Power Supply ......................................................... 75 Figure 3-3: 71M6511 Two-Layer Demo Board with Transformer Power Supply .......................................................... 76 Figure 4-1: 71M6511 4-Layer Demo Board: Electrical Schematic 1/3.......................................................................... 80 Figure 4-2: 71M6511 4-Layer Demo Board: Electrical Schematic 2/3.......................................................................... 81 Figure 4-3: 71M6511 4-Layer Demo Board: Electrical Schematic 3/3.......................................................................... 82 Figure 4-4: D6511T4A8 2-Layer Demo Board (Capacitve Power Supply): Electrical Schematic 1/3 ........................... 83 Figure 4-5: D6511T4A8 2-Layer Demo Board (Capacitve Power Supply): Electrical Schematic 2/3 ........................... 84 Figure 4-6: D6511T4A8 2-Layer Demo Board (Capacitve Power Supply): Electrical Schematic 3/3 ........................... 85 Figure 4-7: 71M6511 2-Layer Demo Board (Xformer Power Supply): Electrical Schematic 1/3................................... 86 Figure 4-8: 71M6511 2-Layer Demo Board (Transformer Power Supply): Electrical Schematic 2/3 ............................ 87 Figure 4-9: 71M6511 2-Layer Demo Board (Xformer Power Supply): Electrical Schematic 3/3................................... 88 Page: 6 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-10: 71M6511 4-Layer Demo Board: Top View............................................................................................... 93 Figure 4-11: 71M6511 4-Layer Demo Board: Bottom View.......................................................................................... 94 Figure 4-12: 71M6511 4-Layer Demo Board: Top Signal Layer................................................................................... 95 Figure 4-13: 71M6511 4-Layer Demo Board: Middle Layer 1, Ground Plane. ............................................................. 96 Figure 4-14: 71M6511 4-Layer Demo Board: Middle Layer 2, Supply Plane ............................................................... 97 Figure 4-15: 71M6511 4-Layer Demo Board: Bottom Signal Layer.............................................................................. 98 Figure 4-16: DM6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Top View............................................. 99 Figure 4-17: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Top Copper Layer ................................ 100 Figure 4-18: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Top Silk-Screen View........................... 101 Figure 4-19: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Bottom Copper Layer........................... 102 Figure 4-20: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Bottom Silk Screen .............................. 103 Figure 4-21: 71M6511 2-Layer Demo Board (Xformer Power Supply): Top View ...................................................... 104 Figure 4-22: 71M6511 2-Layer Demo Board (Xformer Power Supply): Bottom View................................................. 105 Figure 4-23: 71M6511 2-Layer Demo Board (Xformer Power Supply): Top Copper View ......................................... 106 Figure 4-24: 71M6511 2-Layer Demo Board (Xformer Power Supply): Bottom Copper View .................................... 107 Figure 4-25: Debug Board: Electrical Schematic........................................................................................................ 109 Figure 4-26: Debug Board: Top View......................................................................................................................... 110 Figure 4-27: Debug Board: Bottom View.................................................................................................................... 110 Figure 4-28: Debug Board: Top Signal Layer............................................................................................................. 111 Figure 4-29: Debug Board: Middle Layer 1, Ground Plane ........................................................................................ 111 Figure 4-30: Debug Board: Middle Layer 2, Supply Plane ......................................................................................... 112 Figure 4-31: Debug Board: Bottom Trace Layer ........................................................................................................ 112 Figure 4-32: TERIDIAN 71M6511 LQFP64: Pinout (Top View) ................................................................................. 115 List of Tables Table 1-1: Jumper settings on the Debug Board.......................................................................................................... 14 Table 1-2: Straight Cable Connections ........................................................................................................................ 14 Table 1-3: Null-Modem Cable Connections ................................................................................................................. 14 Table 1-4: CE RAM Locations for Calibration Constants ............................................................................................. 31 Table 1-5: Flash Programming Interface Signals ......................................................................................................... 34 Table 1-6: MPU Input Parameters for Metering .......................................................................................................... 37 Table 1-7: MPU Input Parameters for Temperature Compensation ............................................................................ 37 Table 1-8: MPU Parameters for Pulse Source Selection ............................................................................................ 37 Table 1-9: Selectable Pulse Sources .......................................................................................................................... 38 Table 1-10: MPU Instantaneous Output Variables ....................................................................................................... 39 Table 1-11: MPU Status Word Bit Assignment ............................................................................................................ 40 Table 1-12: MPU Accumulation Output Variables ........................................................................................................ 41 Table 1-13: MPU Variables Related to Phase B (6511, Revision 3.05 only) ................................................................ 42 Table 1-14: CLI Commands for MPU Data Memory..................................................................................................... 43 Table 2-1: Calibration Summary................................................................................................................................... 55 Table 2-2: Calibration Summary................................................................................................................................... 57 Table 2-3: Power Saving Measures ............................................................................................................................. 57 Table 3-1: 71M6511 Demo Board Description: 1/3 ...................................................................................................... 69 Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 7 of 115 71M6511/71M6511H Demo Board User's Manual Table 3-2: 71M6511 Demo Board Description: 2/3 ...................................................................................................... 70 Table 3-3: 71M6511 Demo Board Description: 3/3 ...................................................................................................... 71 Table 3-4: Jumper Default Settings.............................................................................................................................. 71 Table 3-5: 71M6511 2-Layer Demo Board Description: 1/2 ......................................................................................... 73 Table 3-6: 71M6511 2-Layer Demo Board Description: 2/3 ......................................................................................... 74 Table 3-7: Jumper Default Settings.............................................................................................................................. 74 Table 4-1: 71M6511 4-Layer Demo Board: Bill of Material .......................................................................................... 89 Table 4-2: D6511T4A8 2-Layer Demo Board: Bill of Material ...................................................................................... 90 Table 4-3: 71M6511 2-Layer Demo Board (Transformer Power Supply): Bill of Material (1/2) .................................... 91 Table 4-4: 71M6511 2-Layer Demo Board (Transformer Power Supply): Bill of Material (2/2) .................................... 92 Table 4-5: Debug Board: Bill of Material .................................................................................................................... 108 Table 4-6: 71M6511 Pin Description Table 1/2 .......................................................................................................... 113 Table 4-7: 71M6511 Pin Description Table 2/2 .......................................................................................................... 114 Page: 8 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 1 1 GETTING STARTED 1.1 GENERAL The TERIDIAN Semiconductor Corporation (TSC) 71M6511 Demo Board is an energy meter IC demonstration board for evaluating the 71M6511/6511H device for single-phase electronic energy metering applications. It incorporates a 71M6511 or 71M6511H integrated circuit, peripheral circuitry such as a serial EEPROM, emulator port, and on board power supply as well as a companion Debug Board that allows a connection to a PC through a RS232 port. The Demo Board allows the evaluation of the 71M6511 energy meter chip for measurement accuracy and overall system use. The board is pre-programmed with a Demo Program (file name 6511_demo.hex) in the FLASH memory of the 71M6511/6511H IC. This embedded application was developed to exercise all low-level functions to directly manage the peripherals, flash programming, and CPU (clock, timing, power savings, etc.). The 71M6511/6511H IC on the Demo Board is pre-programmed with default calibration factors. 1.2 SAFETY AND ESD NOTES Connecting live voltages to the Demo Board system will result in potentially hazardous voltages on the Demo Board. BEFORE OPERATING THE DEMO BOARD, THE JUMPERS ON JP2 AND JP3 (IF INSTALLED) SHOULD BE REMOVED! IT IS RECOMMENDED TO OPERATE THE DEBUG BOARD WITH ITS OWN POWER SUPPLY. THE DEMO SYSTEM IS ESD SENSITIVE! ESD PRECAUTIONS SHOULD BE TAKEN WHEN HANDLING THE DEMO BOARD! EXTREME CAUTION SHOULD BE TAKEN WHEN HANDLING THE DEMO BOARD ONCE IT IS CONNECTED TO LIVE VOLTAGES! Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 9 of 115 71M6511/71M6511H Demo Board User's Manual 1.3 DEMO KIT CONTENTS 71M6511 Demo board containing 71M6511 or 71M6511H IC with preloaded Demo Program (4-layer, round, Demo Board or 2-layer, rectangular Demo Board with capacitive or transformer power supply) Debug Board Two 5VDC/1,000mA universal wall transformers w/ 2.5mm plug (Switchcraft 712A) Serial cable, DB9, Male/Female, 2m length (Digi-Key AE1020-ND) CD-ROM containing documentation (data sheet, board schematics, BOM, layout), Demo Code, and utilities 1.4 DEMO BOARD VERSIONS Three versions of the Demo Board are available, as shown in Figure 1-1: 4-layer Demo Board with round PCB, for demonstration of 4-layer designs (identification number D6511T4B2). 2-layer Demo Board with rectangular PCB, with capacitive power supply, for demonstration of economical 2-layer designs (identification number D6511T4A7). 2-layer Demo Board with rectangular PCB, with transformer power supply, for demonstration of economical 2-layer designs (identification number D6511BT4A4). Figure 1-1: Demo Board Versions. 4-layer (left), 2-layer (right) 1.5 COMPATIBILITY This manual applies to the following hardware and software revisions: 71M6511 or 71M6511H chip revision B03 Demo Kit firmware revision 3.04 and 3.05, or later 4-layer Demo Board revision D6511T4B 2-layer Demo Board D6511BT4A4 or D6511T4A7 Page: 10 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 1.6 SUGGESTED EQUIPMENT AND TEST TOOLS NOT INCLUDED For functional demonstration: PC w/ MS-Windows versions XP or 2000, equipped with RS232 port (COM port) via DB9 connector For software development (MPU code): Signum ICE (In Circuit Emulator): ADM-51 http://signum.temp.veriohosting.com/Signum.htm Keil 8051 "C" Compiler kit: CA51 http://www.keil.com/c51/ca51kit.htm, http://www.keil.com/product/sales.htm For calibration and accuracy tests: * 1.7 Calibration system (see section 2.2 for details) DEMO BOARD TEST SETUP Figure 1-2 and Figure 1-3 show the basic connections of the Demo Boards plus Debug Boards with the external equipment for desktop testing, i.e. without live power applied. For desktop testing, both the Demo and Debug board may be powered with just the 5VDC power supplies. Power (5VDC) Demo Board Two Power Supplies (100VAC to 240VAC, 5V/1ADC Output) Debug Board Power 5VDC Host PC Figure 1-2: 4-Layer Demo Board: Basic Connections Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 11 of 115 71M6511/71M6511H Demo Board User's Manual Spacer removed Host PC Debug Board Demo Board Power Figure 1-3: 2-Layer Demo Board: Basic Connections The Debug Board can be plugged into J2 of the Demo Board. For the 2-Layer Demo Board, one spacer of the Debug Board should be removed, as shown in Figure 1-3. Alternatively, both boards can be connected using a flat ribbon cable, as shown in Figure 1-4. The male-to-female flat ribbon cable is not supplied with the Demo Kit (use Digi-Key P/N A3AKA-1606M-ND or similar). Figure 1-4: 2-Layer Demo Board: Ribbon Cable Connections Page: 12 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual The 71M6511 Demo Board block diagram is shown in Figure 1-5. The demo setup consists of a stand-alone meter Demo Board and an optional Debug Board. The Demo Board contains all circuits necessary for operation as a meter, including display, calibration LED, and internal power supply. The Debug Board, when using a separate power supply, is optically isolated from the meter and interfaces to a PC through a 9-pin serial port. Connections to the external signals to be measured, i.e. scaled AC voltages and current signals derived from shunt resistors or current transformers, are provided on the rear side of the Demo Board. It is recommended to set up the Demo Board with no live AC voltage connected, and to connect live AC voltages only after the user is familiar with the demo system. LOAD 6511 Single Chip Meter DIO6 IA IA External Current Transformer VAR DIO7 V3P3 V3P3 5V LCD DISPLAY IB V3P3 LIVE (VA_IN) Pulse Outputs WATT DIO4 DIO5 EEPROM VA ICE Connector VA DEBUG BOARD MPU HEARTBEAT (5Hz) JP1 DIO14 V3P3 NEUT 3.3v DIO15 GND 5V DC OPTO GND OPTO DIO16 OPTO TX JP2 JP3 OPTO RX V5_DBG CE HEARTBEAT (1Hz) V5_DBG GND_DBG V5_DBG DB9 to PC COM Port RS-232 INTERFACE OPTO OPTO SUPPLY TMUXOUT Debug Connector CKTEST OPTO FPGA (optional) OPTO OPTO SUPPLY V5_DBG GND_DBG J5 (optional) 68 Pin Connector to NI PCI-6534 DIO Board V5_NI 5V DC RTM INTERFACE (OPTIONAL) 11/2/2005 Figure 1-5: The TERIDIAN 6511 Demo Board with Debug Board Block Diagram (CT Configuration) All input signals are referenced to the V3P3 (3.3V power supply to the chip). Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 13 of 115 71M6511/71M6511H Demo Board User's Manual 1.7.1 POWER SUPPLY SETUP There are several choices for meter power supply: * Internal (using the AC line voltage). The internal power supply is only suitable when the line voltage exceeds 220V RMS. * External 5VDC connector (J1) on the Demo Board * External 5VDC connector (J1) on the Debug Board. The three power supply jumpers, JP1, JP2, and JP3 (JP2/JP3 is only provided on the D6511T4B2 Demo Board), must be consistent with the power supply choice. JP1 connects the AC line voltage to the internal power supply. This jumper should usually be left in place. JP2 and JP3 should be left open (unconnected). 1.7.2 CABLE FOR SERIAL CONNECTION (DEBUG BOARD) For connection of the DB9 serial port to a PC, either a straight or a so-called "null-modem" cable may be used. JP1 and JP2 on the Debug Board are plugged in for the straight cable, and JP3/JP4 are empty. The jumper configuration is reversed for the null-modem cable, as shown in Table 1-1. Cable Configuration Mode Straight Cable Null-Modem Cable Jumpers on Debug Board JP1 JP2 JP3 JP4 Default Installed Installed -- -- Alternative -- -- Installed Installed Table 1-1: Jumper settings on the Debug Board JP1 through JP4 can also be used to alter the connection when the PC is not configured as a DCE device. Table 1-2 shows the connections necessary for the straight DB9 cable and the pin definitions. PC Pin Function Demo Board Pin 2 TX 2 3 RX 3 5 Signal Ground 5 Table 1-2: Straight Cable Connections Table 1-3 shows the connections necessary for the null-modem DB9 cable and the pin definitions. PC Pin Function Demo Board Pin 2 TX 3 3 RX 2 5 Signal Ground 5 Table 1-3: Null-Modem Cable Connections Page: 14 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 1.7.3 CHECKING OPERATION A few seconds after power up, the LCD display on the Demo Board should briefly display the following welcome text: H E L L 0 After the welcome text, the Demo Board should display the following information: 3. 0. 0 0 1 The decimal dot in the leftmost segment will be blinking, indicating activity of the MPU inside the 71M6511. 1.7.4 SERIAL CONNECTION SETUP After connecting the DB9 serial port to a PC, start the HyperTerminal application and create a session using the following parameters: Port Speed: 9600 baud Data Bits: 8 Parity: None Stop Bits: 1 Flow Control: XON/XOFF HyperTerminal can be found by selecting Programs start menu. Accessories Communications from the Windows The connection parameters are configured by selecting File Properties and then by pressing the Configure button. Port speed and flow control are configured under the General tab (Figure 1-7, left), bit settings are configured by pressing the Configure button (Figure 1-7, right), as shown below. A setup file (file name "Demo Board Connection.ht") for HyperTerminal that can be loaded with File Open is also provided with the tools and utilities on the supplied CD-ROM. Port parameters can only be adjusted when the connection is not active. The disconnect button, as shown in Figure 1-6 must be clicked in order to disconnect the port. Figure 1-6: Hyperterminal Sample Window with Disconnect Button Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 15 of 115 71M6511/71M6511H Demo Board User's Manual Figure 1-7: Port Speed/Handshake Setup (left) and Port Bit Setup (right) Once, communication to the Demo Board is established, press <CR> and the Demo Program prompt, >, should appear. Type >? to see the Demo Program help menu. Type >i1 to verify that the Demo Program version is revision 3.04 or later. 1.8 USING THE DEMO BOARD The 71M6511/6511H Demo Board is a ready-to-use meter prepared for use with an external current transformer. Using the Demo Board involves communicating with the Demo Code via the command line interface (CLI). The CLI allows all sorts of manipulations to the metering parameters, access to the EEPROM, initiation of auto-cal sequences, selection of the displayed parameters, changing calibration factors and many more operations. Before evaluating the 71M6511/6511H on the Demo Board, users should get familiar with the commands and responses of the CLI. A complete description of the CLI is provided in section 1.8.1. 1.8.1 SERIAL COMMAND LANGUAGE The Demo Code residing in the flash memory of the 71M6511/6511H provides a convenient way of examining and modifying key meter parameters. Once the Demo Board is connected to a PC or terminal per the instructions given in Section 1.7.2 and 1.7.4, typing `?' will bring up the list of commands shown in Figure 1-8. Page: 16 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual >? ?? : Command Line Interpreter On-line help Usage: ?<char> or ?? to get this help page Where <char> is an uppercase letter of the command. The following commands/<char> are available: , - Repeat last command : / - Ignore rest of line C - Compute Engine Control : EE - EEprom Control I - Information message : M - Meter Display Control P - Profile of Meter R - SFR Control : RT - RTC Control T - Trim Controls : Z - Reset ] - Access CE Data RAM : ) - Access MPU Data RAM For Example: ?C to get help on Compute Engine Control. > Figure 1-8: Command Line Interface Help Display The tables below describe the commands in detail. Demo Code revision 3.05 offers more commands than revision 3.04. Commands only available on 3.05 are marked in the tables presented in this chapter. Commands to Display Help on the CLI Commands: ? HELP Description: Command help available for each of the options below. Command combinations: ? Command line interpreter help menu. ?] Display help on access CE data RAM ?) Display help on access MPU RAM ?, Display help on repeat last command ?/ Display help on ignore rest of line ?C Display help on compute engine control and calibration. In 3.05, pulse counter functions are offered. ?EE Display help on EEPROM control ?I Display help on information message ?M Display help on meter display control ?P Display help on profile of meter ?R Display help on SFR control ?RT Display help on RTC control ?T Display help on trim control ?W Display help on the wait/reset command - 3.05 only Examples: Revision 5.4 ?Z Display help on reset ?? Display the command line interpreter help menu. ?C Displays compute engine control help. (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 17 of 115 71M6511/71M6511H Demo Board User's Manual Commands for CE Data Access: ] CE DATA ACCESS Description: Allows user to read from and write to CE data space. Usage: ] [Starting CE Data Address] [option]...[option] Command combinations: ]??? Read consecutive 16-bit words in Decimal ]$$$ Read consecutive 16-bit words in Hex ]=n=n Write consecutive memory values ]U Update default version of CE Data in flash memory ]40$$$ Reads CE data words 0x40, 0x41 and 0x42. ]7E=12345678=9876ABCD Writes two words starting @ 0x7E Example: CE data space is the address range for the CE DRAM (0x1000 to 0x13FF). All CE data words are in 4-byte (32-bit) format. The offset of 0x1000 does not have to be entered when using the ] command, thus typing ]A? will access the 32-bit word located at the byte address 0x1000 + 4 * A = 0x1028. Commands for MPU/XDATA Access: ) MPU DATA ACCESS Description: Allows user to read from and write to MPU data space. Usage: ) [Starting MPU Data Address] [option]...[option] Command combinations: )??? Read three consecutive 32-bit words in Decimal )$$$ Read three consecutive 32-bit words in Hex )a=n=m Write the values n and m to two consecutive addresses starting at a )08$$$$ Reads data words 0x08, 0x0C, 0x10, 0x14 )04=12345678=9876ABCD Writes two words starting @ 0x04 Example: MPU or XDATA space is the address range for the MPU XRAM (0x0000 to 0x7FFF). All MPU data words are in 4-byte (32-bit) format. Typing ]A? will access the 32-bit word located at the byte address 4 * A = 0x28. The energy accumulation registers of the Demo Code can be accessed by typing two Dollar signs ("$$"), typing question marks will display negative decimal values if the most significant bit is set. RAM access is limited to the lower 1KB address range. Read and write operations will "wrap around" at higher addresses, i.e. )200? will yield the same result as )0? Page: 18 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Commands for DIO RAM (Configuration RAM) and SFR Control: R DIO AND SFR CONTROL Description: Allows the user to read from and write to DIO RAM and special function registers (SFRs). Usage: R [option] [register] ... [option] Command combinations: RIx... Select I/O RAM location x (0x2000 offset is automatically added) Rx... Select internal SFR at address x R???... Read consecutive registers in Decimal R$$$... Read consecutive registers in Hex Ra=n=m... Set values of consecutive registers to n and m starting at address a RI0$$$ Read CE0, CE1 and CE2 registers Example: DIO or Configuration RAM space is the address range 0x2000 to 0x20FF. This RAM contains registers used for configuring basic hardware and functional properties of the 71M6511/6511H and is organized in bytes (8 bits). The 0x2000 offset is automatically added when the command RI is typed. The SFRs (special function registers) are located in internal RAM of the 80515 core, starting at address 0x80. Commands for EEPROM Control: EE EEPROM CONTROL Description: Allows user to enable read and write to EEPROM. Usage: EE [option] [arguments] Command combinations: EECn EEPROM Access (1 EERa.b Read EEPROM at address 'a' for 'b' bytes. EESabc..xyz Write characters to buffer (sets Write length) EETa Transmit buffer to EEPROM at address 'a'. EEWa.b...z Write values to buffer EEShello; EET$0210 Writes 'hello' starting at EEPROM address 0x210. Example: Enable, 0 Disable) Due to buffer size restrictions, the maximum number of bytes handled by the EEPROM command is 0x40. Auxiliary Commands: Typing a comma (",") repeats the command issued from the previous command line. This is very helpful when examining the value at a certain address over time, such as the CE DRAM address for the temperature (0x40). The slash ("/") is useful to separate comments from commands when sending macro text files via the serial interface. All characters in a line after the slash are ignored. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 19 of 115 71M6511/71M6511H Demo Board User's Manual Commands controlling the CE, TMUX and the RTM: C COMPUTE ENGINE CONTROL Description: Allows the user to enable and configure the compute engine. Usage: C [option] [argument] Command combinations: CEn Compute Engine Enable (1 0 Disable) CTn Select input n for TMUX output pin CREn RTM output control (1 CRSa.b.c.d Selects CE addresses for RTM output CE0 Disables CE, followed by "CE OFF" display on LCD. The Demo Code will reset if the WD timer is enabled. CT3 Selects the VBIAS signal for the TMUX output pin Example: Enable, Enable, 0 Disable) Commands controlling the Auto-Calibration Function: CL AUTO-CALIBRATION CONTROL Description: Allows the user to initiate auto-calibration and to store calibration values. Usage: CL [option] Command combinations: CLB Begin auto-calibration. Prior to auto-calibration, the calibration coefficients are automatically restored from flash memory. If the coefficients are not unity gain (0x4000), auto-calibration will yield poor results. CLS Save calibration coefficients to EEPROM starting at address 0x0004 CLR Restore calibration coefficients from EEPROM CLD Restore coefficients from flash memory CLB Starts auto-calibration Example: Before starting the auto-calibration process, target values for voltage and current must be entered in I/O RAM prior to calibration (V at 0x2029, I at 0x202A, duration in accumulation intervals at 0x2028), and the target voltage and current must be applied constantly during calibration. No phase adjustment will be performed. Coefficients can be saved to EEPROM using the CLS command. Page: 20 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Commands controlling the Pulse Counter Function (Demo Code Revision 3.05 only) CP PULSE-COUNT CONTROL Description: Allows the user to control the pulse count functions. Usage: CP [option] Command combinations: CPA Start pulse counting for time period defined with the CPD command. Pulse counts will display with commands M15.2, M16.2 CPC Clear the absolute pulse count displays (shown with commands M15.1, M16.1) CPDn Set time window for pulse counters to n seconds, n is interpreted as a decimal number. CPD60 Set time window to 60 seconds. Example: Pulse counts accumulated over a time window defined by the CPD command will be displayed by M15.2 or M16.2 after the defined time has expired. Commands M15.1 and M16.1 will display the absolute pulse count for the W and VAR outputs. These displays are reset to zero with the CPC command (or the XRAM write )1=2). Commands M15.2 and M16.2 will display the number of pulses counted during the interval defined by the CPD command. These displays are reset only after a new reading, as initiated by the CPA command. Commands for Identification and Information: I INFORMATION MESSAGES Description: Allows user to read and write information messages. Usage: I [option] [argument] Command combinations: I0 Displays complete version information I1 Displays Demo Code version string I1=abcdef Change Demo Code version string I2 Displays Copyright string I3 CE Version string I3=abcdef Change CE Code version string I1 Returns Demo Code version Example: The I commands are mainly used to identify the revisions of Demo Code and the contained CE code. P PROFILE OF METER Description: Returns current meter configuration profile Usage: P The profile of the meter is a summary of the important settings of the I/O RAM registers. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 21 of 115 71M6511/71M6511H Demo Board User's Manual Commands for Controlling the Metering Values Shown on the LCD Display: M METER DISPLAY CONTROL (LCD) Description: Allows user to select internal variables to be displayed. Usage: M [option]. [option] Command combinations: M Displays "HELLO" message M0 Disables display updates M1 Temperature (C delta from nominal) M2 Frequency (Hz) M3. [phase] Wh Total Consumption (display wraps around at 999.999) M4. [phase] Wh Total Inverse Consumption (display wraps around at 999.999) M5. [phase] VARh Total Consumption (display wraps around at 999.999) M6. [phase] VAh Total Inverse Consumption (display wraps around at 999.999) M7. [phase] VAh Total (display wraps around at 999.999) M8 Operating Time (in hours) M9 Real Time Clock M10 Calendar Date M11. [phase] V/I Angle at Phase (degrees) M12. 1 Main edge count (accumulated) M12. 2 CE main edge count for the last accumulation interval M13.1 Absolute count for W pulses. Reset with CPC command. Demo Code revision 3.05 only. M13.2 Count for W pulses in time window defined by the CPD command. Demo Code revision 3.05 only. M14.1 Absolute count for VAR pulses. Reset with CPC command. Demo Code revision 3.05 only. M15.2 Count for W pulses in time window defined by the CPD command. Demo Code revision 3.05 only. M3.1 Displays Wh total consumption of phase A. Example: Displays for total consumption wrap around at 999.999Wh (or VARh, VAh) due to the limited number of available display digits. Internal registers (counters) of the Demo Code are 64 bits wide and do not wrap around. When entering the phase parameter, use 1 for phase A, 2 for phase B, and 0 for all phases. Page: 22 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Commands for Controlling the RMS Values Shown on the LCD Display: MR METER RMS DISPLAY CONTROL (LCD) Description: Allows user to select meter RMS display for voltage or current. Usage: MR [option]. [option] Command combinations: MR1. [phase] Displays instantaneous RMS current MR2. [phase] Displays instantaneous RMS voltage MR1.1 Displays phase A RMS current. Example: No error message is issued when an invalid parameter is entered, e.g. MR1.8. Commands for Controlling the MPU Power Save Mode: PS POWER SAVE MODE Description: Enters power save mode Usage: PS Disables CE, ADC, CKOUT, ECK, RTM, SSI, TMUX VREF, and serial port, sets MPU clock to 38.4KHz. Return to normal mode is achieved by resetting the MPU (Z command). Commands for Controlling the RTC: RT REAL TIME CLOCK CONTROL Description: Allows the user to read and set the real time clock. Usage: RT [option] [value] ... [value] Command combinations: RTDy.m.d.w: Day of week Example: (year, month, day, weekday [1 = Sunday]) RTR Read Real Time Clock. RTTh.m.s Time of day: (hr, min, sec). RTAs.t Real Time Adjust: (start, trim). Allows trimming of the RTC. If s > 0, the speed of the clock will be adjusted by `t' parts per billion (PPB). If the CE is on, the value entered with 't' will be changing with temperature, based on Y_CAL, Y_CAL_DEG1 and Y_CAL_DEG2 . RTD05.03.17.5 Programs the RTC to Thursday, 3/17/2005 RTA1.+1234 Speeds up the RTC by 1234 PPB. The "Military Time Format" is used for the RTC, i.e. 15:00 is 3:00 PM. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 23 of 115 71M6511/71M6511H Demo Board User's Manual Commands for Accessing the Trim Control Registers: T TRIM CONTROL Description: Allows user to read trim and fuse values. Usage: T [option] Command combinations: T4 Read fuse 4. T5 Read fuse 5. T6 Read fuse 6. Example: NONE These commands are only accessible for the 6511H (0.1%) parts. When used on a 71M6511 (0.5%) part, the results will be displayed as zero. Reset Commands: W, Z RESET Description: Soft Reset and watchdog control Usage: W, Z Commands: W Halts the Demo Code program, thus suppressing the triggering of the hardware watchdog timer. This will cause a reset, if the watchdog timer is enabled. Demo Code revision 3.05 only. Z Soft reset. This command acts like a hardware reset. The energy accumulators in XRAM will retain their values. Page: 24 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 1.8.2 USING THE DEMO BOARD FOR ENERGY MEASUREMENTS The 71M6511/6511H Demo Board was designed for current transformer (CT), current shunt, or current shunt/CT combinations. The demo code is designed to support both operating modes. The Demo Boards are normally shipped in CT configuration. 1.8.3 USING THE DEMO BOARD IN CT MODE The Demo Board may immediately be used with current transformers having 2,000:1 winding ratio and is programmed for a Kh factor of 1.0 and (see Section 1.8.4 for adjusting the Demo Board for transformers with different turns ratio). Once voltage is applied and load current is flowing, the red LED D5 (controlled by pin DIO6) will pulse each time an energy sum of 1.0 Wh is collected. The LCD display will show the accumulated imported energy in Wh when set to display mode 3 (command >M3 via the serial interface). If no energy is displayed, reversed polarity of the current channel may be the reason. The command >M4 will display the exported energy. Similarly, the red LED D6 (controlled by pin DIO7) will pulse each time a reactive energy sum of 1.0 VARh is collected. The LCD display will show the accumulated energy in VARh when set to display mode 5 (command >M5 via the serial interface). 1.8.4 ADJUSTING THE DEMO BOARD TO DIFFERENT CURRENT TRANSFORMERS The Demo Board is prepared for use with 2000:1 current transformers (CTs). This means that for the unmodified Demo Board, 208A on the primary side at 2000:1 ratio result in 104mA on the secondary side, causing 177mV at the 1.7 resistor pairs R24/R25, R36/R37, R56/R57 (2 x 3.4 in parallel). In general, when IMAX is applied to the primary side of the CT, the voltage Vin at the IA or IB input of the 71M6511 IC is determined by the following formula: Vin = R * I = R * IMAX/N where N = transformer winding ratio, R = resistor on the secondary side If, for example, IMAX = 208A are applied to a CT with a 2500:1 ratio, only 83.2mA will be generated on the secondary side, causing only 141mV. The steps required to adapt a 71M6511 Demo Board to a transformer with a winding ratio of 2500:1 are outlined below: 1) The formula Rx = 177mV/(IMAX/N) is applied to calculate the new resistor Rx. We calculate Rx to 2.115 2) Changing the resistors R24/R25, R106/R107 to a combined resistance of 2.115 (for each pair) will cause the desired voltage drop of 177mV appearing at the IA, or IB inputs of the 71M6511 IC. 3) WRATE should be adjusted to achieve the desired Kh factor, as described in 1.8.2. Simply scaling IMAX is not recommended, since peak voltages at the 71M6511 inputs should always be in the range of 0 through 250mV (equivalent to 177mV rms). If a CT with a much lower winding ratio than 1:2,000 is used, higher secondary currents will result, causing excessive voltages at the 71M6511 inputs. Conversely, CTs with much higher ratio will tend to decrease the useable signal voltage range at the 71M6511 inputs and may thus decrease resolution. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 25 of 115 71M6511/71M6511H Demo Board User's Manual 1.8.5 ADJUSTING THE KH FACTOR FOR THE DEMO BOARD The 71M6511/6511H Demo Board is shipped with a pre-programmed scaling factor Kh of 1.0, i.e. 1Wh per pulse. In order to be used with a calibrated load or a meter calibration system, the board should be connected to the AC power source using the spade terminals on the bottom of the board. The current transformers should be connected to the dual-pin headers on the bottom of the board. The Kh value can be derived by reading the values for IMAX and VMAX (i.e. the RMS current and voltage values that correspond to the 250mV maximum input signal to the IC), and inserting them in the following equation for Kh: Kh = IMAX * VMAX * 47.1132 / (In_8 * WRATE * NACC * X) = 0.99967 Wh/pulse. Where IMAX is the current scaling factor, VMAX is the voltage scaling factor, In_8 is the current shunt gain factor, WRATE is the CE variable controlling Kh, NACC is the product of the I/O RAM variables PRE_SAMPS and SUM_CYCLES, and X is the pulse frequency factor derived from the CE variables PULSE_SLOW and PULSE_FAST. The small deviation between the adjusted Kh of 0.99967 and the ideal Kh of 1.0 is covered by calibration. The default values used for the 71M6511/6511H Demo Board are: WRATE: IMAX: VMAX: In_8: NACC: X: 1556 208 600 1 2520 1.5 (controlled by IA_SHUNT = -15) Explanation of factors used in the Kh calculation: WRATE: The factor input by the user to determine Kh IMAX: The current input scaling factor, i.e. the input current generating 177mVrms at the IA/IB input pins of the 71M6511. 177mV rms is equivalent to 250mV peak. VMAX: The voltage input scaling factor, i.e. the voltage generating 177mVrms at the VA input pins of the 71M6511 In_8: The setting for the additional ADC gain (8 or 1) determined by the CE register IA_SHUNT NACC: The number of samples per accumulation interval, i.e. PRE_SAMPS *SUM_CYCLES X: The pulse rate control factor determined by the CE registers PULSE_SLOW and PULSE_FAST Almost any desired Kh factor can be selected for the Demo Board by resolving the formula for WRATE: WRATE = (IMAX * VMAX * 47.1132) / (Kh * In_8 * NACC * X) For the Kh of 1.0Wh, the value 1556 (decimal) should be entered for WRATE at location 2D (using the CLI command >]2D=+1556). 1.8.6 USING THE DEMO BOARD IN CURRENT SHUNT MODE With a few quick modifications, the 71M6511/6511H Demo Board can be adapted to operate with a current shunt/CT combination or a single shunt. Modifications are shown for the 2-Layer Demo Board. Component references and configuration are slightly different for the 4-Layer Demo Board. Check the schematic and PCB layout given for the 4-Layer Demo Board when applying the modifications. Figure 1-9 shows the connections necessary for this operation mode. The voltage drop across the shunt resistor is fed into the IA input of the 71M6511/6511H, with V3P3 being the reference. The voltage between LIVE and NEUTRAL is divided by the resistor divider associated with the voltage input and supplied to the VA input of the chip. The division ratio is so that the voltage at VA is within 250mV of V3P3. The power supply generates the 3.3VDC from the voltage between the shunt and the load, with "ground" being only 3.3V lower than the voltage at the load. Page: 26 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual In this configuration, the whole Demo Board will be at line voltage! Touching the board or any components must be avoided! The routing of the input sensing traces for the reference V3P3 at the voltage and shunt inputs is very critical. Current shunts used in energy meters are usually of very low resistance, typically 100 to 400. This is because self-heating of the resistor that could lead to non-linear behavior must be avoided. A current shunt of 200 operated at 40A (at a power of 320mW) will only generate 8mV, far below the maximum range of 176mV for the current inputs of the 71M6511/6511H. The 71M6511/6511H has an optional digital gain stage that can be used to increase low signals, as generated by current shunts, by eight. In order to operate the 71M6511/6511H Demo Board (D6511BT4A4, D6511BT4A5, D6511BT4A7 or later) with a current shunt sensor, the following measures must be taken: a) Remove the jumpers on JP16 and JP17. b) Remove R24 and R25 if IA_IN is the input channel for the current shunt or remove R106 and R107 if IB_IN is the input channel for the current shunt. c) Add a 10k resistor at R24 if IA_IN is the input channel for the current shunt or add a 10k resistor at R106 if IB_IN is the input channel for the current shunt. This resistor will provide noise termination and will suppress unwanted readings. d) The LIVE line must be connected to the spade terminal J4 (bottom of the board). e) The blue and white pair of wires from the shunt resistor must be connected to contacts 1 and 2 on J3, as shown in Error! Reference source not found., if IA_IN is the input channel or contacts 1 and 2 on J16 if IB_IN is the input channel. f) Connect the green wire to pin1 of JP16 (pin closest to the regulator output, power supply pin) and the red wire to pin 2 of JP17 (resistor divider output). Both wires are joined at the shunt. g) Through the serial terminal (command line interface), the Demo Program can be set to run in current shunt mode. This is done by issuing the commands >]2A=1 if IA_IN is connected to the shunt or >]2B=1 for IB_IN connected to the shunt. This will cause the Demo Program to select the proper input channels and to apply the gain of 8 to the shunt input channel from the ADC output before processing for power measurement. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 27 of 115 71M6511/71M6511H Demo Board User's Manual SHUNT NEUTRAL The three wires must be connected directly at the shunt resistor RED BLUE GREEN Low crosstalk demands that these three current paths not share a common wire. WHITE LIVE 1 JP17 2 1 J4 3 JP16 3 2 LOAD 1 J3 No connection V3P3JMP V3P3JMP2 LIVE 71M6511/ 71M6511H star point V3P3 NEUTRAL J9 C9 R32 750 NEUTRAL IA V3P3 VA 1000pF 2.5MOhm R15-R18 Voltage Divider Power Supply GND C6 71M6511/6511H Demo Board 6/19/2007 Figure 1-9: Current Shunt Operation Mode (Shown for the D6511T4A7 2-layer PCB) The IMAX variable has to re-calculated for current shunt mode using the formula: IMAX = 177mV/Rshunt The new value for IMAX (XRAM address 0x0A) should be entered, using the command line interface, as follows (example shown assuming Rshunt = 400, with resulting IMAX = 440): >)A=+4400 Note: IMAX values have a LSB resolution of 0.1A, VMAX values have a LSB resolution of 0.1V Note: Since IMAX has been changed, WRATE has to be recalculated to maintain the desired Kh. If desired, the Demo Code can be set to run with increased gain (8 instead of 1) of the current channels, as sometimes required in current shunt mode due to low currents and low shunt resistances. This can be done via the command line interface by the commands >]2A=+15 setting IA_8 to 8 by controlling IA_SHUNT at address 0x2A, if IA_IN is connected to the shunt, or >]2B=+15 setting IB_8 to 8 by controlling IB_SHUNT at address 0x2B if IB_IN is connected to the shunt. Typically, only one shunt resistor is used in a meter. Isolation requires a transformer for the second shunt resistor when using two shunts in a meter. Page: 28 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual The Demo Code will compensate for the increased gain, i.e. the energy and current readings do not have to be scaled. A top-level schematic of the board connected to a shunt resistor is shown in Figure 1-10. IA L6 J3 IA_IN FERRITE GND GND R110 R14 0 750 TP21 IA IA U1 HDR3 R24 10K C17 1000pF L7 1 2 3 C18 1000pF A1 C1 AC2 AC1 C2 A2 6 5 4 6511 V3P3 HDR2 C8 1000pF BAV99DW V3P3 FERRITE IB L4 SHUNT1 J16 IB_IN FERRITE GND GND R111 R104 0 750 TP22 IB IB HDR2 U6 HDR3 R106 3.4 C11 1000pF L5 R107 3.4 C10 1000pF 1 2 3 A1 C1 AC2 AC1 C2 A2 6 5 4 C29 1000pF BAV99DW V3P3 FERRITE L3 JP17 VA FERRITE V3P3 V3P3J2 HDR2 L1 FERRITE C15 1nF JP16 GND HDR3 V3P3_JUMPER L2 LOAD R18 R17 R16 R15 2M 274K 270K 700 TP4 V3P3 V3P3 FERRITE GND HDR2 R32 750 C9 1000pF VA V3P3J2 J9 NEUTRAL C32 30nF RV1 510V L8 R118 J4 1 LIVE 8.06K 0.47uF, 1000Vdc C6 + C1 1N4736A 1 R8 1 D3 + C2 10uF TL431 8 + C4 33uF C5 0.1uF D10 UCLAMP3301D 6 GND LIVE 2200uF, 16V 2 C14 1nF 1 V3P3_JUMPER 1 NEUTRAL 6.8V, 1W R6 D4 R7 100, 2W 1N4148 130 25.5K R20 GND FERRITE 10, 2W 0 JP2 HDR2 Figure 1-10: Current Shunt Top-Level Schematics (Shown for the 2-Layer Board) 1.8.7 ADJUSTING THE DEMO BOARD TO DIFFERENT VOLTAGE DIVIDERS The 6511 Demo Board comes equipped with its own network of resistor dividers for voltage measurement mounted on the PCB. The resistor values (for the 4-layer Demo Board) are 2.5477M (R15-R21, R26-R31 combined) and 750 (R32), resulting in a ratio of 1:3,393.933. This means that VMAX equals 176.78mV*3,393.933 = 600V. A large value for VMAX has been selected in order to have headroom for overvoltages. This choice need not be of concern, since the ADC in the 71M6511 has enough resolution, even when operating at 120Vrms or 240Vrms. If a different set of voltage dividers or an external voltage transformer is to be used, scaling techniques similar to those applied for the current transformer should be used. In the following example we assume that the line voltage is not applied to the resistor divider for VA formed by R15-R21, R26-R31, and R32, but to a voltage transformer with a ratio N of 20:1, followed by a simple resistor divider. We also assume that we want to maintain the value for VMAX at 600V to provide headroom for large voltage excursions. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 29 of 115 71M6511/71M6511H Demo Board User's Manual When applying VMAX at the primary side of the transformer, the secondary voltage Vs is: Vs = VMAX / N Vs is scaled by the resistor divider ratio RR. When the input voltage to the voltage channel of the 71M6511 is the desired 177mV, Vs is then given by: Vs = RR * 177mV Resolving for RR, we get: RR = (VMAX / N) / 177mV = (600V / 30) / 177mV = 170.45 This divider ratio can be implemented, for example, with a combination of one 16.95k and one 100 resistor. 1.9 CALIBRATION PARAMETERS 1.9.1 GENERAL CALIBRATION PROCEDURE Any calibration method can be used with the 71M6511/6511H chips. This Demo Board User's Manual presents calibration methods with three or five measurements as recommended methods, because they work with most manual calibration systems based on counting "pulses" (emitted by LEDs on the meter). Naturally, a meter in mass production will be equipped with special calibration code offering capabilities beyond those of the Demo Code. It is basically possible to calibrate using voltage and current readings, with or without pulses involved. For this purpose, the MPU Demo Code can be modified to display averaged voltage and current values (as opposed to momentary values). Also, automated calibration equipment can communicate with the Demo Boards via the serial interface and extract voltage and current readings. This is possible even with the unmodified Demo Code. A complete calibration procedure is given in Section 2.1 (Application Information). Regardless of the calibration procedure used, parameters (calibration constants) will result that will have to be applied to the 71M6511/6511H chip in order to make the chip apply the modified gains and phase shifts necessary for accurate operation. Table 1-4 shows the names of the calibration constants, their function, and their location in the CE RAM. Again, the command line interface can be used to store the calibration constants in their respective CE RAM addresses. For example, the command >]8=+16302 stores the decimal value 16302 in the CE RAM location controlling the gain of the current channel (CAL_IA). The command >]9=4005 stores the hexadecimal value 0x4005 (decimal 16389) in the CE RAM location controlling the gain of the voltage channel (CAL_VA). Page: 30 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Constant CE Address (hex) CAL_VA RESERVED RESERVED 0x09 0x0B 0x0D Adjusts the gain of the voltage channel. +16384 is the typical value. The gain is directly proportional to the CAL parameter. Allowed range is 0 to 32767. If the gain is 1% slow, CAL should be increased by 1%. CAL_I0 CAL_I1 RESERVED 0x08 0x0A 0x0C Adjusts the gain of the current channels. +16384 is the typical value. The gain is directly proportional to the CAL parameter. Allowed range is 0 to 32767. If the gain is 1% slow, CAL should be increased by 1%. PHADJ_0 PHADJ_11 RESERVED 0x0E 0x0F 0x10 This constant controls the CT phase compensation. No compensation occurs when PHADJ=0. As PHADJ is increased, more compensation is introduced. Note: PHASDJ_11 applies to 3W/1-phase systems. TEMP_NOM 0x11 TEMP_RAWX reading Description Table 1-4: CE RAM Locations for Calibration Constants 1.9.2 CALIBRATION MACRO FILE Once, calibration parameters (calibration constants) have been determined, instead of manually typing them in using the command line interface, macro files may be used to simplify this procedure. The macro file in Figure 1-11 contains a sequence of the serial interface commands that implements changes to the calibration parameters (CE address locations 0x08 to 0x10). It is a simple text file and can be created with Notepad or an equivalent ASCII editor program. The file is executed with the following command of the HyperTerminal program: Transfer->Send Text File. ]8=+16022/ ]9=+16381/ ]a=+16019/ ]e=+115/ ]f=+113/ ce1 CAL_IA (gain=CAL_IA/16384) CAL_VA (gain=CAL_VA/16384) CAL_IB (gain=CAL_IB/16384) PHADJ_A (default 0) PHADJ_B (default 0) Figure 1-11: Typical Calibration Macro file It is possible to send the calibration macro file to the 71M6511/71M6511H for "temporary" calibration. This will temporarily change the CE data values. Upon power up, these values are refreshed back to the default values stored in flash memory. Thus, until the flash memory is updated, the macro file must be loaded each time the part is powered up. The macro file is run by first issuing the CE0 command to turn off the compute engine and then sending the file with the transfer send text file procedure. Note: Use the Transfer Revision 5.4 Send Text File command! (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 31 of 115 71M6511/71M6511H Demo Board User's Manual 1.9.3 UPDATING THE 6511_DEMO.HEX FILE The io_merge program updates the 6511_demo.hex file with the values contained in the macro file. This program is executed from a DOS command line window. Executing the io_merge program with no arguments will display the syntax description. To merge macro.txt and old_6511_demo.hex into new_6511_demo.hex, use the command: io_merge old_6511_demo.hex macro.txt new_6511_demo.hex The new hex file can be written to the 71M6511/71M6511H through the ICE port using an in-circuit emulator. This step makes the calibration to the meter permanent. 1.9.4 UPDATING CALIBRATION DATA IN FLASH MEMORY WITHOUT USING THE ICE It is possible to make data permanent that had been entered temporarily into the CE RAM. The transfer to flash memory is done using the following serial interface command: >]U Thus, after transferring calibration data with manual serial interface commands or with a macro file, all that has to be done is invoking the U command. Similarly, calibration data can also stored in EEPROM using the CLS command. After reset, calibration data is copied from the EEPROM, if present. Otherwise, calibration data is copied from the flash memory. Writing 0xFF into the first few bytes of the EEPROM deactivates any calibration data previously stored to the EEPROM. 1.9.5 AUTOMATIC GAINS CALIBRATION Starting with Demo Code revision 3.04, it is possible to perform a simple automatic calibration. This calibration is performed for resistive loads only and will not correct phase angle. The steps required for the calibration are: 1. Enter operating values for voltage and current in I/O RAM. The voltage is entered at address 0x2029 (e.g. with the command )29=+2400 for 240V), the current is entered at 0x202A (e.g. with the command )2A=+300 for 30A) and the duration measured in accumulation intervals is entered at 0x2028. 2. The operating voltage and current defined in step 1 must be applied to the meter (Demo Board). 3. The CLB (Begin Calibration) command is then entered via the serial interface. The operating voltage and current must be maintained accurately while the calibration is being performed. 4. The calibration procedure will automatically reset CE addresses 08, 09, 0x0A, 0x0B, 0x0C, and 0x0D to nominal values (0x4000), and 0x0E, 0x0F and 0x10 to zero prior to starting the calibration. Automatic calibration also reads the chip temperature and enters it in CE location 0x11 for proper temperature compensation. 5. Completion of the automatic calibration will be signaled by the LCD showing the "HELLO" message. Enter M3 or another serial interface command to bring the display back to normal. 6. CE addresses 0x08 and 0x09 will now show values other than 0x4000. These values can be stored in EEPROM by issuing the CLS command. Note: Current transformers of a given type usually have very similar phase angle for identical operating conditions. If the phase angle is accurately determined for one current transformer, the corresponding phase adjustment coefficient PHADJ_X can be entered for all calibrated units. Page: 32 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 1.9.6 LOADING THE 6511_DEMO.HEX FILE INTO THE DEMO BOARD Hardware Interface for Programming: The 71M6511/6511H IC provides an interface for loading code into the internal flash memory. This interface consists of the following signals: E_RXTX (data) E_TCLK (clock) E_RST (reset) These signals, along with V3P3 and GND are available on the emulator header J14. Production meters may be equipped with much simpler programming connectors, e.g. a 5x1 header. Programming of the flash memory requires either the ADM51 in-circuit emulator by Signum Systems (http//www.signumsystems.com) or the Flash Download Board Module (FDBM) provided by TERIDIAN Semiconductor. In-Circuit Emulator: If firmware exists in the 71M6511/6511H flash memory, the memory has to be erased before loading a new file into memory. In order to erase the flash memory, the RESET button of the emulator software has to be clicked followed by the ERASE button (Figure 1-12). Once the flash memory is erased, the new file can be loaded using the Load command in the File menu. The dialog box shown in Figure 1-13 makes it possible to select the file to be loaded by clicking the Browse button. Once the file is selected, pressing the OK button loads the file into the flash memory of the IC. At this point, the emulator probe (cable) can be removed. Once the 71M6511/6511H IC is reset using the reset button on the Demo Board, the new code starts executing. Flash Download Board Module (FDBM): Follow the instructions given in the User Manual for the FDBM. The hardware watchdog timer must be disabled during all programming operations. Figure 1-12: Emulator Window Showing Reset and Erase Buttons Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 33 of 115 71M6511/71M6511H Demo Board User's Manual Figure 1-13: Emulator Window Showing Erased Flash Memory and File Load Menu 1.9.7 THE PROGRAMMING INTERFACE OF THE 71M6511/6511H Flash Downloader/ICE Interface Signals The signals listed in Table 1-5 are necessary for communication between the Flash Downloader or ICE and the 71M6511/6511H. Signal Direction Function E_TCLK Output from 71M6511/6511H Data clock E_RXTX Bi-directional Data input/output E_RST Bi-directional Flash Downloader Reset (active low) Table 1-5: Flash Programming Interface Signals The E_RST signal should only be driven by the Flash Downloader when enabling these interface signals. The Flash Downloader must release E_RST at all other times. Page: 34 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 1.10 DEMO CODE 1.10.1 DEMO CODE DESCRIPTION The Demo Board is shipped preloaded with Demo Code revision 3.0.4 or later in the 71M6511 or 71M6511H chip. The code revision can easily be verified by entering the command >i1 via the serial interface (see section 1.8.1). Check with your local TERIDIAN representative or FAE for the latest revision. Some Demo Boards are shipped with Demo Code revision 3.03. These boards can be updated to revision 3.04 or later using either an in-circuit emulator (ICE) or the Flash Download Board Module (FDBM), as described in section 1.9.6. The Demo Code is useful due to the following features: * It provides basic metering functions such as pulse generation, display of accumulated energy, frequency, date/time, and enables the user to evaluate the parameters of the metering IC such as accuracy, harmonic performance, etc. * It maintains and provides access to basic household functions such as real-time clock (RTC). * It provides access to control and display functions via the serial interface, enabling the user to view and modify a variety of meter parameters such as Kh, calibration coefficients, temperature compensation etc. * It provides libraries for access of low-level IC functions to serve as building blocks for code development. A detailed description of the Demo Code can be found in the Software User's Guide (SUG). In addition, the comments contained in the library provided with the Demo Kit can serve as useful documentation. The Software User's Guide contains the following information: Revision 5.4 * Design guide * Design reference for routines * Tool Installation Guide * List of library functions * 80515 MPU Reference (hardware, instruction set, memory, registers) * Description of serial interface commands (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 35 of 115 71M6511/71M6511H Demo Board User's Manual 1.10.2 DEMO CODE MPU PARAMETERS In the Demo Code, certain MPU XRAM parameters have been given fixed addresses in order to permit easy external access. These variables can be read via the serial interface, as described in section 1.8.1, with the )n$ command and written with the )n=xx command where n is the word address. Note that accumulation variables are 64 bits long and are accessed with )n$$ (read) and )n=hh=ll (write) in the case of accumulation variables. MPU INPUT PARAMETERS All MPU Input Parameters are loaded by the MPU at startup and should not need adjustment during meter calibration. MPU Input Parameters for Metering XDATA Word Address Default Value 0x00 8311 Description Name WCREEP_THR For each element, if WSUM_X or VARSUM_X of that element exceeds WCREEP_THR, the sample values for that element are not zeroed. Otherwise, the accumulators for Wh, VARh, and VAh are not updated and the instantaneous value of IRMS for that element is zeroed. LSB = 6.6952*10-13 VMAX IMAX Wh The default value 8310 is equivalent to 2.5Wh/h. Demo Code revision 3.05: WCREEP_THR applies to phase A only. Bit 0: Sets VA calculation mode. 0 0x01 CONFIG 0: VRMS*ARMS 1: W 2 + VAR 2 Bit 1: Clears accumulators for Wh, VARh, VAh. This bit need not be reset. 0 0x02 191181742 Demo Code revision 3.04: Not implemented. PK_VTHR Demo Code revision 3.05: When the voltage exceeds this value, bit 5 in the MPU status word is set, and the MPU might choose to log a warning. Event logs are not implemented in Demo Code. LSB = 6.6952*10-13*VMAX2 V2hRMS The default value of 191181742 is equivalent to 407.3VRMS if VMAX = 600V and a 1-second accumulation interval is used. 0 0x03 24856631 Demo Code revision 3.04: Not implemented. PK_ITHR Demo Code revision 3.05: When the current exceeds this value, bit 6 in the MPU status word is set, and the MPU might choose to log a warning. Event logs are not implemented in Demo Code. LSB = 6.6952*10-13*IMAX2 V2hRMS The default value of 24856631 is equivalent to 50.9ARMS if IMAX = 208A and a 1-second accumulation interval is used. 0x09 6000 VMAX The nominal external RMS voltage that corresponds to 250mV peak at the ADC input. The meter uses this value to convert internal quantities to external. LSB=0.1V 0x0A 2080 IMAX The nominal external RMS current that corresponds to 250mV peak at the ADC input. The meter uses this value to convert internal quantities to external. LSB=0.1A Page: 36 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 0x13 61 ICREEP_THR For each element, if ISQSUM of that element exceeds ICREEP_THR, the sample values for that element are not zeroed. Otherwise, the accumulators for Wh, VARh, and VAh are not updated and the instantaneous value of IRMS for that element is zeroed. LSB = 6.6952*10-13 MAX2 Wh The default value 61 is equivalent to 80mA. Demo Code revision 3.05: WCREEP_THR applies to phase A only. Table 1-6: MPU Input Parameters for Metering MPU Input Parameters for Temperature Compensation XDATA Word Address Default Value Name 4 0 Y_CAL 5 0 Y_CALC 6 0 Y_CALC2 B 0 PPMC Description Implement RTC trim. CORRECTION ( ppm) = Y _ CAL Y _ CALC Y _ CALC 2 +T +T2 10 100 1000 PPM/C*26.84. Linear temperature compensation. A positive value will cause the meter to run faster when hot. This is applied to both V and I and will therefore have a double effect on products. Default is 0. 2 PPM/C *1374. Square law compensation. A positive value will cause the meter to run faster when hot. This is applied to both V and I and will therefore have a double effect on products. Default is 0. C 0 PPMC2 D 9585 DEGSCALE Scale factor for TEMP_X. TEMP_X=DEGSCALE*2-22*(TEMP_RAW_X-TEMP_NOM). Table 1-7: MPU Input Parameters for Temperature Compensation MPU Input Parameters for Pulse Generation XDATA Word Address Default Value Name Description 7 1 PULSEW_SRC This address contains a number that points to the selected pulse source. Selectable pulse sources are listed in Table 1-9. 8 5 PULSER_SRC This address contains a number that points to the selected pulse source. Selectable pulse sources are listed in Table 1-9. Table 1-8: MPU Parameters for Pulse Source Selection Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 37 of 115 71M6511/71M6511H Demo Board User's Manual Any of the values listed in Table 1-9 can be selected for as a source for PULSEW and PULSER. The designation "source_I" refers to values imported by the consumer, "source_E" refers to energy exported by the consumer (energy generation). Number Pulse Source 0 Reserved 1 WASUM 2 Description Number Pulse Source 18 Reserved 19 Reserved WBSUM 20 WASUM_I Imported real energy on element A 3 Reserved 21 WBSUM_I Imported real energy on element B 4 Reserved 22 Reserved 5 VAR0SUM 23 Reserved 6 VAR1SUM 24 VARASUM_I Imported reactive energy on element A 7 Reserved 25 VARBSUM_I Imported reactive energy on element B 8 IASQSUM 26 Reserved 9 IBSQSUM 27 Reserved 10 Reserved 28 WASUM_E Exported real energy on element A 11 Reserved 29 WBSUM_E Exported real energy on element B 12 VASQSUM 30 Reserved 13 Reserved 31 Reserved 14 Reserved 32 VARASUM_E Exported reactive energy on element A 15 Reserved 33 VARBSUM_E Exported reactive energy on element B 16 VAASUM 34 Reserved 17 VABSUM default for PULSEW_SRC default for PULSER_SRC Description Table 1-9: Selectable Pulse Sources Page: 38 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual MPU INSTANTANEOUS OUTPUT VARIABLES The Demo Code processes CE outputs after each accumulation interval. It calculates instantaneous values such as VRMS, IRMS, W and VA as well as accumulated values such as Wh, VARh, and VAh. Table 1-10 lists the calculated instantaneous values. XRAM Word Address Name 0x14 0x15 0x16 Vrms_A reserved reserved 0x17 0x18 0x19 Irms_A Irms_B reserved 0x1A 0x1B 0x1C IPhase_A reserved reserved Description Vrms: LSB = 3.7610 10 -8 VMAX Nacc Irms from element 0, 1, 2. LSB = 3.7610 10 -8 IMAX In8 Nacc Phase between voltage and current. The number of degrees I lags V. LSB=0.001, range: 0...+360 Frequency of the voltage signal selected by the CE input. If the selected voltage is below the sag threshold, Frequency = 0. 0x1D Frequency LSB 0x1E Delta_T 0x1F 0x20 reserved reserved FS 0.587 10 - 6 Hz 32 2 Deviation from Calibration temperature. LSB = 0.1 0C. 0x21 Status 0x22 OperatingTime MPU Status Word 0x23 Reserved Total operating time. LSB = 0.01h = 36s Table 1-10: MPU Instantaneous Output Variables Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 39 of 115 71M6511/71M6511H Demo Board User's Manual MPU STATUS WORD The MPU maintains the status of certain meter and I/O related variables in the Status Word. The Status Word is located at address 0x21. The bit assignments are listed in Table 1-11. Status Word Bit Name 0 Reserved 1 SAGA 2 Reserved Reserved 3 Reserved Reserved 4 F0 5 MAXV Overvoltage. 1 when overvoltage is detected. 6 MAXI Overcurrent. 1 when overcurrent is detected. 7 ONE_SEC Reserved 8 VXEDGE Reserved 9 Reserved 10 Reserved 11 XFER 12 CREEP 13-31 Reserved DESCRIPTION Reserved for sag flag phase A - not implemented1 Reconstructed line signal flag Reserved Creep bit. This bit is 1 when creep is detected. The creep bit is only set when a creep condition is active in both phases. Note: 1: Not implemented in Demo Code revision 3.04 Table 1-11: MPU Status Word Bit Assignment Page: 40 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual MPU ACCUMULATION OUTPUT VARIABLES Accumulation values are accumulated from XFER cycle to XFER cycle (see Table 1-12). They are all in 64bit format. The 6511 has an LSB of 6.6925*10-13*VMAX*IMAX*In_8 Wh. Thus, the accumulators will hold at least 136 years of data when XFER rate is 1Hz. The CLI commands with two Dollar signs e.g. )39$$ should be used to read the variables. When using the commands with two question marks, e.g. )39??, negative decimal values will be displayed when the most significant bit is set. XDATA Word Address Name 0x2F Reserved 0x31 Reserved 0x33 Reserved 0x35 Reserved 0x37 Reserved 0x39 Wh_A Total Watt hours consumed through phase A1) 0x3B Whe_A Total Watt hours generated (inverse consumed) through phase A1) 0x3D VARh_A Total VAR hours consumed through phase A2) 0x3F VARhe_A Total VAR hours generated (inverse consumed) through phase A2) 0x41 VAh_A Total VA hours in phase A3) 0x43 Wh_B Total Watt hours consumed through phase B1) 0x45 Whe_B Total Watt hours generated (inverse consumed) through phase B1) 0x47 VARh_B Total VAR hours consumed through phase B2) 0x49 VARhe_B Total VAR hours generated (inverse consumed) through phase B2) 0x4B VAh_B 0x4D Reserved 0x4F Reserved 0x51 Reserved 0x53 Reserved 0x55 Reserved Description Total VA hours in phase B3) Table 1-12: MPU Accumulation Output Variables Notes: 1) : If EQU = 0, Wh_A = real component of IA*VA and Wh_B = real component of IB*VA. If EQU = 1, Wh_A = real component of VA * (IA - IB)/2 and Wh_B = real component of VA*IB. 2) : If EQU = 0, VARh_A = reactive component of IA*VA and VARh_B = reactive component of IB*VA. If EQU = 1, VARh_A = VA * (IA - IB)/2 and Wh_B = VA*IB. 3) : If EQU = 0, VAh_A = apparent energy based on IA*VA and VAh_B = apparent energy based on IB*VA. If EQU = 1, VAh_A = apparent energy based on VA * (IA - IB)/2 and VAh_B = apparent energy based on VA*IB. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 41 of 115 71M6511/71M6511H Demo Board User's Manual MPU VARIABLES INDEPENDENTLY CONTROLLING THE SECOND CURRENT CHANNEL The 6511 Demo Code revision 3.05 offers independent scaling and creep suppression parameters for the second current channel (phase B). This is useful for meter configurations where different sensors are used for the primary and secondary channel. An example for this would be a meter using a CT for phase A and an additional resistive shunt for phase B to counter tampering. In most cases, the input voltage at the IA and IB inputs generated by the current flowing through both sensors will not be identical due to the differing characteristics of the sensors. In order to enable comparative measurements and true application of tariffs, Demo Code revision 3.05 offers a set of variables used to scale the IB channel (phase B). The variables added in 6511 Demo Code revision 3.05 are shown in Table 1-13. Note that the values for IMAX, ICREEP2, and WCREEP2 are closely coupled: When entering a different value for IMAX2, ICREEP2 and WCREEP2 should be changed accordingly, if the accuracy of the creep detection is of interest. XRAM Word Address Default Value Name Description 0x2B 2080 IMAX2 The nominal external RMS current that corresponds to 250mV peak at the IB input. The meter uses this value to convert internal quantities to external. LSB=0.1A 0x2C 61 ICREEP2 If the squared current (ISQSUM from the CE) of phase B is below ICREEP2, the sample values for phase B are zeroed. In that case, the accumulators for Wh, VARh, and VAh are not updated and the instantaneous value of IRMS for phase B is zeroed. The default value corresponds to 0.00636A2 (80mA), if the default setting for IMAX2 is used. LSB = 6.6952*10-13 IMAX2 Wh 0x2D 8311 WCREEP2 If WSUM_2 or VARSUM_2 are below WCREEP2, the sample values for phase B are zeroed. In that case, the accumulators for Wh, VARh, and VAh are not updated and the instantaneous value of IRMS for phase B is zeroed. The default value corresponds to 2.5W, if the default settings for VMAX and IMAX2 are used. LSB = 6.6952*10-13 VMAX IMAX2 Wh Table 1-13: MPU Variables Related to Phase B (6511, Revision 3.05 only) Page: 42 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 1.10.3 USEFUL CLI COMMANDS INVOLVING THE MPU AND CE Table 1-14 shows a few essential commands involving MPU data memory. Command Description >)1=2 Clears the accumulators for Wh, VARh, and VAh by setting bit 1 of the CONFIG register. >)7=1 Switches the Wh pulse source to W0SUM >)7=2 Switches the Wh pulse source to W1SUM (e.g. when testing with single phase CT applied to phase B) >)A=+2080 Applies the value corresponding to 208A to the IMAX register >)9=+6000 Applies the value corresponding to 600V to the VMAX register >)22? Displays the operating time since the last power up (in 1/100 of hours) >)39$$ Displays the total accumulated Wh energy for phase A (two $$ used for full 64-bit hexadecimal display) >MR2.1 Displays the current RMS voltage in phase A >MR1.2 Displays the current RMS current in phase B ]U Stores the current CE RAM variables in flash memory. The stored variables will be applied by the MPU at the next reset or power-up. Table 1-14: CLI Commands for MPU Data Memory Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 43 of 115 71M6511/71M6511H Demo Board User's Manual Page: 44 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 2 2 APPLICATION INFORMATION 2.1 CALIBRATION THEORY A typical meter has phase and gain errors as shown by S, AXI, and AXV in Figure 2-1. Following the typical meter convention of current phase being in the lag direction, the small amount of phase lead in a typical current sensor is represented as -S. The errors shown in Figure 2-1 represent the sum of all gain and phase errors. They include errors in voltage attenuators, current sensors, and in ADC gains. In other words, no errors are made in the `input' or `meter' boxes. INPUT I L L is phase lag ERRORS -S METER IRMS A XI V IDEAL = I , S is phase lead W V RMS AXV ERROR ACTUAL = I AXI IDEAL = IV cos( L ) ACTUAL = IV AXI AXV cos( L - S ) IDEAL = V , ACTUAL = V AXV ACTUAL - IDEAL = ACTUAL - 1 IDEAL IDEAL Figure 2-1: Watt Meter with Gain and Phase Errors. During the calibration phase, we measure errors and then introduce correction factors to nullify their effect. With three unknowns to determine, we must make at least three measurements. If we make more measurements, we can average the results. 2.1.1 CALIBRATION WITH THREE MEASUREMENTS The simplest calibration method is to make three measurements. Typically, a voltage measurement and two Watt-hour (Wh) measurements are made. A voltage display can be obtained for test purposes via the command >MR2.1 in the serial interface. Let's say the voltage measurement has the error EV and the two Wh measurements have errors E0 and E60, where E0 is measured with L = 0 and E60 is measured with L = 60. These values should be simple ratios-- not percentage values. They should be zero when the meter is accurate and negative when the meter runs slow. The fundamental frequency is f0. T is equal to 1/fS, where fS is the sample frequency (2560.62Hz). Set all calibration factors to nominal: CAL_IA = 16384, CAL_VA = 16384, PHADJA = 0. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 45 of 115 71M6511/71M6511H Demo Board User's Manual From the voltage measurement, we determine that 1. AXV = EV + 1 We use the other two measurements to determine S and AXI. IV AXV AXI cos(0 - S ) - 1 = AXV AXI cos( S ) - 1 IV cos(0) 2. E0 = 2a. AXV AXI = 3. E 60 = IV AXV AXI cos(60 - S ) cos(60 - S ) - 1 = AXV AXI -1 IV cos(60) cos(60) 3a. E 60 = AXV AXI [cos(60) cos( S ) + sin(60) sin( S )] -1 cos(60) E0 + 1 cos( S ) = AXV AXI cos( S ) + AXV AXI tan(60) sin( S ) - 1 Combining 2a and 3a: 4. E 60 = E 0 + ( E 0 + 1) tan(60) tan( S ) 5. tan( S ) = 6. S = tan -1 E 60 - E 0 ( E 0 + 1) tan(60) E 60 - E 0 ( E 0 + 1) tan(60) and from 2a: 7. AXI = E0 + 1 AXV cos( S ) Now that we know the AXV, AXI, and S errors, we calculate the new calibration voltage gain coefficient from the previous ones: CAL _ V NEW = CAL _ V AXV We calculate PHADJ from S, the desired phase lag: [ ] tan( S ) 1 + (1 - 2 -9 ) 2 - 2(1 - 2 -9 ) cos(2f 0T ) PHADJ = 2 -9 -9 (1 - 2 ) sin( 2f 0T ) - tan( S ) 1 - (1 - 2 ) cos(2f 0T ) 20 Page: 46 of 115 [ (c) 2005-2007 TERIDIAN Semiconductor Corporation ] Revision 5.4 71M6511/71M6511H Demo Board User's Manual And we calculate the new calibration current gain coefficient, including compensation for a slight gain increase in the phase calibration circuit. CAL _ I AXI CAL _ I NEW = 1 1+ 2 - 20 PHADJ (2 + 2 - 20 PHADJ - 2(1 - 2 -9 ) cos(2f 0T )) 1 - 2(1 - 2 -9 ) cos(2f 0T ) + (1 - 2 -9 ) 2 2.1.2 CALIBRATION WITH FIVE MEASUREMENTS The five measurement method provides more orthogonality between the gain and phase error derivations. This method involves measuring EV, E0, E180, E60, and E300. Again, set all calibration factors to nominal, i.e. CAL_IA = 16384, CAL_VA = 16384, PHADJA = 0. First, calculate AXV from EV: 1. AXV = EV + 1 Calculate AXI from E0 and E180: IV AXV AXI cos(0 - S ) - 1 = AXV AXI cos( S ) - 1 IV cos(0) 2. E0 = 3. E180 = 4. E 0 + E180 = 2 AXV AXI cos( S ) - 2 5. AXV AXI = 6. AXI = IV AXV AXI cos(180 - S ) - 1 = AXV AXI cos( S ) - 1 IV cos(180) E 0 + E180 + 2 2 cos( S ) ( E 0 + E180 ) 2 + 1 AXV cos( S ) Use above results along with E60 and E300 to calculate S. 7. E 60 = IV AXV AXI cos(60 - S ) -1 IV cos(60) = AXV AXI cos( S ) + AXV AXI tan(60) sin( S ) - 1 8. E300 = IV AXV AXI cos(-60 - S ) -1 IV cos(-60) = AXV AXI cos( S ) - AXV AXI tan(60) sin( S ) - 1 Subtract 8 from 7 9. E 60 - E300 = 2 AXV AXI tan(60) sin( S ) use equation 5: Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 47 of 115 71M6511/71M6511H Demo Board User's Manual E 0 + E180 + 2 tan(60) sin( S ) cos( S ) 10. E 60 - E300 = 11. E 60 - E300 = ( E 0 + E180 + 2) tan(60) tan( S ) 12. S = tan -1 ( E 60 - E300 ) tan(60)( E 0 + E180 + 2) Now that we know the AXV, AXI, and S errors, we calculate the new calibration voltage gain coefficient from the previous ones: CAL _ V NEW = CAL _ V AXV We calculate PHADJ from S, the desired phase lag: [ ] tan( S ) 1 + (1 - 2 -9 ) 2 - 2(1 - 2 -9 ) cos(2f 0T ) PHADJ = 2 20 -9 -9 (1 - 2 ) sin( 2f 0T ) - tan( S ) 1 - (1 - 2 ) cos(2f 0T ) [ ] And we calculate the new calibration current gain coefficient, including compensation for a slight gain increase in the phase calibration circuit. CAL _ I NEW = 2.2 CAL _ I AXI 1 1+ 2 - 20 PHADJ (2 + 2 PHADJ - 2(1 - 2 -9 ) cos(2f 0T )) 1 - 2(1 - 2 -9 ) cos(2f 0T ) + (1 - 2 -9 ) 2 - 20 CALIBRATION PROCEDURES Calibration requires that a calibration system is used, i.e. equipment that applies accurate voltage, load current and load angle to the unit being calibrated, while measuring the response from the unit being calibrated in a repeatable way. By repeatable we mean that the calibration system is synchronized to the meter being calibrated. Best results are achieved when the first pulse from the meter opens the measurement window of the calibration system. This mode of operation is opposed to a calibrator that opens the measurement window at random time and that therefore may or may not catch certain pulses emitted by the meter. It is essential for a valid meter calibration to have the voltage stabilized a few seconds before the current is applied. This enables the Demo Code to initialize the 71M6511/6511H and to stabilize the PLLs and filters in the CE. This method of operation is consistent with meter applications in the field as well as with metering standards. Each meter phase must be calibrated individually. The procedures below show how to calibrate a meter phase with either three or five measurements. The PHADJ equations apply only when a current transformer is used for the phase in question. Note that positive load angles correspond to lagging current (see Figure 2-2). Page: 48 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Voltage Positive direction Current lags voltage (inductive) +60 Current -60 Current leads voltage (capacitive) Voltage Generating Energy Using Energy Figure 2-2: Phase Angle Definitions The calibration procedures described below should be followed after interfacing the voltage and current sensors to the 71M6511/6511H chip. When properly interfaced, the V3P3 power supply is connected to the meter neutral and is the DC reference for each input. Each voltage and current waveform, as seen by the 71M6511/6511H, is scaled to be less than 250mV (peak). 2.2.1 CALIBRATION PROCEDURE WITH THREE MEASUREMENTS The calibration procedure is as follows: 1) All calibration factors are reset to their default values, i.e. CAL_IA = CAL_VA = 16384, and PHADJ_A = 0. 2) An RMS voltage Videal consistent with the meter's nominal voltage is applied, and the RMS reading Vactual of the meter is recorded. The voltage reading error Axv is determined as Axv = (Vactual - Videal ) / Videal Revision 5.4 3) Apply the nominal load current at phase angles 0 and 60, measure the Wh energy and record the errors E0 and E60. 4) Calculate the new calibration factors CAL_IA, CAL_VA, and PHADJ_A, using the formulae presented in section 2.1.1 or using the spreadsheet presented in section 2.2.3. 5) Apply the new calibration factors CAL_IA, CAL_VA, and PHADJ_A to the meter. The memory locations for these factors are given in section 1.9.1. 6) Test the meter at nominal current and, if desired, at lower and higher currents and various phase angles to confirm the desired accuracy. 7) Store the new calibration factors CAL_IA, CAL_VA, and PHADJ_A in the flash memory of the meter. If the calibration is performed on a TERIDIAN Demo Board, the methods shown in sections 1.9.3 and 1.9.3 can be used. 8) For added temperature compensation, read the value in CE RAM location 0x54 and write it to CE RAM location 0x11. If Demo Code 3.05 or later is used, this will automatically calculate the correction coefficients PPMC and PPMC2 from the nominal temperature entered in CE location 0x11 and from the characterization data contained in the on-chip fuses. (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 49 of 115 71M6511/71M6511H Demo Board User's Manual 2.2.2 CALIBRATION PROCEDURE WITH FIVE MEASUREMENTS The calibration procedure is as follows: 1) All calibration factors are reset to their default values, i.e. CAL_IA = CAL_VA = 16384, and PHADJ_A = 0. 2) An RMS voltage Videal consistent with the meter's nominal voltage is applied, and the RMS reading Vactual of the meter is recorded. The voltage reading error Axv is determined as Axv = (Vactual - Videal ) / Videal 3) Apply the nominal load current at phase angles 0, 60, 180 and -60 (-300). Measure the Wh energy each time and record the errors E0, E60, E180, and E300. 4) Calculate the new calibration factors CAL_IA, CAL_VA, and PHADJ_A, using the formulae presented in section 2.1.2 or using the spreadsheet presented in section 2.2.3. 5) Apply the new calibration factors CAL_IA, CAL_VA, and PHADJ_A to the meter. The memory locations for these factors are given in section 1.9.1. 6) Test the meter at nominal current and, if desired, at lower and higher currents and various phase angles to confirm the desired accuracy. 7) Store the new calibration factors CAL_IA, CAL_VA, and PHADJ_A in the flash memory of the meter. If the calibration is performed on a TERIDIAN Demo Board, the methods shown in sections 1.9.3 and 1.9.3 can be used. 8) For added temperature compensation, read the value in CE RAM location 0x54 and write it to CE RAM location 0x11. If Demo Code 3.05 or later is used, this will automatically calculate the correction coefficients PPMC and PPMC2 from the nominal temperature entered in CE location 0x11 and from the characterization data contained in the on-chip fuses. 2.2.3 CALIBRATION SPREADSHEETS Calibration spreadsheets are available from TERIDIAN Semiconductor. They are also included in the CDROM shipped with any Demo Kit. Figure 2-3 shows the spreadsheet for three measurements with three phases in use (only one phase needs to be used for the 71M6511/6511H chip). Figure 2-3 shows the spreadsheet for five measurements with three phases (only one phase needs to be used for the 71M6511/6511H chip). Page: 50 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 71M6511/71M6513/71M6515 Calibration Worksheet Three Measurements Enter values in yellow fields Results will show in green fields... [Hz] AC frequency: 50 (click on yellow field to select from pull-down list) PHASE A: % fraction Energy reading at 0 0 0 Energy reading at +60 0 0 Voltage reading at 0 0 0 Expected voltage Measured voltage 240 240 PHASE B: Energy reading at 0 Energy reading at +60 Energy reading at 0 10 10 10 Expected voltage Measured voltage 240 264 PHASE C: Energy reading at 0 Energy reading at +60 Energy reading at 0 Expected voltage Measured voltage -3.8 -15.4 -3.8 REV Date: 4.0 9/28/2005 WJH Author: CAL_IA CAL_VA PHADJ_A Voltage 16384 16384 0 Current lags voltage (inductive) Positive direction 0.1 0.1 0.1 CAL_IB CAL_VB PHADJ_B 16384 14895 0 -0.038 -0.154 -0.038 CAL_IC CAL_VC PHADJ_C 16357 17031 -12434 +60 Current -60 Current leads voltage (capacitive) Voltage Generating Energy Using Energy Readings: Enter 0 if the error is 0%, 240 230.88 enter -3 if meter runs 3% slow. Figure 2-3: Calibration Spreadsheet for Three Measurements 71M6511/71M6513/71M6515 Calibration Worksheet Five Measurements PI REV Date: 0.023803667 Ts AC frequency: 60 [Hz] (click on yellow field to select from pull-down list) PHASE A: % fraction Energy reading at 0 2 0.02 CAL_IA Energy reading at +60 2.5 0.025 CAL_VA Energy reading at -60 1.5 0.015 PHADJ_A Energy reading at 180 2 0.02 Voltage error at 0 1 0.01 Expected voltage PHASE B: Energy reading at 0 Energy reading at +60 Energy reading at -60 Energy reading at 180 Voltage error at 0 Expected voltage PHASE C: Energy reading at 0 Energy reading at +60 Energy reading at -60 Energy reading at 180 Voltage error at 0 Expected voltage 240 242.4 % 2 2 2 2 1 fraction 0.02 0.02 0.02 0.02 0.01 240 242.4 % 0 0 0 0 0 fraction 0 0 0 0 0 240 240 Author: 4.0 9/28/2005 WJH Voltage 16219 16222 445 Measured voltage CAL_IB CAL_VB PHADJ_B Results will show in green fields... Enter values in yellow fields! Positive direction Current Current leads voltage (capacitive) Voltage Generating Energy 16384 16384 0 +60 -60 16223 16222 0 Measured voltage CAL_IC CAL_VC PHADJ_C Current lags voltage (inductive) Using Energy Readings: Enter 0 if the error is 0%, enter +5 if meter runs 5% fast, enter -3 if meter runs 3% slow. Measured voltage Figure 2-4: Calibration Spreadsheet for Five Measurements Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 51 of 115 71M6511/71M6511H Demo Board User's Manual 2.2.4 COMPENSATING FOR NON-LINEARITIES Nonlinearity is most noticeable at low currents, as shown in Figure 2-5, and can result from input noise and truncation. Nonlinearities can be eliminated using the QUANT variable. 12 error [%] 10 error 8 6 4 2 0 0.1 1 10 100 I [A] Figure 2-5: Non-Linearity Caused by Quantification Noise The error can be seen as the presence of a virtual constant noise current. While 10mA hardly contribute any error at currents of 10A and above, the noise becomes dominant at small currents. The value to be used for QUANT can be determined by the following formula: error V I 100 QUANT = - VMAX IMAX LSB Where error = observed error at a given RMS voltage (V) and RMS current (I), VMAX = voltage scaling factor, as described in section 1.8, IMAX = current scaling factor, as described in section 1.8, LSB = QUANT LSB value = 7.4162*10-10W Example: Assuming an observed error as in Figure 2-5, we determine the error at 1A RMS to be +1%. If VMAX is 600V and IMAX = 208A, and if the measurement was taken at 240V RMS, we determine QUANT as follows: 1 240 1 100 QUANT = - = -11339 600 208 7.4162 10 -10 QUANT is to be written to the CE location 0x2F. It does not matter which current value is chosen as long as the corresponding error value is significant (5% error at 0.2A used in the above equation will produce the same result for QUANT). Input noise and truncation can cause similar errors in the VAR calculation that can be eliminated using the QUANT_VAR variable. QUANT_VAR is determined using the same formula as QUANT. Page: 52 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 2.2.5 CALIBRATING METERS WITH COMBINED CT AND SHUNT RESISTOR In many cases it is desirable to discourage tampering by using two current sensors. Simple tampering methods based on connecting the low side of the load to earth ground (neutral) can be detected by adding a second current sensor in the neutral path, as shown in Figure 2-6. In this configuration, the shunt resistor is connected to the IA channel while the current transformer is connected to the IB channel of the 71M6511. Calibrating this arrangement requires a few extra steps above the regular calibration. The calibration procedure applies to the sensor arrangement described above (SHUNT = IA, CT = IB) and Demo Code 3.04. Preparation: 1. Set the meter equation field of the configuration RAM for EQU to zero using the command: RI0=10 // EQU = 0; CE_EN =1; TMUX = 0; 2. For the sake of calculation, individual WRATE parameters for Pulse generation, i.e. WRATE_SHUNT and WRATE_CT will be used. 3. It is also necessary to compute and estimate IMAX_SHUNT and IMAX_CT parameters for meter billing purposes. 4. Using IMAX_SHUNT and VMAX, the energy calculations for channel A should be performed. 5. The energy calculations for channel B should be performed using IMAX_CT and VMAX. 6. The LSB values for measurements for W0SUM, W1SUM, VAR0SUM, VAR1SUM, I0SQSUM, I1SQSUM, and V0SQSUM should be modified to compute the correct energy values. That is, IMAX_SHUNT and IMAX_CT should be applied separately to individual channels based on the sensor connections. 7. Before starting a calibration, all calibration factors must be in their default state, i.e. CAL_IA (0x08), CAL_VA (0x09), CAL_IB (0x0A) must be +16384. PHADJ_A (0x0E) and PHADJ_B (0x0F) should be zero. LIVE NEUT SHUNT CT LOAD 71M6511 IB IA VA V3P3 Figure 2-6: 71M6511 with Shunt and CT Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 53 of 115 71M6511/71M6511H Demo Board User's Manual The calibration procedure, using Demo Code revision 3.04, is as follows: Calibrating for Shunt Resistor (Channel A): 1. Calculate IMAX for the shunt resistor (IMAX_SHUNT). This can be done by using the following formula: IMAX_SHUNT = ViMAX/RSH The ViMAX value is the maximum analog input voltage for the channel, typically 177mV (RMS), and RSH is the resistance value of the shunt resistor. The value obtained for IMAX_SHUNT is stored at the MPU address 0x0A, using the CLI command )A= IMAX_SHUNT 2. Compute WRATE_SHUNT based on IMAX_SHUNT and VMAX and the formula given in 1.8.2: WRATE_SHUNT = (IMAX_SHUNT * VMAX * 47.1132) / (Kh * In_8 * NACC * X) Use VMAX = 600V (RMS) for the 6511 Demo Board if the resistor divider for VA has not been changed. 3. Update the WRATE register (at CE address 0x2D) with WRATE_SHUNT, using the command ]2D= WRATE_SHUNT. 4. Test for accuracy at 15A, 240V at phase angle 0, phase angle 60 and at phase angle -60. 5. Apply the error values to the calibration spreadsheet (revision 2.0 or later) and determine the calibration factors for channel A, i.e. CAL_IA, CAL_VA, and PHADJ_A. 6. Update the CE registers 0x08, 0x09 and 0x0E of the compute engine with the calibration factors obtained from the spreadsheet, using the commands ]8=CAL_IA, ]9=CAL_VA, and ]E=PHADJ_A. 7. Retest for accuracy at several currents and phase angles. At this point, channel A is calibrated. WSUM will be based on the voltage applied to the meter and the current flowing through the shunt resistor. The pulses generated will be based on the parameters entered for channel A. Calibration for CT (Channel B): 1. Compute IMAX for the CT channel (IMAX_CT), based on the CT turns ratio N and the termination resistor value RT using the formula: IMAX_CT = 177mV* N / RT This value is used in the following step as IMAX_CT. 2. Compute WRATE_CT based on the values obtained for IMAX_CT and the formula given in 1.8.2: WRATE_CT = (IMAX_CT * VMAX * 47.1132) / (Kh * In_8 * NACC * X) 3. Update the WRATE register (CE address 0x2D) with WRATE_CT, using the command ]2D= WRATE_CT. 4. Enter the command >)7=2. Configure W1SUM as external pulse source since the CT is connected to Channel 1 for VA*IB. 5. Test for accuracy at 15A, 240V at phase angle 0, phase angle 60 and at phase angle -60. 6. Apply these values to the calibration spread sheet (revision 4.0 or later) and derive the calibration factor PHADJ_B. 7. Update only the CE address 0x0F with the value for PHADJ_B using the command ]F= PHADJ_B. Page: 54 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 8. Adjust CAL_IB for the total error found in the accuracy test using the formula CAL_IB = 16384 * (1 - error/100) That is, if the chip reports an error of -2.5%, CAL_IB should be adjusted to a value of (16384 * (1 - (-2.5/100)). 9. Since CAL_VA and CAL_IA have already been adjusted for channel A, these registers should not be updated. 10. Retest for accuracy at several currents and phase angles. After completing the calibration, the energy values W0SUM, based on VA*IA and W1SUM, based on VA*IB are accessible to the MPU firmware. The pulse rate is controlled by W1SUM and determined by the parameters selected for the CT channel (VA, IB). Differences between W0SUM and W1SUM, indicating tampering, can be detected by the MPU for each accumulation interval. The user has to customize the Demo Code to utilize the values obtained from the VA, IA, and IB channels for proper calculation of tariffs. Table 2-1 summarizes the important parameters used in the calibration procedure. Channel, Sensor Formulae I Measurement Using Parameters W Pulse Generation VAR Pulse Generation A, Shunt Resistor WASUM = VA*IA VARASUM = VA*IA IMAX_SHUNT IMAX = IMAX_SHUNT WRATE = WRATE_SHUNT WASUM VARASUM B, CT WBSUM = VA*IB VARBSUM = VA*IB IMAX_SHUNT IMAX = IMAX_CT WRATE = WRATE_CT WBSUM VARBSUM Table 2-1: Calibration Summary In Demo Code revision 3.05, the calibration procedure is simplified since separate IMAX parameters for both channels are available. The calibration procedure, is as follows: Calibrating for Shunt Resistor (Channel A): 1. Calculate IMAX for the shunt resistor (IMAX_SHUNT). This can be done by using the following formula: IMAX_SHUNT = ViMAX/RSH The ViMAX value is the maximum analog input voltage for the channel, typically 177mV (RMS), and RSH is the resistance value of the shunt resistor. The value obtained for IMAX_SHUNT is stored at the MPU address 0x0A, using the CLI command )A= IMAX_SHUNT 2. Compute WRATE_SHUNT based on IMAX_SHUNT and VMAX and the formula given in 1.8.2: WRATE_SHUNT = (IMAX_SHUNT * VMAX * 47.1132) / (Kh * In_8 * NACC * X) Use VMAX = 600V (RMS) for the 6511 Demo Board if the resistor divider for VA has not been changed. Revision 5.4 3. Update the WRATE register (at CE address 0x2D) with WRATE_SHUNT, using the command ]2D= WRATE_SHUNT. 4. Test for accuracy at 15A, 240V at phase angle 0, phase angle 60 and at phase angle -60. (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 55 of 115 71M6511/71M6511H Demo Board User's Manual 5. Apply the error values to the calibration spreadsheet (revision 4.0 or later) and determine the calibration factors for channel A, i.e. CAL_IA, CAL_VA, and PHADJ_A. 6. Update the CE registers 0x08, 0x09 and 0x0E of the compute engine with the calibration factors obtained from the spreadsheet, using the commands ]8=CAL_IA, ]9=CAL_VA, and ]E=PHADJ_A. 7. Retest for accuracy at several currents and phase angles. At this point, channel A is calibrated. WSUM will be based on the voltage applied to the meter and the current flowing through the shunt resistor. The pulses generated will be based on the parameters entered for channel A. Calibration for CT (Channel B): 1. Compute IMAX for the CT channel (IMAX_CT), based on the CT turns ratio N and the termination resistor value RT using the formula: IMAX_CT = 177mV* N / RT Store the value obtained for IMAX_CT at the MPU address 0x2B (IMAX2), using the CLI command )2B= IMAX_CT. This value is used in the following step as IMAX_CT. 2. Compute WRATE_CT based on the values obtained for IMAX_CT and the formula given in 1.8.2: WRATE_CT = (IMAX_CT * VMAX * 47.1132) / (Kh * In_8 * NACC * X) 3. Update the WRATE register (CE address 0x2D) with WRATE_CT, using the command ]2D= WRATE_CT. 4. Enter the command >)7=2 to configure W1SUM as the external pulse source, since the CT is connected to Channel 1 for VA*IB. 5. Test channel B for accuracy at 15A, 240V at phase angle 0, phase angle 60 and at phase angle - 60. 6. Apply the error values to the calibration spread sheet (revision 4.0 or later) and derive the calibration factor PHADJ_B. 7. Update only the CE address 0x0F with the value for PHADJ_B using the command ]F= PHADJ_B. 8. Adjust CAL_IB for the total error found in the accuracy test using the formula CAL_IB = 16384 * (1 - error/100) 9. Since CAL_VA and CAL_IA have already been adjusted for channel A, these registers should not be updated. 10. Retest channel B for accuracy at several currents and phase angles. After completing the calibration, the energy values W0SUM, based on VA*IA and W1SUM, based on VA*IB are accessible to the MPU firmware. The pulse rate is controlled by W1SUM and determined by the parameters selected for the CT channel (VA, IB). Differences between W0SUM and W1SUM, indicating tampering, can be detected by the MPU for each accumulation interval. The user has to customize the Demo Code to utilize the values obtained from the VA, IA, and IB channels for proper calculation of tariffs. Page: 56 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Table 2-2 summarizes the important parameters used in the calibration procedure. Channel, Sensor Formulae I Measurement Using Parameters W Pulse Generation VAR Pulse Generation A, Shunt Resistor WASUM = VA*IA VARASUM = VA*IA IMAX_SHUNT IMAX = IMAX_SHUNT WRATE = WRATE_SHUNT WASUM VARASUM B, CT WBSUM = VA*IB VARBSUM = VA*IB IMAX_CT IMAX = IMAX_CT WRATE = WRATE_CT WBSUM VARBSUM Table 2-2: Calibration Summary Due to Demo Code revision 3.05 offering separate IMAX parameters for channels A and B it is possible to define individual creep settings for each channel (see section 1.10.2 for details). 2.3 POWER SAVING MEASURES In many cases, especially when operating the TERIDIAN 71M6511/71M6511H from a battery, it is desirable to reduce the power consumed by the chip to a minimum. This can be achieved with the measures listed in Table 2-3. Power Saving Measure Software Control Typical Savings Disable the CE CE_EN = 0 0.16mA Disable the ADC ADC_DIS = 1 1.8mA Disable clock test output CKTEST CKOUTDIS = 1 0.6mA Disable emulator clock ECK_DIS = 1 0.1mA Set flash read pulse timing to 33 ns FLASH66Z =1 0.04mA Disable the LCD voltage boost circuitry LCD_BSTEN = 0 0.9mA Disable RTM outputs RTM_EN = 0 0.01mA Disable SSI output SSI_EN = 0 Select DGND for the multiplexer input TMUX[3:0] = 0 Disable reference voltage output VREF_DIS = 1 Reduce the clock for the MPU MPU_DIV = 5 0.4mA/MHz Table 2-3: Power Saving Measures Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 57 of 115 71M6511/71M6511H Demo Board User's Manual 2.4 SCHEMATIC INFORMATION In this section, hints on proper schematic design are provided that will help designing circuits that are functional and sufficiently immune to EMI (electromagnetic interference). 2.4.1 COMPONENTS FOR THE V1 PIN The V1 pin of the 71M6511/6511H can never be left unconnected. A voltage divider should be used to establish that V1 is in a safe range when the meter is in mission mode (V1 must be lower than 2.9V in all cases in order to keep the hardware watchdog timer enabled). For proper debugging or loading code into the 71M6513 mounted on a PCB, it is necessary to have a provision like the header JP1 shown above R1 in Figure 2-7. A shorting jumper on this header pulls V1 up to V3P3 disabling the hardware watchdog timer. JP1 V3P3 2 R1 10K 1 HDR 1x2 L1 V1 D10 FERRITE UCLAMP3301D R2 21.5K C1 10uF C2 1000pF GND Figure 2-7: Voltage Divider for V1 On the 6511 Demo Boards this feature is implemented with resistors R83/R86, capacitor C34 (2-Layer Demo Board only) and TP10. See the board schematics in the Appendix for details. 2.4.2 RESET CIRCUIT Even though a functional meter will not necessarily need a reset switch, the 71M6511 Demo Boards provide a reset pushbutton that can be used when prototyping and debugging software. When a circuit is used in an EMI environment, the RESETZ pin should be supported by the external components shown in Figure 2-8. R1 should be in the range of 200, R2 should be around 10. The capacitor C1 should be 1nF. R1 and C1 should be mounted as close as possible to the IC. In cases where the trace from the pushbutton switch to the RESETZ pin poses a problem, R2 can be removed. V3P3 R1 200 SW1 R3 PB-SW R2 10 RESETZ 0 C2 0.1uF C1 1000pF GND Figure 2-8: External Components for RESETZ Page: 58 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 2.4.3 OSCILLATOR The oscillator of the 71M6511 drives a standard 32.768kHz watch crystal (see Figure 2-9). Crystals of this type are accurate and do not require a high current oscillator circuit. The oscillator in the 71M6511 has been designed specifically to handle watch crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT pin. 71M651X 10pF XIN crystal XOUT 10pF Figure 2-9: Oscillator Circuit It is not necessary to place an external resistor across the crystal, i.e. R91 on the 4-Layer Demo Board must not be populated. Capacitor values for the crystal must be <15pF. 2.4.4 EEPROM EEPROMs should be connected to the pins DIO4 and DIO5 (see Figure 2-10). These pins can be switched from regular DIO to implement an I2C interface by setting the I/O RAM register DIO_EEX (0x2008[4]) to 1. Pull-up resistors of 3k must be provided for both the SCL and SDA signals. V3P3 651X 3k EEPROM DIO4 SCL DIO5 SDA Figure 2-10: EEPROM Circuit Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 59 of 115 71M6511/71M6511H Demo Board User's Manual 2.4.5 LCD The 71M6511 has an on-chip LCD controller capable of controlling static or multiplexed LCDs. Figure 2-11 shows the basic connection for LCDs. Note that the LCD module itself has no power connection. 651X LCD segments commons Figure 2-11: LCD Connections Figure 2-12 shows how 5V LCDs can be operated even when a 5V supply is not available. Setting the I/O RAM register LCD_BSTEN to 1 starts the on-chip boost circuitry that will output an AC frequency on the VDRV pin. Using a small coupling capacitor, two general-purpose diodes and a reservoir capacitor, a 5VDC voltage is generated which can be fed back into the VLCD pin of the 71M6511. The LCD drivers are enabled with the I/O register LCD_ON; I/O register LCD_FS is used to adjust contrast, and LCD_MODE selects the operation mode (LCD type). V3P3 LCD_BSTEN VDRV V3P3 5VDC 651X VLCD Contrast LCD_FS ON/OFF LCD_EN LCD type LCD_MODE 5V LCD segments commons Figure 2-12: LCD Boost and LCD Control Registers Page: 60 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 2.4.6 OPTICAL INTERFACE The 71M6511 IC is equipped with two pins supporting the optical interface: OPT_TX and OPT_RX. The OPT_TX pin can be used to drive a visual or IR light LED with up to 20mA, a series resistor (R2 in Figure 2-13) helps limiting the current). The OPT_RX pin can be connected to the collector of a photo-transistor, as shown in Figure 2-13. 3.3V R1 71M651X OPT_RX Phototransistor 3.3V OPT_TX R2 LED Figure 2-13: Optical Interface Block Diagram On the 4-Layer Demo Boards, the current limiting resistor R79 is provided in between the OPT_TX pin of the chip and pin 2 of J12 (Figure 2-14). C21 on these boards should be shorted to create a DC path from the collector of the photo-transistor to the OPT_RX pin. 50mm (2") 71M6511/6513 OP804SL J12 V3P3 OPT_TX R79 V3P3 OP233W OPT_RX R1 C21 R84 GND R85 OP233W OP804SL Demo Board Figure 2-14: Optical Port Circuitry on the 4-Layer Demo Board The IR diode should be connected between terminal 2 of header J12 on the Demo Board (cathode) and the V3P3 voltage (anode), which is accessible at terminal 1 of header J12 (see Figure 2-14). The value of R79 may be increased or decreased in order to vary the diode current. R84 and R85 should be removed when operating the photo-transistor in the configuration shown. Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 61 of 115 71M6511/71M6511H Demo Board User's Manual J12 on the 2-Layer Demo Boards has all the provisions for connecting the IR LED and photo-transistor (see Figure 2-15). Depending on the required LED current, R79 may have to be scaled. Similarly, R84 may be scaled or removed, depending on the current generated by the photo-transistor. V3P3 OPT_TX J12 R79 OPT_TX_OUT 100 GND OPT_RX 1 2 3 4 5 HDR5x1 R84 47K GND OPTICAL I/F Figure 2-15: Optical Port Circuitry on the 2-Layer Demo Board 2.4.7 CONNECTING THE RX PIN Due to unique circuitry on the RX input, its behavior is slightly different from the other digital inputs of the 651X family of metering ICs. The Rx pin (serial port receive pin) of the 71M6511/6511H is internally clamped to the V3P3 supply as shown in Figure 2-16. This means, the voltage of signals applied to this pin will be clamped to V3P3D + 0.6V, i.e. nominally 3.9V. Note that this clamp voltage exceeds the 3.6V Absolute Maximum Rating of the RX input. Inputs above 1.6V (VIL) are guaranteed to be recognized as logic 1. Inputs below 0.8V (VIL) are guaranteed to be recognized as logic 0. Input voltages between 0.8V and 1.6V must be avoided. 71M6511 RX To serial receiver V3P3 Figure 2-16: Internal Diode Clamp on the RX Pin If inputs higher than 3.6V are expected at the RX pin, e.g. when interfacing to 5V-based driving circuitry such as RS232 transceivers/receivers, TTL or CMOS logic, a resistor attenuator should be used in order to restrict the RX input voltage. Page: 62 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 2-17 shows the recommended resistor network consisting of R1 (17k) and R2 (33k). This network scales the input voltage VIN of 5.5V to 3.6V, and an input voltage of 2.5V will be scaled to 1.6V. For the low voltage level, VIN voltages below 1.2V will be scaled to 0.8V. The maximum current at 5.5V input voltage is 5.5V/(50k) + IIH = 110A + 1A = 111A. 71M6511 VIN R1 = 17k RX R2 = 33k Figure 2-17: Resistor Network for RX Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 63 of 115 71M6511/71M6511H Demo Board User's Manual 2.5 TESTING THE DEMO BOARD This section will explain how the 71M6511/6511H IC and the peripherals can be tested. Hints given in this section will help evaluating the features of the Demo Board and understanding the IC and its peripherals. 2.5.1 FUNCTIONAL METER TEST This is the test that every Demo Board has to pass before being integrated into a Demo Kit. Before going into the functional meter test, the Demo Board has already passed a series of bench-top tests, but the functional meter test is the first test that applies realistic high voltages (and current signals from current transformers) to the Demo Board. Meter under Test AC Voltage Optical Pickup for Pulses Current CT Pulse Counter Calibrated Outputs Figure 2-18 shows a meter connected to a typical calibration system. The calibrator supplies calibrated voltage and current signals to the meter. It should be noted that the current flows through the CT or CTs that are not part of the Demo Board. The Demo Board rather receives the voltage output signals fro the CT. An optical pickup senses the pulses emitted by the meter and reports them to the calibrator. Some calibration systems have electrical pickups. The calibrator measures the time between the pulses and compares it to the expected time, based on the meter Kh and the applied power. PC Calibrator Figure 2-18: Meter with Calibration System TERIDIAN Demo Boards are not calibrated prior to shipping. However, the Demo Board pulse outputs are tested and compared to the expected pulse output. Figure 2-19 shows the screen on the controlling PC for a typical Demo Board. The number in the red field under "As Found" represents the error measured for phase A, while the number in the red field under "As Left" represents the error measured for phase B. Both numbers are given in percent. This means that for the measured Demo Board, the sum of all errors resulting from tolerances of PCB components, CTs, and 71M6511/6511H tolerances was -2.8% and -3.8%, a range that can easily be compensated by calibration. Page: 64 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 2-19: Calibration System Screen 2.5.2 EEPROM Testing the EEPROM provided on the Demo Board is straightforward and can be done using the serial command line interface (CLI) of the Demo Code. To write a string of text characters to the EEPROM and read it back, we apply the following sequence of CLI commands: >EEC1 Enables the EEPROM >EESthis is a test Writes text to the buffer >EET80 Writes buffer to address 80 Written to EEPROM address 00000080 74 68 69 73 20 69 73 20 61 .... Response from Demo Code >EER80.E Reads text from the buffer Read from EEPROM address 00000080 74 68 69 73 20 69 73 20 61 .... Response from Demo Code >EEC0 Revision 5.4 Disables the EEPROM (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 65 of 115 71M6511/71M6511H Demo Board User's Manual 2.5.3 RTC Testing the RTC inside the 71M6511/6511H IC is straightforward and can be done using the serial command line interface (CLI) of the Demo Code. To set the RTC and check the time and date, we apply the following sequence of CLI commands: >M10 LCD display to show calendar date >RTD05.09.27.3 Sets the date to 9/27/2005 (Tuesday) >M9 LCD display to show time of day >RTT10.45.00 Sets the time to 10:45:00. AM/PM distinction: 1:22:33PM = 13:22:33 2.5.4 HARDWARE WATCHDOG TIMER The hardware watchdog timer of the 71M6511/6511H is disabled when the voltage at the V1 pin is at 3.3V (V3P3). On the Demo Boards, this is done by plugging in a jumper at TP10 between the V1 and V3P3 pins. Programming the flash memory or emulation using the ADM51 In-Circuit-Emulator can only be done when a jumper is plugged in at TP10 between V1 and V3P3. Conversely, removing the jumper at TP10 will enable the hardware watchdog timer. 2.5.5 LCD Various tests of the LCD interface can be performed with the Demo Board, using the serial command line interface (CLI): The display outputs are enabled by setting the LCD_EN register to 1. Register Name Address [bits] R/W Description LCD_EN 2021[5] R/W Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are the COM and SEG outputs. To access the LCD_EN register, we apply the following CLI commands: >RI21$ Reads the hex value of register 0x2021 >25 Response from Demo Code indicating the bit 5 is set >RI21=5 Writes the hex value 0x05 to register 0x2021 causing the display to be switched off >RI21=25 Sets the LCD_EN register back to normal The 71M6511/6511H provides a charge pump capable of boosting the 3.3VDC supply voltage up to 5.0VDC. The boost circuit is enabled with the LCD_BSTEN register. The 6511 Demo Boards have the boost circuit enabled by default. Register Name Address [bits] R/W Description LCD_BSTEN 2020[7] R/W Enables the LCD voltage boost circuit. Page: 66 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual To disable the LCD voltage boost circuit, we apply the following CLI commands: >RI20$ Reads the hex value of register 0x2020 >8E Response from Demo Code indicating the bit 7 is set >RI20=E Writes the hex value 0x0E to register 0x2020 causing the LCD boost to be switched off >RI20=8E Enables the LCD boost circuit The LCD_CLK register determines the frequency at which the COM pins change states. A slower clock means lower power consumption, but if the clock is too slow, visible flicker can occur. The default clock frequency for the 71M6511/6511H Demo Boards is 150Hz (LCD_CLK = 01). Register Name Address [bits] R/W Description LCD_CLK[1:0] 2021[1:0] R/W Sets the LCD clock frequency, i.e. the frequency at which SEG and COM pins change states. fw = CKADC/128 = 38,400 9 8 7 6 00: fw/2 , 01: fw/2 , 10: fw/2 , 11: fw/2 To change the LCD clock frequency, we apply the following CLI commands: >RI21$ Reads the hex value of register 0x2021 >25 Response from Demo Code indicating the bit 0 is set and bit 1 is cleared. >RI21=24 Writes the hex value 0x24 to register 0x2021 clearing bit 0 - LCD flicker is visible now >RI21=25 Writes the original value back to LCD_CLK Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 67 of 115 71M6511/71M6511H Demo Board User's Manual 2.6 TERIDIAN APPLICATION NOTES Please contact your local TERIDIAN sales representative for TERIDIAN Application Notes. Available application notes are listed below. Number Title AN_651X_008 Optical Port AN_651X_009 Temperature Compensation AN_651X_013 Emulator Upgrade AN_651X_016 EMC/EMI Guidelines AN_651X_017 LCD AN_651X_018 Chop Enable AN_651X_019 RX Pin AN_651X_022 Calibration Procedures AN_6511_006 Current Shunt AN_651X_020 Calibration for Shunt and CT AN_651X_023 EMI-EMC Proof Meter Design Using the 6511 Page: 68 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 3 3 HARDWARE DESCRIPTION 3.1 4-LAYER BOARD DESCRIPTION: JUMPERS, SWITCHES, TEST POINTS The items described in the following tables refer to the flags in Figure 3-1. Item # (Figure 3.1) Electrical Schematic & PCB Silk-Print Reference 1 JP1 PS_SEL[0] Two-pin header. When the jumper is installed the on- board power supply (AC signal) is used to power the Demo Board. When not installed, the board must be powered by an external supply connect to J1. Normally installed. 2 J9 Neutral This is the NEUTRAL line voltage input. It is connected to the 3.3V net of the 71M6511/71M6511H. This input comes in from the bottom of the board. 3 JP2, JP3 PS_SEL[1], PS_SEL[2] Two-pin headers. When both jumpers are installed, external power is not required for the Debug Board that attaches to the 71M6511 Demo Board at J2. Normally left open. Name Use Caution! Do not install JP2/JP3! 4 J1 5 Volt supply 5 J4 VA_IN Plug for connection of the external 5 VDC power supply. VA_IN is the line voltage input. It has a resistor divider that leads to the VA pin on the chip that is the voltage input to the A/D converter. This input comes in from the bottom of the board. Caution: High Voltage. Do not touch these pins! 6 JP17 None Two-pin header. When the jumper is installed the resistor divider for VA is referenced to V3P3. The jumper must be removed when the board is used with a shunt resistor/CT combination on the IA and IB inputs. Normally installed. 7 JP16 None Two-pin header. When the jumper is installed V3P3 is connected to the 3.3V regulator D1. The jumper must be removed when the board is used with a shunt resistor/CT combination on the IA and IB inputs. Normally installed. Table 3-1: 71M6511 Demo Board Description: 1/3 Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 69 of 115 71M6511/71M6511H Demo Board User's Manual Item # (Figure 3.1) Elec. Schematic & PCB Silk-print Reference Name 8 TP2 VA 9 SW2 RESET 10 SW1 Pulse Rate Select 11 JP9 EEPROM Write Protect 12 J12 Supply and Optical Test Point 13 JP12 DIO Test Point 14 J2 DEBUG 15 J10, J11 LCD LCD connection. The LCD daughter board connects between these two 2x12 header jumpers. 16 BT1 Battery Terminal Two-pin header for connection of a 3.6V battery. The top pin is the positive terminal and the bottom pin is ground. 17 JP8 VBAT Selection Three-pin header that allows selection of power to the VBAT pin. When the jumper is placed between terminals 1 and 2 (default setting for Demo Board) VBAT is tied to the IC supply. When placed between terminals 2 and 3 VBAT is powered by an external battery. 18, 19 TP17, TP18 Test Mode Test Points TMUXOUT and CKTEST test point. 20 J14 EMULATOR I/F 2x10 emulator connector port for Signum ICE ADM-51. 21 J13 Voltage Connections 22 TP7 VREFOUT 23 TP10 V1 Test Point Two-pin header representing the comparator voltage input test point and ground. A jumper should be placed between V1 and V3P3 to disable the watchdog timer. 24 JP10 VLCD Select Three-pin header for selecting the voltage to the LCD. The top pin is 5V and the bottom pin is 3.3V. The default setting for the jumper is 5V Use Two-pin header test point. One pin is the VA line voltage input to the IC and the other pin is V3P3. Chip reset switch: The RESTZ pin has an internal pull up that allows normal chip operation. When the switch is pressed, the RESTZ pin is pulled low which resets the IC into a known state. Switch connected to the DIO17 pin (non functional in demo code). SW1 should always be kept in the lower position. Three-pin header that allows selection of the write protection or read/write capability for the EEPROM (U4) on the Demo Board. Default setting of the Demo Board is to place a jumper between terminal 1 and 2 of JP9. 4-pin header. Pins 1 and 3 can be used to measure the supply voltage to the 6511 IC. Terminal 2 monitors the TX_OPT output of the 6511 IC. Terminal 4 monitors the OPT_RX input to the 6511 IC. 7-pin test point. For monitoring DIO15 to DIO21. Debug Board connection connector. 2x8 pin header. Five-pin header. Connect jumper to the bottom two pins as the default Two-pin header. The top terminal is VREF, the bottom terminal is ground Table 3-2: 71M6511 Demo Board Description: 2/3 Page: 70 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Item # (Figure 3.1) Elec. Schematic & PCB Silk-print Reference Name 25 TP11, TP12 XIN, XOUT One-pin header test points that monitor the crystal inputs XIN and XOUT. 26 J3, J16 IA_IN, IB_IN Current shunt connections. Two-pin headers on bottom of the PCB. One terminal is 3.3V; the other is the shunt current. 27 TP1, TP19 IA, IB Two-pin headers that provide line current sense to the IC test points. One terminal is ground; the other is the respective line current sense input to the IC. 28 TP20 SSI 5x2 header. High-speed serial interface. One row is GND. Use Table 3-3: 71M6511 Demo Board Description: 3/3 Table 3-4 summarizes the jumper settings required for CT operation (factory default). Jumper Header Default Setting Function in Default (Factory) Setting JP1 Installed JP2/JP3 Not installed Enables the internal power supply JP8 V3P3-VBAT JP9 1-2 JP10 5V-VLCD Selects 5V supply provided by the VLCD driver for LCD operation. JP16 Installed Enables function of the Demo Board in CT mode JP17 Installed Enables function of the Demo Board in CT mode J13 V1IN-V3P3 TP10 V1-V3P3 Disconnects power and ground of the Demo Board from power and ground of the Debug Board. Headers are not populated on newer Demo Boards. Terminates the VBAT input properly when no battery is used. Enables read and write operations for the EEPROM (U5) Provides V3P3 to the V1 pin. Provides V3P3 to the voltage divider used for V1 pin. Table 3-4: Jumper Default Settings Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 71 of 115 71M6511/71M6511H Demo Board User's Manual 27 7 2 1 4 5 26 25 3 8 24 6 23 9 22 10 21 20 11 19 18 12 17 28 13 16 15 14 Figure 3-1: 71M6511 4-Layer Demo Board: Board Description Page: 72 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 3.2 2-LAYER BOARD DESCRIPTION: JUMPERS, SWITCHES, TEST POINTS Jumpers, headers, and connectors are largely identical for the two versions of the 2-Layer Demo Boards (capacitive and transformer power supply). The items described in the following tables refer to the flags in Figure 3-2 and Figure 3-3. Item # (Figure 3.2/3.3) Schematic & PCB Silk Screen Reference Name 1 J1 5 Volt supply 2 D5 WATTS 3 D6 VARS 4 TP22 VARS 5 J2 DEBUG Debug Board connector. 2x8 pin header. 6 TP21 WATTS Test points for pulses generated by the WATTS LED. 7 J12 V3P3, OPT_TX, V3P3, OPT_RX, GND 8 JP8 V3P3, VBAT, GND 9 JP17 SHUNT I/O 2-pin header. In CT mode, a jumper must be plugged into JP17. In shunt mode, one wire from the shunt resistor is connected to pin 1. 10 TP17 TMUXOUT, CKTEST 2-pin header providing test points for TMUXOUT and CKTEST. 11 JP10 V3P3, VLCD, 5V 12 TP20 SSI 13 J14 EMULATOR I/F 14 TP10 V1, V3P3 15 J13 V3P3, V1IN 2-pin header. A jumper should be placed between V1IN and V3P3 to supply 3.3V to the resistor divider generating V1. 16 TP7 GND, VREFOUT 2-pin header. Pin 2 is ground; pin 1 is the VREF output of the IC. 17 TP19 IB 2-pin header test point. Pin is the IB input to the IC and the other pin is V3P3. 18 TP1 IA 2-pin header test point. Pin is the IA input to the IC and the other pin is V3P3. Use Plug for connection of the external 5 VDC power supply. LED emitting WATT pulses. LED emitting VAR pulses. Test points for pulses generated by the VARS LED. 5-pin header. Pins 1 and 3 carry the supply voltage to the 6511 IC. Pin 2 is the TX_OPT output of the 6511 IC. Pin 4 is the OPT_RX input to the 6511 IC. Pin 5 is ground. 3-pin header for connection of a 3.6V battery. The battery is connected to pin 2 (+) and pin 3 (-). If no battery is used, a jumper is plugged over pins 1 and 2. 3-pin header for selecting the VLCD voltage. Pin 3 is 5V and pin 1 is 3.3V. The default setting for the jumper is 5V. 5x2 header. High-speed serial interface. One row is ground. 2x10 emulator connector port for Signum ICE ADM-51. 2-pin header representing the V1 comparator voltage input test point and ground. A jumper should be placed between V1 and V3P3 to disable the watchdog timer. Table 3-5: 71M6511 2-Layer Demo Board Description: 1/2 Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 73 of 115 71M6511/71M6511H Demo Board User's Manual Item # in Figure 3.2/3.3 Schematic & PCB Silk Screen Reference Name Use 19 TP13, TP14 GND Ground test points. 20 J3 IA_IN 3-pin header on the bottom of the board for connection of the CT for phase A. Pin 3 may be used to ground an optional cable shield. In shunt configuration, two wires from the shunt resistor representing the voltage across the shunt are connected to pins 1 and 2. 21 J16 IB_IN 3-pin header on the bottom of the board for connection of the CT for phase B. Pin 3 may be used to ground an optional cable shield. 22 J4 LIVE This is the line voltage input that feeds both the resistor divider leading to the VA pin on the chip and the internal power supply. The line voltage wire is connected to the spade terminal on the bottom of the board. 23 TP2 V3P3, VA 24 JP1 25 SW2 RESET Chip reset switch: The RESTZ pin has an internal pull up that allows normal chip operation. When the switch is pressed, the RESTZ pin is pulled low which resets the IC into a known state. 26 J9 NEUTRAL This is the NEUTRAL line voltage input. It is connected to the 3.3V net of the 71M6511/71M6511H. The neutral wire is connected to the spade terminal on the bottom of the board. 27 TP15 GND 28 JP4 SHUNT I/O Caution: High Voltage. Do not touch this pin! 2-pin header test point. Pin 1 is the VA line voltage input to the IC, pin 2 is V3P3. 2-pin header. When a jumper is installed, the on-board power supply (AC signal) is used to power the Demo Board. When not installed, the board must be powered by an external supply connected to J1. Normally installed. Ground test point. 3-pin header on the bottom side of the board. A wire from the shunt resistor connects to pin 2, while an optional shield can be connected to pin 3. When operating in CT mode, a jumper is plugged across pins 1 and 2. Table 3-6: 71M6511 2-Layer Demo Board Description: 2/3 Table 3-7 summarizes the jumper settings required for CT operation (factory default). Jumper Header Default Setting JP1 Installed JP8 V3P3-VBAT JP9 1-2 JP10 5V-VLCD JP4 1-2 Enables function of the Demo Board in CT mode JP17 Installed Enables function of the Demo Board in CT mode J13 V1IN-V3P3 TP10 V1-V3P3 Function in Default (Factory) Setting Enables the internal power supply Terminates the VBAT input properly when no battery is used. Enables read and write operations for the EEPROM (U5) Selects 5V supply provided by the VLCD driver for LCD operation. Provides V3P3 to the V1 pin. Provides V3P3 to the voltage divider used for V1 pin. Table 3-7: Jumper Default Settings Page: 74 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 7 8 9 10 11 6 13 5 14 4 15 3 16 2 17 1 18 27 19 26 25 24 28 22 23 21 20 Figure 3-2: D6511T4A8 Two-Layer Demo Board with Capacitive Power Supply Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 75 of 115 71M6511/71M6511H Demo Board User's Manual 7 8 9 10 11 12 6 13 5 14 4 15 3 16 2 17 1 18 27 19 26 25 24 28 22 23 21 20 Figure 3-3: 71M6511 Two-Layer Demo Board with Transformer Power Supply Page: 76 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 3.3 BOARD HARDWARE SPECIFICATIONS (4-LAYER) PCB Dimensions Diameter 6.5" (165.1mm) Thickness 0.062" (1.6mm) Height w/ components and 3/8" spacers 1.5" (38.1mm) Environmental Operating Temperature -40...+85C (function of crystal oscillator affected outside -10C to +60C) Storage Temperature -40C...+100C Power Supply Using AC Input Signal 180V...700V rms DC Input Voltage (powered from DC supply) 5VDC 0.5V Supply Current 25mA typical Input Signal Range AC Voltage Signal (VA) 0...240V rms AC Current Signals (IA, IB) from Transducer Interface Connectors DC Supply Jack (J1) to Wall Transformer 0...0.25V p/p Concentric connector, 2.5mm Emulator (J14) 10x2 Header, 0.05" pitch Input Signals Spade terminals and 0.1" headers on PCB bottom Debug Board (J2) 8x2 Header, 0.1" pitch Target Chip (U5) LQFP64 Socket SSI Connector (TP19) 5x2 Header, 0.1" pitch Functional Specification Time Base Frequency 32.768kHz, 20PPM at 25C Time Base Temperature Coefficient Controls and Displays Reset -0.04PPM/C2 (max) Button (SW2) Numeric Display 8-digit LCD, 8-segments per digit, 12.7mm character height, 89.0 x 17.7mm view area "Watts", "VARS" red LEDs (D5, D6) Measurement Range Voltage Current Revision 5.4 120...700 V rms (resistor division ratio 1:3,398) 1.7 termination for 2,000:1 CT input (200A) (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 77 of 115 71M6511/71M6511H Demo Board User's Manual 3.4 BOARD HARDWARE SPECIFICATIONS (2-LAYER) PCB Dimensions Dimensions 4.5" x 3.8" (114.3mm x 96.5mm) Thickness 0.062" (1.6mm) Height w/ components 2.0" (51mm) Environmental Operating Temperature -40...+85C (function of crystal oscillator affected outside -10C to +60C) Storage Temperature -40C...+100C Power Supply Using AC Input Signal 180V...700V rms DC Input Voltage (powered from DC supply) 5VDC 0.5V Supply Current 25mA typical Input Signal Range AC Voltage Signal (VA) 0...240V rms AC Current Signals (IA, IB) from Transducer Interface Connectors DC Supply Jack (J1) to Wall Transformer 0...0.25V p/p Concentric connector, 2.5mm Emulator (J14) 10x2 Header, 0.05" pitch Input Signals Spade terminals and 0.1" headers on PCB bottom Debug Board (J2) 8x2 Header, 0.1" pitch Target Chip (U5) LQFP64 Socket SSI Connector (TP19) 5x2 Header, 0.1" pitch Functional Specification Time Base Frequency 32.768kHz, 20PPM at 25C Time Base Temperature Coefficient Controls and Displays Reset -0.04PPM/C2 (max) Button (SW2) Numeric Display 8-digit LCD, 8-segments per digit, 12.7mm character height, 89.0 x 17.7mm view area "Watts", "VARS" red LEDs (D5, D6) Measurement Range Voltage Current Page: 78 of 115 120...700 V rms (resistor division ratio 1:3,398) 1.7 termination for 2,000 :1 CT input (200A) (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4 4 DEMO BOARD ELECTRICAL SECTION This section includes the following documentation, tables and drawings: 71M6511 4-Layer Demo Board Description 71M6511 Demo Board Electrical Schematic 71M6511 Demo Board Bill of Materials 71M6511 Demo Board PCB Silk screen layer - Top and Bottom side 71M6511 Demo Board PCB Metal Layer - Top and Bottom side 71M6511 Demo Board PCB Metal Layer - Middle 1, ground plane 71M6511 Demo Board PCB Metal Layer - Middle 2, supply plane 71M6511 2-Layer Demo Board Description 71M6511 Demo Board Electrical Schematic 71M6511 Demo Board Bill of Materials 71M6511 Demo Board PCB Silk screen layer - Top and Bottom side 71M6511 Demo Board PCB Metal Layer - Top and Bottom side Debug Board Description Debug Board Electrical Schematic Debug Board Bill of Materials Debug Board PCB Silk screen layer - Top and Bottom side Debug Board PCB Metal Layer - Top and Bottom side signal layer Debug Board PCB Metal Layer - Middle 1, ground plane Debug Board PCB Metal Layer - Middle 2, supply plane 71M6511 Pin-Out and Mechanical Description 71M6511 Pin Description 71M6511 Pin-out Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 79 of 115 71M6511/71M6511H Demo Board User's Manual 4.1 71M6511 4-LAYER DEMO BOARD ELECTRICAL SCHEMATIC VIA13 V3P3_JUMPER RV1 NC 1 1N4736A C6 6.8V, 1W V3P3 1 R2 8.06K 1 2 3 D3 HDR2X1 + C1 2200uF, 16V + C2 10uF, 10V R4 RAPC712 R6 D4 R7 100, 2W 1N4148 130 TL431 8 D1 + C4 33uF, 10V C5 0.1uF 6 2 5VDC EXT SUPPLY J1 1 1 2 1 JP16 25.5K R8 VA_IN GND POWER SUPPLY SELECTION JP2/JP3: DO NOT POPULATE 68 JP2 JP3 1 2 POWER SUPPLY SELECTION V3P3 IN EXT 5VDC SUPPLY THRU J1 OUT NC R100 R101 GND V3P3 GND HDR2X1 NC JP14 NC 1 2 JP1 ON BOARD SUPPLY JP13 NC POWER SUPPLY SELECTION TABLE SELECTION * JP12 * 1 2 HDR2X1 * = 1206 PACKAGE 1 2 HDR2X1 * R9 1 2 1 2 0.47uF, 1000Vdc JP1 0 R102 GND_DBG V5_DBG V3P3 GND NC SEG34/DIO14 SEG36/DIO16 GND GND GND GND GND_DBG V5_DBG J2 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 SEG35/DIO15 V3P3 CKTEST_T TMUXOUT_T UART_TX_T UART_RX GND_DBG V5_DBG HEADER 8X2 DEBUG CONNECTOR (pin 1, 2, 3 removed) NC R10 CKTEST 62 R11 TMUXOUT 62 R12 UART_TX 62 Figure 4-1: 71M6511 4-Layer Demo Board: Electrical Schematic 1/3 If the 4-Layer Demo Board has to be operated in an EMI environment, see Application Note 651X_016 and follow the schematic guidelines therein for necessary component modifications. Page: 80 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual VIA1 1 1 NC J4 VA_IN VA_IN 1 SPADE R15 220K R16 220K R17 220K R18 220K R19 220K R20 220K R21 V3P3_JUMPER2 220K R26 R27 R28 R29 R30 R31 220K 220K 220K 220K 120K 4.7K VIA10 1 JP17 HDR2X1 IA_IN IA_IN ' IA R32 750 R14 R110 0 U1 1 R24 3.4 * R25 3.4 * 1 2 3 HDR2X1 C9 1000pF IA V3P3 750 HDR2X1 NC 2 1 A1 C1 AC2 1 2 6 5 4 C8 1000pF V3P3 VA CURRENT SHUNT CONNECTIONS * = 1206 PACKAGE V3P3_JUMPER NEUTRAL 1 SPADE C14 1000pF GND VIA11 IB_IN 1 1 NC J16 IB_IN IB_IN ' IB_IN IB_IN 1 2 R104 R111 0 HDR2X1 VIA12 1 U6 1 R106 3.4 * NC IB V3P3 750 R107 3.4 * 1 2 3 A1 C1 AC2 AC1 C2 A2 BAV99DW 6 5 4 R105 0 1 2 IB C29 1000pF * = 1206 PACKAGE Figure 4-2: 71M6511 4-Layer Demo Board: Electrical Schematic 2/3 (c) 2005-2007 TERIDIAN Semiconductor Corporation TP19 HDR2X1 V3P3 CURRENT SHUNT CONNECTIONS Revision 5.4 TP1 HDR2X1 R22 0 AC1 C2 A2 BAV99DW V3P3_JUMPER2 J9 IA_IN 1 2 1 TP2 VA J3 VIA3 V3P3 1 NC VOLTAGE CONNECTIONS 1 NC 1 2 1 VIA2 Page: 81 of 115 SRDY MUX_SYNC V3P3 R73 NC GND 1 D5 WATTS R74 DIO06 V3P3 VARS R75 V3P3 C16 NC 10K SSI 1 2 3 RESETZ HDR3X1 RESET 10 PB-SW GND R82 1K R86 21.5K C22 0.1uF C23 1000pF C24 GND 10pF R91 NC C25 GND 10pF XIN Y1 TP11/TP12 32.768Khz 1 2 HDR2X1 XOUT GND V3P3 VA VBIAS IB IA VREF V1 OPT_RX GND XIN TEST XOUT VLCD E_RST E_TCLK 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 R94 GNDA V3P3A VA VBIAS IB IA VREF V1 OPT_RX GNDA XIN TEST XOUT VLCD E_RST E_TCLK 10K GND GND C26 220nF JP10 V3P3 1 2 3 VLCD SEL: 1--2 = 3.3V LCD 2--3 = 5V LCD 1 2 3 4 HDR12X2 LCD MSB FEMALE OPTICAL I/F HEADER VCC WP SCL SDA J12 1 2 3 4 OPT_TX_OUT 100 C20 GND 8 7 6 5 R79 C21 0.1uF OPT_RX_OUT OPT_RX 0.1uF V3P3 WP SEG24/DIO04 SEG25/DIO05 R84 47K HDR4X1 R85 470 GND SER EEPROM SERIAL EEPROM 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG07 SEG06 SEG36/DIO16 SEG35/DIO15 SEG34/DIO14 SEG02 SEG01 SEG00 R108 3K R109 3K OPTICAL I/F V3P3 DIO02 DIO01 DIO00 V3P3 J14 V3P3 R88 10K R89 3K E_RXTX R97 62 E_TCLK R98 62 E_RST R99 62 RXTX TCLK RST_EMUL 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 GND 0.05" HEADER 10X2 EMULATOR I/F C28 2 V3P3 NC A1 NC GND COM0 COM1 COM2 COM3 old dio3 HDR3X1 C27 D7 GND U4 GND GND E_RXTX OPT_TX TMUXOUT UART_TX SEG03 VDRV CKTEST V3P3 SEG04 SEG05 SEG37/DIO17 COM0 COM1 COM2 COM3 VLCD TP14 TP U5 6511-64TQFP SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG7/MUX_SYNC SEG6/SRDY SEG36/DIO16 SEG35/DIO15 SEG34/DIO14 SEG02 SEG01 SEG00 OPT_TX GND NC 2 4 6 8 10 12 14 16 18 20 22 24 10K HDR3X1 NC SEG27/DIO07 SEG26/DIO06 SEG25/DIO05 SEG24/DIO04 LCD CONNECTORS 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND GND R103 V3P3 HDR2X1 GND TP13 TP JP15 1 3 5 7 9 11 13 15 17 19 21 23 V3P3 JP9 WP SEL: 2--3 = RD ONLY 1--2 = RD/WR SEG31/DIO11 SEG30/DIO10 SEG29/DIO09 SEG28/DIO08 R78 V3P3 VBAT SELECTOR RESETZ V2P5 VBAT UART_RX SEG31/DIO11 SEG30/DIO10 SEG29/DIO09 SEG28/DIO08 SEG27/DIO07 SEG26/DIO06 SEG25/DIO05 SEG24/DIO04 SEG19 SEG18 SEG17 SEG16 GND MALE PULSE OUTPUT BATTERY (3.6V) SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 2 4 6 8 10 12 14 16 18 20 22 24 HDR12X2 LCD LSB SEG27/DIO07 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 HDR3X1 GND VREFOUT 2 1 V3P3 0.1uF BP1206 RESETZ V2P5 VBAT RX SEG31/DIO11 SEG30/DIO10 SEG29/DIO9 SEG28/DIO8 SEG27/DIO7 SEG26/DIO6 SEG25/DIO5 SEG24/DIO4 SEG19 SEG18 SEG17 SEG16 1 2 3 C18 VREF TP7 2 1 GND HDR2X1 GNDD E_RXTX OPT_TX TMUXOUT TX SEG3/SCLK VDRV CKTEST V3P3D SEG4/SDATA SEG5/SFR SEG37/DIO17 COM0 COM1 COM2 COM3 V1 TP10 C19 0.1uF GND V1IN V3P3 J11 1 3 5 7 9 11 13 15 17 19 21 23 10K BT1 CMP R83 10K LED RED JP8 V3P3 VBAT GND R77 SW2 C17 0.1uF + R76 DIO07 V3P3 SEG26/DIO06 SEG11 SEG10 SEG09 SEG08 SEG07 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 10K 1 2 1 3 5 7 9 2 4 6 8 10 HEADER 5X2 GND D6 V2P5 TP20 GND HDR3X1 SEG37/DIO17 2 3 LED RED 1 2 3 SW1 NC R112 R113 R114 R115 R116 NC NC NC NC NC J13 J10 PULSE RATE SELECT DO NOT POPULATE SEG07 SFR SEG06 SEG05 SCLK SDATA SEG03 SEG04 71M6511/71M6511H Demo Board User's Manual CPUMP 1 3 BAT54S/SOT TP17 1 2 HDR2X1 0.1uF GND 33nF TMUXOUT GND TMUXOUT CKTEST GND CKTEST TP18 1 2 HDR2X1 Figure 4-3: 71M6511 4-Layer Demo Board: Electrical Schematic 3/3 Page: 82 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4.2 71M6511 2-LAYER DEMO BOARD WITH CAPACITIVE POWER SUPPLY - ELECTRICAL SCHEMATIC 3 2 1 JP16 GND C7 * 0.47uF, 1000VDC L8 1 C16 LIVE LIVE R6 D4 100, 2W 1N4148 1 8.06K + C1 2200uF, 16V 8 U2 1 TL431 + C2 10uF, 10V R4 RAPC712 + C4 33uF, 16V C5 0.1uF R7 VA_IN 10, 3W R118 D8 C3 1000pF UCLAMP3301D 25.5K GND JP1 130 * * = 1206 PACKAGE 1 2 J4 6.8V, 1W 1 2 3 2 1N4736A 1 R8 1 D3 6 0.03uF, 250VDC V3P3 R2 5Vdc EXT SUPPLY J1 2 C32 RV1 VARISTOR L1 1000pF V3P3_JUMPER PS_SEL[0] R9 68.1 POWER SUPPLY SELECTION TABLE SELECTION PS_SEL[0] (JP1) ON BOARD SUPPLY IN EXT 5Vdc SUPPLY THRU J1 OUT * C37 NC GND GND GND GND J2 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 R10 V3P3 CKTEST 62 UART_RX R11 TMUXOUT 62 HEADER 8X2 R12 DEBUG CONNECTOR UART_TX R13 10K 62 GND Figure 4-4: D6511T4A8 2-Layer Demo Board (Capacitve Power Supply): Electrical Schematic 1/3 Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 83 of 115 71M6511/71M6511H Demo Board User's Manual GND J3 IA_IN IA_IN ' JP17 L6 1 2 3 IA_IN * R110 R14 0 L7 GND VA_IN VA_IN R15 R16 R17 R18 2M 274K 270K 698 V3P3_JUMPER2 TP2 L2 VA R32 750 2 1 R25 3.4 * U1 1 2 3 V3P3_JUMPER NEUTRAL C14 1000pF GND AC1 C2 A2 6 5 4 C8 1000pF * C6 1000pF = 1206 PACKAGE C12 1000pF NOTE: When using current shunts, R24 and R106 should be 10K and R25 and R107 should be NC GND J9 A1 C1 AC2 1 2 IA V3P3 GND NEUTRAL 1 TP1 V3P3 BAV99DW C9 1000pF TP15 VOLTAGE CONNECTIONS * L3 VA V3P3_JUMPER2 TP R24 3.4 CURRENT SHUNT/CT CONNECTIONS IA 750 2 1 C13 1000pF V3P3 L4 J16 IB_IN IB_IN ' IB_IN 1 2 3 L5 * R111 R104 0 IB 750 GND * R106 3.4 CURRENT SHUNT/CT CONNECTIONS R107 3.4 * A1 C1 AC2 AC1 C2 A2 6 5 4 1 2 IA U6 1 2 3 TP19 V3P3 C29 1000pF BAV99DW V3P3 * C10 1000pF = 1206 PACKAGE C11 1000pF GND Figure 4-5: D6511T4A8 2-Layer Demo Board (Capacitve Power Supply): Electrical Schematic 2/3 Page: 84 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual U7 TP21 SEG00 1 2 SEG01 D5 R74 V3P3 SEG02 SEG26/DIO06 SEG03 DIO6 (WATTS) 10K TP22 0.1uF 1 10 V1 2 1 1000pF VREF V3P3 GND VREFOUT 2 1 TP10 GND TP7 R86 21.5K C30 R82 1K + C34 10uF V3P3 GND C35 0.1uF C23 1000pF GND C21 1000pF C21 CLOSE TO U5 C24 15pF C25 Y1 32.768kHz C22 0.1uF GND 0.1uF GND V3P3 VA VBIAS IB IA VREF V1 OPT_RX GND XIN TEST XOUT VLCD E_RST E_TCLK 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 R94 GND GND GND GND C26 0.22uF VLCD SEL 1--2 = 3.3V LCD 1 2--3 = 5V LCD 2 V3P3 U5 6511-64TQFP 3 JP10 C28 C27 0.033uF 2 D7 V3P3 CPUMP 1 3 BAT54S/SOT TMUXOUT 1 2 VIM-808-DP 0.1uF GND 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM1 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG31/DIO11 SEG30/DIO10 SEG29/DIO09 SEG28/DIO08 COM0 OPTICAL I/F SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG7/MUX_SYNC SEG6/SRDY SEG36/DIO16 SEG35/DIO15 SEG34/DIO14 SEG02 SEG01 SEG00 GND E_RXTX OPT_TX TMUXOUT UART_TX SEG03 VDRV CKTEST V3P3 SEG04 SEG05 VLCD TP13 TP 1 2 GNDA V3P3A VA VBIAS IB IA VREF V1 OPT_RX GNDA XIN TEST XOUT VLCD E_RST E_TCLK 10K 15pF SEG07 ,COM2, 8F,8E,NC 8A,8G,8D 7F,7E,NC 7A,7G,7D NC,NC,6L 6F,6E,NC 6A,6G,6D 5F,5E,NC 5A,5G,5D NC,NC,4L 4F,4E,NC 4A,4G,4D 3F,3E,NC 3A,3G,3D NC,NC,2L 2F,2E,NC 2A,2G,2D 1F,1E,NC 1A,1G,1D COM1,, V3P3 RESETZ V2P5 VBAT UART_RX SEG31/DIO11 SEG30/DIO10 SEG29/DIO09 SEG28/DIO08 SEG27/DIO07 SEG26/DIO06 SEG25/DIO05 SEG24/DIO04 SEG19 SEG18 SEG17 SEG16 GND R83 10K COM2 OPT_TX GND R79 J12 GND U4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG07 SEG06 GND 1 2 3 4 NC A1 NC GND VCC WP SCL SDA 8 7 6 5 GND C20 OPT IF OPT_RX 0.1uF V3P3 R84 47K SEG24/DIO04 SEG25/DIO05 V3P3 RXTX TCLK RST_EMUL GND GND SER EEPROM SERIAL EEPROM 1 2 3 4 5 OPT_TX_OUT 100 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 J13 SEG06 GND C18 uclamp3301D SEG27/DIO07 LCD 8B,8C,7DP NC 7B,7C,6DP NC NC 6B,6C,5DP NC NC 5B,5C,4DP NC NC 4B,4C,3DP NC NC 3B,3C,2DP NC NC 2B,2C,1DP NC 1B,1C,NC ,,COM3 JP8 RESETZ V2P5 VBAT RX SEG31/DIO11 SEG30/DIO10 SEG29/DIO9 SEG28/DIO8 SEG27/DIO7 SEG26/DIO6 SEG25/DIO5 SEG24/DIO4 SEG19 SEG18 SEG17 SEG16 V1IN V3P3 10K R108 3K R109 3K J17 1 2 3 4 5 HEADER 5 V3P3 Only populate J14 or J17, not both J14 V3P3 R119 10K SEG02 SEG01 SEG00 R88 10K R89 3K E_RXTX R97 62 E_TCLK R98 62 E_RST R99 62 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2 1 R76 DIO7 (VARS) PULSE OUTPUT 1 2 3 C19 0.1uF D9 C31 0.1uF VBAT V3P3 VBAT 2 CMP GND R100 0 D6 V3P3 COM0 COM1 COM2 RESET SEG05 C17 0.1uF 200 R77 SW2 GND R75 V3P3 V2P5 GNDD E_RXTX OPT_TX TMUXOUT TX SEG3/SCLK VDRV CKTEST V3P3D SEG4/SDATA SEG5/SFR SEG37/DIO17 COM0 COM1 COM2 COM3 C33 SEG04 NOTE: Place C18, R75 and R100 close to U5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NOTE: Place C36 as close as C36 possible to the E_RST pin on U5 RXTX TCLK RST_EMUL 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 GND HEADER 10X2 EMULATOR I/F 1000pF GND TMUXOUT CKTEST TP17 Figure 4-6: D6511T4A8 2-Layer Demo Board (Capacitve Power Supply): Electrical Schematic 3/3 Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 85 of 115 71M6511/71M6511H Demo Board User's Manual 71M6511 2-LAYER DEMO BOARD WITH TRANSFORMER - ELECTRICAL SCHEMATICS 3 2 1 JP4 GND 5 * 3 7 TRNSFMR 67115100 1 2 3 RAPC712 + C1 2200UF, 16V 1N4736A LIVE VA_IN 10, 2W R118 130, 1% JP1 PS_SEL[0] C7 NC TL431 8 R4 VA_IN 1 2 1 + C2 10uF, 16V * R7 L8 J4 U3 + C4 33UF, 10V C5 0.1UF 1 1 8.06K, 1% D3 2 - R8 1 4 R2 V3P3 V3P3_Debug RV1 VARISTOR 5Vdc EXT SUPPLY J1 L1 D8 C3 1000pF 6 9 2 1 T3 1 1 BR1 HD04 + C32 .03uF,250VDC NC, 1000VDC CMP C15 1000pF NEUTRAL C36 NOTE: SHORT 1 to 2 for CT SHORT 2 to 3 for SHUNT 3301D 2 4.3 25.5K, 1% GND * = 1206 PACKAGE * R9 68, 1% J2 GND GND GND GND 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 R10 V3P3_Debug CKTEST_T TMUXOUT_T UART_TX_T UART_RX CKTEST 62 R11 TMUXOUT HEADER 8X2 62 R12 DEBUG CONNECTOR UART_TX R13 10k 62 GND Figure 4-7: 71M6511 2-Layer Demo Board (Xformer Power Supply): Electrical Schematic 1/3 Page: 86 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual JP17 J3 NOTE: JP17 ON for CT. OFF for SHUNT 2 1 IA_IN IA_IN ' Ferrite Bead 600ohm L10 L6 1 2 3 IA_IN R110 * 0 R14 VA_IN VA_IN R16 R17 R18 2M, 1% 274K, 1% 274K, 1% 698, 1% L2 REFA VA TP2 2 1 L3 VA R32 750, 1% REFA * A1 C1 AC2 AC1 C2 A2 6 5 4 C8 1000pF BAV99DW * = 1206 PACKAGE V3P3 C6 1000pF C12 1000pF NOTE: When using a current shunt, R24 and R106 should be 10K and R25 and R107 should be NC GND NEUTRAL NEUTRAL 1 NEUTRAL C14 1000pF VOLTAGE CONNECTIONS * 1 2 3 V3P3 GND GND J9 R25 3.4, 1% C9 1000pF TP15 TP GND L4 J16 IB_IN IB_IN ' 1 2 3 IB_IN * R111 0 R104 IB TP19 V3P3 750, 1% L5 R106 R107 3.4, 1% 3.4, 1% * CURRENT SHUNT/CT CONNECTIONS * 1 2 3 A1 C1 AC2 AC1 C2 A2 6 5 4 C29 1000pF BAV99DW V3P3 C11 1000pF C10 1000pF * = 1206 PACKAGE GND Figure 4-8: 71M6511 2-Layer Demo Board (Transformer Power Supply): Electrical Schematic 2/3 (c) 2005-2007 TERIDIAN Semiconductor Corporation 1 2 IA U6 GND Revision 5.4 1 2 IA U1 R24 3.4, 1% CURRENT SHUNT/CT CONNECTIONS C13 1000pF TP1 V3P3 750, 1% L7 GND R15 IA Page: 87 of 115 U7 TP21 SEG00 SEG01 1 2 SRDY SEG07 MUX_SYNC SEG06 SEG05 SFR SCLK SEG03 SEG04 SDATA 71M6511/71M6511H Demo Board User's Manual NOTE: DO NOT POPULATE TP20 D5 V3P3 R112 R113 R114 R115 R116 NC NC NC NC NC DIO4 R74 SEG02 SEG26/DIO06 SEG03 10K TP22 SEG04 0 1 10 V1IN V3P3 J13 GND R83 10K, 1% V1 L9 NOTE: Place L9, C18, and C34 as close as R86 21.5K possible to U5 C18 1000pF GND GND V3P3 VA VBIAS IB IA VREF 1000pF C35 GND V3P3 Y1 32.768KHZ R94 GND 10PF GNDA V3P3A VA VBIAS IB IA VREF V1 OPT_RX GNDA XIN TEST XOUT VLCD E_RST E_TCLK 10K NOTE: Place C24, C25, and Y1 as close as possible to U5 GND GND GND TP14 TP GND C26 .22uF VLCD SEL 1--2 = 3.3V LCD 1 2--3 = 5V LCD 2 V3P3 1 2 SEG07 VIM-808-DP ,COM2, 8F,8E,NC 8A,8G,8D 7F,7E,NC 7A,7G,7D NC,NC,6L 6F,6E,NC 6A,6G,6D 5F,5E,NC 5A,5G,5D NC,NC,4L 4F,4E,NC 4A,4G,4D 3F,3E,NC 3A,3G,3D NC,NC,2L 2F,2E,NC 2A,2G,2D 1F,1E,NC 1A,1G,1D COM1,, 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM1 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG31/DIO11 SEG30/DIO10 SEG29/DIO09 SEG28/DIO08 COM0 JP8 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 U5 SEG7/MUX_SYNC SEG6/SRDY 6513-100TQFP SEG36/DIO16 SEG35/DIO15 SEG34/DIO14 SEG02 SEG01 SEG00 GND E_RXTX OPT_TX TMUXOUT UART_TX SEG03 VDRV CKTEST V3P3 SEG04 SEG05 VLCD TP13 TP COM2 V3P3 OPT_TX R79 J12 1 2 3 4 5 OPT_TX_OUT GND 100 GND U4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG09 SEG08 SEG07 SEG06 GND 1 2 3 4 NC A1 NC GND 8 7 6 5 OPT IF OPT_RX 0.1UF V3P3 R84 47K SEG24/DIO04 SEG25/DIO05 V3P3 RXTX TCLK RST_EMUL GND AT24C1024W SERIAL EEPROM R108 3K R109 3K V3P3 R119 3K SEG02 SEG01 SEG00 VCC WP SCL SDA GND C20 GND OPTICAL I/F V3P3 R89 3K R97 62 E_TCLK R98 62 E_RST R99 62 RXTX TCLK RST_EMUL 20 18 16 14 12 10 8 6 4 2 J17 1 2 3 4 5 EMULATOR I/F Only populate J14 or J17, not both J14 V3P3 R88 3K E_RXTX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C25 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 OPT_RX GND XIN TEST XOUT VLCD E_RST E_TCLK 0.1uF C24 0.1UF 0.1uF GND C23 SEG06 GND C30 R82 1K + C34 10uF 10PF C19 0.1UF C22 10uF GND VREFOUT 2 1 TP7 Ferrite Bead 600ohm SEG27/DIO07 PULSE OUTPUT 1 2 3 GND 3301D VREF TP10 C21 1000pF GND C37 V3P3 2 1 NOTE: Place R1, R3, and C21 as close as possible to U5 10K 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 2 1 D9 C31 0.1uF VBAT V3P3 VBAT 2 CMP R76 DIO5 LCD 8B,8C,7DP NC 7B,7C,6DP NC NC 6B,6C,5DP NC NC 5B,5C,4DP NC NC 4B,4C,3DP NC NC 3B,3C,2DP NC NC 2B,2C,1DP NC 1B,1C,NC ,,COM3 19 17 15 13 11 9 7 5 3 1 GND HEADER 10X2 EMULATOR I/F COM0 COM1 COM2 RESET D6 V3P3 GND R3 R77 SW2 GND C17 0.1UF R1 200 0.1uF RESETZ V2P5 VBAT UART_RX SEG31/DIO11 SEG30/DIO10 SEG29/DIO09 SEG28/DIO08 SEG27/DIO07 SEG26/DIO06 SEG25/DIO05 SEG24/DIO04 SEG19 SEG18 SEG17 SEG16 C33 RESETZ V2P5 VBAT RX SEG31/DIO11 SEG30/DIO10 SEG29/DIO9 SEG28/DIO8 SEG27/DIO7 SEG26/DIO6 SEG25/DIO5 SEG24/DIO4 SEG19 SEG18 SEG17 SEG16 TP20 SSI SEG05 GNDD E_RXTX OPT_TX TMUXOUT TX SEG3/SCLK VDRV CKTEST V3P3D SEG4/SDATA SEG5/SFR SEG37/DIO17 COM0 COM1 COM2 COM3 GND V2P5 + 2 4 6 8 10 1 3 5 7 9 V3P3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 3 805 package JP10 C28 C27 .033uF 2 D7 V3P3 CPUMP 1 3 BAT54S/SOT TMUXOUT 1 2 0.1UF GND TMUXOUT CKTEST TP17 Figure 4-9: 71M6511 2-Layer Demo Board (Xformer Power Supply): Electrical Schematic 3/3 Page: 88 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4.4 71M6511 4-LAYER DEMO BOARD BILL OF MATERIAL Item Quantity 1 15 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 1 1 8 1 4 1 4 2 1 1 1 1 1 2 1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 5 6 1 1 2 1 1 1 1 4 1 1 1 1 3 1 6 2 3 11 4 1 1 5 1 1 1 1 1 1 1 4 1 4 1 2 1 1 1 Reference Part Footprint Digi-Key P/N P/N Manufacturer TP1-TP2,JP1-JP3,BT1,J3, TP7,JP16,J16,TP17-TP19, JP17,TP11/TP12 C1 C2 C4 C5,C15,C17,C19,C20-C22,C28 C6 C8,C9,C23,C29 C18 SW1,C16,R91,R103 C25,C24 C26 C27 D1 D3 D4 D5,D6 D7 VIA1-VIA3,G1-G9,JP4,JP11, VIA10-VIA13,J15 JP8,JP9,TP10,JP10,J13 JP2,JP3,JP12-JP15 J1 J2 J4,J9 J10 J11 J12 J14 RV1,R100,R101,R102 R2 R4 R6 R7 R8,R110,R111 R9 R10-R12,R97-R99 R22,R105 R14,R32,R104 R15-R21,R27-R29 R24,R25,R106,R107 R30 R31 R74,R75,R76,R78,R94 R77 R79 R82 R83 R84 R85 R86 R89,R88,R108,R109 SW2 TP13-TP16 TP20 U1,U6 U4 U5 Y1 HDR2X1 HDR2X1 S1011-36-ND PZC36SAAN Sullins 2200uF, 16V 10uF, 10V 33uF, 10V 0.1uF 0.47uF, 1000Vdc 1000pF 0.1uF NC 10pF 0.220uF 0.033uF TL431 1N4736A 1N4148 LED RED BAT54S/SOT NC Radial RC1812 RC1812 RC0805 RECT. RC0805 RC1206 N/A RC0805 RC0805 RC0805 SO8 DO41 DO35 RADIAL SOT23 N/A P5143-ND 478-1672-1-ND 478-1687-1-ND 445-1349-1-ND BC1918-ND PCC221CGCT-ND PCC104BCT-ND N/A PCC100CNCT-ND 445-1352-1-ND PCC1834CT-ND 296-1288-1-ND 1N4736ADICT-ND 1N4148DICT-ND 67-1612-ND BAT54SDICT-ND N/A ECA-1CM222 TAJB106K010R TAJB336K010R C2012X7R1H104K 222 383 30474 ECJ-2VC1H221J ECJ-3VB1H104K N/A ECJ-2VC1H100D C2012X7R1E224K ECJ-2VB1H333K TL431AIDR 1N4736A-T 1N4148-T SSL-LX5093SRC/E BAT54S-7 N/A Panasonic AVX AVX TDK BC Components Panasonic Panasonic N/A Panasonic TDK Panasonic TI DIODES DIODES LUMEX DIODES N/A HDR3X1 NC RAPC712 HEADER 8X2 SPADE HDR12X2 HDR12X2 HDR4X1 0.05" HEADER 10X2 NC 8.06K 25.5K 100, 2W 130 0 68 62 0 750 220K 3.4 120K 4.7K 10K 10 100 1k 10K 47K 470 21.5K 3K PB-SW TP HEADER 5X2 BAV99DW SER EEPROM 6511-64TQFP 32.768Khz HDR3X1 HDR2X1 DC CONN 8X2PIN SPADE HDR12X2 HDR12X2 HDR4X1 HDR0.05 S1011-36-ND N/A SC1152-ND S2011-36-ND A24747CT-ND WM6824-ND S4312-ND S1011-36-ND A3210-ND N/A 311-8.06KCCT-ND 311-25.5KCCT-ND 100W-2-ND 311-130FCT-ND P0.0ECT-ND 311-68.0FCT-ND P62ACT-ND P0.0ACT-ND RR12P750DCT-ND RR08P220KBCT-ND 311-3.4FCT-ND RR12P120KBCT-ND RR12P4.7KBCT-ND P10KACT-ND P10ACT-ND P100ACT-ND P1.0KACT-ND P10.0KCCT-ND P47KACT-ND P470ACT-ND P21.5KCCT-ND P3.0KACT-ND P8051SCT-ND N/A S2011-36-ND BAV99DWDICT-ND AT24C1024W10SI2.7-ND N/A XC488CT-ND PZC36SAAN PZC36SAAN RAPC712 PZC36DAAN 62395-1 10-89-1241 PPPC122LFBN PZC36SAAN 104068-1 N/A 9C08052A8061FKHFT 9C08052A2552FKHFT RSF200JB-100R 9C12063A1300FGHFT ERJ-8GEY0R00V 9C12063A68R0FKHFT ERJ-6GEYJ620V ERJ-6GEY0R00V RR1220P-751-D RR0816P-224-B-T5 9C12063A3R40FGHFT RR1220P-124-B-T5 RR1220P-472-B-T5 ERJ-GEYJ103V ERJ-GEYJ100V ERJ-GEYJ101V ERJ-GEYJ102V ERJ-6ENF1872V ERJ-6GEYJ473V ERJ-6GEYJ471V ERJ-6ENF2152V ERJ-6GEYJ302V EVQ-PJX05M N/A Sullins Sullins Switchcraft Sullins AMP Molex/Waldom Sullins Sullins AMP N/A Yageo Yageo Yageo Yageo Panasonic Yageo Panasonic Panasonic SUSUMU SUSUMU Yageo SUSUMU SUSUMU Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic TDK Sullins DIODES ATMEL YAMAICHI ECS RC0805 RC0805 AXIAL RC1206 RC1206 RC1206 RC0805 RC0805 RC0805 RC0805 RC1206 RC0805 RC0805 RC0805 RC0805 RC0805 RC0805 RC0805 RC0805 RC0805 RC0805 RC0805 SMT SW Paper Clip HDR5X2 SOT263 SO8 64TQFP SMT XTAL BAV99DW-7 AT24C1024W-10SI-2.7 64TQFP SOCKET ECS-.327-12.5-17-TR Table 4-1: 71M6511 4-Layer Demo Board: Bill of Material Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 89 of 115 71M6511/71M6511H Demo Board User's Manual 4.5 BOM FOR 71M6511 2-LAYER DEMO BOARD (CAPACITIVE POWER SUPPLY) Digi-Key/Mouser Part Number P5143-ND 478-1672-1-ND 445-1298-1-ND Part Number Manufacturer 2200uF 10uF, 10V 1000pF PCB Footprint Radial RC1812 RC0603 ECA-1CM222 TAJB106K010R C1608X7R2A102K Panasonic AVX TDK 33uF, 16V 0.1uF RC1812 RC0603 478-1688-1-ND 445-1314-1-ND TAJB336K016R C1608X7R1H104K AVX TDK 0.47uF, 1000VDC 10pF 0.22uF 0.033uF 0.03uF, 250V 1N4736A 1N4148 LED BAT54S/SOT Tranzorb DC Connector HEADER 8X2 HEADER 3 Faston HEADER 5 HEADER 2 10X2 CONNECTOR HEADER 2 HEADER 3 Ferrite bead, 600 Ohm VARISTOR 8.06K, 1% 25.5K, 1% 100, 2W 130, 1% 1 68.1, 1% 62 10K Block RC0603 RC0805 RC0603 Axial DO41 DO35 RADIAL SOT23 SOD-323 RAPC712 8X2PIN 3X1PIN BC1918-ND 445-1269-1-ND 445-1350-1-ND PCC2284CT-ND 75-125LS30-R 1N4736ADICT-ND 1N4148DICT-ND 67-1612-ND BAT54S-FDICT-ND X SC1152-ND S2011E-36-ND S2011E-36-ND A24747CT-ND S2011E-36-ND S2011E-36-ND A3210-ND S2011E-36-ND S2011E-36-ND 445-1556-1-ND 581-VZD510XX P8.06KHCT-ND P25.5KHCT-ND 100W-2-ND P130FCT-ND P1.0ECT-ND P68.1FCT-ND P62GCT-ND P10KGCT-ND 222 383 30474 C1608COG1H100D C2012X7R1H224K ECJ-1VB1H333K 125LS30-R 1N4736A-T 1N4148-T SSL-LX5093SRC/E BAT54S-7-F UCLAMP3301D.TCT RAPC712 PBC36DAAN PBC36SAAN 62395-1 PBC36SAAN PBC36SAAN 104068-1 PBC36SAAN PBC36SAAN MMZ2012S601A VE24M00511K ERJ-3EKF8061V ERJ-3EKF2552V RSF200JB-100R ERJ-8ENF1300V ERJ-8GEYJ1R0V ERJ-8ENF68R1V ERJ-3GEYJ620V ERJ-3GEYJ103V BC Components TDK TDK Panasonic Vishay DIODES DIODES LUMEX DIODES SEMTECH Switchcraft Sullins Sullins AMP Sullins Sullins AMP Sullins Sullins TDK AVX Panasonic Panasonic Yageo Panasonic Panasonic Panasonic Panasonic Panasonic 750, 1% 2M, 1% 274K, 1% 270K, 1% 698, 1% 3.4, 1% 750, 1% 200 10 100 1K 10.0K, 1% 47K 21.5K, 1% 3K 0 0 10, 3W Pushbutton Switch TP RC0805 Axial RC0805 RC0805 RC0805 RC1206 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC0603 RC1206 axial P750CCT-ND 71-RN65DF-2.0M P274KCCT-ND RHM270KCCT-ND P698CCT-ND 311-3.40FCT-ND P750HCT-ND P200GCT-ND P10GCT-ND P100GCT-ND P1.0KGCT-ND P10.0KHCT-ND P47KGCT-ND P21.5KHCT-ND P3.0KGCT-ND P0.0GCT-ND P0.0ECT-ND 71-CW2B-10 P8051SCT-ND S2011E-36-ND ERJ-6ENF7500V RN65D2004FB14 ERJ-6ENF2743V MCR10EZHF2703 ERJ-6ENF6980V 9C12063A3R40FGHFT ERJ-3EKF7500V ERJ-3GEYJ201V ERJ-3GEYJ100V ERJ-3GEYJ101V ERJ-3GEYJ102V ERJ-3EKF1002V ERJ-3GEYJ473V ERJ-3EKF2152V ERJ-3GEYJ302V ERJ-3GEY0R00V ERJ-8GEY0R00V CW02B10R00JB12 EVQ-PJX05M PBC36SAAN Panasonic Dale Panasonic Rohm Panasonic Yageo Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Vishay Panasonic Sullins TP BAV99DW REGULATOR, 1% Serial EEPROM 71M6511 64TQFP Socket LCD 32.768kHz 1X1PIN SOT363 SO8 Item Q Reference Part 1 2 3 1 2 14 4 5 1 10 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1 2 1 1 1 1 1 2 1 2 1 1 2 2 2 1 1 2 3 8 1 1 1 1 1 1 1 6 6 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 2 1 1 1 1 4 1 1 1 1 1 1 1 1 3 1 2 1 1 8 55 56 57 58 59 1 2 1 1 1 1 1 1 C1 C2,C34 C3,C6,C7,C8,C9,C10,C11, C12,C13,C14,C18,C23, C29,C36 C4 C5,C17,C19,C20,C22,C28, C30,C31,C33,C35 C16 C24,C25 C26 C27 C32 D3 D4 D5,D6 D7 D8,D9 J1 J2 J3,J16 J4,J9 J12,J17 J13 J14 JP1,JP17 JP8,JP10,JP16 L1,L2,L3,L4,L5,L6,L7,L8 RV1 R2 R4 R6 R7 R8 R9 R10,R11,R12,R97,R98,R99 R13,R74,R76,R88,R94, R119 R14,R104 R15 R16 R17 R18 R24,R25,R106,R107 R32 R75 R77 R79 R82 R83 R84 R86 R89,R108,R109 R100 R110,R111 R118 SW2 TP1,TP2,TP7,TP10,TP17, TP19,TP21,TP22 TP15 U1,U6 U2 U4 U5 at U5 U7 Y1 60 61 5X1PIN 2X1PIN 2X1PIN 3X1PIN RC1206 radial RC0603 RC0603 Axial RC1206 RC1206 RC1206 RC0603 RC0603 2X1PIN 64TQFP 64TQFP S2011E-36-ND PBC36SAAN Sullins BAV99DW-7-F BAV99DW-FDICT-ND DIODES 296-1288-1-ND TL431AIDR Texas Instruments AT24C1024W-10SI-2.7-ND AT24C1024W-10SI-2.7 ATMEL X 71M6511-IGT Teridian X IC149-064-169-S5 Yamaichi 153-1056-ND VIM-808-DP-RC-S-HV VARITRONIX XC488CT-ND ECS-.327-12.5-17-TR ECS Table 4-2: D6511T4A8 2-Layer Demo Board: Bill of Material Page: 90 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4.6 BOM FOR 71M6511 2-LAYER DEMO BOARD (TRANSFORMER POWER SUPPLY) PCB Footprint Digi-Key/Mouser Part Number Item Q Reference Part 1 1 BR1 Bridge Rectifier 2 1 C1 2200uF BULK/Radial P5143-ND ECA-1CM222 3 1 C2 10uF RC1812 478-1672-1-ND TAJB106K010R AVX 4 14 C3,C6,C8-C15,C18,C21,C23 1000pF RC0603 445-1298-1-ND C1608X7R2A102K TDK 5 1 C4 33uF RC1812 478-1688-1-ND TAJB336K016R AVX 6 10 C5,C17,C19,C20,C22,C28, 0.1uF RC0603 445-1314-1-ND C1608X7R1H104K TDK 7 1 C7 NC Axial -- -- -- 8 2 C24,C25 10pF RC0603 445-1269-1-ND C1608COG1H100D TDK Part Number Manufacturer HD04 Panasonic C29 C30,C31,C33,C35 9 1 C26 0.22uF RC0805 445-1350-1-ND C2012X7R1H224K TDK 10 1 C27 0.033uF RC0603 PCC1769CT-ND ECJ-1VB1E333K Panasonic 11 1 C32 0.03uF Axial 75-125LS30 125LS30 Vishay 12 1 C36 NC Axial 13 1 D3 1N4736A DO41 1N4736ADICT-ND 1N4736A-T DIODES 14 2 D5,D6 LED RADIAL 67-1612-ND SSL-LX5093SRC/E LUMEX 15 1 D7 BAT54S/SOT SOT23 BAT54SDICT-ND BAT54S-7 DIODES 16 2 D8,D9 UCLAMP3301D SOD-323 -- UCLAMP3301D.TCT SEMTECH 17 1 J1 DC Connector RAPC712 SC1152-ND RAPC712 Switchcraft 18 1 J2 HEADER 8X2 8X2PIN S2011-36-ND PZC36DAAN Sullins 19 2 J3,J16 HEADER 3 3X1PIN S1011-36-ND PZC36SAAN Sullins 20 1 J13 HEADER 2 2X1PIN S1011-36-ND PZC36SAAN Sullins Table 4-3: 71M6511 2-Layer Demo Board (Transformer Power Supply): Bill of Material (1/2) Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 91 of 115 71M6511/71M6511H Demo Board User's Manual 21 2 J4,J9 Spade Terminal 22 2 J12,J17 HEADER 5 A24747CT-ND 62395-1 AMP 5X1PIN S1011-36-ND PZC36SAAN Sullins 23 1 J14 10X2 CONNECTOR 24 2 JP1,JP17 HEADER 2 A3210-ND 104068-1 AMP 2X1PIN S1011-36-ND PZC36SAAN Sullins 25 4 JP4,JP8,JP10,JP16 HEADER 3 3X1PIN 26 10 L1-L10 Ferrite bead, 600 Ohm RC1206 S1011-36-ND PZC36SAAN Sullins 445-1556-1-ND MMZ2012S601A 27 1 RV1 VARISTOR radial 581-VZD510XX VE24M00511K TDK AVX 28 1 R1 200 RC0603 P200GCT-ND ERJ-3GEYJ201V Panasonic 29 1 R2 8.06K, 1% RC0603 P8.06KHCT-ND ERJ-3EKF8061V Panasonic 30 1 R3 0 RC0603 P0.0GCT-ND ERJ-3GEY0R00V Panasonic 31 1 R4 25.5K, 1% RC0603 P25.5KHCT-ND ERJ-3EKF2552V Panasonic 32 1 R7 130, 1% RC1206 311-130FCT-ND 9C12063A1300FGHFT Yageo 33 1 R8 1 RC1206 311-1.00FCT-ND 9C12063A1R00FGHFT Yageo 34 1 R9 68, 1% RC1206 311-68.0FCT-ND 9C12063A68R0FKHFT Yageo 35 6 R10-R12,R97-R99 62 RC0603 P62GCT-ND ERJ-3GEYJ620V Panasonic 36 3 R14,R32,R104 750, 1% RC0603 P750HCT-ND ERJ-3EKF7500V Panasonic 37 1 R15 2M, 1% Axial 71-RN65DF-2.0M RN65D2004FB14 Dale 38 2 R16,R17 274K, 1% RC0805 P274KCCT-ND ERJ-6ENF2743V Panasonic 39 1 R18 698, 1% RC0805 P698CCT-ND ERJ-6ENF6980V Panasonic 40 4 R24,R25,R106,R107 3.4, 1% RC1206 311-3.40FCT-ND 9C12063A3R40FGHFT Yageo 41 4 R13,R74,R76,R94 10K RC0603 P10KGCT-ND ERJ-3GEYJ103V Panasonic 42 1 R77 10 RC0603 P10GCT-ND ERJ-3GEYJ100V Panasonic 43 1 R79 100 RC0603 P100GCT-ND ERJ-3GEYJ101V Panasonic 44 1 R82 1K RC0603 P1.0KGCT-ND ERJ-3GEYJ102V Panasonic 45 1 R83 10.0K, 1% RC0603 P10.0KHCT-ND ERJ-3EKF1002V Panasonic 46 1 R84 47K RC0603 P47KGCT-ND ERJ-3GEYJ473V Panasonic 47 1 R86 21.5K RC0603 P21.5KHCT-ND ERJ-3EKF2152V Panasonic 48 5 R112-R116 NC RC0603 49 5 R88,R89,R108,R109,R119 3K RC0603 P3.0KGCT-ND ERJ-3GEYJ302V Panasonic 50 2 R110,R111 0 RC1206 P0.0ECT-ND ERJ-8GEY0R00V Panasonic 51 1 R118 10, 2W Axial 10W-2-ND RSF200JB-10R Yageo 52 1 SW2 SWITCH P8051SCT-ND EVQ-PJX05M Panasonic 53 1 T3 TRNSFMR 67115100 54 8 TP1,TP2,TP7,TP10,TP17, Test Point 2X1PIN S1011-36-ND PZC36SAAN Sullins 55 TP19,TP21,TP22 56 1 TP10 Test Point 3X1PIN S1011-36-ND PZC36SAAN Sullins 57 3 TP13-TP15 Test Point Test Point 5011K-ND 5011 Keystone 58 1 TP20 HEADER 5X2 5X2PIN S2011-36-ND PZC36DAAN Sullins 59 2 U1,U6 BAV99DW SOT363 BAV99DWDICT-ND BAV99DW-7 DIODES 296-1288-1-ND AT24C1024W10SI2.7ND TL431AIDR Texas Instruments 60 1 U3 REGULATOR, 1% SO8 1 U4 EEPROM SOIC8 1 U5 71M6511 64TQFP 63 1 at U5 64TQFP Socket 64TQFP 64 1 Y1 32.768kHz 65 1 U7 LCD 153-1056-ND 61 62 AT24C1024W-10SI-2.7 ATMEL 71M6511-IGT TERIDIAN -- IC149-064-169-S5 Yamaichi XC488CT-ND ECS-.327-12.5-17-TR ECS VIM-808-DP-RC-S-HV VARITRONIX -- Table 4-4: 71M6511 2-Layer Demo Board (Transformer Power Supply): Bill of Material (2/2) Page: 92 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4.7 71M6511 4-LAYER DEMO BOARD PCB LAYOUT Figure 4-10: 71M6511 4-Layer Demo Board: Top View Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 93 of 115 71M6511/71M6511H Demo Board User's Manual Figure 4-11: 71M6511 4-Layer Demo Board: Bottom View Page: 94 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-12: 71M6511 4-Layer Demo Board: Top Signal Layer Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 95 of 115 71M6511/71M6511H Demo Board User's Manual Figure 4-13: 71M6511 4-Layer Demo Board: Middle Layer 1, Ground Plane. Page: 96 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-14: 71M6511 4-Layer Demo Board: Middle Layer 2, Supply Plane Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 97 of 115 71M6511/71M6511H Demo Board User's Manual Figure 4-15: 71M6511 4-Layer Demo Board: Bottom Signal Layer Page: 98 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4.8 PCB LAYOUT FOR THE 71M6511 2-LAYER DEMO BOARD (CAPACITIVE POWER SUPPLY) Figure 4-16: DM6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Top View Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 99 of 115 71M6511/71M6511H Demo Board User's Manual Figure 4-17: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Top Copper Layer Page: 100 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-18: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Top Silk-Screen View Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 101 of 115 71M6511/71M6511H Demo Board User's Manual Figure 4-19: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Bottom Copper Layer Page: 102 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-20: D6511T4A8 2-Layer Demo Board (Capacitive Power Supply): Bottom Silk Screen Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 103 of 115 71M6511/71M6511H Demo Board User's Manual 4.9 PCB LAYOUT FOR THE 71M6511 2-LAYER DEMO BOARD (TRANSFORMER POWER SUPPLY) Figure 4-21: 71M6511 2-Layer Demo Board (Xformer Power Supply): Top View Page: 104 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-22: 71M6511 2-Layer Demo Board (Xformer Power Supply): Bottom View Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 105 of 115 71M6511/71M6511H Demo Board User's Manual Figure 4-23: 71M6511 2-Layer Demo Board (Xformer Power Supply): Top Copper View Page: 106 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-24: 71M6511 2-Layer Demo Board (Xformer Power Supply): Bottom Copper View Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 107 of 115 71M6511/71M6511H Demo Board User's Manual 4.10 DEBUG BOARD BILL OF MATERIAL Item Quantity Reference Part PCB Footprint Digi-Key Part Number Part Number Manufacturer 1 21 C1-C3,C5-C10,C12-C23 0.1uF RC0805 445-1349-1-ND C2012X7R1H104K TDK 2 1 C4 33uF, 10V RC1812 478-1687-1-ND TAJB336K010R AVX 3 1 C11 10uF, 16V RC1812 478-1673-1-ND TAJB106K016R AVX 4 2 D2,D3 LED RC0805 160-1414-1-ND LTST-C170KGKT LITEON 5 4 G1,G2,G3,G4 Spacer MTHOLE 2202K-ND 2202K-ND Keystone Electronics 6 4 4-40, 1/4" screw H342-ND PMS 4400 - 0025 PH Building Fasteners 7 2 4-40, 5/16" screw H343-ND PMS 4400- 0031 PH Building Fasteners 8 2 H216-ND HNZ440 Building Fasteners 9 1 J1 DC Connector 4-40 nut RAPC712 SC1152-ND RAPC712 Switchcraft 10 1 J2 DB9, right angle DSUB9_SKT A2100-ND 745781-4 AMP 11 1 J3 HEADER (F) 8X2 8X2PIN 929852-01-36-ND 929852-01-36-10 3M 12 4 JP1,JP2,JP3,JP4 HEADER 2 2X1PIN S1011-36-ND PZC36SAAN Sullins 13 4 R1,R5,R7,R8 10K RC0805 P10KACT-ND ERJ-6GEYJ103V Panasonic 14 2 R2,R3 1K RC0805 P1.0KACT-ND ERJ-6GEYJ102V Panasonic 15 1 R4 NC RC0805 N/A N/A N/A 16 1 R6 0 RC0805 P0.0ACT-ND ERJ-6GEY0R00V Panasonic Panasonic 17 1 SW2 PB switch P8051SCT-ND EVQ-PJX05M 18 5 U1,U2,U3,U5,U6 ISOLATOR SOIC8 ADUM1100AR-ND ADUM1100AR ADI 19 2 TP5,TP6 Test Point -- 5011K-ND 5011 Keystone Electronics 20 1 U4 RS232 DRIVER 28SSOP MAX3237CAI-ND MAX3237CAI MAXIM Table 4-5: Debug Board: Bill of Material Page: 108 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4.11 DEBUG BOARD SCHEMATICS V5_DBG V5_DBG 10K V5_DBG + C4 33uF, 10V RAPC712 TP5 TP C7 0.1uF DISPLAY SEL TP6 TP 1 2 3 4 GND_DBG V5_DBG SW2 VDD1 DIN VDD1 GND1 VDD2 GND2 DOUT GND2 V3P3 GND DIO02 GND 8 7 6 5 V5_DBG C5 0.1uF GND_DBG V5_DBG R2 1K DB9_RS232 8 GND_DBG 7 DIO01_DBG 6 GND_DBG 5 D2 LED VDD2 GND2 DOUT GND2 VDD1 DIN VDD1 GND1 V3P3 DIO01 V3P3 GND 1 2 3 4 V5_DBG GND_DBG JP1 HDR2X1 C11 10uF, 16V (B Case) 0.1uF C9 0.1uF RXPC GND_DBG C13 NORMAL GND_DBG JP2 HDR2X1 R3 0.1uF GND_DBG C14 0.1uF 232VP1 27 C17 0.1uF 232VN1 V+ U4 MAX3237CAI C1+ VCC NORMAL 26 1 2 C11 2 JP3 HDR2X1 4 V- C2+ C2- NULL RX232 V5_DBG R4 NC R5 10K 8 9 11 13 14 T1OUT T2OUT T3OUT T4OUT T5OUT R1IN R2IN R3IN ENB SHDNB T1IN T2IN T3IN T4IN T5IN R1OUTBF R1OUT R2OUT R3OUT 15 1 2 JP4 HDR2X1 5 6 7 10 12 25 232C1M1 1 232C2P1 3 232C2M1 24 23 22 19 17 16 21 20 18 GND TX232 28 232C1P1 GND_DBG TXISO GND U5 GND_DBG GND_DBG 8 7 6 5 VDD2 GND2 DOUT GND2 VDD1 DIN VDD1 GND1 1 2 3 4 V3P3 UART_TX V3P3 GND GND ADUM1100 VDD1 DIN VDD1 GND1 V3P3 DIO00 V3P3 GND 1 2 3 4 GND C22 0.1uF U6 V5_DBG GND_DBG GND_DBG 1 2 3 4 VDD1 DIN VDD1 GND1 VDD2 GND2 DOUT GND2 8 7 6 5 V3P3 GND UART_RX GND ADUM1100 0.1uF C12 GND ADUM1100 0.1uF C16 STATUS LEDs 0.1uF DIO00 DIO02 GND GND GND GND GND_DBG V5_DBG C20 0.1uF V5_DBG RXISO C23 0.1uF R8 10K VDD2 GND2 DOUT GND2 V5_DBG C19 0.1uF GND_DBG R7 10K LED 8 GND_DBG 7 DIO00_DBG 6 GND_DBG 5 DIO00 C15 0.1uF C18 0.1uF D3 1K RS232 TRANSCEIVER 2 NULL MBAUD TXPC C10 GND U3 1 2 + V5_DBG V5_DBG 0.1uF C8 GND ADUM1100 DIO01 J2 C6 GND U2 GND_DBG 5 9 4 8 3 7 2 6 1 0.1uF ADUM1100 C3 0.1uF GND_DBG GND_DBG GND 1 2 3 GND 5Vdc EXT SUPPLY J1 U1 GND_DBG R1 C2 GND C1 0.1uF C21 0.1uF J3 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 DIO01 V3P3 CKTEST TMUXOUT UART_TX UART_RX_T GND_DBG V5_DBG HEADER 8X2 UART_RX_T DEBUG CONNECTOR R6 0 GND_DBG Figure 4-25: Debug Board: Electrical Schematic Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 109 of 115 71M6511/71M6511H Demo Board User's Manual 4.12 DEBUG BOARD PCB LAYOUT Figure 4-26: Debug Board: Top View Figure 4-27: Debug Board: Bottom View Page: 110 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual Figure 4-28: Debug Board: Top Signal Layer Figure 4-29: Debug Board: Middle Layer 1, Ground Plane Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 111 of 115 71M6511/71M6511H Demo Board User's Manual Figure 4-30: Debug Board: Middle Layer 2, Supply Plane Figure 4-31: Debug Board: Bottom Trace Layer Page: 112 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 71M6511/71M6511H Demo Board User's Manual 4.13 TERIDIAN 71M6511/6511H PIN-OUT INFORMATION Power/Ground/NC Pins: Name Pin # Type Description GNDA 49, 58 P Analog ground: This pin should be connected directly to the ground plane. GNDD 1 P Digital ground: This pin should be connected directly to the ground plane. V3P3A 50 P Analog power supply: A 3.3V power supply should be connected to this pin. V3P3D 9 P Digital power supply: A 3.3V power supply should be connected to this pin. VBAT 46 P Battery backup power supply. A battery or super-capacitor is to be connected between VBAT and GNDD. If no battery is used, connect VBAT to V3P3D. V2P5 47 O Output of the internal 2.5V regulator. This pin should be bypassed to GND with a 0.1F capacitor VLCD 62 P LCD power supply. Pin # Type IA 54 I Line Current Sense Input: This pin is a voltage input to the internal A/D converter. Typically, it is connected to the output of a current transformer. VA 51 I Line Voltage Sense Input: This pin is a voltage input to the internal A/D converter. Typically, it is connected to the output of a resistor divider. IB 53 I Line Current Sense Input: This pin is a voltage input to the internal A/D converter. Typically, it is connected to the output of a current transformer. V1 56 I For normal operation, a voltage of 2.6V to 2.8V has to be supplied to this pin. A voltage below VBIAS will reset the chip. Clamping V1 to V3P3 will disable the hardware watchdog timer. VREF 55 O Voltage Reference for the ADC. A 0.1F capacitor to GNDA should be connected to this pin. VBIAS 52 O The reference voltage used by the power fault detection circuit. XIN 59 XOUT 61 I Crystal Inputs: A 32kHz style crystal should be connected across these pins. Typically, a 10pf capacitor is also connected from each pin to GNDA. It is important to minimize the capacitance between these pins. See crystal manufacturer datasheet for details. VDRV 7 O Voltage boost output. Analog Pins: Name Description Table 4-6: 71M6511 Pin Description Table 1/2 Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 113 of 115 71M6511/71M6511H Demo Board User's Manual Digital Pins: Name Pin # Type COM3, COM2, COM1, COM0 16 15 14 13 O LCD Common Outputs: These 4 pins provide the select signals for the LCD display. See pinout O Dedicated LCD Segment Output. See pinout O Multi-use pin, configurable as either LCD SEG driver or DIO. See pinout O Multi-use pin, configurable as either LCD SEG driver or DIO. SEG7/MUX_SYNC 24 O Multi-use-pin LCD Segment Output/ MUX_SYNC is output for Synchronous serial interface SEG6/SRDY 23 I/O Multi-use-pin, LCD Segment Outputs/ SRDY input for Synchronous serial interface. SEG5/SFR 11 O Multi-use-pin, LCD Segment Output/ SFR output for Synchronous serial interface. SEG4/SDATA 10 O Multi-use-pin, LCD Segment Output/ SDATA output for Synchronous serial interface. SEG3/SCLK 6 O Multi-use-pin, LCD Segment Output/ SCLK output for Synchronous serial interface. CKTEST 8 O Clock PLL output. Can be enabled and disabled by CKOUT_EN. TMUXOUT 4 O Digital output test multiplexer. Controlled by DMUX[3:0]. SEG19...SEG8, SEG2...SEG0 SEG24/DIO4... SEG31/DIO11 SEG34/DIO14... SEG37/DIO17 Description OPT_RX 57 I OPT LED Receive Input: This pin receives a signal from an external photodetect diode used in an IR serial interface. OPT_TX 3 O OPT LED Transmit Output: This pin is designed to directly drive an LED for transmitting data in an IR serial interface. Can be tristated with OPT_TXDIS to be multiplexed with other GPIO pins. RESETZ 48 I Chip reset: This input pin is used to reset the chip into a known state. For normal operation, this pin is set to 1. To reset the chip, this pin is driven to 0. This pin has an internal 30A (nom.) current source pull up. A 0.1F capacitor to GNDD should be connected to this pin. RX 45 I UART input. TX 5 O UART output. E_RXTX 2 I/O Emulator serial data. This pin has an internal pull-up resistor. E_TCLK 64 O Emulator clock. This pin has an internal pull-up resistor. E_RST 63 I/O Emulator reset. This pin has an internal pull-up resistor. TEST 60 I Enables Production Test. Must be grounded in normal operation. Table 4-7: 71M6511 Pin Description Table 2/2 Page: 114 of 115 (c) 2005-2007 TERIDIAN Semiconductor Corporation Revision 5.4 VBIAS VA V3P3A GNDA 51 50 49 55 52 VREF 56 IA V1 57 IB OPT_RX 58 53 GNDA 59 54 TEST XIN 60 VLCD XOUT 61 E_RST 63 62 E_TCLK 64 71M6511/71M6511H Demo Board User's Manual GNDD 1 48 RESETZ E_RXTX 2 47 V2P5 OPT_TX 3 46 VBAT TMUXOUT 4 45 RX TX 5 44 SEG31/DIO11 SEG3/SCLK 6 43 SEG30/DIO10 VDRV 7 42 SEG29/DIO9 CKTEST 8 41 SEG28/DIO8 40 SEG27/DIO7 39 SEG26/DIO6 SEG25/DIO5 V3P3D TERIDIAN 71M6511-IGT 9 30 31 SEG13 SEG14 SEG15 29 SEG12 32 28 SEG11 27 SEG9 SEG10 SEG16 26 33 SEG8 16 25 SEG17 COM3 24 34 SEG7/MUX_SYNC 15 23 SEG18 COM2 SEG6/SRDY 35 22 14 SEG36/DIO16 COM1 21 SEG19 SEG35/DIO15 SEG24/DIO4 36 20 37 13 19 12 COM0 SEG2 SEG37/DIO17 SEG34/DIO14 38 SEG1 11 18 SEG5/SFR 17 10 SEG0 SEG4/SSDATA Figure 4-32: TERIDIAN 71M6511 LQFP64: Pinout (Top View) User Manual: This User Manual contains proprietary product definition information of TERIDIAN Semiconductor Corporation (TSC) and is made available for informational purposes only. TERIDIAN assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. TERIDIAN Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp., 6440 Oak Canyon Rd., Irvine, CA 92618-5201 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Revision 5.4 (c) 2005-2007 TERIDIAN Semiconductor Corporation Page: 115 of 115 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: 71M6511-DB