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11
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Operation Description
The FAN53601/11 is a 6 MHz, step-down switching volta ge
regulator av aila ble i n 6 00 mA o r 1 A o pti ons that deliver s a
fixed output from an input voltage supply of 2.3 V to 5.5 V.
Using a proprietary architecture w ith synchronous
rectification, the FAN53601/11 is capable of delivering a
peak efficiency of 92%, while maintaining efficiency over
80% at load currents as low as 1 mA.
The regulator operates at a nominal fixed frequency of
6 MHz, which reduc es the v alue of the exter na l c o mpo nents
to as low as 470 nH for the output inductor and 4.7 µF for the
output capacitor. In addition, the PWM modulator can be
sy nchr oniz ed to an ex ternal f requenc y s ourc e.
Control S cheme
The FAN53601/11 uses a proprietary, non-linear, fixed-
frequency PWM modulator to deliver a fast load transient
response, while maintaining a constant switching frequency
over a wide range of operating conditions. The regulator
performance is independent of the output capacitor ESR,
allow ing for the use of ceramic output capacitors. Although
this type of operati on normally results in a swi tching frequency
that varies w ith input voltage and load current, an internal
f requency loop holds the switc hing f r equency cons tant ov er a
l arge range of input voltages and load currents.
For very light loads, the FAN53601/11 operates in
Discontinuous Current Mode (DCM) single-pu lse PFM Mode,
w hich pr oduces low output ri pple c o mp ared w ith other PFM
architectures. Transition between PWM and PFM is
seamless, allowing for a smooth transition betw een DCM
and CCM.
Combined w ith exceptional transient response
characteristics, the very low quiescent current of the
controller mai nta ins high eff iciency ; even at ver y lig ht l oads ;
while preserving fast transient response for applications
requiring tight output regulation.
E nable and S oft-Start
When EN is LOW, all circuits are off and the IC draw s
~250 nA of current. When EN is HIGH and VIN is above its
UVLO threshold, the regulator begins a soft-start cycle. The
output ra mp during sof t-s tart is a f ixed s lew r ate of 50 mV/µs
from Vout = 0 to 1 V, then 12.5 mV/µs until the output reaches
its setpoint. Regardless of the state of the MODE pin, PFM
Mode is enabled to prevent current from being discharged
from COUT if soft-start begins w hen COUT is charged.
In addit ion, a ll voltage options c an be order ed with a f eature
that actively discharges FB to ground through a 230 Ω path
when EN is LOW. Raising EN above its threshold voltage
activates the part and starts the soft-start cycle. During soft-
start, the internal reference is ramped using an exponential
RC s hape to prev ent ov ers hoot of the output voltage. Current
limiting minimizes inrush during soft-start.
The c urrent-l imi t f ault respons e pro tec ts the IC in the ev ent
of an over-current condition present during soft-start. As a
res ult, the IC may f ail to start if heavy loa d is applie d duri ng
startup and/or if ex ces sive COUT is used.
The current required to charge COUT during soft-start
commonly referred to as “displacement current” is given as:
(1)
where
refers to the soft-start slew rate.
To prev ent shut dow n dur ing s of t-s tart, the f ollowing condition
must be met:
(2)
where IMAX(DC) is the maximum load current the IC is
guaranteed to support.
Startup into Larg e COUT
Multiple soft-start cycles are required for no-load startup if
COUT is greater than 15 µF. Large COUT requires light initial
load to ensure the FA N53601/11 s tarts approp riately. The I C
shuts dow n for 1.3 ms w hen IDISP exceeds ILIMIT for more
than 200 µs of current limit. The IC then begins a new soft-
start c yc le. Since COUT retains its charge w hen the IC is o ff,
the IC reaches regulation after multiple soft-start attempts.
MODE Pin
Logic 1 on this pin forces the IC to stay in PWM Mode. A
logic 0 al low s the IC to automatically sw itch to PFM during
light loads. If the MODE pin is toggled w ith a frequency
betw een 1.3 MHz and 1.7 MHz, the converter synchronizes
its sw itching frequency to four times the frequency on the
MODE pin.
The MODE pin is internally buffered w ith a Schmitt trigger,
which all ows the MODE pi n to be drive n w ith slow rise an d
fall times. An asymmetric duty cycle for frequency
synchronization is also permitted as long as the minimum
time below VIL(MAX) or above VIH(MAX) is 100 ns.
Current L imit, Fault S hutdown, and Restart
A heavy load or short circuit on the output causes the current
in the induc tor to incr ease un til a maxi mum current threshold
is r eached in the high-side sw itch. Upon r eachi ng this poi nt,
the high-side sw itch tur ns o ff, prev enting high cur rents fr om
caus ing damage. The reg ulator continues to li mit the c urr ent
cycle-by-cyc le. A fter 16 c yc les of cur rent limit, the reg ulator
triggers an over-current fault, causing the regulator to shut
dow n for about 1.3 ms before attempting a restart.
If the fault is caused by short circuit, the soft-start circuit
attempts to restart and produces an over-current fault after
about 200 µs, w hich results in a duty cycle of less than 15%,
limiting pow er dissipation.
The closed-loop peak-current limit is not the same as the
open-loop tested current limit, ILIM(OL), in the Electrical
Characteristics table. This is primarily due to the effect of
propagation delays of the IC current limit comparator.
Under-Voltag e L ockout (UVLO)
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.