ANALOG DEVICES CMOS 12-Bit Successive Approximation ADC AD7982 FEATURES 12-Bit Successive Approximation ADC Four High Impedance Input Channels Analog Input Voltage Range of 0 to +5V with Positive Reference of +5V Conversion Time of 100ys per Channel No Missed Codes Over Full Temperature Range Low Total Unadjusted Error + 1LSB max Autozero Cycle for Low Offset Voltage Monolithic Construction GENERAL DESCRIPTION The AD7582 is a medium speed, 4-channel 12-bit CMOS A/D converter which uses the successive approximation technique to provide a conversion time of 100ys per channel. An auto-zero - cycle occurs at the start of each conversion resulting in very low system offset voltages, typically less than 100uV. The device is designed for easy microprocessor interface using standard control signals; CS (decoded device address), RD (READ) and WR (WRITE). The 4-channel input multiplexer is controlled via address inputs AO and Al. Conversion results are available in two bytes, 8LSBs and 4MSBs, over an 8-bit three state output bus. Either byte can be read first. Two converter busy flags are available to facilitate polling of the converters status. The analog input voltage range is OV to +5V when using a reference voltage of +5V. The four analog inputs are all high impedance inputs with tight channel-to-channel matching typically 0.1LSBs. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM Caz Vop Vss Vee AD7582 @8) NC AUTOZERO COMPARATOR 4_f aGnp (7) SAR LN THREE STATE 4 DATA OUTPUT OUT cik @3) Y{ DRIVERS no i RD CS WR ByYsL DGND PRODUCT HIGHLIGHTS 1.. The AD7582 is a complete 4 channel 12-bit A/D converter in either a 28-pin DIP or 28-terminal surface mount package requiring only a few passive components and a voltage reference. 2. Autozero cycle realizes very low offset voltages, typically 100pV. 3. The four channel input multiplexer (user addressable) features high input impedance and excellent channel-to-channel matching. 4. Standard microprocessor control signals to allow easy inter- facing to most popular 8- and 16-bit microprocessors. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703AD7582SPECIFICATIONS Stsstesa Scat waa 7 OMe me Parameter K Version! B Version! T Version? Units Conditions/Comments ACCURACY Resolution 12 12 12 Bits Total Unadjusted Error? +] +1 +1 LSB max All channels, AINO-AIN3 Differential Nonlinearity +1 +] +] LSB max No missing codes guaranteed Full Scale Error (Gain Error) + 1/4 +4 +1/4 LSB max All channels, AINO-AIN3 Full Scale TC is typically Sppm/C Offset Error? +1/4 +1/4 +1/4 LSB max Allchannels, AINO-AIN3 Offset Error TC is typically Sppm/C Channel to Channel Mismatch* +14 + 1/4 +1/4 LSB max ANALOGINPUTS Analog Input Range Oto +5 Oto +5 Oto +5 Vv Vrer= +5.0V Camm, On Channel Input Capacitance 8 8 8 pF typ Iam, Input Leakage Current AINO-AIN3; 0 to +5V + 25C 10 10 10 nA max | Tin tO Tinax 100 100 100 nA max REFERENCE INPUT Vrer (For Specified Performance) +5 +5 +5 Vv +5% Vrer Range +4to +6 +4to +6 +4to +6 Vv Degraded transfer accuracy Vrer Input Reference Current 1.0 : 1.0 1.0 mA max Vaer= +5.0V POWER SUPPLY REJECTION Vpp Only + 1/8 +1/8 + 1/8 LSB typ Vpp= + 14.25V to + 15.75V Vss =-5V Vss Only +1/8 +1/8 +1/8 LSB typ Vss = 4.75V to 5.25V Vpp= +15V LOGICINPUTS RD (Pin 18), CS (Pin 19), WR (Pin 20) BYSL (Pin 21), AO (Pin 24), Al (Pin 25) Vy, Input Low Voltage +0.8 +0.8 +0.8 V max Vec= +5V 5% Vin Input High Voltage +2.4 +2.4 +2.4 Vmin Iyn Input Current + 25C +1 +] +1 pA max Vin = Oto Voc Tin tO T max +10 +10 +10 pA max Cyn Input Capacitance? 10 10 10 pF max CLK (Pin 23) Vix; Input Low Voltage +0.8 +0.8 +0.8 V max Vec= +5V +5% Vin, Input High Voltage +3.0 +3.0 +3.0 Vmin iy, Input Low Current +10 +10 +10 pA max Thy, Input High Current +1,5 +1.5 +1.5 mA max LOGIC OUTPUTS DBO-DB?7 (Pins 10-17), BUSY (Pin 22)* Voz, Output Low Voltage +0.4 +0.4 +0.4 V max Voc= +5V +5%, Ismx = 1.6mA* Vou, Output High Voltage +4.0 +4.0 +4.0 V min Vec= +5V +5%, Isource = 200HA Floating State Leakage Current (Pins 10-17) +] +1 +1 pA max Vour = 0V to Vec Floating State Output Capacitance 15 15 15 pF max CONVERSION TIME With External Clock 100 100 100 ps min forx = 140kHz With Internal Clock, Ta = + 25C 50/100 50/100 50/100 wsmin/max | Using recommended clock components as shown in Figure 6. POWER REQUIREMENTS Vpp +15 +15 +15 VNOM + 5% for specified performance Vss -5 -5 5 VNOM + 5% for specified performance Vec +5 +5 +5 VNOM + 5% for specified performance Ipp 7.5 75 7.5 mA max Typically 4mA with Vpp= + 15V Iss 75 75 75 mA max Typically 3mA with Vss= 5V lec 100 100 100 pA typ Vin = Vit or Via 1.0 1.0 1.0 mA max Power Dissipation 75 75 75 mW typ WR=RD = CS = BUSY = Logic HIGH NOTES Temperature Range as follows: K,B Versions; 40C to + 85C T Version; 55C to + 125C "Includes Full Scale Error, Offset Error and Relative Accuracy. 3Guaranteed by Design, not Production tested. *Tsinx for BUSY (pin 22) is 1.0 milliamp. Conversion Time includes autozero cycle time. _ Power supply current is measured when AD7582 is inactive i.e., WR =RD = cs = BUSY = Logic HIGH. Specifications subject to change without notice. ~2 REV. BAD7582 TIMING SPECIFICATIONS! ,, = +150, Voo= +5V, Voq= 3V, Var = +5) Limit at + 25C | Limit at Tins Tmax | Limit at Tain, Tmax Parameter (All Grades) (K & B Grades) (T Grade) Units Conditions/Comments ty 0 0 0 nsmin | CStoWR Setup Time t2 (INT? 200 240 280 nsmin | WR Pulse Width (Internal Clock Operation) t2(EXT) 10 10 10 psmin | WR Pulse Width (External Clock Operation) ts 0 0 0 ns min CS to WR Hold Time ts 130 160 200 ns typ 200 250 300 ns max WR to BUSY Propagation Delay ts 0 0 0 ns min AO, Al Valid to WR Setup Time te 20 20 20 ns min AO, Al Valid to WR Hold Time ty 0 0 0 ns min BUSY toCS Setup Time ts 0 0 0 nsmin | CStoRD Setup Time to 200 240 280 ns min RD Pulse Width to 0 0 0 ns min CS to RD Hold Time tu 50 50 50 ns min BYSL to RD Setup Time ti 0 0 0 nsmin | BYSLtoRD Hold Time ti3? 150 180 200 ns typ 200 240 280 nsmax | RD to Valid Data(Bus Access Time) ti4* 20 20 20 ns min RD to Three State Output 130 150 150 ns max (Bus Relinquish Time) NOTES Timing Specifications are guaranteed by Design, not Production tested. All input control signals are specified with t, = t= 20ns (10% to 90% of + 5V) and timed froma voltage level of + 1.6V. Data is timed from Vin Vit or Von, Vot- ?When using an external clock source the WR pulse width must be extended to provide the minimum auto-zero cycle time of 104.8. See External Clock Operation. Specifications subject to change without notice. CS (PIN.19) \ ty ts WR (PEN 20} \ BUSY (PIN 22) ts eo AO, Al Vin (PINS 24,25) Vi Figure 1. Start Cycle Timing BV 3k DBN DBN 3k 5 100pF 100pF DGND Son a. High-Z to Voy b. High-Z to Vor Figure 3. Load Circuits for Access Time Test (t3) REV. B 3t)3 is measured with the load circuits of Figure 3 and defined as the time required for an output to cross 0.8V or 2.4V. 4t)4 is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 4. BUSY (PIN 22) CS (PIN 19} RD (PIN 18) BYTE SELECT (PIN 21) tia TA HIGH IMPEDANCE BUS DA (PINS 10-17) LOW BYTE DATA HIGH BYTE DATA NOTES. THE TWO-BYTE CONVERSION RESULT CAN BE READ IN EITHER ORDER. FIGURE IS FOR LOW BYTE, HIGH BYTE ORDER. IF BYSL CHANGES WHILE CS & RD ARE LOW THE DATA WILL CHANGE TO REFLECT THE BYSL INPUT. Figure 2. Read Cycle Timing 5V DBN DBN 3k 10pF 10pF Seno b. Vo. to High-Z DGND @. Vow to High-Z Figure 4. Load Circuits for Output Float Delay Test (t,4)AD7582 ABSOLUTE MAXIMUM RATINGS* Storage Temperature .........5.3 65C to + 150C (Ta = +25C unless otherwise stated) Junction Temperature... 2... .0...0.0-20. +150C VpptoDGND ............0000 0.3V, +17V DIP Package, Power Dissipation ........... 875mW VsstoDGND 2... eee +0.3V,-7V -Sya Thermal Impedance... - 1s ss 72C AGNDtoDGND............ ~0.3V, Veer +0. 3V Lead Temperature, Soldering (10sec)... . 2... + 260C VectoDGND ............. _ 0.3V Vpp +0.3V Cerdip Package, Power Dissipation ......... 1000mW Veer toAGND ............. ~0.3V, Vpp +0.3V Oya Thermal Impedance Pe 51C/W AIN (0-3) toAGND .......... 0.3V Vpp +0.3V Lead Temperature, Soldering (10sec) se ee ee + 300C Digital Input Voltage to DGND 2 PLCC Package, Power Dissipation .......... 500mW (Pins 18-21, 23-25) Ce ne ne 0.3V, Vpp +0.3V Oya Thermal Impedance So tr ns 80C/W Digital Output Voltage to DGND Lead Temperature, Soldering 3 (Pins 10-17, 22).........0.. ~0.3V, Vpp +0.3V Vapor Phase (60sec) ..........-.0.. +215C Operating Temperature Range Infrared (ISsec). 2 0. ee et +210C rommer oe (K Version) ue es ~ 40C to* 85C *Stresses above those listed under Absolute Maximum Ratings may ndustrial (B Version) Tore te eee ens 40C to + 85C cause permanent damage to the device. This is a stress rating only and Extended (T Version). .......... 55C to + 125C functional operation of the device at these or any other conditions above : those indicated in the operational sections of this specification is not ORDERING GUIDE implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Total Unadjusted Temperature Error Package Model? Range Tan -I'max | Option AD7582KN | 40Cto +85C | +1LSB N-28 AD7582BQ 40Cto + 85C } +1LSB Q-28 AD7582TQ 55C to + 125C | +1 LSB Q-28 AD7582KP 40Cto + 85C | +1LSB P-28A NOTES 1To order MIL-STD-883, Class B processed parts, add /883B to part number. Contact your local sales office for military data sheet. 2N = Plastic DIP; Q = Cerdip, P = Plastic Leaded Chip Carrier. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V, which readily , j accumulate on the human body and on test equipment, can discharge without detection. Although Te . es these devices feature proprietary ESD protection circuitry, permanent damage may still occur on Ag: these devices if they are subjected to high energy electrostatic discharges. Therefore, proper precautions are recommended to avoid any performance degradation or loss of functionality. chebedaedaib aba had eneh Adee PIN CONFIGURATIONS DIP PLCC e 28] Voo CAZ 1 Aina | 2 27) Ves AIN 1 | 3 26| NC AIN 2 { 4 25] Atl AIN3 | 5 AD7582 24] AO TOP VIEW Veer LE] o 23] CLK AIN 1 |=] ain 2 [~] ain o [=] caz 13} Voo Vss BES (Not to Scale) ano | 7 22} BUSY AD7582 2] TOP VIEW DGND | 8 BYSL (Not to Scale) Vec [8 20] Wa DB7 | 10 13| & pee | 11 18] 7 pps [12 [17] 080 (LSB) pes [73 [6] DBs fre] [13] [+4] [15] [26] [17] 2&8 8 2 @ [2 pB3 | 14 15 | DB2 aaaaa 4% a NC = NOCONNECT Nc = NOCONNECT A _4- REV. BAD7582 PIN FUNCTION DESCRIPTION PIN co N AU RR WN 10-17 18 19 20 21 22 23 24 25 26 27 28 REV. B MNEMONIC CAZ AINO AIN 1 AIN 2 AIN 3 VREF AGND DGND Vec BYSL BUSY CLK AO Al N/C Vpp DESCRIPTION Autozero Capacitor Input. Connect other side of capacitor to AGND. Analog Input, channel 0 Analog Input, channel 1 Analog Input, channel 2 Analog Input, channel 3 Voltage reference input. The AD75872 is specified with Vpgr = + 5.0V. Analog Ground Digital Ground Logic Supply. For Voc = +5V digital inputs and outputs are TTL compatible. Three state data outputs. They become active when CS & RD are brought low. Individual pin function is dependent upon the Byte Select (BYSL) input. DATA BUS OUTPUT, CS & RD = LOW BYSL = HIGH BYSL = LOW Pin 10 BUSY! DB7 Pin 11 LOW? DB6 Pin 12 LOW? DB5 Pin 13 LOW? DB4 Pin 14 DB11(MSB) DB3 Pin 15 DB10 DB2 Pin 16 DB9 DBI Pin 17 DB8 DBO(LSB) BUSY (Pin 10) is a converter status flag and is HIGH during a conversion. *Pins 11-13 output a logic LOW when BYSL is HIGH. DB11DBO0 are the 12-bit conversion results, DB11 is the MSB. READ input. This active LOW signal, in combination with CS, is used to enable the output data three- state drivers. CHIP SELECT Input. Decoded device address, active LOW. Used in combination with either RD or WR for control. WRITE Input. This active LOW signal, in combination with CS, is used to start a new conversion ona selected channel. When the AD7582 internal clock is used, the minimum WR pulse width is t2 INT). When an external clock source is used, the minimum WR pulse width must be extended to include the autozero cycle time. For external clock operation, the minimum WR pulse width is t2 (EXT). BYTE SELECT. This control input determines whether the high or low byte of data is placed on the output data bus during a data READ operation (CS & RD LOW). See description of pins 10-17. BUSY indicates converter status. BUSY is LOW during conversion, otherwise BUSY is held at a logic HIGH. CLOCK Input for internal/external clock operation. Internal : Connect Rcy x and Cc_x;/Cc_x2 timing components. See Figure 6 and Figure 7. External : Connect external 74HC compatible clock source as shown in Figure 8. Address Input AO. See pin 25 description. Address Input Al. Address inputs AO and A1 select the input channel to be converted. The address input latch is transparent when CS & WR are LOW. The address inputs are latched by WR returning HIGH. Al | Ad CHANNEL SELECTED 0 0 AINO 0 1 AIN 1 1 0 AIN 2 1 1 AIN3 No connect pin. Negative supply, 5V. Positive supply, + 15V.AD7582 Operating Information OPERATIONAL DIAGRAM | An operational diagram for the AD7582 is shown in Figure 5. The only passive components required are the autozero capacitor Caz and timing components Rcr x, Ccrx; & Ccrx2 for the internal clock oscillator. If the AD7582 is to be used with an external clock source, then only Caz is required. Individual pin functions are described in detail on the previous page. Caz ANALOG INPUTS O0TO +5V, REFERRED TO AGND STATUS OUTPUT pe contro. | INPUTS + Spl. > 2xINST4 DGND pB10/DB2 (15) (14) 0B11/DB3 HP 8-BIT DATA BUS Figure 5. AD7582 Operational Diagram INTERNAL CLOCK OPERATION The clock circuitry for internal clock operation is shown in Figure 6 and the AD7582 operating waveforms are shown in Figure 7. Veco. +5V IN914 x2 : Figure 6. Circuitry Required for Internal Clock Operation ty (INT)* WR LS wo XX 1, ness Busy h MINIMUM LEVELS DEFINED BY AUTOZERO Voc betCYCLE TIME INPUT SCHMITT TRIGGER cLK = Asst emcee TTT TTT ES 0B11 DB10 OB9 DB8 DB7 DB6 DBS DB4 DB3 O82 DB1 DBO (MSB) {LSB} DECISION POINTS. *to{INT) 1S THE MINIMUM WRITE PULSE WIDTH WHEN USING INTERNAL CLOCK. SEE TIMING SPECIFICATIONS. Figure 7. Operating Waveforms - Internal Clock Between conversions (BUSY = HIGH) the AD7582 is in the autozero cycle. When WR goes LOW (with CS LOW) to start a new conversion, the input multiplexer is switched to the selected channel N, via address inputs AO, Al. The autozero capacitor Caz now charges to AIN NVos where Vos is the input offset voltage of the autozro comparator. A minimum time of 10us is required for this autozero cycle. In applications using the internal clock oscillator, it is not necessary for WR to remain LOW for this period of time since it is auto- matically provided by the AD7582. This is achieved by switching a constant current load across the clock capacitors, Ccy x); and Ce_x2, causing the voltage at the CLK input pin to slowly decay from Voc. This occurs after WR returns HIGH; WR returning HIGH also latches the multiplexer address inputs AO, Al (see Figure 7). The Schmitt trigger circuit monitoring the voltage on the CLK input ends the autozero cycle when its LOW input trigger level is reached. At this point, the constant current load across the clock capacitors is removed allowing them to charge towards Vcc via Rc, x. When the voltage at the CLK input reaches the HIGH trigger level, the constant current load is replaced across Coy x; and Ccy x2. The MSB decision is made when the LOW trigger level is reached. This cycle repeats itself 12 times to provide 12 clock pulses for the conversion cycle. The circuit arrangement of Figure 6 provides the relatively slow autozero cycle time at the beginning of a conversion while allowing the clock oscillator to speed up once the autozero cycle is complete. EXTERNAL CLOCK OPERATION For external clock operation Rc, x, Ce_x, and Cer x: are discarded and the CLK input is driven from a 74HC compatible clock source. The mark/space ratio of the external clock can vary from 40/60 to 60/40. The AD7582 WR pulse width must now be extended to provide the minimum autozero cycle time of . 10js:since this is no longer provided automatically by the AD7582. Referring to the operating waveforms of Figure 9, the minimum WR pulse width when using an external clock source is t) (EXT). Multiplexer address inputs AO and A1, in addition to the CS input must now remain valid for the external WR pulse width. One approach to stretching the available wP signals is shown in the general 8-bit .P interface circuit of Figure 20. It is not necessary to synchronize the external clock source with the extended WR pulse width, the MSB decision being made on the second falling edge of the clock input after the WR input returns HIGH. 74HC COMPATIBLE CLOCK SOURCE, (23) cLK fork = 140kHz AD7582 Voono Figure 8. External Clock Operation -6- REV. BAD7582 5 nN Lee te 1EXT)* 2 _____4 - hi a Q AD, At BUSY rr L MINIMUM AUTOZERO pt- CYCLE TIME +) AUTOZERO CYCLE t t CYCLE ee Ww CLK DECISION POINTS *t2(EXT) IS THE MINIMUM WRITE PULSE WIDTH WHEN USING EXTERNAL CLOCK. SEE TIMING SPECIFICATIONS. Figure 9. Operating Waveforms External Clock READING DATA The 12-bit conversion data plus a converter status flag are available over an 8-bit wide data bus. Data is transferred from the AD7582 in right-justified format (i.e., the LSB is the most right-hand bit in a 16-bit word). Two READ operations are required, the Byte Select (BYSL) input determining which byte-8 least significant bits or 4 most significant bits plus status flagis to be read first. Since the AD7582 uses the successive approximation register (SAR) to hold conversion results (refer to. Functional Diagram), it is necessary to wait until a conversion is finished before reading valid 12-bit data. Executing a READ instruction (HIGH or LOW byte) to the AD7582 while a conversion is in progress will place the existing contents of the SAR onto the data bus. Three different approaches can ensure valid 12-bit data is available for reading. 1. Insert a software delay greater than the ADC conversion time between the conversion start instruction and the data read instructions. . At user-defined intervals after a conversion start instruction, poll the internal converter status flag, BUSY. This signal is available on pin 10 during a HIGH byte READ instruction and is the most left-hand bit in a 16-bit right-justified word. The status bit can be shifted into a microprocessors ac- cumulator-carry position for testing (BUSY is HIGH during conversion). Use the externally available BUSY (pin 22) signal as an interrupt to the microprocessor. This signal is LOW during a conversion and returns HIGH at conversion end. Executing a WRITE instruction while conversion is in progress will restart the conversion. REV. B COMPONENT SELECTION 1. Autozero Capacitor, Caz The autozero capacitor must be a low leakage, low dielectric absorption type such as polystyrene, polypropylene or teflon. To. minimize noise connect the outside foil of Caz to AGND (pin 7), the analog system ground. Caz should be 2,200pF. . Clock Oscillator Components, Retx, Cork: and Cerx2 Clock pulses are generated by the action of series connected capacitors, Coy x; and Ce. charging through an external resistor Rey x and discharging through an internal switch. Nominal conversion time versus temperature for the recom- mended Rey x and Ceyx)/Ce_x?2 combination is shown in Figure 10. Due to process variations, the actual operating frequency for this Rcoyx and Co_x)/Co_K2 combination can vary from device to device by up to 20%. For this reason, Analog Devices recommends using an external clock in the following situations: a. Applications requiring a conversion time which is within 20% of 100us, the maximum conversion time for specified accuracy (a 140kHz clock frequency gives a 100us con- version time). . Applications which cannot accommodate conversion time differences which may occur due to unit clock frequency variations or temperature variations. It is possible to replace the fixed Rc x resistor with a 50k potentiometer in series with a fixed 22k02 resistor to allow individual adjustment of internal clock frequency. Reducing the value of Rc, x from 56k to 47k decreases the conversion time by typically 12us. Reik = 56k Ccik1 = 3.9nF Ccik2 = 560pF CONVERSION TIME - Lis 55 25 0 +25 +50 +75 AMBIENT TEMPERATURE - C +100 +125 Figure 10. Typical Conversion Time vs. Temperature Using Internal ClockAD7582 APPLYING THE AD7582 The high input impedance of the analog channels, AINOQAIN3, aliows simple analog interfacing. Zero to +5V signal sources can be connected directly to the analog input channels without additional buffering for source impedances up to 5k2 (see Figure 11). The input/output transfer characteristic and transition points for this input signal range are shown in Figure 12 and Table I respectively. The designed transition points on the AD7582 transfer characteristic occur on integer multiples of 1LSB: The output code is Natural Binary with ILSB = (F.S.) (1/4096) = (5/4096)V = 1.22mV. *ADDITIONAL PINS OMITTED FOR CLARITY, ONLY CHANNEL 0 SHOWN Figure 11. Unipolar 0 to +5V Operation 00---011 + DIGITAL OUTPUT \N 4 FS=5V 90---010 {LSB = FS/4096 00---G01 + 00---000 A a ' 1 OV 1LSB 2LSB 3LSB FS~2LSB FS-1LSB ANALOG INPUT, ANY CHANNEL Figure 12. Ideal Input/Output Transfer Characteristic for Unipolar Circuit of Figure 17 Table |. Transition Points for Unipolar 0 to + 5V Operation Analog Input, Volts Digital Output 0.00122 000 001 AL 0.00244 A, 000 010 4 2.49878 7 Oil 111 T 2.50000 100 000 L 2.50122 L 100 001 AL @ 4.99756 7 111 110 4.99878 111 111 Signal ranges other than 0 to + 5V are easily accommodated by using resistor divider networks to produce 0 to + 5V signal ranges at the AD7582 input pins. Figure 13 shows a divider network on channel 0 to allow an AIN 0 signal range of 0 to +10V. The input resistors must be selected to match within 0.01% and should be the same type and from the same man- ufacturer so that their temperature coefficients match. Note that since the source impedance has not been included in the resistor divider ratio, it must now be as low as possible. For Figure 13 with a source impedance of 0.50 the maximum error across the network is approximately 0.5SLSB. The LSB size is (F.S.)(1/4096) = (10/4096)V = 2.44mV. R2, 10k Vs OY) Vsi0TO +10V 0.01% AD7582* AGND *ADDITIONAL PINS OMITTED FOR CLARITY, ONLY CHANNEL 0 SHOWN Figure 13. Unipolar 0 to +10V Operation Bipolar signal ranges of ~5V to +5V are accommodated by referencing the resistor divider network to Vrgr as shown in Figure 14 for channel 0. With the resistor values shown, the signal source must be capable of sinking 0.5mA. The input/output transfer characteristic and transition points for this +5V signal range are shown in Figure 15 and Table II respectively. The output code is Offset Binary with an LSB size of (F.S.)(1/4096) = (10/4096)V = 2.44mV. With an analog input (Vs) of 1.22mV, the input offset voltage of Al should be adjusted until the ADC output flickers between. 0111 1111 1111 and 1000 0000 0000. Alternatively the 1/2LSB signal offset can be included in the signal conditioning elec- tronics. Vrer ; AD7582* AIN 6 *ADDITIONAL PINS OMITTED FOR CLARITY, ONLY CHANNEL 0 SHOWN Figure 14. Bipolar ~5V to +5V Operation 11-141 i I 111-110 i | 4 aL ! ~ me ' 100---010 7 100---001 + -V2LsB ' 00-001 T pe { 2 C. l 100---000 4) 45 +FS _ isp O11---411 + | + V/2LSB I 011-110 Fy rel va ~ | | ---001 4 FS=10V 000---004 \ 4LSB =FS/4096 000---000 fC i a oY ov ANALOG INPUT, ANY CHANNEL Figure 715. Ideal Input/Output Transfer Characteristic for Bipolar Circuit of Figure 14 Table If. Transition Points for Bipolar 5V to + 5V Operation Analog Input, Volts Digital Output 4.99878 000 001 L 4.99634 - 000 010 wa 0.00122 100 000 lL + 0.00122 100 001 +4,99389 111 110 T 3459634 111 111 REV. BAD7582 Applications Power Supply Decoupling: All power supplies to the AD7582 should be bypassed with either 10F tantulum or electrolytic capacitors. To ensure good high frequency performance, each capacitor should be bypassed with an 0.01F disc ceramic capacitor. All capacitors should be placed as close as possible to the AD7582. Reference Circuit: Figure 16 shows how to configure an AD584LH to produce a reference voltage of 5.00V. R2 provides a typical adjustment range of +75mV. The AD584LH will contribute less than 1LSB of gain error over the commercial temperature range. Figure 16. AD584LH as Reference Generator Transient currents flow at the Vpgr input during a conversion. To avoid dynamic errors place a 0.01,,F disc ceramic from the VreEF pin to AGND. Proper Layout: Layout for a printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or close to the autozero capacitor. The analog inputs, the reference input and the autozero input should be screened by AGND. A single point analog ground separate from the logic system ground should be established at pin 7 (AGND) or as close as possible to the AD7582. This single point analog ground should be connected to the digital system ground, to which pin 8 (DGND) is connected, at one point only and as close to the AD7582 as possible. The autozero capacitor, bypass capacitors for the refer- ence input and the analog supplies, AIN commons and any input signal screening should be returned to the analog ground point. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. Noise: Input signal leads to AIN 0-3 and signal return leads from AGND (pin 7) should be kept as short as possible to minimize input noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended. Also since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedances as much as possible. In applications where the AD7582 data outputs are connected to a continuously busy (and noisy) microprocessor bus it is possible to get LSB errors in conversion results. These errors are due to feedthrough from the microprocessor bus to the autozero com- parator. The problem exists only for ceramic package versions of the AD7582. Stopping bus activity during a conversion eliminates this problem. Alternatively the AD7582 can be isolated from the microprocessor bus by means of three-state buffers. Microprocessor Interfacing MICROPROCESSOR INTERFACING When the AD7582 is used with its own internal clock oscillator, microprocessor interfacing is straightforward and requires at most a few external gates (see Figures 17 through 19, 21 and 22). When the AD7582 is used with an external clock source, additional circuitry is required to extend the uP control signals (see Figure 20). MC6800, MC6809 and 6502 MICROPROCESSORS A typical interface to the AD7582 with any of the above micro- processors is shown in Figure 17. The decoder can be enabled high using VMA in 6800 systems or enabled low by NORing to and 2 in 6502 systems or by NORing E and Q in 6809 systems. Address lines AO, Al, and A2 of the 6800 have been tied to AO, Al and BYSL respectively of the AD7582. Assuming the AD7582 is assigned a memory block starting at address 8000H, the input multiplexer is addressed as follows: 8000H Channel 0 8001H Channel 1 8002H Channel 2 8003H Channel 3 REV. B A write instruction to one of these addresses will start a conversion of the selected channel. To read the conversion results, it is necessary only to bring control inputs CS and RD low. The BYSL input (tied to A2 of the wP) determines whether the data high or low byte is placed onto the 8-bit data bus. A read instruction to any one of the previous channel addresses will result in the low byte of data being transferred to the ~P (BYSL = Low). Similarly a read instruction to any address having A2 HIGH and within the assigned memory block, e.g., 8004H, transfers the high byte of data to the iP. The converter status flag BUSY can be polled at intervals to check whether the present conversion has finished and valid 12-bit data is available. This is accomplished by the following instructions on the 6800: LDA A_ $8004 Load Fiag from AD7582 ASL A Shift Flag into Carry BCC FETCH Branch to Data Fetch Subroutine if BUSY is LOWAD7582 A2 A0-A15 ADDR BUS Al @ A0 BYSL DECODE AG Ai BYS LOGIC s EOR $2 6502 DBO-DB7 6800 6809 Do-D7 DATA BUS \ AD7582* *LINEAR CIRCUITRY OMITTED FOR CLARITY. AD7582 OPERATING ON INTERNAL CLOCK. Figure 17, AD7582 MC6800, 6809, 6502 Interface 8085A, Z80 MICROPROCESSORS A typical interface to either of these microprocessors is shown in Figure 18. Not shown in the figure is the 8-bit latch required to demultiplex the 8085A common address/data bus. This interface uses slightly different low-level address decoding than the previous interface. Address lines AO, Ai & A2 of the P have been tied to BYSL, AO & Al respectively of the AD7582. This allows the 16-bit data move instructions on both the 8085A and the Z80 to be used when reading conversion results. Assuming the AD7582 is again assigned a memory block starting at address 8000H the input multiplexer is now addressed as follows: 8000H Channel 0 8002H Channel 1 8004H Channel 2 8006H Channel 3 A write instruction to one of these addresses will start a conversion of the selected channel. The 12-bit conversion results can be read (low byte first then high byte) by a single read instruction; On the 8085A LHLD 8000 Az AQ-A15 ADDR BUS Al -@ @ | ao DECODE 0 A1 BYSL LOGIC. = (oJ ag AD7582* RD RD WR WR 085A Do-b7 Z80 | DBO-DB7 DATA BUS S *LINEAR CIRCUITRY OMITTED FOR CLARITY. AD7582 OPERATING ON INTERNAL CLOCK. Figure 18. AD7582 8085A, 280 Interface -10- moves the conversion results into register pair HL. On the Z80 LD BC, (8000) moves the conversion results into register pair BC MC68000, MC68008 MICROPROCESSOR Figure 19 shows an AD7582MC68000/MC68008 interface. Address lines Al, A2 and A3 of the wP are connected to BYSL, AO & Al inputs respectively of the AD7582. With the simple decoding logic shown in Figure 19, the AD7582 is decoded in a memory block from COO0OH to FFFFH. The input multiplexer is now addressed as follows: C000H Channel 0 C004H Channel 1 Co00sH Channel 2 CO00CH Channel 3 A write instruction to one of these addresses will start a conversion of the selected channel, i.e., MOVE. W DO $c004 starts a conversion of channel 1. When the conversion is complete, the P acquires the result by reading from the AD7582, i.e, MOVEP. W $000(A2), DO This instruction places the conversion data in the DO register of the iP. Address register A2 should contain an odd-order address for the AD7582, e.g., $C003. ADDRESS DECODE LOGIC Al4 @ pas AZ > A2 -@ -4q ADDR BUS 4 a ALLE. 1 LY DTACK cs t|_ )>_~J RD AD7582* ri Ln E> wr DB0-DB7 A1-A19 Mmc6s8000 MC68008 D0-D7 DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY. AD7582 OPERATING ON INTERNAL CLOCK. Figure 19. AD7582 - MC68000/MC68008 Interface MICROPROCESSOR INTERFACE TO AD7582 WITH EXTERNAL CLOCK Figure 20 shows the additional circuitry generally required to interface an 8-bit uP to the AD7582 operating from an external clock source. During a write operation, the 74121 monostable (one-shot) is triggered to latch the data (AQ, Al and CS) in the 7477, a 4-bit bistable latch. The monostable timing components (not shown in Figure 20) should be chosen to provide an output pulse width corresponding to tz (EXT), the minimum autozero cycle time. To avoid any possibility of spurious triggering, the monostable should be enabled by a valid memory address signal. During a data read cycle, the 7477 latch is transparent and data is read normally. Note that the wP write and read cycle times are unaffected by the interface circuitry. REV. BAD7582 Az ADDR BUS At AO-A1S 50 . 74HC77 I . Do Gof-m4} ag = BYSL 80gs DI. Qt] at ADDRESS DECODE 9 D2. O2 peed CS HOLD 74121 a WR Wa t ae AD7582* wh en Oo 140kHz VALID } T4HC ie4 CLK MEMORY COMPATIBLE ADDRESS SO. WAVE RD RD 8-BIT uP DB0-D87 b0-D7 DATA BUS G *LINEAR CIRCUITRY OMITTED FOR CLARITY. AD7582 OPERATING WITH EXTERNAL CLOCK. Figure 20. Interface to AD7582 Using External Clock 8088, 8086 MICROPROCESSORS Figure 21 shows an AD7582-8088 interface. Address lines AO, Al and A2 are connected to BYSL, AO and Al inputs respectively of the AD7582. With the simple decoding shown in Figure 21 the AD7582 is decoded in a memory block from 4000H to 7FFFH. The input multiplexer is now addressed as follows: 4000H Channel 0 4002H Channel 1 4004H Channel 2 4006H Channel 3 A write instruction to one of these addresses will start a conversion of the selected channel, i.e, MOV 4004, AX starts a conversion of channel 2. When the conversion is finished the 8088 acquires the result by reading from the AD7582, i.e., MOV AX, 4000 places the conversion data in the accumulator. ADDRESS DECODE LOGIC MINIIX -O V ce AIS | AB-A15 A14 ADDRESS BUS az A2 & AO e 7 4, 1 8088 AO At BYSL s 10/M 4 /-9 AD7582* RD RD WR WR DB0-DB7 ALE +|sTB 8282 ADO-AD7 DATA BUS \ *LINEAR CIRCUITRY OMITTED FOR CLARITY. AD7582 OPERATING ON INTERNAL CLOCK Figure 21. AD7582 8088 Interface REV. B Figure 22. shows.an AD7582-8086 interface. Address lines Al, A2 and A3 are connected to BYSL,; AO and Al inputs respectively of the AD7582. The AD7582 is again decoded in a memory block from 4000H to 7FFFH. The input multiplexer is now addressed as follows: 4000H Channel 0 4004H Channel 1 4008H Channel 2 400CH Channel 3 A write instruction to one of these addresses will start a conversion of the selected channel, i.e, MOV 4008, AX starts a conversion of channel 2. When the conversion is finished, the 8086 acquires the result by reading from the AD7582 in two read cycles, i.e., MOV AL, 4000 MOV AH, 4002 places the conversion data in the accumulator. ADDRESS DECODE LoGic MNIMIX f-O Voc A15 az AB ADDRESS BUS @. Al 8086 AO Al BYSL ics MitO AD7582* RD RD WR WR L 8282 DBO-DB7 ALE [=| STB (2) 10 ADO-AD15 * DATA BUS AD7 *LINEAR CIRCUITRY OMITTED FOR CLARITY. AD7582 OPERATING ON INTERNAL CLOCK. Figure 22, AD7582 8086 Interface AD7582-AD585 SAMPLE-HOLD INTERFACE Figure 23 shows an AD585 Sample-Hold Amplifier driving Ap of the AD7582. At a sampling frequency of 8kHz the maximum input signal frequency is 4kHz. The AD7582 is configured for bipolar operation to allow an input signal swing of +5V. No clock components are shown for the AD7582 but the conversion time of the AD7582 should be adjusted for 100 microseconds. With an external hold capacitor of 100pF, the acquisition time for the sample-hold amplifier is 10 microseconds. The circuit operates from 0C to +70C. -li-AD7582 To take a sample of the input, a WRITE instruction is executed to the-AD7582 control.inputs.: The converter busy flag, BUSY, is driven low indicating that a conversion is in progress. The falling edge of this BUSY signa!-places the sample-hold amplifier into.the HOLD mode freezing the input signal to the AD7582. After 100 microseconds the conversion is finished and the BUSY signal is brought high. This allows a time of 25 microseconds for the AD585 to come out of the hold mode and acquire the input signal in time for the next sample. Between the end of one conversion and the start of the next, the conversion results must be read from the converter. Careful circuit layout and power supply decoupling are necessary to obtain maximum performance from the system. Decoupling capacitors in the diagram are all 10yF electroytics in parallel with 0.01pF disc ceramics. +V5 Figure 23. AD7582-AD585 Interface MECHANICAL Dimensions shown 28-Pin Plastic DIP (N-28) 28 15 0.550 (13.97) 0.530 (13.462) 1 14 (3.980) 0.606 (15.39) 0.594 (15.09) 1450 (36.83) 0.594 (15.09) 1-440 (36.576) | y 0.160 (4.07) i 0.140 (3.56) P, at} 15 0 0.012 (0.305) 0.008 (0.203) 0.020 (0.508) 0,105 (2.67) 0.065 (1.65) 0.175 (4.45) 0.015 (0.381) 0.095 (2:41) 0.045 (1.14). 0.120 (3.05) LEADS ARE SOLDER DIPPED OR TIN-PLATED ALLOY 42 OR COPPER. INFORMATION in inches and (mm). 28-Pin PLCC (P-28A) 28-Pin Cerdip (Q-28) <__ 1.490 (37.84) MAX | LOL oe 23 15 1 @ 14 OTT ST ero er LY GLASS SEALANT 0.22 | ke ia | 0.44 (2.79) 0.099 (2.28) 0.02 (0.5) 0.06 (1.52) 0.016 (0.406) 0.05 (1.27) 12- 0.048 (1.21) 0.048 (1.21) >| melt . : Y [* 0.042 (4.07) + [ soaa ion S; = Aq 5 PINT 25 U a 0.048 (1.21) IDENTIFIER [1 0.456 (11.58) wea 0.042 (7.07) | 0.450 (11.43) yee ~y q O Ls q H 6 0.021 (0.53) 0,495 (12.57) . l A 8.075 (0.38 Q 1 | 0.485 (12.32) ey A (0.38) Ca we I+ 0.032 (0.81) K [ 5.026 (0-66) 12 18 \ A (0-66) = w o.ase (11.58) = | 0.025 (0.63) 0.450 (11.43) > 0.015 (0.38) 0.040 (1.01) 0.495 (12.57) 0.025 (0.64) > 0.110 (2.79) 0.485 (12.32) 0.180 (4.87) >| 3085 (2-18) 0.165 (4.19) 0.525 (13.33) 0.515 (13.08) y 0.18 (4.57) 0.620 (15.74) MAX 0.125 (3.175) MIN 2.620 (15.74) |g 0.590 (14.93) 0.012 (0.305) \ 4 0.008 (0.203) REV. B oO o cd = I aD o oO oO < a 5 Zz a uu kK z x a.