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© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 1
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
FAN4800A/C, FAN4801/02/02L
PFC/PWM Controller Combination
Features
Pin-to-Pin Compatible with ML4800 and FAN4800
and CM6800 and CM6800A
PWM Configurable for Current-Mode or
Feed-forward Voltage-Mode Operation
Internally Synchronized Leading-Edge PFC and
Trailing-Edge PWM in one IC
Low Operating Current
Innovative Switching-Charge Multiplier Divider
Average-Current-Mode for Input-Current Shaping
PFC Over-Voltage and Under-Voltage Protections
PFC Feedback Open-Loop Protection
Peak Current Limiting for PFC
Cycle-by-Cycle Current Limiting for PWM
Power-On Sequence Control and Soft-Start
Brownout Protection
Interleaved PFC/PWM Switching
FAN4801/02/02L Improve Efficiency at Light Load
fRTCT=4•fPFC=4•fPWM for FAN4800A and FAN4801
fRTCT=4•fPFC=2•fPWM for FAN4800C and
FAN4802/02L
Applications
Desktop PC Power Supply
Internet Server Power Supply
LCD TV, Monitor Power Supply
UPS
Battery Charger
DC Motor Power Supply
Monitor Power Supply
Telecom System Power Supply
Distributed Power
Description
The highly integrated FAN4800A/C and FAN4801/02/2L
are specially designed for power supplies that consist of
boost PFC and PWM. They require very few external
components to achieve versatile protections /
compensation. They are available in 16-pin DIP and
SOP packages.
The PWM can be used in either current or voltage
mode. In voltage mode, feed-forward from the PFC
output bus can reduce the secondary output ripple.
Compared with older productions, ML4800 and
FAN4800, FAN4800A/C and FAN4801/02/02L have
lower operation current that save power consumption in
external devices. FAN4800A/C and FAN4801/1S/2/2L
have accurate 49.9% maximum duty of PWM that
makes the hold-up time longer. Brownout protection and
PFC soft-start functions are not in ML4800 and
FAN4800.
To evaluate FAN4800A/C, FAN4801/02/2L for replacing
existing FAN4800 and ML4800 boards, five things must
be completed before the fine-tuning procedure:
1. Change RAC resister from the old value to a higher
resister: between 6M to 8M.
2. Change RT/CT pin from the existing values to
RT=6.8K and CT=1000pF to have fPFC=64KHz,
fPWM=64KHz.
3. VRMS pin needs to be 1.224V at VIN=85 VAC for
universal input application from line input from
85VAC to 270 VAC. Both poles for the Vrms of
FAN4801/02/02L don’t need to substantially slower
than FAN4800; about 5 to 10 times.
4. At full load, the average VEA needs to ~4.5V and the
ripple on the VEA needs to be less than 400mV.
5. Soft-Start pin, the soft-start current has been
reduced to half from the FAN4800 capacitor.
Related Resources
AN-8027 - FAN480X PFC+PWM Combination
Controller Application
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 2
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Ordering Information
Part Number Operating
Temperature Range Package Packing Method
FAN4800ANY -40°C to +105°C 16-Pin Dual In-Line Package (DIP) Tube
FAN4800CNY -40°C to +105°C 16-Pin Dual In-Line Package (DIP) Tube
FAN4800AMY -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel
FAN4800CMY -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel
FAN4801NY -40°C to +105°C 16-Pin Dual In-Line Package (DIP) Tube
FAN4802NY -40°C to +105°C 16-Pin Dual In-Line Package (DIP)) Tube
FAN4802LNY -40°C to +105°C 16-Pin Dual In-Line Package (DIP)) Tube
FAN4801MY -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel
FAN4802MY -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel
FAN4802LMY -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel
Part Number PFC:PWM Frequency Ratio Brownout / In Range In / Out
FAN4800ANY 1:1 1.05V / 1.9V N.A
FAN4800AMY 1:1 1.05V / 1.9V N.A
FAN4800CNY 1:2 1.05V / 1.9V N.A
FAN4800CMY 1:2 1.05V / 1.9V N.A
FAN4801NY 1:1 1.05V / 1.9V 1.95V / 2.45V
FAN4802NY 1:2 1.05V / 1.9V 1.95V / 2.45V
FAN4802LNY 1:2 0.9V / 1.65V 1.95V / 2.45V
FAN4801MY 1:1 1.05V / 1.9V 1.95V / 2.45V
FAN4802MY 1:2 1.05V / 1.9V 1.95V / 2.45V
FAN4802LMY 1:2 0.9V / 1.65V 1.95V / 2.45V
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 3
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Application Diagram
IEA
RAMP
RT/CT
FBPWM
SS
VRMS
ISENSE
IAC
ILIMIT
GND
OPWM
OPFC
VDD
VREF
FBPFC
VEA
FAN4800A/C
FAN4801/02/02L
VDD
VREF
Secondary
Figure 1. Typical Application Current Mode
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 4
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Application Diagram
IEA
RAMP
RT/CT
FBPWM
SS
VRMS
ISENSE
IAC
ILIMIT
GND
OPWM
OPFC
VDD
VREF
FBPFC
VEA
FAN4800A/C
FAN4801/02/02L
VDD
VREF
Secondary
VREF
Figure 2. Typical Application Voltage Mode
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 5
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Block Diagram
Figure 3. FAN4800A/C Function Block Diagram
Figure 4. FAN4801/02/02L Function Block Diagram
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 6
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Marking Information
Figure 5. DIP Top Mark
Figure 6. SOP Top Mark
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die-Run Code
T – Package Type (M:SOP)
P – Y: Green Package
M – Manufacture Flow Code
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 2-Digit Week Code
TT – 2-Digit Die-Run Code
T – Package Type (M:SOP)
P – Y: Green Package
M – Manufacture Flow Code
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 7
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Pin Configuration
Figure 7. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1 IEA
Output of PFC Current Amplifier. The signal from this pin is compared with an internal
sawtooth to determine the pulse width for PFC gate drive.
2 IAC
Input AC Current. For normal operation, this input provides current reference for the multiplier.
The suggested maximum IAC is 100µA.
3 ISENSE
PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of
multiplier and PFC ILIMIT comparator.
4 VRMS
Line-Voltage Detection. Line voltage detection. The pin is used for PFC multiplier.
5 SS
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10µA constant
current source. The voltage on FBPWM is clamped by SS during startup. In the event of a
protection condition occurring and/or PWM disabled, the SS pin is quickly discharged.
6 FBPWM
PWM Feedback Input. The control input for voltage-loop feedback of PWM stage.
7 RT/CT
Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT.
8 RAMP
PWM RAMP Input. In current mode, this pin functions as the current sense input; when in
voltage mode, it is the feed forward sense input from PFC output 380V (feedforward ramp).
9 ILIMIT
Peak Current Limit Setting for PW M. The peak current limits setting for PWM.
10 GND
Ground.
11 OPWM
PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally
clamped under 15V to protect the MOSFET.
12 OPFC
PFC Gate Drive. The totem pole output drive for PWM MOSFET. This pin is internally clamped
under 15V to protect the MOSFET.
13 VDD
Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and
9.3V, respectively. The operating current is lower than 10mA.
14 VREF
Reference Voltage. Buffered output for the internal 7.5V reference.
15 FBPFC
Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input
of PFC error amplifier. This pin is connected to the PFC output through a divider network.
16 VEA
Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop.
A compensation network is connected between this pin and ground.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 8
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VDD DC Supply Voltage 30 V
VH SS, FBPWM, RAMP, OPWM, OPFC -0.3 30.0 V
VL IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA -0.3 7.0 V
VVREF VREF 7.5 V
VIEA IEA 0 VVREF+0.3 V
VN ISENSE -5.0 0.7 V
IAC Input AC Current 1 mA
IREF VREF Output Current 5 mA
IPFC-OUT Peak PFC OUT Current, Source or Sink 0.5 A
IPWM-OUT Peak PWM OUT Current, Source or Sink 0.5 A
PD Power Dissipation TA < 50°C 800 mW
ΘJA Thermal Resistance (Junction-to-Air) DIP 80.80 °C/W
SOP 104.10 °C/W
TJ Operating Junction Temperature -40 +125 °C
TSTG Storage Temperature Range -55 +150 °C
TL Lead Temperature (Soldering) +260 °C
ESD Electrostatic Discharge Capability
Human Body Model,
JESD22-A114 4.5 kV
Charged Device Model,
JESD22-C101 1000 V
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Max. Unit
TA Operating Ambient Temperature -40 +105 °C
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 9
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Electrical Characteristics
VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications.
Symbol Parameter Conditions Min. Typ. Max. Units
VDD Section
IDD ST Startup Current VDD=VTH-ON-0.1V; OPFC OPWM Open 30 80 µA
IDD-OP Operating Current VDD=13V; OPFC OPWM Open 2.0 2.6 5.0 mA
VTH-ON Turn-On Threshold
Voltage
10 11 12 V
VTH Hysteresis 1.5 1.9 V
VDD-OVP V
DD OVP 27 28 29 V
VDD-OVP VDD OVP Hysteresis 1 V
Oscillator
fOSC-RT/CT RT/CT Frequency RT=6.8kΩ, CT=1000pF 240 256 268 kHz
fOSC
PFC & PWM Frequency
RT=6.8kΩ, CT=1000pF
60 64 67
kHz
FAN4800C,FAN4802/02L
PWM Frequency 120 128 134
fDV Voltage Stability 11V ≦ VDD ≦ 22V 2 %
fDT Temperature Stability -40°C ~ +105°C 2 %
fTV Total Variation
(PFC and PWM)(3) Line, Temperature 58 70 kHz
fRV Ramp Voltage(3) Valley to Peak 2.8 V
IDischarge Discharge Current VRAMP=0V, VRT/CT=2.5V 6.5 15 mA
fRANGE Frequency Range(3) 50 75 kHz
tPFCD PFC Dead Time RT=6.8kΩ, CT=1000pF 400 600 800 ns
VREF
VVREF Reference Voltage IREF=0mA, CREF=0.1µF 7.4 7.5 7.6 V
VVREF1 Load Regulation of
Reference Voltage
CREF=0.1µF, IREF=0mA to 3.5mA
VVDD=14V, Rise/Fall Time > 20µs 30 50 mV
VVREF2 Line Regulation of
Reference Voltage CREF=0.1µF, VVDD=11V to 22V 25 mV
VVREF-DT
Temperature Stability(3) -40°C ~ +105°C 0.4 0.5 %
VVREF-TV
Total Variation(3) Line, Load, Temperature 7.35 7.65 V
VVREF-LS
Long-Term Stability(3) T
J=125°C, 0 ~ 1000HRs 5 25 mV
IREF-MAX. Maximum Current VVREF > 7.35V 5 mA
IOS
Output Short Circuit(3) 25 mA
PFC OVP Comparator
VPFC-OVP Over-Voltage Protection 2.70 2.75 2.80 V
VPFC-OVP PFC OVP Hysteresis 200 250 300 mV
Low-Power Detect Comparator
VEAOFF V
EA Voltage OFF OPFC 0.2 0.3 0.4 V
VIN OK Comparator
VRD-FBPFC
Voltage Level on FBPFC
to Enable OPWM During
Startup
2.3 2.4 2.5 V
VRD-FBPFC Hysteresis 1.15 1.25 1.35 V
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 10
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Electrical Characteristics (Continued)
VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications.
Symbol Parameter Conditions Min. Typ. Max. Units
Voltage Error Amplifier
FBPFC Input Voltage Range(3) 0 6 V
Vref Reference Voltage at T=25°C 2.45 2.50 2.55 V
AV Open-Loop Gain(3) 35 42 dB
Gmv Transconductance VNONINV=VINV, VVEA=3.75V at T=25°C 50 70 90 µmho
IFBPFC-L Maximum Source Current VFBPFC=2V, VVEA=1.5V 40 50 µA
IFBPFC-H Maximum Sink Current VFBPFC=3V, VVEA=6V -50 -40 µA
IBS Input Bias Current -1 1 µA
VVEA-H Output High Voltage on
VVEA 5.8 6 V
VVEA-L Output Low Voltage on
VVEA 0.1 0.4 V
Current Error Amplifier
VISENSE Input Voltage Range
(ISENSE Pin)(3) -1.5 0.7 V
GmI Transconductance VNONINV=VINV, VIEA=3.75V 78 88 100 µmho
VOFFSET Input Offset Voltage VVEA=0V, IAC Open -10 10 mV
VIEA-H Output High Voltage 6.8 7.4 8.0 V
VIEA-L Output Low Voltage 0.1 0.4 V
IL Source Current VISENSE=-0.6V, VIEA=1.5V 35 50 µA
IH Sink Current VISENSE=+0.6V, VIEA=4.0V -50 -35 µA
AI Open-Loop Gain(3) 40 50 dB
Tri-Fault Detect
tFBPFC_OPEN Time to FBPFC Open(3) VFBPFC=VPFC-UVP to FBPFC OPEN,
470pF from FBPFC to GND 2 4 ms
VPFC-UVP PFC Feedback Under-
Voltage Protection 0.4 0.5 0.6 V
Gain Modulator
IAC Input for AC Current(3) Multiplier Linear Range 0 100 µA
GAIN GAIN Modulator(4)
IAC=17.67µA, VRMS=1.080V
VFBPFC=2.25V, at T=25°C 7.50 9.00 10.50
IAC=20µA, VRMS=1.224V VFBPFC=2.25V,
at T=25°C 6.30 7.00 7.70
IAC=25.69µA, VRMS=1.585V
VFBPFC=2.25V, at T=25°C 3.80 4.20 4.60
IAC=51.62µA, VRMS=3.169V
VFBPFC=2.25V, at T=25°C 0.95 1.05 1.16
IAC=62.23µA, VRMS=3.803V
VFBPFC=2.25V, at T=25°C 0.66 0.73 0.80
BW Bandwidth(3) I
AC=40µA 2 kHz
Vo(gm) Output Voltage=5.7kΩ ×
(ISENSE-IOFFSET)(3)
IAC=20µA, VRMS=1.224V VFBPFC=2.25V,
at T=25°C 0.74 0.82 0.90 V
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 11
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Electrical Characteristics (Continued)
VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications.
Symbol Parameter Conditions Min. Typ. Max. Units
PFC ILIMIT Comparator
VPFC-ILIMIT
Peak Current Limit
Threshold Voltage,
Cycle-by-Cycle Limit
-1.25 -1.15 -1.05 V
Vpk PFC ILIMIT-Gain Modulator
Output
IAC=17.67µA, VRMS=1.08V
VFBPFC=2.25V, at T=25°C 200 mV
PFC Output Driver
VGATE-CLAMP Gate Output Clamping
Voltage VDD=22V 13 15 17 V
VGATE-L Gate Low Voltage VDD=15V; IO=100mA 1.5 V
VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 V
tr Gate Rising Time VDD=15V; CL=4.7nF; O/P=2V to 9V 40 70 120 ns
tf Gate Falling Time VDD=15V; CL=4.7nF; O/P=9V to 2V 40 60 110 ns
DPFC-MAX Maximum Duty Cycle VIEA<1.2V 94 97 %
DPFC-MIN Minimum Duty Cycle VIEA>4.5V 0 %
Brownout
VRMS-UVL V
RMS Threshold Low FAN4800A/C, FAN4801/02 1.00 1.05 1.10 V
FAN4802L 0.85 0.90 0.95 V
VRMS-UVH V
RMS Threshold High FAN4800A/C, FAN4801/02 1.85 1.90 1.95 V
FAN4802L 1.60 1.65 1.70 V
VRMS-UVP Hysteresis FAN4800A/C, FAN4801/02 750 850 950 mV
FAN4802L 650 750 850 mV
tUVP Under-Voltage Protection
Delay Time 340 410 480 ms
Soft-Start
VSS-MAX Maximum Voltage VDD=15V 9.5 10.0 10.5 V
ISS Soft-Start Current 10 µA
PWM ILIMIT Comparator
VPWM-ILIMIT Threshold Voltage 0.95 1.00 1.05 V
tPD Delay to Output 250 ns
tPWM-Bnk Leading-Edge Blanking
Time 170 250 350 ns
Range (FAN4801/02/02L)
VRMS-L RMS AC Voltage Low When VRMS=1.95V at132VRMS 1.90 1.95 2.00 V
VRMS-H RMS AC Voltage High When VRMS=2.45V at150VRMS 2.40 2.45 2.50 V
VEA-L VEA Low When VVEA=1.95V at 30% Loading,
When VVEA=2.80V at 60% Loading 1.90 1.95 2.00 V
VEA-H VEA High When VVEA=2.45V at 40% Loading,
When VVEA=3.35V at 70% Loading 2.40 2.45 2.50 V
Itc Two-Level Current FBPFC Two-Level Current 18 20 22 µA
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 12
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Electrical Characteristics (Continued)
VDD=15V, TA=25°C, RT=6.8kΩ, CT=1000pF unless noted operating specifications.
Symbol Parameter Conditions Min. Typ. Max. Units
PWM Output Driver
VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 13 15 17 V
VGATE-L Gate Low Voltage VDD=15V; IO=100mA 1.5 V
VGATE-H Gate High Voltage VDD=13V; IO=100mA 8 V
tr Gate Rising Time VDD=15V; CL=4.7nF 30 60 120 ns
tf Gate Falling Time VDD=15V; CL=4.7nF 30 50 110 ns
DPWM-MAX Maximum Duty Cycle 49.0 49.5 50.0 %
VPWM-LS PWM Comparator Level Shift 1.3 1.5 1.8 V
Notes:
3. This parameter, although guaranteed by design, is not 100% production tested.
4. Gain=K × 5.3 × (VRMS
2)-1; K=(ISENSE － IOFFSET) × [IAC × (VEA － 0.7V)]-1; VEA(MAX.)=5.6V.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 13
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Typical Characteristics
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
20.0
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
IDD-ST(uA)
2.78
2.80
2.82
2.84
2.86
2.88
2.90
2.92
2.94
2.96
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
I
DD-OP
(uA)
Figure 8. IDD-ST vs. Temperatu re Figure 9. IDD-OP vs. Temp erature
10.8
10.9
11.0
11.1
11.2
11.3
11.4
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
VTH-ON (V
)
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
△VTH(V)
Figure 10. VTH-ON vs. Temperature Figure 11. VTH vs. Temperature
27.86
27.88
27.90
27.92
27.94
27.96
27.98
28.00
28.02
28.04
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
VDD-OVP(V)
64.2
64.3
64.4
64.5
64.6
64.7
64.8
64.9
65.0
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
FOSC-FAN4801/1S(kHz)
Figure 12. VDD-OVP vs. Temperatu re Figure 13. fOSC-FAN4801/1S vs. Temperature
128.4
128.6
128.8
129.0
129.2
129.4
129.6
129.8
130.0
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
F
OSC-FAN4802/2L
(kHz)
615
620
625
630
635
640
645
650
655
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
tPFCD(ns)
Figure 14. fOSC-FAN4802/2L vs. Temperature Figure 15. tPFCD vs. T emperature
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 14
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Typical Characteristics
7.475
7.480
7.485
7.490
7.495
7.500
7.505
7.510
7.515
7.520
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
VREF
(V)
0
1
2
3
4
5
6
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
△VVREF1(mV)
Figure 16. VVREF vs. Temperature Figure 17. VVREF1 vs. Temperature
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
△VVREF2(mV)
18.0
18.5
19.0
19.5
20.0
20.5
21.0
21.5
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
IREF-MAX.(mA)
Figure 18. VVREF2 vs. Temperature Figure 19. IREF-MAX. vs. Temperature
2.730
2.732
2.734
2.736
2.738
2.740
2.742
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
PFC-OVP
(V)
250.8
251.0
251.2
251.4
251.6
251.8
252.0
252.2
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
△V
PFC-OVP
(mV)
Figure 20. VPFC-OVP vs. Temperature Figure 21. VPFC-OVP vs. Temperature
2.388
2.390
2.392
2.394
2.396
2.398
2.400
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
VRD-FBPFC(V)
1.240
1.245
1.250
1.255
1.260
1.265
1.270
1.275
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
△VRD-FBPFC(V)
Figure 22. VRD-FBPFC vs. Temperatu re Figure 23. VRD-FBPFC vs. Temperatu re
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 15
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Typical Characteristics
2.488
2.490
2.492
2.494
2.496
2.498
2.500
2.502
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
ref
(V)
71
72
72
73
73
74
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
Gmv(umho)
Figure 24. Vref vs. Temperature Figure 25. GmV vs. Temperature
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
OFFSET
(mV)
78
80
82
84
86
88
90
92
94
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
Gm
I
(umho)
Figure 26. VOFFSET vs. Temperature Figure 27. GmI vs. Temperature
6.70
6.75
6.80
6.85
6.90
6.95
7.00
7.05
7.10
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
GAIN2
5.4
5.5
5.6
5.7
5.8
5.9
6.0
6.1
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
Rmul(kΩ)
Figure 28. GAIN2 vs. Temperature Figure 29. Rmul vs. Temperature
-1.1825
-1.1820
-1.1815
-1.1810
-1.1805
-1.1800
-1.1795
-1.1790
-1.1785
-1.1780
-1.1775
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
PFC-ILIMIT
(V)
250
255
260
265
270
275
280
285
290
295
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
△V
pk
(mV)
Figure 30. VPFC-ILIMIT vs. Temperature Figure 31. Vpk vs. Temperatu re
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 16
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Typical Characteristics
1.002
1.003
1.004
1.005
1.006
1.007
1.008
1.009
1.010
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
VPWM-ILIMIT (V)
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10.0
10.1
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
ISS(uA)
Figure 32. VPWM-ILIMIT vs. Temperature Figure 33. ISS vs. Temperature
1.038
1.039
1.040
1.041
1.042
1.043
1.044
1.045
1.046
1.047
1.048
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
VRMS-UVP(V)
862.0
862.5
863.0
863.5
864.0
864.5
865.0
865.5
866.0
866.5
867.0
867.5
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
△VRMS-UVP(mV)
Figure 34. VRMS-UVP vs. T emp eratu re Figure 35. VRMS-UVP vs. Temperature
1.931
1.932
1.933
1.934
1.935
1.936
1.937
1.938
1.939
1.940
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
RMS-L
(V)
2.435
2.436
2.437
2.438
2.439
2.440
2.441
2.442
2.443
2.444
2.445
2.446
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
RMS-H
(V)
Figure 36. VRMS-L vs. Temperature Figure 37. VRMS-H vs. Temperature
1.928
1.930
1.932
1.934
1.936
1.938
1.940
1.942
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
EA-L
(V)
2.424
2.426
2.428
2.430
2.432
2.434
2.436
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110
℃
125
℃
V
EA-H
(V)
Figure 38. VEA-L vs. Temperature Figure 39. VEA-H vs. Temperature
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 17
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Typical Characteristics
13.9
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.7
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
GATE-CLAMP-PFC
(V)
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
GATE-CLAMP-PWM
(V)
Figure 40. VGATE-CLAMP-PFC vs. Temperature Figure 41. VGATE-CLAMP-PWM vs. Temperatu re
95.88
95.90
95.92
95.94
95.96
95.98
96.00
96.02
96.04
96.06
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
D
PFC-MAX
(%)
49.50
49.55
49.60
49.65
49.70
49.75
49.80
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110
℃
125
℃
D
PWM-MAX
(%)
Figure 42. DPFC-MAX vs. Temperature Figure 43. DPWM-MAX vs. Temperatu re
19.4
19.6
19.8
20.0
20.2
20.4
20.6
20.8
21.0
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
I
tc
(uA)
1.430
1.435
1.440
1.445
1.450
1.455
1.460
-40℃-25℃-10℃5℃20℃35℃50℃65℃80℃95℃110℃125℃
V
PWM-LS
(V)
Figure 44. Itc vs. Temperature Figure 45. VPWM-LS vs. Temperature
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 18
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Functional Description
The FAN4800A/C and FAN4801/02/02L consist of an
average current controlled, continuous boost Power
Factor Correction (PFC) front-end and a synchronized
Pulse Width Modulator (PWM) back-end. The PWM can
be used in current or voltage mode. In voltage mode,
feed forward from the PFC output bus can be used to
improve the line regulation of PWM. In either mode, the
PWM stage uses conventional trailing-edge, duty-cycle
modulation. This propriety leading/trailing edge
modulation results in a higher usable PFC error
amplifier bandwidth and can significantly reduce the
size of the PFC DC bus capacitor.
The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor).
The PWM section of the FAN4800A, FAN4801/1S
operates at the same frequency as the PFC; and
FAN4800C, FAN4802/2L operates at double with PFC.
In addition to power factor correction, a number of
protection features are built into this series. They
include soft-start, PFC over-voltage protection, peak
current limiting, brownout protection, duty cycle limiting,
and under-voltage lockout (UVLO).
Gain Modulator
The gain modulator is the heart of the PFC, as the
circuit block controls the response of the current loop to
line voltage waveform and frequency, RMS line voltage,
and PFC output voltages. There are three inputs to the
gain modulator:
1. A current representing the instantaneous input
voltage (amplitude and wave shape) to the PFC. The
rectified AC input sine wave is converted to a
proportional current via a resistor and is fed into the
gain modulator at IAC. Sampling current in this way
minimizes ground noise, required in high-power,
switching-power conversion environments. The gain
modulator responds linearly to this current.
2. A voltage proportional to the long-term RMS AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at VRMS. The output of the gain
modulator is inversely proportional to VRMS (except
at unusually low values of VRMS, where special gain
contouring takes over to limit power dissipation of the
circuit components under brownout conditions).
3. The output of the voltage error amplifier, VEA. The
gain modulator responds linearly to variations in this
voltage.
The output of the gain modulator is a current signal, in
the form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual ground
(negative) input of the current error amplifier. In this way,
the gain modulator forms the reference for the current
error loop and ultimately controls the instantaneous
current draw of the PFC from the power line. The
general form of the output of the gain modulator is:
2
(0.7)
GAINMOD IAC VEA
IK
VRMS
(1)
Note that the output current of the gain modulator is
limited around 159μA and the maximum output voltage
of the gain modulator is limited to 159μA x 5.7K=0.906V.
This 0.906V also determines the maximum input power.
However, IGAINMOD cannot be measured directly from
ISENSE. ISENSE=IGAINMOD – IOFFSET and IOFFSET can only
be measured when VEA is less than 0.5V and IGAINMOD
is 0A. Typical IOFFSET is around 31μA ~ 48μA.
Selecting RAC for IAC Pin
The IAC pin is the input of the gain modulator and also
a current mirror input and requires current input.
Selecting a proper resistor RAC provides a good sine
wave current derived from the line voltage and helps
program the maximum input power and minimum input
line voltage. RAC=VIN peak x 56KΩ. For example, if the
minimum line voltage is 75VAC, the RAC=75 x 1.414 x
56KΩ=6MΩ.
Current Amplifier Error, IEA
The current error amplifier’s output controls the PFC
duty cycle to keep the average current through the
boost inductor a linear function of the line voltage. At
the inverting input to the current error amplifier, the
output current of the gain modulator is summed with a
current, which results in a negative voltage being
impressed upon the ISENSE pin.
The negative voltage on ISENSE represents the sum of
all currents flowing in the PFC circuit and is typically
derived from a current sense resistor in series with the
negative terminal of the input bridge rectifier.
The inverting input of the current error amplifier is a
virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC,
an increase in positive current from the gain modulator
causes the output stage to increase its duty cycle until
the voltage on ISENSE is adequately negative to cancel
this increased current. Similarly, if the gain modulator’s
output decreases, the output duty cycle decreases to
achieve a less negative voltage on the ISENSE pin.
PFC Cycle-By-Cycle Current Limiter
As well as being a part of the current feedback loop, the
ISENSE pin is a direct input to the cycle-by-cycle
current limiter for the PFC section. If the input voltage at
this pin is less than -1.15V, the output of the PFC is
disabled until the protection flip-flop is reset by the clock
pulse at the start of the next PFC power cycle.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 19
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
TriFault Detect™
To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the FAN4800A/C, FAN4801/02/02L
includes TriFault Detect. This feature monitors FBPFC
for certain PFC fault conditions.
In a feedback path failure, the output of the PFC could
exceed safe operating limits. With such a failure,
FBPFC exceeds its normal operating area. Should
FBPFC go too LOW, too HIGH, or OPEN, TriFault
Detect senses the error and terminates the PFC output
drive.
TriFault detect is an entirely internal circuit. It requires
no external components to serve its protective function.
PFC Over-Voltage Protection
In the FAN4800A/C, FAN4801/02/02L, the PFC OVP
comparator serves to protect the power circuit from
being subjected to excessive voltages if the load
changes suddenly. A resistor divider from the high-
voltage DC output of the PFC is fed to FBPFC. When
the voltage on FBPFC exceeds 2.75V, the PFC output
driver is shut down. The PWM section continues to
operate. The OVP comparator has 250mV of hysteresis
and the PFC does not restart until the voltage at FBPFC
drops below 2.50V. VDD OVP can also serve as a
redundant PFC OVP protection. VDD OVP threshold is
28V with 1V hysteresis.
Selecting PFC RSENSE
RSENSE is the sensing resistor of the PFC boost
converter. During the steady state, line input current x
RSENSE equals IGAINMOD x 5.7KΩ.
At full load, the average VEA needs to around 4.5V and
ripple on the VEA needs to be less than 400mV.
Choose the resistance of the sensing resistor:
4.5 0.7 5.7 2
25.60.7
IN
sense KIACGainV
RLine input Power (2)
where 5.6 is VEA maximum output.
PFC Soft-Start
PFC startup is controlled by VEA level. Before FBPFC
voltage reaches 2.4V, the VEA level is around 2.8V. At
90VAC, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage.
The FAN4800A/C, FAN4801/02 disables PFC as lower
AC input such that the VRMS is less than 1.05V. The
brownout voltage of FAN4802L is lower than
FAN4801/1S/2, such that the VRMS is less than 0.9V.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a
negative resistor because an increase in the input
voltage to the PWM causes a decrease in the input
current. This response dictates the proper
compensation of the two transconductance error
amplifiers. Figure 46 shows the types of compensation
networks most commonly used for the voltage and
current error amplifiers, along with their respective
return points. The current-loop compensation is
returned to VREF to produce a soft-start characteristic
on the PFC: As the reference voltage increases from
0V, it creates a differentiated voltage on IEA, which
prevents the PFC from immediately demanding a full
duty cycle on its boost converter. Complete design is
referred in application note AN-6078SC.
There is an RC filter between RSENSE and ISENSE pin.
There are two reasons to add a filter at the ISENSE pin:
1. Protection: During startup or inrush current
conditions, there is a large voltage across RSENSE,
which is the sensing resistor of the PFC boost
converter. It requires the ISENSE filter to attenuate
the energy.
2. To reduce L, the boost inductor: The ISENSE filter
also can reduce the boost inductor value since the
ISENSE filter behaves like an integrator before the
ISENSE pin, which is the input of the current error
amplifier, IEA.
The ISENSE filter is an RC filter. The resistor value of
the ISENSE filter is between 100Ω and 50Ω because
IOFFSET x RFILTER can generate a negative offset voltage
of IEA. Selecting an RFILTER equal to 50Ω keeps the
offset of the IEA less than 3mV. Design the pole of
ISENSE filter at fPFC/6, one sixth of the PFC switching
frequency, so the boost inductor can be reduced six
times without disturbing the stability. The capacitor of
the ISENSE filter, CFILTER, is approximately 100nF.
Figure 46. Compensation Network Connection for the
Voltage and Current Error Amplifiers
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 20
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Two-Level PFC Function
To improve the efficiency, the system can reduce PFC
switching loss at low line and light load by reducing the
PFC output voltage. The two-level PFC output of
FAN4801/02/02L can be programmable.
As Figure 47 shows, FAN4801/02/02L detect VEA pin
and VRMS pin to determine the system operates low
line and light load or not. At the second-level PFC, there
is a current of 20µA through RF2 from FBPFC pin. So
the second-level PFC output voltage can be calculated
as.
12 2
2
(2.5 20 )
FF F
F
RR
Output V uA R
R (3)
For example, if the second-level PFC output voltage is
expected as 300V and normal voltage is 387V,
according to the equation, RF2 is 28kΩ RF1 is 4.3MΩ.
The programmable range of second level PFC output
voltage is 340V ~ 300V.
Figure 47. Two-Level PFC Scheme
Oscillator (RT/CT)
The oscillator frequency is determined by the values of
RT and CT, which determine the ramp and off-time of
the oscillator output clock:
/
/
1
RT CT RT CT DEAD
ftt
(4)
The dead time of the oscillator is derived from the
following equation:
/
1
ln 3.8
RT CT T T VREF
tCR
VREF
(5)
at VREF=7.5V and tRT/CT=CT x RT x 0.56.
The dead time of the oscillator is determined using:
2.8 360
7.78
DEAD T T
V
tCC
mA
(6)
The dead time is so small (tRT/CT>>tDEAD) that the
operating frequency can typically be approximated by:
/
/
1
RT CT RT CT
ft
(7)
Pulse Width Modulator (PWM)
The operation of the PWM section is straightforward,
but there are several points that should be noted.
Foremost among these is the inherent synchronization
of PWM with the PFC section of the device, from which
it also derives its basic timing. The PWM is capable of
current-mode or voltage-mode operation. In current-
mode applications, the PWM ramp (RAMP) is usually
derived directly from a current sensing resistor or
current transformer in the primary of the output stage. It
is thereby representative of the current flowing in the
converter’s output stage. ILIMIT, which provides cycle-by-
cycle current limiting, is typically connected to RAMP in
such applications. For voltage-mode operation and
certain specialized applications, RAMP can be
connected to a separate RC timing network to generate
a voltage ramp against which FBPWM is compared.
Under these conditions, the use of voltage feed-forward
from the PFC bus can assist in line regulation accuracy
and response. As in current-mode operation, the ILIMIT
input is used for output stage over-current protection.
No voltage error amplifier is included in the PWM stage,
as this function is generally performed on the output
side of the PWM’s isolation boundary. To facilitate the
design of opto-coupler feedback circuitry, an offset has
been built into the PWM’s RAMP input that allows
FBPWM to command a 0% duty cycle for input voltages
below typical 1.5V.
PWM Cycle-By-Cycle Current Limiter
The ILIMIT pin is a direct input to the cycle-by-cycle
current limiter for the PWM section. Should the input
voltage at this pin ever exceed 1V, the output flip-flop is
reset by the clock pulse at the start of the next PWM
power cycle. When the ILIMIT triggers the cycle-by-cycle
bi-cycle current, it limits the PWM duty cycle mode and
the power dissipation is reduced during the dead-short
condition.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the
PFC and inhibits the PWM if the voltage on FBPFC is
less than its nominal 2.4V. Once the voltage reaches
2.4V, which corresponds to the PFC output capacitor
being charged to its rated boost voltage, the soft-start
begins.
PWM Soft-Start (SS)
PWM startup is controlled by selection of the external
capacitor at soft-start. A current source of 10µA
supplies the charging current for the capacitor and
startup of the PWM begins at 1.5V.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 21
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
PWM Control (RAMP)
When the PWM section is used in current mode, RAMP
is generally used as the sampling point for a voltage,
representing the current in the primary of the PWM’s
output transformer. The voltage is derived either from a
current sensing resistor or a current transformer. In
voltage mode, RAMP is the input for a ramp voltage
generated by a second set of timing components (RRAMP,
CRAMP) that have a minimum value of 0V and a peak
value of approximately 6V. In voltage mode, feed
forward from the PFC output bus is an excellent way to
derive the timing ramp for the PWM stage.
Generating VDD
After turning on the FAN4800A/C, FAN4801/02/02L at
11V, the operating voltage can vary from 9.3V to 28V.
The threshold voltage of the VDD OVP comparator is
28V and its hysteresis is 1V. When VDD reaches 28V,
OPFC is LOW, and the PWM section is not disturbed.
There are two ways to generate VDD: use auxiliary
power supply around 15V or use bootstrap winding to
self-bias the FAN4800A/C, FAN4801/02/02L system.
The bootstrap winding can be taped from the PFC boost
choke or the transformer of the DC-to-DC stage.
Leading/Trailing Modulation
Conventional PWM techniques employ trailing-edge
modulation, in which the switch turns on right after the
trailing edge of the system clock. The error amplifier
output is then compared with the modulating ramp up.
The effective duty cycle of the trailing edge modulation
is determined during the on-time of the switch.
In the case of leading-edge modulation, the switch is
turned off exactly at the leading edge of the system
clock. When the modulating ramp reaches the level of
the error amplifier output voltage, the switch is turned
on. The effective duty-cycle of the leading-edge
modulation is determined during off-time of the switch.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 22
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Physical Dimensions
16 9
81
NOTES: UNLESS OTHERWISE SPECIFIED
A THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
19.68
18.66
6.60
6.09
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
3.42
3.17
3.81
2.92
(0.40)
2.54
17.78
0.58
0.35
1.78
1.14
5.33 MAX
0.38 MIN 8.13
7.62
0.35
0.20
15
0
8.69
A
A
TOP VIEW
SIDE VIEW
Figure 48. 16-Pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the m ost recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 23
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
Physical Dimensions (Continued)
Figure 49. 16-Pin Small Outline Package (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the m ost recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN4800A/C, FAN4801/02/02L • Rev. 1.0.3 24
FAN4800A/C, FAN4801/02/02L — PFC/PWM Controller Combination
www.onsemi.com
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