1
®
FN8174.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9271
Single Supply/Low Power/256-Tap/SPI Bus
Single Digitally-Controlled (XDCP™)
Potentiometer
FEATURES
• 256 Resistor Taps
• SPI Serial Interface for wri te, read, and transfer
operations of the potentiometer
• Wiper Resistance, 100Ω typical @ VCC = 5V
• 16 Nonvolatile Data Registers
• Nonvolatile Storage of Multiple Wiper Positions
• P ower -on Recall. Loads Sa ved Wiper P osition on
Power-up.
• Standby Current < 3µA Max
•V
CC: 2.7V to 5.5V Operation
•50kΩ, 100kΩ versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 14-Lead TSSOP
• Low Power CMOS
• Pb-Free Plus Anneal Available (RoHS Compliant )
DESCRIPTION
The X9271 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS
integr ated circuit.
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and a four
nonvolatile Data Registers t hat can be directly written to
and read by the user. The contents of the WCR controls
the position of the wiper on the resistor arr a y though the
switches. Powerup recalls the contents of the default
data register (DR0) to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter ad justments , and signal processing .
FUNCTIONAL DIAGRAM
50kΩ and 100kΩ
RH
RL
RW
POT
VCC
VSS
SPI
Bus
Power-on Recall
Wiper Counter
Register (WCR)
Data Registers
16 Bytes
Interface
Bus
Interface
and Control
Address
Data
Status
Write
Read
Transfer
Inc/Dec
Control
256-taps
Data Sheet November 22, 2005
2FN8174.2
November 22, 2005
Ordering Information
PART NUMBER PART MARKING
VCC LIMITS
(V)
POTENTIOMETER
ORGANIZATION
(kΩ)
TEMPERATURE
RANGE (°C) PACKAGE
X9271UV14* X9271UV 5 ±10% 50 0 to +70 14 Ld TSSOP (4.4mm)
X9271UV14I* X9271UV I -40 to 85 14 Ld TSSOP (4.4mm)
X9271UV14IZ* (Note) X9271UV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
X9271UV14Z* (Note) X9271UV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)
X9271TV14* X9271TV 100 0 to +70 14 Ld TSSOP (4.4mm)
X9271TV14I* X9271TV I -40 to 85 14 Ld TSSOP (4.4mm)
X9271TV14IZ* (Note) X9271TV ZI -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
X9271TV14Z* (Note) X9271TV Z 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)
X9271UV14-2.7* X9271UV F 2.7 to 5.5 50 0 to +70 14 Ld TSSOP (4.4mm)
X9271UV14I-2.7* X9271UV G -40 to 85 14 Ld TSSOP (4.4mm)
X9271UV14IZ-2.7* (Note) X9271UV ZF -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
X9271UV14Z-2.7* (Note) X9271UV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)
X9271TV14-2.7* X9271TV F 100 0 to +70 14 Ld TSSOP (4.4mm)
X9271TV14I-2.7* X9271TV G -40 to 85 14 Ld TSSOP (4.4mm)
X9271TV14IZ-2.7* (Note) X9271TV ZG -40 to 85 14 Ld TSSOP (4.4mm) (Pb-free)
X9271TV14Z-2.7* (Note) X9271TV ZF 0 to +70 14 Ld TSSOP (4.4mm) (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
X9271
3FN8174.2
November 22, 2005
DETAILED FUNCTIONAL DIAGRAM
CIRCUIT LEVEL APPLICATIONS
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparat ors and detectors
• Control the volume in audio circuits
• Trim out the offset v oltage error in a v oltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatsto ne bridge circuits
• Control the gain, chara cteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the freq ue n cy an d du ty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Provide a control variable (I, V, or R) in feedback
circuits
SYSTEM LEVEL APPLICATIONS
• Adjust the contrast in LCD displays
• Control the power le vel of LED transmitt ers in
communication systems
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
• Control the gain in audio and home ente rtainment
systems
• Provide the variable DC bias for tuners in RF
wireless systems
• Set the operating points in temperature cont rol
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
R0R1
R2R3
WIPER
COUNTER
REGISTER
(WCR)
RH
RL
DATA
RW
INTERFACE
AND
CONTROL
CIRCUITRY
VCC
VSS
Bank 0
R0R1
R2R3
Bank 1
R0R1
R2R3
Bank 2
R0R1
R2R3
Bank 3
12 additional nonvolatile registers
3 Banks of 4 registers x 8-bits
CS
SCK
A0
SO
SI
HOLD
WP
A1
Control
256-taps
50kΩ and 100kΩ
Power-on Recall
X9271
4FN8174.2
November 22, 2005
PIN CONFIGURATION
PIN ASSIGNMENTS
VCC
RL
VSS
1
2
3
4
5
6
78
14
13
12
11
10
9
A0
RW
SCK
CS
TSSOP
RH
X9271
S0
NC
SI HOLD
WP
A1
TSSOP Symbol Function
1 SO Serial Data Output.
2 A0 Device Address.
3 NC No Connect.
4CS
Chip Select.
5 SCK Serial Clock.
6 SI Serial Data Input.
7V
SS System Ground.
8WP
Hardware Write Protect.
9 A1 Device Address.
10 HOLD Device select. Pause the serial bus.
11 RWWiper Terminal of the Potentiometer.
12 RH High Terminal of the Potentiometer.
13 RL Low Terminal of the Potentiometer.
14 VCC System Supply Voltage.
X9271
5FN8174.2
November 22, 2005
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the f alling edge of the serial clock.
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial cloc k.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9271.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is no t u se d, HO LD should be held HIGH at
all times. CMOS level input.
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the the 8-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9271.
CHIP SELECT (CS)
When CS is HIGH, the X9271 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9271, placing it
in the active power mode. It should be noted th at after
a power-up, a HIGH to LOW transition on CS is
required prior to th e start of an y oper ation.
Potentiometer Pins
RH, RL
The RH and RL pins are equivalent to the terminal
connections on a me chanical potent iometer.
RW
The wiper pin are equivalent to the wiper terminal of a
mechanica l potentiome ter.
Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS
pin is the system gr ound.
Other Pins
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
NO CONNECT.
No connect pins should be left floating. This pins are
used f or Inter sil man uf acturing and testing purposes.
X9271
6FN8174.2
November 22, 2005
PRINCIPLES OF OPERATION
Device Description
SERIAL INTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entir e operat ion.
The SO and SI pins can be connected together, since
they have three state outputs. This ca n help to reduce
system pin count.
ARRAY DESCRIPTION
The X9271 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(RW) output. Within each individual array only one
s witch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
s witches (See Table 1).
POWER-UP AND DOWN RECOMMENDATIONS.
There are no restrictions on the power-up or power-
down conditions of VCC and the voltages applied to
the potentiometer pins provided that VCC is always
more positive than or equal to VH, VL, and VW, i.e.,
VCC ≥ VH, VL, VW. The VCC ramp rate specification is
always in effect.
Figure 1. Detailed Potentiometer Block Diagram
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY REGISTER 0 REGISTER 1
REGISTER 2 REGISTER 3
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
INC/DEC
LOGIC
UP/DN
CLK
MODIFIED SCK
UP/DN
RH
RL
RW
8 8
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 00[H] THEN RW = RL
IF WCR = FF[H] THEN RW = RH
WIPER
(WCR)
BANK_0 Only
(DR0) (DR1)
(DR2) (DR3)
X9271
7FN8174.2
November 22, 2005
DEVICE DESCRIPTION
Wiper Counter Register (WCR)
The X9271 contains a Wiper Counter Register for the
DCP potentiometer. The Wiper Counter Register can
be envisioned as a 8-bit parallel and serial load
counter with its outputs decoded to select one of 256
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step
at a time by the Increment/ Decrement instruction.
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up .
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9271 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the R0 value into the WCR. The
DR0 va lue of Bank 0 is the def ault v alue .
Data Registers (DR3–DR0)
The potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms .
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
paramet ers or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data ( 0 ~255).
Status Regist er (SR)
This 1-bit Status Register is used to store the system
status.
WIP: Write In Progress status bit, read only.
– When WI P=1, indicates th at high-v oltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress
Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
Table 2. Data Register, DR (8-bit), DR[7:0]: Used to store wipe r positions or data (Nonvolat ile, NV).
Table 3. Status Register, SR (WIP is 1-bit)
WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
VVVVVVVV
(MSB) (LSB)
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
NV NV NV NV NV NV NV NV
MSB LSB
WIP
(LSB)
X9271
8FN8174.2
November 22, 2005
DEVICE DESCRIPTION
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9271; this is fixed as
0101[B] (refer to Tab le 4).
The A1 - A0 bits in the ID byte is the internal slave
address . The ph ysical de vice addre ss is defined b y the
state of the A1 - A0 input pins. The slave address is
externally specified by the user. The X9271 compares
the serial data stream with the address input state; a
successful compare of both ad dress bits is required f or
the X9271 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1 - A0 inputs
can be actively driven b y CMOS inpu t sig nals or ti ed to
VCC or VSS.
INSTRUCTION BYTE (I[3:0])
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[3 :0]) . The RB a nd RA bits po int t o one of th e
four Data Registers. P0 is the POT selection; since the
X9271 is single POT, the P0=0. The format is shown in
Table 5.
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registe rs orga niz ed int o four banks. Bank
0 is the def ault bank of registers. Only Bank 0 registers
can be used for data register to Wiper Counter
Register operations.
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
betwee n the Wiper Count er Registe r .
Register Selection (DR0 to DR3) Table
Register Bank Selection (Bank 0 to Bank 3) Table
Table 4. Identification Byte Format
RB RA Register
Selection Operations
0 0 0 Data Register Read and Write;
Wiper Counter Register
Operations
0 1 1 Data Register Read and Write;
Wiper Counter Register
Operations
1 0 2 Data Register Read and Write;
Wiper Counter Register
Operations
1 1 3 Data Register Read and Write;
Wiper Counter Register
Operations
P1 P0 Bank
Selection Operations
0 0 0 Data Register Read and Write;
Wiper Counter Register
Operations
0 1 1 Data Register Read and Write
Only
1 0 2 Data Register Read and Write
Only
1 1 3 Data Register Read and Write
Only
ID3 ID2 ID1 ID0 0 0 A1 A0
0101
(MSB) (LSB)
Device Type
Identifier Set to 0
for proper operation Internal
Slave Address
X9271
9FN8174.2
November 22, 2005
Table 5. Instruction Byte Format
DEVICE DESCRIPTION
Instructions
Five of the eight instructions are three bytes in length.
These instructions are:
–Read Wiper Counter Register – read the current
wiper position of the potentiometer;
–Write Wiper Counter Register – change current
wiper position of the potentiometer;
–Read Data Register – read the contents of the
selected Data Register;
–Write Data Register – write a new value to the
selected Data Register.
–Read Status - This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transf er from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique f ormat (See Figure 4).
Two instructions require a two-byte sequence to
complete (Figure 2). These instructions transfer data
between the host and the X9271; either between the
host and one of the data registers or directly between
the host and the Wiper Counter Register. These
instructions are:
–XFR Data Register to Wiper Counter Register –
This tran sfers the contents of one specified Data
Register to the associated Wiper Counter Register.
–XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
The final command is Increment/Decrement (Figure 5
and 6). It is different from the other commands,
because it’s length is indeterminate. Once the
command is issued, the master can clock the selected
wiper up and/or down in one resistor segment steps;
thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (tHIGH) while SI is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similar ly, for each SCK clock
pulse while SI is LOW, the selected wiper will move
one resistor segme nt to wards the RL terminal.
See Instruction format for more details.
Write in Process (WIP bit)
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a Write In Process bit
(WIP). The WIP bit is read with a Read Status
command.
I3 I2 I1 P0 RB RA P1 P0
(MSB) (LSB)
Instruction Opcode Register Selection Pot Selection (WCR Selection)
Set to P0=0 for potentiometer operations
P1 and P0 are used also for register Bank Selection
for SPI Register Write and Read operations
X9271
10 FN8174.2
November 22, 2005
Figure 2. Two-Byte Instruction Seque nce
Figure 3. Three-Byte Instruction Sequence (Write)
Figure 4. Three-Byte Instruction Sequence (Read)
ID3 ID2 ID1 ID0 0 A1 A0 I3 I2 I1 RB RA P0
SCK
SI
CS
0101
Device ID Internal Instruction
Opcode
Address Register
0
I0
0
P1
Address Pot/Bank
Address
0
0
These commands only valid when P1 = P0 = 0
0
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/Bank
Address
00
P1
WCR[7:0] valid only when P1 = P0 = 0;
or
Data Register Bit [7:0] for all values of P1 and P0
0101
A1 A0 I3 I2 I1 I0 RB RA P0
SCL
SI
D7 D6 D5 D4 D3 D2 D1 D0
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/Bank
Address
00
P1
WCR[7:0] valid only when P1 = P0 = 0;
S0
XXXXXXXX
Don’t Care
or
Data Register Bit [7:0] for all values of P1 and P0
X9271
11 FN8174.2
November 22, 2005
Figure 5. Increment/Decrement Instruction Sequenc e
Figure 6. Increment/Decr ement Timing Limits
Table 6. Instruction Set
Note: 1/0 = data is one or zero
0101
A1 A0 I3 I2 I1 I0 RA RB P0
SCL
SI
CS
00
ID3 ID2 ID1 ID0
Device ID Internal Instruction
Opcode
Address Register
Address Pot/Bank
Address
00
P1
0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
0
Instruction Instruction Set OperationI3 I2 I1 I0 RB RA P1P0
Read Wiper Counter
Register 100100 01/0Read the contents of the Wiper Counter
Register
Write Wiper Counter
Register 101000 01/0Write new value to the Wiper Counter
Register
Read Data Register 10111/01/01/01/0Read the contents of the Data Register
pointed to by P1 - P0 and RB - RA
Write Data Register 11001/01/01/01/0Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to
Wip er Counter Register 11011/01/00 0Transfer the contents of the Data Register
pointed to by RB - RA (Bank 0 only) to the
Wiper Counter Register
XFR Wiper Counter
Register to Data Register 11101/01/00 0Transfer the contents of the Wiper Counter
Re g i s te r to the Register pointed to by RB-RA
(Bank 0 only)
Increment/Decrement
Wiper Counter Register 001000 0 0Enable Increment/decrement of the Wiper
Counter Register
Read Status (WIP bit) 010100 0 1Read the status of the internal write cycle, by
checking the WIP bit.
SCK
SI
VW
INC/DEC CMD ISSUED
tWRID
VOLTAGE OUT
X9271
12 FN8174.2
November 22, 2005
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
Write Data Register (DR)
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses Wiper Position
(Sent by X9271 on SO) CS
Rising
Edge
010100A1A010010000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses Data Byte
(Sent by Host on SI) CS
Rising
Edge
010100A1A010100000
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses Data Byte
(Sent by X9271 on SO) CS
Rising
Edge
010100A1A01011RBRAP1 P0 D7D 6D5D4D3D2D1D0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses Data Byte
(Sent by Host on SI) CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 1 0 0A1A01 1 0 0RBRAP1 P0 D7D 6D5D4D3D2D1D0
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0 1 0 100A1A01110RB RA 0 0
X9271
13 FN8174.2
November 22, 2005
Transfer Data Register (D R) to Wiper Counter Register (WCR)
Increment/Decrement Wiper Counte r Register (WCR)
Read Status Regist er (SR)
Notes: (1) “A1 ~ A0”: stands for the de vice addresses sent by the master .
(2) WCRx refers to wiper position data in the Wiper Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LO W during active SCK phase (high).
(4) “X:”: Don’t Care.
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses CS
Rising
Edge
010100A1A01101RBRA00
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses Increment/Decrement
(Sent by Master on SDA) CS
Rising
Edge
0 1 0 1 0 0 A1 A0 0 0 1 0 X X 0 0 I/D I/D . . . . I/D I/D
CS
Falling
Edge
Device Type
Identifier Device
Addresses Instruction
Opcode DR/Bank
Addresses Data Byte
(Sent by X9271 on SO) CS
Rising
Edge
010100A1A0010100010000000 WIP
X9271
14 FN8174.2
November 22, 2005
ABSOLUTE MAXIMUM RATINGS
Temperature under bias.....................-65°C to +135°C
Storage temperature .........................-65°C to +150°C
Voltage on SCK an y address inp ut
with respect to VSS ................................. -1V to +7V
∆V = |(VH - VL)|.....................................................5.5V
Lead temperature (soldering, 10 seconds)........ 300°C
IW (10 seconds)..................................................±6mA
COMMENT
Stresses abo v e th ose listed under “Ab solute Maxim um
Ratings” may cause per m anen t dam age to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
aff ect de vice reliability.
ANALOG CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successiv e tap positions when used as a
potentiometer . It is a measure of the error in step size.
(3) MI = RT O T / 255 or (RH - RL) / 255, single pot
(4) During power-up VCC > VH, VL, and VW.
(5) n = 0, 1, 2, …,255; m =0, 1, 2, …., 254.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
RTOTAL End to End Resistance 100 kΩT version
RTOTAL End to End Resistance 50 kΩU version
End to End Resistance
Tolerance ±20 %
Power Rating 50 mW 25°C, each pot
IW Wiper Current ±3 mA
RWWiper Resistance 300 ΩIW = ± 3mA @ VCC = 3V
RWWiper Resistance 150 ΩIW = ± 3mA @ VCC = 5V
VTERM Voltage on any RH or RL Pin VSS VCC VV
SS = 0V
Noise -120 dBV/√Hz Ref: 1V
Resolution 0.4 %
Absolute Linearity(1) ±1 MI(3) Rw(n)(actual) - Rw(n)(expected)(5)
Relative Linearity(2) ±0.2 MI(3) Rw(n + 1) - [Rw(n) + MI](5)
Temperature Coefficient of
RTOTAL
±300 ppm/°C
Ratiometric Temp. Coefficient 20 ppm/°C
CH/CL/CWPotentiometer Capacitancies 10/10/25 pF See Macro model
RECOMMENDED OPERATING CONDITIONS
Temp Min. Max.
Commercial 0°C+70°C
Industrial -40°C+85°C
Device Supply Voltage (VCC)(4) Limits
X9271 5V ± 10%
X9271-2.7 2.7V to 5.5V
X9271
15 FN8174.2
November 22, 2005
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
A.C. TEST CONDITIONS
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (V CC-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Units
ICC1 VCC supply current
(active) 400 µAf
SCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC2 VCC supply current
(nonvolatile write) 15mAf
SCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ISB VCC current (standby) 3 µASCK = SI = V
SS, Addr. = VSS,
CS = VCC = 6V
ILI Input leakage current 10 µAV
IN = VSS to VCC
ILO Output leakage current 10 µAV
OUT = VSS to VCC
VIH Input HIGH voltage VCC x 0.7 VCC + 1 V
VIL Input LOW voltage -1 VCC x 0.3 V
VOL Output LOW voltage 0.4 V IOL = 3mA
VOH Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V
VOH Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V
Parameter Min. Units
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Test Max. Units Test Conditions
CIN/OUT(6) Input / Output capacitance (SI) 8 pF VOUT = 0V
COUT(6) Output capacitance (SO) 8 pF VOUT = 0V
CIN(6) Input capacitance (A0, CS, WP, HOLD, and
SCK) 6pFV
IN = 0V
Symbol Parameter Min. Max. Units
tr VCC(6) VCC Power-up rate 0.2 50 V/ms
tPUR(7) Power-up to initiation of read operation 1 ms
tPUW(7) Power-up to initiation of write operation 50 ms
Input Pulse Levels VCC x 0.1 to VCC x 0.9
Input rise and fall times 10ns
Input and output timing level VCC x 0.5
X9271
16 FN8174.2
November 22, 2005
EQUIVALENT A.C. LOAD CIRCUIT
AC TIMING
Symbol Parameter Min. Max. Units
fSCK SSI/SPI clock frequency 2.5 MHz
tCYC SSI/SPI clock cycle time 500 ns
tWH SSI/SPI clock high time 200 ns
tWL SSI/SPI clock low time 200 ns
tLEAD Lead time 250 ns
tLAG Lag time 250 ns
tSU SI, SCK, HOLD and CS input setup time 50 ns
tHSI, SCK, HOLD and CS input hold time 50 ns
tRI SI, SCK, HOLD and CS input rise time 2 µs
tFI SI, SCK, HOLD and CS input fall time 2 µs
tDIS SO output disable time 0 250 ns
tVSO output valid time 200 ns
tHO SO output hold time 0 ns
tRO SO output rise time 100 ns
tFO SO output fall time 100 ns
tHOLD HOLD time 400 ns
tHSU HOLD setup time 100 ns
tHH HOLD hold time 100 ns
tHZ HOLD low to output in high Z 100 ns
tLZ HOLD high to output in low Z 100 ns
TINoise suppression time constant at SI, SCK, HOLD and CS inputs 10 ns
tCS CS deselect time 2 µs
tWPASU WP, A0 setup time 0 ns
tWPAH WP, A0 hold time 0 ns
5V
1462Ω
100pF
SO pin RH
10pF
CLCL
RW
RTOTAL
CW
25pF 10pF
RL
SPICE Macromodel
2714Ω
3V
1382Ω
100pF
SO pin
1217Ω
X9271
17 FN8174.2
November 22, 2005
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
Symbol Parameter Typ. Max. Units
tWR High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Units
tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs
tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs
WAVEFORM INPUTS OUTPUTS
Must be
steady Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
X9271
18 FN8174.2
November 22, 2005
TIMING DIAGRAMS
Input Timing
Output Timing
Hold Timing
...
CS
SCK
SI
SO
MSB LSB
High Impedance
tLEAD
tH
tSU tFI
tCS
tLAG
tCYC
tWL
...
tRI
tWH
...
CS
SCK
SO
SI ADDR
MSB LSB
tDIS
tHO
tV
...
...
CS
SCK
SO
SI
HOLD
tHSU tHH
tLZ
tHZ
tHOLD
tRO tFO
X9271
19 FN8174.2
November 22, 2005
XDCP Timing (for All Load Instructions)
Write Protect and Device Address Pins Timing
...
CS
SCK
SI MSB LSB
VWx
tWRL
...
SO High Impedance
CS
WP
A0
A1
tWPASU tWPAH
(Any Instruction)
X9271
20 FN8174.2
November 22, 2005
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
Application Circuits
VR
RW
+VR
I
Three terminal P otentiometer;
Variable v oltage divider Two terminal Variable Resistor;
Variable current
Noninverting Amplifier Voltage Regulator
Offset Voltage Adjustment Comparator with Hysterisis
+
–
VSVO
R2
R1
VO = (1+R2/R1)VS
R1
R2
Iadj
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
VO (REG)VIN 317
+
–
VS
VO
R2
R1
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} V O(min)
100kΩ
10kΩ10kΩ
10kΩ
-12V+12V
TL072
+
–
VSVO
R2
R1
}
}
X9271
21 FN8174.2
November 22, 2005
Application Circuits (continued)
Attenuator Filter
Inverting Amplifier Equivalent L-R Circuit
+
–
VSVO
R3
R1
VO = G VS
-1/2 ≤ G ≤ +1/2 GO = 1 + R2/R1
fc = 1/(2πRC)
+
–
VS
VO
R2
R1
ZIN = R2 + s R 2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
+
–
VS
Function Generator
R2
R4R1 = R2 = R3 = R4 = 10kΩ
+
–
VS
R2
R1
R
C
}
}
VO = G VS
G = - R2/R1
R2
C1
R1
R3
ZIN
+
–R2
+
–
R1
}
}
RA
RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
C
VO
X9271
22
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8174.2
November 22, 2005
PACKAGING INFORMATION
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLI M ETERS)
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
See Detail “A”
.031 (. 80)
.041 (1.05)
.169 (4.3)
.177 (4.5) .252 (6.4) BSC
.025 (.65) BSC
.193 (4.9)
.200 (5.1)
.002 (. 05)
.006 (. 15)
.047 (1.20)
.0075 (.19)
.0118 (.30)
0° - 8 °
.010 (. 25)
.019 (.50)
.029 (.75)
Gage Plane
Seating Plane
DetailA (20X)
X9271
