HY5DU283222BFP-33 - SK Hynix

This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.0 / Feb. 2005 1

HY5DU283222BF(P)

128M(4Mx32) GDDR SDRAM

HY5DU283222BF(P)

Rev. 1.0 / Feb. 2005 2

1HY5DU283222BF(P)

Revision History

No. History Draft Date Remark

0.1 1) Defined Target Spec. Jun. 2004

0.2 1) Added 200MH z speed bin Jun. 2004

0.3 1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/

250Mhz speed bin Sep. 2004

0.4 1) Changed IDD & 500Mhz speed bin insert,

2) Changed tRCDWR, tWR at 450Mhz speed bin Oct. 2004

1.0 1) Changed IDD Spec.

2) Changed CAS Latency to 4 clock from 5 clock at 350MHz speed bin Feb. 2005

Rev. 1.0 / Feb. 2005 3

1HY5DU283222BF(P)

DESCRIPTION

The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data R ate(DDR) S ynchronous DR AM, ideally suited f or the

point-to-point applications which requires high bandwidth.

The Hynix 4Mx32 DDR S DRAMs offer fully synchronous operations referenced to both rising and falling edges of the

clock. While all addresses and contro l inputs ar e latched on th e rising edges of the CK (falling edg es of the /CK), Data,

Data strobes and W rite data mas ks inputs ar e samp led on both rising and falling edges of it. The data paths are inter-

nally pipelined and 2-bit prefetched to achieve very high bandwidth. All inp ut and output voltage lev els are compatible

with SSTL_2.

FEATURES

•The Hynix HY5DU283222BF(P) guarantee until

200MHz speed at DLL_off condition

•2.5V V

DD and VDDQ wide range max power supply

supports

• All inputs and outputs are compatible with SSTL_2

interface

• 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous - data transaction aligned to

bidirectional data strobe (DQS0 ~ DQS3)

• Data outputs on DQS edges when read (edged DQ)

Data inputs on DQS centers when write (c entered

DQ)

• Data(DQ) and W rite mask s(DM) latched on the both

rising and falling edges of the data strobe

• All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

• Write mask byte controls by DM (DM0 ~ DM3)

• Programmable /CAS Latency 5 / 4 / 3 supported

• Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

• Internal 4 bank operations with single pulsed / R AS

• tRAS Lock-Out function supported

• Auto refresh and self refresh supported

• 4096 refresh cycles / 32ms

• Half strength and Matched Impedance driver option

controlled by EMRS

ORDERING INFORMATION

Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.

We'll add "P" character after "F" for Lead free product.

For example, the part number of 300MHz Lead free product is HY5DU283222BFP-33.

Part No. Power Supply Clock

Frequency Max Data Rate interface Package

HY5DU283222BF(P)-2

VDD/ VDDQ = 2.5V

500MHz 1000Mbps/pin

SSTL_2 12mm x 12mm

144Ball FBGA

HY5DU283222BF(P)-22 450MHz 900Mbps/pin

HY5DU283222BF(P)-25 400MHz 800Mbps/pin

HY5DU283222BF(P)-28 350MHz 700Mbps/pin

HY5DU283222BF(P)-33 300MHz 600Mbps/pin

HY5DU283222BF(P)-36 275MHz 550Mbps/pin

HY5DU283222BF(P)-4 250MHz 500Mbps/pin

HY5DU283222BF(P)-5 200MHz 400Mbps/pin

Rev. 1.0 / Feb. 2005 4

1HY5DU283222BF(P)

PIN CONFIGURATION (Top View)

ROW and COLUMN ADDRESS TABLE

Items 4Mx32

Organization 1M x 32 x 4banks

Row Address A0 ~ A11

Column Address A0 ~ A7

Bank Address BA0, BA1

Auto Precharge Flag A8

Refresh 4K

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Rev. 1.0 / Feb. 2005 5

1HY5DU283222BF(P)

PIN DESCRIPTION

PIN TYPE DESCRIPTION

CK, /CK Input Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossi ng ).

CKE Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates in tern al cl ock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for ou tput disab le. CKE

must be maintained high throughout READ and WRITE accesses. Input buff ers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

/CS Input Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the co mmand code.

BA0, BA1 Input Bank Address In puts : BA0 and BA1 def ine to whic h bank an ACTIVE, R ead, W rit e or PR E-

CHARGE command is being applied.

A0 ~ A11 Input

Address Input s: Provid e the row ad dress f or ACTIVE co mmands, and the colu mn address

and AUT O PR ECHARGE bit f o r READ/WRITE comman ds, to select one lo ca tion ou t of the

memory array in the respective bank. A8 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mod e register is loaded durin g the MODE REGISTER SET command

(MRS or EMRS).

/RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

DM0 ~ DM3 Input

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE acces s. DM is sam-

pled on both edges of D QS. Although DM pi ns are input onl y, the DM loading matches the

DQ and DQS loading. DM0 c o rres po nd s to the data on DQ0-Q7; DM1 corres po nds t o t h e

data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the

data on DQ24-Q31.

D Q S 0 ~ D Q S 3 I / O

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. DQS0 corresponds to the data on

DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on

DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31

DQ0 ~ DQ31 I/O Data input / output pin : Data Bus

VDD/VSS Supply Power supply for internal circuits and input buffers.

VDDQ/VSSQ Supply Power supply for output buffers for noise immunity.

VREF Supply Reference voltage for inputs for SSTL interface.

NC NC No connection.

Rev. 1.0 / Feb. 2005 6

1HY5DU283222BF(P)

FUNCTIONAL BLOCK DIAGRAM

4Banks x 1Mbit x 32 I/O Double Data Rate Synchronous DRAM

Command

Decoder

CLK

/CLK

CKE

/CS

/RAS

/CAS

/WE

DM(0~3)

Address

Buffer

A0-11

Bank

Control 1Mx32/Bank0

Column Decoder

Column Address

Counter

Sense AMP

2-bit Prefetch Unit

1Mx32 /Bank1

1Mx32 /Bank2

1Mx32 /Bank3

Mode

Register Row

Decoder

Input Buffer Output Buffer

Data Strobe

Transmitter

Data Strobe

Receiver

DQS(0~3)

DS

Write Data Register

2-bit Prefetch Unit DS

DQ[0:31]

64 32

32

64

BA0,BA1

DLL

Block

CLK_DLL

CLK,

/CLK

Mode

Register

Rev. 1.0 / Feb. 2005 7

1HY5DU283222BF(P)

SIMPLIFIED COMMAND TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE ADDR A8/

AP BA Note

Extended Mode Register SetH XLLLL OP code 1,2

Mode Register Set H XLLLL OP code 1,2

Device Desele ct HX

HXXX X1

No Operation LHHH

Bank Active H X L L H H RA V 1

Read H X LHLHCA

LV1

Read with Autoprecharge H1,3

Write HXLHLLCA

LV1

Write with Autoprecharge H1,4

Precharge All Banks HXLLHLX

HX1,5

Precharge selected Bank LV1

Read Burst Stop H X L H H L X 1

Auto Refresh H HLLLH X 1

Self Refresh

EntryH LLLLH

X

1

Exit L H HXXX 1

LHHH

Precharge Power

Down Mode

Entry H L HXXX

X

1

LHHH 1

Exit L H HXXX 1

LHHH 1

Active Power

Down Mode Entry H L HXXX

X

1

LVVV 1

Exit L H X 1

Note :

1. DM(0~3) states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), th en th ere will be no command presented

to activated bank until CK(n+BL/2+ tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+ tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=V alid Data Input, OP Code=Operand Code, NOP=No Operation )

Rev. 1.0 / Feb. 2005 8

1HY5DU283222BF(P)

WRITE MASK TRUTH TABLE

Function CKEn-1 CKEn /CS, /RAS,

/CAS, /WE DM(0~3) ADDR A8/

AP BA Note

Data Write H X X L X 1,2

Data-In Mask H X X H X 1,2

Note :

1. Write Mask command masks burst write data with reference to DQS(0~3) and it is not related with read data.

2. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23;

DM3 corresponds to the data on DQ24-Q31.

Rev. 1.0 / Feb. 2005 9

1HY5DU283222BF(P)

OPERATION COMMAND TRUTH TABLE - I

Current

State /CS /RAS /CAS /WE Address Command Action

IDLE

HXXX X DSEL NOP or power down3

LHHH X NOP NOP or power down3

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4

L L H H BA, RA ACT Row Activ ation

LLHLBA, AP PRE/PALL NOP

LLLH X AREF/SREF Auto Refresh or Self Refresh5

L L L L OPCODE MRS Mode Register Set

ROW

ACTIVE

HXXX X DSEL NOP

LHHH X NOP NOP

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP Begin read : optional AP6

L H L L BA, CA, AP WRITE/WRITEAP Begin write : optional AP6

LLHHBA, RA ACT ILLEGAL4

LLHLBA, AP PRE/PALL Precharge7

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

READ

H X X X X DSEL Continue burst t o end

L H H H X NOP Continue burst to end

L H H L X BST Terminate burst

L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA, RA ACT ILLEGAL4

L L H L BA, AP PRE/P A LL Term burst, precharg e

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

H X X X X DSEL Continue burst t o end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8

L H L L BA, CA, AP WRITE/WRITEAP Term burst, new write:optional AP

Rev. 1.0 / Feb. 2005 10

1HY5DU283222BF(P)

OPERATION COMMAND TRUTH TABLE - II

Current

State /CS /RAS /CAS /WE Address Command Action

WRITE

LLHHBA, RA ACT ILLEGAL4

L L H L BA, AP PRE/P A LL Term burst, precharg e

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

READ

WITH

AUTOPRE-

CHARGE

H X X X X DSEL Continue burst t o end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10

LLHHBA, RA ACT ILLEGAL4,10

LLHLBA, AP PRE/PALL ILLEGAL4,10

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

AUTOPRE-

CHARGE

H X X X X DSEL Continue burst t o end

L H H H X NOP Continue burst to end

LHHL X BST ILLEGAL

L H L H BA, CA, AP READ/READAP ILLEGAL10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10

LLHHBA, RA ACT ILLEGAL4,10

LLHLBA, AP PRE/PALL ILLEGAL4,10

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

PRE-

CHARGE

H X X X X DSEL NOP-Enter IDLE after tRP

L H H H X NOP NOP-Enter IDLE after tRP

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10

LLHHBA, RA ACT ILLEGAL4,10

L L H L BA, AP PRE/PALL NOP-Enter IDLE after tRP

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

Rev. 1.0 / Feb. 2005 11

1HY5DU283222BF(P)

OPERATION COMMAND TRUTH TABLE - III

Current

State /CS /RAS /CAS /WE Address Command Action

ROW

ACTIVATING

H X X X X DSEL NOP - Enter ROW ACT after tRCD

L H H H X NOP NOP - Enter ROW ACT after tRCD

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10

LLHHBA, RA ACT ILLEGAL4,9,10

LLHLBA, AP PRE/PALL ILLEGAL4,10

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

RECOVERING

H X X X X DSEL NOP - Enter ROW ACT after tWR

L H H H X NOP NOP - Enter ROW ACT after tWR

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL

LLHHBA, RA ACT ILLEGAL4,10

LLHLBA, AP PRE/PALL ILLEGAL4,11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

WRITE

RECOVERING

WITH

AUTOPRE-

CHARGE

H X X X X DSEL NOP - Enter precharge after tDPL

L H H H X NOP NOP - Enter prechar ge after tDPL

LHHL X BST ILLEGAL4

L H L H BA, CA, AP READ/READAP ILLEGAL4,8,10

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10

LLHHBA, RA ACT ILLEGAL4,10

LLHLBA, AP PRE/PALL ILLEGAL4,11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

REFRESHING

H X X X X DSEL NOP - Enter IDLE after tRC

L H H H X NOP NOP - Enter IDLE after tRC

LHHL X BST ILLEGAL11

L H L H BA, CA, AP READ/READAP ILLEGAL11

Rev. 1.0 / Feb. 2005 12

1HY5DU283222BF(P)

OPERATION COMMAND TRUTH TABLE - IV

Note :

1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,

BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.

2. All entries assum e that CKE was active(high level) during the preceding clock cycle.

3. If both banks are idle and CKE is inactive(low le vel), then in power down mode.

4. Illegal to bank in spec ifi e d stat e. Fu nction may be legal in the bank indicated by Bank Address(BA) depending on the state of

that bank.

5. If both banks are idle and CKE is inactive(low le vel), then self refresh mode .

6. Illegal if tRCD is not met.

7. Illegal if tRAS is not met.

8. Must satisfy bus contention, bus turn around, and / or writ e recovery requirements.

9. Illegal if tRRD is not met.

10. Illegal for single bank, but legal for other banks in multi-bank devices.

11. Illegal for all banks.

Current

State /CS /RAS /CAS /WE Address Command Action

WRITE

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL11

LLHHBA, RA ACT ILLEGAL11

LLHLBA, AP PRE/PALL ILLEGAL11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

MODE

REGISTER

ACCESSING

H X X X X DSEL NOP - Enter IDLE after tMRD

L H H H X NOP NOP - Enter IDLE after tMRD

LHHL X BST ILLEGAL11

L H L H BA, CA, AP READ/READAP ILLEGAL11

L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL11

LLHHBA, RA ACT ILLEGAL11

LLHLBA, AP PRE/PALL ILLEGAL11

LLLH X AREF/SREF ILLEGAL11

LLLLOPCODE MRS ILLEGAL11

Rev. 1.0 / Feb. 2005 13

1HY5DU283222BF(P)

CKE FUNCTION TRUTH TABLE

Note :

When CKE=L, all DQ and DQS(0~3) must be in Hi-Z state.

1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.

2. All command can be stored after 2 clocks from low to high transition of CKE.

3. Illegal if CK is suspended or stopped during the power down mode.

4. Self refresh can be entered only from the all banks idle state.

5. Disabling CK may cause malfunction of any bank which is in active state.

Current

State CKEn-

1CKEn /CS /RAS /CAS /WE /ADD Action

SELF

REFRESH1

HXXXXXX INVALID

L H H X X X X Exit self refresh, enter idle after tSREX

L H L H H H X Exit self refresh, enter idle after tSR E X

LHLHHLX ILLEGAL

LHLHLXX ILLEGAL

LHLLXXX ILLEGAL

L LXXXXX NOP, continue self refresh

POWER

DOWN2

HXXXXXX INVALID

L H H X X X X Exit power down, enter idle

L H L H H H X Exit power down, enter idle

LHLHHLX ILLEGAL

LHLHLXX ILLEGAL

LHLLXXX ILLEGAL

L L X X X X X NOP, continue power down mode

ALL BANKS

IDLE4

H H X X X X X See operation command truth table

HLLLLHX Enter self refresh

H L H X X X X Exit power down

H L L H H H X Exit power down

HLLHHLX ILLEGAL

HLLHLXX ILLEGAL

HLLLHXX ILLEGAL

HLLLLLX ILLEGAL

L LXXXXX NOP

ANY STATE

OTHER

THAN

ABOVE

H H X X X X X See operation command truth table

HLXXXXX ILLEGAL5

LHXXXXX INVALID

L LXXXXX INVALID

Rev. 1.0 / Feb. 2005 14

1HY5DU283222BF(P)

SIMPLIFIED STATE DIAGRAM

MRS SREF

SREX

PDEN

PDEX

ACT

AREF

PDEX

PDEN

BST

READWRITE

WRITE

WRITEAP

READ

READAP READAP

PRE(PALL)

Command Input

Automatic Sequence

IDLE

AUTO

REFRESH

PRE-

CHARGE

POWER-UP

POWER APPLIED

MODE

REGISTER

SET

POWER

DOWN

WRITE

WITH

AUTOPRE-

CHARGE

POWER

DOWN

WRITE

READ

WITH

AUTOPRE-

CHARGE

BANK

ACTIVE

READ

SELF

REFRESH

Rev. 1.0 / Feb. 2005 15

1HY5DU283222BF(P)

POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those

specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is

applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS

LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,

where they will remain until driven in normal operation (by a read access). After all power supply and reference volt-

ages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable com-

mand.

Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be

brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED

MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE

REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating

parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-

ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command

for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the

DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-

MOS low state. (All the other input pins may be undefined.

No power sequencing is specifi ed during power up or power down given the following cirteria :

• VDD and VDDQ are driven from a single power converter output.

• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).

• VREF tracks VDDQ/2.

• A minimum resistance of 42 ohms (2 2 ohm series r esistor + 22 ohm parallel resistor - 5% tolerance) limits the

input current from the VTT supply into any pin.

If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must

be adhered to during power up :

2. Start clock and maintain stable clock for a minimum of 200usec.

3. After stable power and clock, apply NOP condition and take CKE high.

4. Issue Extended Mode Register Set (EMRS) to enable DLL.

5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200

cycles of clock are required for locking DLL)

6. Issue Precharge commands for all banks of the device.

7. Issue 2 or more Auto Refresh commands.

8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.

Voltage description Sequencing Voltage relationship to avoid latch-up

VDDQ After or with VDD < VDD + 0.3V

VTT After or with VDDQ < VDDQ + 0.3V

VREF After or with VDDQ < VDDQ + 0.3V

Rev. 1.0 / Feb. 2005 16

1HY5DU283222BF(P)

Power-Up Sequence

CODE

CODE CODE CODE

CODE

CODE CODE CODE

CODE

CODE CODE

CODE

NOP PRE MRS

EMRS PRE

NOP MRS

AREF ACT RD

VDD

VDDQ

VTT

VREF

/CLK

CLK

CKE

CMD

DM

ADDR

A10

BA0, BA1

DQS

DQ'S

LVCMOS Low Lev el

tIS tIH

tVTD

T=200usec tRP tMRD tRP tRFC tMRD

tXSRD*

READ

Non-Read

Command

Power UP

VDD and CK stable Precharge All EMRS Set MRS Set

Reset DLL

(with A8=H)

Precharge All 2 or more

Auto Refresh

MRS Set

(wit h A 8=L)

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

tMRD

Rev. 1.0 / Feb. 2005 17

1HY5DU283222BF(P)

MODE REGISTER SET (MRS)

The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,

burst type, test mode, DLL reset. The mode register is progr am via MRS command . This command is issued by the low

signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state an d CKE

must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write

the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is

determined, the information will be held until resetted by another MRS command.

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 RFU DR TM CAS Latency BT Burst Length

A2 A1 A0 Burst Length

Sequential Interleave

0 0 0 Reserved Reserved

001 2 2

010 4 4

011 8 8

1 0 0 Reserved Reserved

1 0 1 Reserved Reserved

1 1 0 Reserved Reserved

1 1 1 Reserved Reserved

A3 Burst Type

0 Sequential

1 Interleave

A6 A5 A4 CAS Latency

000 Reserved

001 Reserved

010 Reserved

011 3

100 4

101 5

110 Reserved

111 Reserved

A7 Test Mode

0Normal

1Vendor

test mode

A8 DLL Reset

0No

1Yes

BA0 MRS Type

0MRS

1EMRS

Rev. 1.0 / Feb. 2005 18

1HY5DU283222BF(P)

BURST DEFINITION

BURST LENGTH & TYPE

Read and write accesses to th e DDR SD RAM are bu rst orien ted, wi th the burst length being programmable. The burst

length determines the maximum number of column locations that can be accessed for a given Read or Write com-

mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All

accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is

reached. The block is uniquely selected by A1- Ai when the burst length is se t to two , by A2- Ai when the burst length is

set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column addr ess bit f or a

given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within

the block. The programmed burst length applies to both Read and Write bursts.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the

burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the

burst type and the starting column address, as shown in Burst Definitionon Table

Burst Length Starting Address (A2,A1,A0) Sequential Interleave

2XX0 0, 1 0, 1

XX1 1, 0 1, 0

4

X00 0, 1, 2, 3 0, 1, 2, 3

X01 1, 2, 3, 0 1, 0, 3, 2

X10 2, 3, 0, 1 2, 3, 0, 1

X11 3, 0, 1, 2 3, 2, 1, 0

8

000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7

001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6

010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5

011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4

100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3

101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2

110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1

111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0

Rev. 1.0 / Feb. 2005 19

1HY5DU283222BF(P)

CAS LATENCY

The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the

availability of the first burst of output data. The latency can be programmed 3 / 4 / 5 clocks.

If a Read comma nd is registered at clock ed ge n, and the latency is m clocks, the data is av aila ble nominally coinciden t

with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled f or normal oper ation. DLL enable is requ ired during pow er up init ializat ion, an d upon ret urn-

ing to normal operation after having disabled the DLL fo r the purpose of debug or evaluation. The DLL is automatically

disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any

time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally

applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

This device supports both Half strength driver and Matched imped ance driver, intended for lighter load and/or point-to-

point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2,

Class II, and Matched impedance driver, about 30% of Full drive strength.

Rev. 1.0 / Feb. 2005 20

1HY5DU283222BF(P)

EXTENDED MODE REGISTER SET (EMRS)

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-

tions include DLL enable/disable, output driver strength se lection(optional). These f unctions are contr olled via the bits

shown below. The Extended Mode Register is pr ogrammed via the Mode Register Set command ( BA0=1 an d BA1=0)

and will retain the stored information until it is programmed again or the device loses power.

The Extended Mode Register mus t be loaded when all banks are idle and no bursts are in progress, and the controller

must wait the specified time before initiating any subsequent operation. Violating either of these requirements will

result in unspecified operation.

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 1 RFU* DS RFU* DS DS DLL

A0 DLL enable

0Enable

1Diable

BA0 MRS Type

0MRS

1EMRS

A6 A1 Output Driver Impedance Control

00 Full

0 1 Half

10 RFU*

11 Weak

* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.

Rev. 1.0 / Feb. 2005 21

1HY5DU283222BF(P)

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with ≤ 5ns of duration.

3. VREF is expected to be equal to 0.5 *VDDQ of the transmitting device, and to track variations in the DC level of the same.

Peak to peak noise on VREF may not exceed ± 2% of the DC value.

DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note : 1. VIN = 0 to 3.6V, All other pins a re no t tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V

Parameter Symbol Rating Unit

Ambient Temperature TA0 ~ 70 oC

Storage Temperature TSTG - 55 ~ 125 oC

Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V

Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V

Output Short Circuit Current IOS 50 mA

Power Dissipation PD2W

Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 oC ⋅ sec

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage VDD 2.375 2.5 2.7 V 1

Power Supply Voltage VDDQ 2.375 2.5 2.7 V 1

Input High Voltage VIH VREF + 0.15 - V DDQ + 0.3 V

Input Low Voltage VIL -0.3 - VREF - 0.15 V 2

Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V

Reference Voltage VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V3

Parameter Symbol Min. Max Unit Note

Input Leakage Current ILI -2 2 uA 1

Output Leakage Current ILO -5 5 uA 2

Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA

Output Low Voltage VOL -VTT - 0.76 V IOL = +15.2mA

Rev. 1.0 / Feb. 2005 22

1HY5DU283222BF(P)

DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note :

1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.

Parameter Sym

bol Test Condition

Speed

Unit Note

222 25 28 33 36 4 5

Operating Current IDD0

One bank; Active - Precharge;

tRC=tRC(min); tCK=tCK(min);

DQ,DM and DQS inputs

changing twice per clock cycle;

address and control inputs

changing once per clock cycle

350 320 290 260 240 230 220 210 mA 1

Operating Current IDD1 Burst length=2, One bank active

tRC ≥ tRC(min), IOL=0mA 360 330 300 270 250 240 230 220 mA 1

Precharge Standby

Current in Power

Down Mode IDD2P CKE ≤ VIL(max), tCK=min 90 70 50 50 50 50 50 50 mA

Precharge Standby

Current in Non Power

Down Mode IDD2N CKE ≥ VIH(min), /CS ≥ VIH(min),

tCK = min, Input signals are

changed one time during 2clks 310 280 250 220 200 190 180 180 mA

Active Standby Cur-

rent in Power Down

Mode IDD3P CKE ≤ VIL(max), tCK=min 90 70 50 50 50 50 50 50 mA

Active Standby Cur-

rent in Non Power

Down Mode IDD3N CKE ≥ VIH(min), /CS ≥ VIH(min),

tCK=min, Input signals are

changed one time during 2clks 360 330 300 270 250 240 230 220 mA

Burst Mode Operating

Current IDD4 tCK ≥ tCK(min), IOL=0 m A

All banks active 700 650 600 550 500 450 450 400 mA 1

Auto Refresh Current IDD5 tRC ≥ tRFC(min),

All banks active 400 400 350 350 300 300 270 270 mA 1,2

Self Refresh Current IDD6 CKE ≤ 0.2V 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 mA

Operating Current -

Four Bank Operation IDD7 Four bank interleaving with

BL=4, Refer to the following

page for detailed test condition 900 800 700 600 500 400 400 400 mA

Rev. 1.0 / Feb. 2005 23

1HY5DU283222BF(P)

AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note :

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting devic e and must track variations in the DC level of the sam e.

AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage refe renced to VSS = 0V)

Parameter Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ , DQS and DM signals VIH(AC) VREF + 0.35 V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.35 V

Input Differential Voltage, CK and /CK inpu ts VID(AC) 0.7 VDDQ + 0.6 V 1

Input Cross in g Point Voltage, CK and /CK inpu ts VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2

Parameter Value Unit

Reference Voltage VDDQ x 0.5 V

Termination Voltage VDDQ x 0.5 V

AC Input High Level Voltage (VIH, min) VREF + 0.35 V

AC Input Low Level Voltage (VIL, max) VREF - 0.35 V

Input Timing Measurement Reference Level Voltage VREF V

Output Timing Meas urement Re ference Le vel Voltage VTT V

Input Signal maximum peak swing 1.5 V

Input minimum Signal Slew Rate 1 V/ns

Termination Resistor (RT)50Ω

Series Resistor (RS)25Ω

Output Load Capacitance for Access Time Measurement (CL)30 pF

Rev. 1.0 / Feb. 2005 24

1HY5DU283222BF(P)

AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)

Parameter Symbol 222 25 28 Unit Note

Min Max Min Max Min Max Min Max

Row Cycle Ti me tRC 23-22-19-17-

CK

Auto Re fresh Row Cycl e Time tRFC 25-24-21-19-

CK

Row A ctive Ti me tRAS 15 100K 14 100K 12 100K 11 100K CK

Row Addres s to Column Addr ess Dela y fo r

Read tRCDRD 8-7-6-6-

CK

Row Addres s to Column Addr ess Dela y fo r

Write tRCDWR 5-4-3-3-

CK

Row Active to Row Active Delay tRRD 5-4-4-4-

CK

Column Address to Column Address Delay tCCD 1-1-1-1-

CK

Row Precharge Time tRP 8-7-6-6-

CK

Write Recovery Time tWR 5-4-3-3-

CK

Last Data-In to Read Command tDRL 3-2-2-2-

CK

Auto Precharge Write Recovery +

Precharge Time tDAL 13 - 11 - 9 - 9 - CK

System Clock Cycle Time CL=5 tCK 2 10 2.2 10 2.5 10 - - ns

CL=4 tCK ------2.810

ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK

Data-Out edge to Clock edge Skew tAC -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.6 0.6 ns

DQS-Out edge to Clock edge Skew t DQSCK -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.6 0.6 ns

DQS-Out edge to Data-Out edge Skew tDQSQ - 0.35 - 0.35 - 0.35 - 0.35 ns

Data-Out hold time from DQS tQH tHPmin

-tQHS -tHPmin

-tQHS -ns 1,6

Clock Half Period tHP tCH/L

min -tCH/L

min -ns 1,5

Data Hold Skew Factor tQHS - 0.35 - 0.35 - 0.35 - 0.35 ns 6

Input Se tup Time tIS 0.6 - 0.75 - 0.75 - 0.75 - ns 2

Input Hold Time tIH 0.6 - 0.75 - 0.75 - 0.75 - ns 2

Write DQS High Level Width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK

Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK

Clock to First R ising edge of DQS -In tDQSS 0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 CK

Data-In Setup Time to DQ S-In (DQ & DM ) tDS 0.35 - 0.35 - 0.35 - 0.35 - ns 3

Rev. 1.0 / Feb. 2005 25

1HY5DU283222BF(P)

Note :

1. This calculation accoun ts for tDQSQ(max), the pulse width dist ort ion of on-chip circuit and ji tter.

2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

3. Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).

4. Minimum of 200 cycles of stable input clocks afte r Self Refres h Exi t command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDR A M.

5. Min (tCL, tCH) refe rs to the smaller of the ac tual clock low ti me and the actual clock high time as provided to the device (i.e. this

value can be greater than the minim um sp ecification lim i ts for tCL and tCH).

6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).

tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits , data pin to pin skew and

output pattern effects, and p-chann e l to n-channel variation of the output drivers.

7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.

Signal transitions through the DC region must be monotonic.

Data-In Hold Time to DQS-In (DQ & DM) tDH 0.35 - 0.35 - 0.35 - 0.35 - ns 3

Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 CK

Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK

Write DQS Preamble Setup Time tWPRES 0-0-0-0-

ns

Write DQS Preamble Hold Time tWPREH 0.35 - 0.35 - 0.35 - 0.35 - CK

Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK

Mode Register Set Delay tMRD 2-2-2-2-

CK

Exit Self Refresh to Any Execute Command tXSC 200 - 200 - 200 - 200 - CK 4

Power Down Exit Time tPDEX 2tCK

+ tIS -2tCK

+ tIS -CK

Average Periodic Refresh Interval tREFI - 7.8 - 7.8 - 7.8 - 7.8 us

Parameter Symbol 222 25 28 Unit Note

Min Max Min Max Min Max Min Max

Rev. 1.0 / Feb. 2005 26

1HY5DU283222BF(P)

AC CHARACTERISTICS - I (continue)

Parameter Symbol 33 36 45Unit Note

Min Max Min Max Min Max Min Max

Row Cycle Time tRC 15-14-13-10-

CK

Auto Refres h Row Cycl e Time tRFC 17-16-15-12-

CK

Row Act ive T ime tRAS 10 100K 9 100K 8 100K 7 100K CK

Row Address to Column Address

Delay for Read tRCDRD 6-5-5-4-

CK

Row Address to Column Address

Delay for Write tRCDWR 3-2-2-2-

CK

Row Act ive t o Row Ac tive De lay tRRD 3-3-3-2-

CK

Column Address to Column Address

Delay tCCD 1-1-1-1-

CK

Row Precharge Time tRP 6-5-5-4-

CK

Write Rec overy Time tWR 3-3-3-2-

CK

Last Data-In to Read Command tDRL 2-2-2-2-

CK

Auto Precharge Write Recovery +

Precharge Time tDAL 9-8-8-6-

CK

System Clock Cycle Time CL=4 tCK 3.3 10 3.6 10 4 10 - - ns

CL=3 ------510

ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK

Data-Out edge to Clock edge Skew tAC -0.60.6-0.60.6-0.60.6-0.60.6

ns

DQS-Out edge to Clock edge Skew tDQSCK -0.60.6-0.60.6-0.60.6-0.60.6

ns

DQS-Out edge to

Data-Out edge Skew tDQSQ - 0.35 - 0.4 - 0.4 - 0.4 ns

Data-Out hold time from DQS tQH tHPmin

-tQHS -tHPmin

-tQHS -ns 1,6

Clock Half Period tHP tCH/L

min -tCH/L

min -ns 1,5

Data Hold Skew Factor tQHS - 0.35 - 0.4 - 0.4 - 0.4 ns 6

Input Setup Time tIS 0.75 - 0.75 - 0.75 - 0.75 - ns 2

Input Hold Time tIH 0.75 - 0.75 - 0.75 - 0.75 - ns 2

Write DQS High Level Width t DQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK

Write DQS Low Level Width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK

Clock to First Rising edge of DQS-In tDQSS 0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 CK

Data-In Setup Time to DQS-In

(DQ & DM) tDS 0.35 - 0.4 - 0.4 - 0.4 - ns 3

Rev. 1.0 / Feb. 2005 27