PRELIMINARY
Dual 1:5 Differential Fanout Buff
er
FastEdge™ Ser ie
s
CY2PP321
0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-07508 Rev. *A Revised March 31, 2003
Features
• Dual sets of five ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/insertable
• <50-ps output-to-output skew
• <500-ps device-to-device skew
• Less than 10-ps intrinsic jitter
• 500-ps propagation delay (typical)
• Operation up to 1.5 GH z
• PECL mode supply range: VCC = 2.3 75V to 3.465V w ith
VEE = 0V
• ECL mode supply range: VEE = –2.375V to –3.465V with
VCC = 0V
•Industrial temperature range: –40°C to 85°C
• 32-pin 1.4-mm TQFP package
• Temperature compensation as 100K ECL
Description
The CY2PP3210 is a low-skew, low propagation delay dual
1-to-5 differential fanout buffer targeted to meet the require-
ment s of high perf ormance clock and dat a distrib ution applica-
tion s. The de vice is im plemente d on SiGe technolo gy and ha s
a fully differential internal architecture that is optimized to
achiev e low signal skew s at ope rating frequenci es of up to 1.5
GHz.
The dev ic e fea ture s two differenti al i npu t p a ths tha t are differ-
entia l inter nally. The C Y2PP32 10 may functi on not onl y as a
differential clock buffer but also as a signal level translator and
fano ut distrib uting a singl e-en ded si gnal. An extern al bia s pin,
VBB, is provid ed for an ECL/PECL single-end ed or differenti al
signal to 10 ECL/PECL differential loads. In such an applica-
tion, the VBB pin should be connected to either one of the
CLKA# or CLKB# inputs and bypassed to VCC via a 0.01µF
capacitor. Traditionally, in ECL, it is used to provide the refer-
ence le ve l to a receiving sin gle -en ded input that mi gh t hav e a
different self bias point.
Since th e CY2PP 321 0 introd uces n eglig ible jitte r to the ti ming
budget, it is the ideal choice for distributing high-frequency,
high-precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, su ch as interna l temperature compensati on,
ensure that the CY2PP3210 delivers consistent, guaranteed
performance over different platforms.
Block Diagram Pin Configuration
QB0
QB0#
QB1
QB1#
QB3
QB3#
QB4
QB4#
QB2
QB2#
CLKB
CLKB#
VCC
QA0
QA0#
QA1
QA1#
QA2
QA2#
QA3
QA3#
QA4
QA4#
CLKA
CLKA#
VCC
VBB
CY2PP3210
VCCO
QA0
QA0#
QA1
QA1#
QA2
QA2#
VCCO
VCCO
QB4#
QB4
QB3#
QB3
QB2#
QB2
VCCO
QA3
QA3#
QA4
QA4#
QB0
QB0#
QB1
QB1#
VCC
N.C.
CLKA
CLKA#
VBB
CLKB
CLKB#
VEE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
PRELIMINARY FastEdge™ Serie
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CY2PP321
0
Document #: 38-07508 Rev. *A Page 2 of 11
Governing Agencies
The fo llowing agenc ies provide s pecificatio ns that apply t o the CY2PP3210. The a gency name a nd relevant spe cification i s listed
below.
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull Down, PU for Pull Up, PC for Pull Center, O for output, OS for open source
and PWR for Power.
2. I n EC L mo de ( neg ativ e p ower su pply mod e), VEE is either –3.3V or–2.5V and VCC is connected to GND (0V). In PECL mode (positive power supply mode), VEE
is connected to GND (0V) and VCC is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (VCC) and are
between VCC and VEE.
3. VBB is available for use for single ended bias mode when VCC is +3.3V.
Pin Description
Pin Name I/O Type Description
3,4 CLKA, CLKA# I,PD[1]
I,PC ECL/PECL Default Differential clock input pair
6,7 CLKB, CLKB# I,PD
I,PC ECL/PECL Alternate Differential clock input pair
2N.C. No connect. Pad only
31,29,27,24,22 QA(0:4) O,OS ECL/PECL True output
30,28,26,23,21 QA#(0:4) O,OS ECL/PECL Complement output
20,18,15,13,11 QB(0:4) O,OS ECL/PECL True output
19,17,14,12,10 QB#(0:4) O,OS ECL/PECL Complement output
5 VBB[3] OBiasReference vo lt age outpu t for single end ed ECL or PECL operation
8 VEE[2] –PWR Power Power supply, negative connection
1 VCC +PWR Power Power supply, positive connection
9,16,25,32 VCCO +PWR Power Power supply, positive connection
Agency Name Specification
JED EC JESD 51 (Th eta JA)
JESD 8–2 (ECL)
JESD 65–A (skew,jitter)
IEEE 1596.3 (Jitter specs)
UL 94 (Moisture Grading)
Mil–Spec 883E Method 1012.1
(Thermal Theta JC)
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Document #: 38-07508 Rev. *A Page 3 of 11
.
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
VCC Supply Voltage Non-functional –0.3 4.6 VDC
VCC Operating Voltage Functional 2.5 – 5% 3.3+5% VDC
VBB Output Re ference Voltage Relative to VCC VCC–1.525 Vcc–1.325 VDC
IBB Output Reference Current Relative to VBB 200 uA
VTT Output Termination Voltage VTT = 0V for VCC = 2.5V VCC–2 VDC
VIN Input Voltage Relative to VCC –0.3 VCC+0.3 VDC
VOUT Output Voltage Relative to VCC –0.3 VCC+0.3 VDC
LUILatch Up Immunity Functional 300 mA
TSTemperature, Storage Non-functional –65 +150 °C
TATemperature, Operating Ambient Functional –40 +85 °C
ØJc Dissipation, Junction to Case Functional TBD TBD °C/W
ØJa Dissipation, Junction to Ambient Functional 40 60 °C/W
ESDhESD Protection (Human Body Model) 2000 Volts
MSL Moisture Sensitivity Level TBD TBD N.A.
GATES Total Functional Gate Count Assembled Die 50 Each
UL–94 Flammability Rating At 1/8 in. V–0 N.A.
FIT Failure in Time Manufacturing test 1 ppm
PECL DC Electrical Specifica tions
Parameter Description Condition Min. Max. Unit
VCC2.5V 2.5 Operating Voltage 2.5V ± 5%, VEE = 0.0V 2.375 2.625 V
VCC3.3V 3.3 Operating Voltage 3.3V ± 5%, VEE = 0.0V 3.135 3.465 V
VIL Input Voltage, Low VCC–1.945 VCC–1.625 V
VIH Input Voltage, High Define VCC and load current VCC–1.165 VCC–0.880 V
IIN Input Current[4] Vin = [VILmin = 2.406V or
VIHmax= 1.655V] at VCC = 3.6V 200 uA
Clock input pair CLKA, CLKA#, CLKB1, CLKB1#(PECL Differential signals)
VPP Differential input voltage[5] Differential operation 0.1 1.3 V
VCMR Differential cross point voltage[6] Differ ential operation 1.2 VCC V
IIN Input Current[4] VIN = VIL or VIN = VIH 200 uA
PECL Outputs QA((0:4),#),QB((0:4),#)(PECL Differential signals)
VOH Output H igh Voltag e IOH = –30 mA[7] VCC–1.145 VCC–0.895 V
VOL Output Low Volt age
VCC = 3.3V ± 5%
VCC = 2.5V ± 5%
IOL = –5 ma[7] VCC–1.945
VCC –1.945 VCC–1.695
VCC–1.695 V
Notes:
4. Input have internal pullup / pulldown or biasing resistors which affe ct the i nput current.
5. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality
6. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within th e VC M R ( D C) r a ng e a n d th e i n pu t
swing lies within the VPP (DC) specification.
7. Equivalent to a termination of 50 Ω to VTT.
PRELIMINARY FastEdge™ Serie
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CY2PP321
0
Document #: 38-07508 Rev. *A Page 4 of 11
Supply Current and VBB
IEE Maximum Quiesce nt Supply Current
without output termination current[8] VEE pin 130 mA
VBB Output refe renc e vol t ag e IBB = 200 uA VCC–1.525 VCC–1.325 V
IPUP Internal Pull-up Current TBD TBD mA
IPDWN Internal Pull-down Current TBD TBD mA
CIN Input pin capacitance TBD TBD pF
COUT Output pin capacitance TBD TBD pF
LIN Pin Inductance TBD TBD nH
ZOUT Out put impedance TBD TBD Ω
PECL DC Electrical Specifica tions(continued)
Parameter Description Condition Min. Max. Unit
ECL DC Electrical Specifications
Parameter Description Condition Min. Max. Unit
VEE –2.5 Negative Power Supply –2.5V ± 5%, VEE = 0.0V –2.375 –2.625 V
VEE –3.3 Negative Power Supply –3.3V ± 5%, VEE = 0.0V –3.135 –3.465 V
VIL Input Voltage, Low –1.945 –1.625 V
VIH Input Vo ltage, High Define VCC and load current –1.165 –0.880 V
IIN Input Current[4] VIN = VIL or Vin = VIH 200 uA
Clock input pair CLKA,CLKA#,CLKB,CLKB# (ECL Differential signals)
VPP Differential input voltage[5] Differential operation 0.1 1.3 V
VCMR Differential cross point voltage[6] Differential operation VEE+1.2 –0.3 V
IIN Input Current[4] VIN = VIL or VIN = VIH 150 uA
ECL Outputs QA((0:4),#),QB((0:4),#) (ECL Differential sign als)
VOH Output High Voltage IOH = –30 mA [7] –1.145 –0.895 V
VOL Output Low Voltage
VEE = –3.3V ± 5%
VEE = –2.5V ± 5%
IOL = –5 ma [7] –1.945
–1.945 –1.695
–1.695 V
Supply Current and VBB
IEE Maximum Quiescent Supply Current
without output termination current [8] VEE pin 125 mA
VBB Output reference voltag e IBB = 200 uA –1.525 –1.325 V
AC Electrical Specifications[9]
Parameter Description Condition Min. Max. Unit
Clock input pair CLKA, CLKA#, CLKB,CLKB# (PECL or ECL differential signals)
VPP Differential input voltage[10] Differential Operatio n 0.1 1.3 V
VCMR Differential cross point voltage[11] Different ial Operatio n VEE+1.2 0 V
FIN Input Frequency[12] 50% Duty Cycle Standard Load 3,500 MHz
TPD Propagation Delay CLKA or CLKB to
QA((0:4),#),QB((0:4),#) pairs 660-MHz 50% Duty Cycle Standard Load Differ-
ential Operation 280 750 ps
Notes:
8. ICC Cal culat ion: I CC = (number of differential output pairs used ) x (IOH + IOL) + IEE or ICC = (number of differential output pairs used) x (VOH –VTT)/Rload +
(VOL –VTT)/Rload +IEE.
9. AC characteristics apply for parallel output termination of 50W to VTT.
10. VPP (AC) is the minimum Differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew.
11. VCMR (AC) is the crosspoint of the Differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range
and the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay , device and part-to-part skew.
12. The CY2PP3210 is fully operation up to 1.5 GHz.
PRELIMINARY FastEdge™ Serie
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CY2PP321
0
Document #: 38-07508 Rev. *A Page 5 of 11
T iming Definitions
Note:
13. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
ECL Clock Outputs QA((0:4),#),QB((0:4),#)
Vo(P-P) Differential output voltage
(peak-to-peak) Differential PRBS
fo < 50 MHz
fo < 0.8 GHz
fo < 1.0 GHz
0.45
0.4
0.375
–V
VMCR Common Voltage Range VCC–1.425 V
tsk(O) Output-to-output skew 660-MHz 50% Duty Cycle Standard Load Differ-
ential Operation –50ps
tsk(PP) Output-to-output skew (part-to-part) 660-MHz 50% Duty Cycle Standard Load Differ-
ential Operation – 500 ps
tCCJ Output cycle-to-cycle jitter (Intrinsic) 660-MHz 50% Duty Cycle Standard Load Differ-
ential Operation TBD TBD ps
tsk(P) Output pulse skew [13] 660-MHz 50% Duty Cycle Standard Load Differ-
ential Operation TBD TBD ps
TR,TFOutput Rise/Fall time 660-MHz 50% Duty Cycle Differential 20% to 80% – 0.3 ns
TTB Total Timing Budget 660-MHz 50% Duty Cycle Standard Load TBD TBD ps
DJDeterministic/Intrinsic Jitter 660-MHz 50% Duty Cycle Standard Load – 10 ps
r.m.s.
AC Electrical Specifications[9](continued)
Parameter Description Condition Min. Max. Unit
VIH
VIL
VCMRVPP
VCMR Min = 1.2V
VPP range
0.1V - 1.3V
VCMR Max = VCC
VC C = 3.3V
VCC
GND GND = 0.0V
Figure 1. PECL Waveform Definitions
VIH
VIL
VCMR
VPP
VCC
VEE
VC C = 0.0V VCMR max = 0
VCM R m in VEE -1.0V
VEE = -2.5V or -3.3V
VPP range = 0.1
to 1.3V
Figure 2. ECL Differential Waveform Definitions
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Document #: 38-07508 Rev. *A Page 6 of 11
tr, tf,
20-80% VO(p-p
)
Figure 3. Rise and Fall Time with Reference to the Output
VOD
VPP /
VDIF
TPD
Figure 4. TPD Propagation Delay of Both CLKA or CLKA to QA((0:4),#),QB((0:4),#) Pair PECL/ECL to PECL/ECL
tsk (P ) O u tp u t p u ls e sk e w = | tP L H - tP HL |
VPP /
VDIF
VO(P-P)
tPLH tPHL
Figure 5. Output Pulse Skew
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Document #: 38-07508 Rev. *A Page 7 of 11
Test Configurations
Standard test load using a differential pulse generator and
differential mea su r ement instrument.
VPP /
VDIF
VO(P-P)
VO(P-P)
Qn
Qn+m
tsk(0)
Figure 6. Output-to-Output Skew
Pulse
Generator
Z = 50 ohm Zo = 50 ohm
VTT
VTT
RT = 50 ohm
Zo = 50 ohm
VTT
5"
5"
VTT
RT = 50 ohm
DUT
CY2PP3210 RT = 50 ohm
RT = 50 ohm
Figure 7. CY2PP3210 AC Test Reference
PRELIMINARY FastEdge™ Serie
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Document #: 38-07508 Rev. *A Page 8 of 11
Applicati ons Information
Termination Examples
1.3 V
Zo = 50 ohm
1.3 V
5"
5"
CY2PP3210
RT = 50 ohm
RT = 50 ohm
VCC = 3.3V
VEE = 0V
Figure 8. Standard LVPECL – PECL Output Termination
VTT
Zo = 50 ohm
VTT
5"
5"
CY2PP3210
RT = 50 ohm
RT = 50 ohm
VCC
VEE
VBB
Figure 9. Driving a PECL Single-Ended Input
3.3 V
Zo = 50 ohm
3.3 V
5"
5"
CY2PP3210
120 ohm
120 ohm
V CC = 3 .3 V
VEE = 0V
LVDS
51 ohm
(2 places)
33 ohm
(2 places)
LVPECL to
LVDS
Figure 10. Low-Volt age Po sitive Emitter-Cou pled Log ic (LVPECL) to a Low-Voltage Differential
Signaling (LVDS) Interface
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Document #: 38-07508 Rev. *A Page 9 of 11
Evaluation Material
Ordering Information
Part Number Package Type Product Flow
CY2 PP3210AI 32-p in TQFP Industrial, –40° to 85°C
CY2PP3210AIT 32-pin TQFP – Tape and Reel Industrial, –40° to 85°C
Figure 11. Demonstration PCB
PRELIMINARY FastEdge™ S
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Document #: 38-07508 Rev. *A Page 10 of 11
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. C ypress Semicond uctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
FastEdge is a trademark of Cypress Semiconductor . All product and company na mes mentioned i n this document are trademarks
of their respective holders.
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
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Document #: 38-07508 Rev. *A Page 11 of 11
Document History Page
Document Title: CY2PP3210 FastEdge™ Series Dual 1:5 Differential Fanout Buffer
Document Number: 38-07508
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 122396 02/12/03 RGL New Data Sheet
*A 125458 04/17/03 RGL Corrected pins 26 to 31 from Q2#, Q2, Q1#, Q1, Q0#, Q0 to QA2#, QA2,
QA1#, QA1,QA0#, QA0 in the Pin Configuration diagram
Changed pins 9, 16, 25, 32 from VCC to VCCO
Changed the title to FastEdge™ Series Dual 1:5 Differential Fanout Buffer
