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P/N:PM1301 REV. 1.2, NOV. 06, 2006
CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEA TURES
• Byte mode only:
- 262,411 x8 (MX29LV002C/002NC)
- 524,288 x8 (MX29LV004C)
- 1,048,576 x8 (MX29LV008C)
• Secto r Structure
- 16K-Byte x 1, 8K-Byte x 2, 32K-Byte x 1
64K-Byte x 3 (MX29LV002C), 64K-Byte x 7 (MX29LV004C), 64K-Byte x 15 (MX29LV008C)
• Secto r Pro tect
- Pro vides secto r pro tect function to prevent pro gram o r erase o peratio n in the protected secto r
- Pro vides chip unpro tect functio n to allow co de changing
- Pro vides tempo rary secto r unprotect functio n fo r co de changing in previo usly protected secto r
• Single Power Supply Operatio n
- 2.7 to 3.6 volt fo r read, erase , and pro gram o peratio ns
• Latch-up protected to 250mA fro m -1V to Vcc + 1V
• Low Vcc write inhibit : Vcc <= 1.4V
• Compatible with JEDEC standard
- Pino ut and so ftware co mpatible to single power supply Flash
PERFORMANCE
• High Performance
- F ast access time: 45R (MX29LV004C o nly), 55R(fo r MX29LV004C and MX29LV008C), 70/90nS
- F ast program time: 9uS/Byte typical utilizing accelerate function
- Fast erase time: 0.7s/sector
• Low Power Co nsumption
- Low active read current: 7mA (typical) at 5MHz
- Low standby current: 200nA (typical)
• Minimum 100,000 erase/program cycle
• 10 years data retentio n
SOFTW ARE FEA TURES
• Erase Suspend/ Erase Resume
- Suspends secto r erase o peration to read data from or pro gram data to ano ther sector which is not being erased
• Status Reply
- Data# Polling & To ggle bits pro vide detection o f program and erase o peratio n completion
• Support Common Flash Interface (CFI) o nly fo r 29L V002C/002NC , 29L V004C.
HARDWARE FEATURES
• Ready/Busy# (R Y/BY#) Output o nly fo r 29LV004C, 29LV008C .
- Pro vides a hardware metho d of detecting pro gram and erase o peration completion
• Hardware Reset (RESET#) Input
- Pro vides a hardware metho d to reset the internal state machine to read mode
PACKAGE
• 32-Pin TSOP (for MX29L V002C/002NC)
• 32-Pin PLCC (for MX29L V002C/002NC and MX29LV004C)
• 40-Pin TSOP (fo r MX29L V004C and MX29LV008C)
•All Pb-free devices are RoHS Compliant
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV002C/002NC PIN CONFIGURATIONS
32 PLCC
32 TSOP (TYPE 1)
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A17 Address Input
Q0~Q7 Data Input/Output
CE# Chip Enable Input
WE# Write Enable Input
RESET# Hardware Reset Pin/Sector Protect
Unlock
OE# Output Enable Input
VCC Power Supply Pin (+3V)
GND Ground Pin
1
4
5
9
13
14 17 20
21
25
29
32 30 A14
A13
A8
A9
A11
OE#
A10
CE#
Q7
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
Q3
Q4
Q5
Q6
A12
A15
A16
RESET#
VCC
WE#
A17
MX29LV002C/
002NC T/B
NC on MX29LV002NC
A11
A9
A8
A13
A14
A17
WE#
VCC
RESET#
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29LV002C/002NC T/B
NC on MX29LV002NC
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C PIN CONFIGURATIONS
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A18 Address Input
Q0~Q7 Data Input/Output
CE# Chip Enable Input
WE# Write Enable Input
RESET# Hardware Reset Pin/Secto r Protect
Unlo ck (fo r 40-TSOP)
OE# Output Enable Input
R Y/BY# Ready/Busy# Output (fo r 40-TSOP)
VCC P ower Supply Pin (2.7V~3.6V)
GND Ground Pin
32 PLCC
40 TSOP (Standard T ype) (10mm x 20mm)
1
4
5
9
13
14 17 20
21
25
29
32 30 A14
A13
A8
A9
A11
OE#
A10
CE#
Q7
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
Q3
Q4
Q5
Q6
A12
A15
A16
A18
VCC
WE#
A17
MX29LV004C T/B
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
GND
NC
NC
A10
Q7
Q6
Q5
Q4
VCC
VCC
NC
Q3
Q2
Q1
Q0
OE#
VSS
CE#
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
MX29LV004C T/B
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C PIN CONFIGURATIONS
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A19 Address Input
Q0~Q7 Data Input/Output
CE# Chip Enable Input
WE# Write Enable Input
RESET# Hardware Reset Pin
OE# Output Enable Input
R Y/BY# Ready/Busy Output
VCC P ower Supply Pin (2.7V~3.6V)
GND Ground Pin
40 TSOP (Standard T ype) (10mm x 20mm)
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
GND
NC
A19
A10
Q7
Q6
Q5
Q4
VCC
VCC
NC
Q3
Q2
Q1
Q0
OE#
GND
CE#
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
MX29LV008CT/CB
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH V OLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q7
A0-AM
AM: MSB address
CE#
OE#
WE#
RESET#
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Table 1. BLOCK STRUCTURE
Sector Sector Size Address range Sector Address
Byte Mode Byte Mode (x8) A 17 A 16 A 15 A 14 A 1 3
SA0 64Kbytes 00000-0FFFF 0 0 X X X
SA1 64Kbytes 10000-1FFFF 0 1 X X X
SA2 64Kbytes 20000-2FFFF 1 0 X X X
SA3 32Kbytes 30000-37FFF 1 1 X X X
SA4 8Kbytes 38000-39FFF 0 0 X X X
SA5 8Kbytes 3A000-3BFFF 0 1 X X X
SA6 16Kbytes 3C000-3FFFF 1 0 X X X
Sector Sector Size Address range Sector Address
Byte Mode Byte Mode (x8) A 1 7 A 1 6 A 1 5 A 1 4 A 13
SA0 16Kbytes 00000-03FFF 0000X
SA1 8Kbytes 04000-05FFF 00010
SA2 8Kbytes 06000-07FFF 00011
SA3 32Kbytes 08000-0FFFF 0 0 1 X X
SA4 64Kbytes 10000-1FFFF 0 1 X X X
SA5 64Kbytes 20000-2FFFF 1 0 X X X
SA6 64Kbytes 30000-3FFFF 1 1 X X X
MX29L V002CB SECTOR ARCHITECTURE
MX29LV002CT SECTOR ARCHITECTURE
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Sector Sector Size Address range Sector Address
Byte Mode Byte Mode (x8) A18 A 17 A16 A15 A14 A 13
SA0 64Kbytes 00000-0FFFF 0 0 0 X X X
SA1 64Kbytes 10000-1FFFF 0 0 1 X X X
SA2 64Kbytes 20000-2FFFF 0 1 0 X X X
SA3 64Kbytes 30000-3FFFF 0 1 1 X X X
SA4 64Kbytes 40000-4FFFF 1 0 0 X X X
SA5 64Kbytes 50000-5FFFF 1 0 1 X X X
SA6 64Kbytes 60000-6FFFF 1 1 0 X X X
SA7 32Kbytes 70000-77FFF 1 1 1 0 X X
SA8 8Kbytes 78000-79FFF 1 1 1 1 0 0
SA9 8Kbytes 7A000-7BFFF 1 1 1 1 0 1
SA10 16Kbytes 7C000-7FFFF 1 1 1 1 1 X
Sector Sector Size Address range Sector Address
Byte Mode Byte Mode (x8) A18 A 1 7 A 1 6 A 15 A14 A 1 3
SA0 16Kbytes 00000-03FFF 0 0 0 0 0 X
SA1 8Kbytes 04000-05FFF 0 0 0 0 1 0
SA2 8Kbytes 06000-07FFF 0 0 0 0 1 1
SA3 32Kbytes 08000-0FFFF 0 0 0 1 X X
SA4 64Kbytes 10000-1FFFF 0 0 1 X X X
SA5 64Kbytes 20000-2FFFF 0 1 0 X X X
SA6 64Kbytes 30000-3FFFF 0 1 1 X X X
SA7 64Kbytes 40000-4FFFF 1 0 0 X X X
SA8 64Kbytes 50000-5FFFF 1 0 1 X X X
SA9 64Kbytes 60000-6FFFF 1 1 0 X X X
SA10 64Kbytes 70000-7FFFF 1 1 1 X X X
MX29LV004CB SECTOR ARCHITECTURE
MX29L V004CT SECT OR ARCHITECTURE
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Sector Sector Size Address range Sector Address
A19 A18 A17 A16 A15 A14 A13
SA0 64Kbytes 00000h-0FFFFh 0000XXX
SA1 64Kbytes 10000h-1FFFFh 0001XXX
SA2 64Kbytes 20000h-2FFFFh 0010XXX
SA3 64Kbytes 30000h-3FFFFh 0011XXX
SA4 64Kbytes 40000h-4FFFFh 0100XXX
SA5 64Kbytes 50000h-5FFFFh 0101XXX
SA6 64Kbytes 60000h-6FFFFh 0110XXX
SA7 64Kbytes 70000h-7FFFFh 0111XXX
SA8 64Kbytes 80000h-8FFFFh 1000XXX
SA9 64Kbytes 90000h-9FFFFh 1 0 0 1 X X X
SA10 64Kbytes A0000h-AFFFFh 1 0 1 0 X X X
SA11 64Kbytes B0000h-BFFFFh 1 0 1 1 X X X
SA12 64Kbytes C0000h-CFFFFh 1 1 0 0 X X X
SA13 64Kbytes D0000h-DFFFFh 1 1 0 1 X X X
SA14 64Kbytes E0000h-EFFFFh 1 1 1 0 X X X
SA15 32Kbytes F0000h-F7FFFh 1 1110XX
SA16 8Kbytes F8000h-F9FFFh 111110 0
SA17 8Kbytes FA000h-FBFFFh 111110 1
SA18 16kbytes FC000h-FFFFFh 111111X
MX29LV008CT SECTOR ARCHITECTURE
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29L V008CB SECTOR ARCHITECTURE
Sector Sector Size Address range Sector Address
A19 A18 A17 A16 A15 A14 A13
SA0 16Kbytes 00000h-03FFFh 000000 X
SA1 8Kbytes 04000h-05FFFh 000001 0
SA2 8Kbytes 06000h-07FFFh 000001 1
SA3 32Kbytes 08000h-0FFFFh 00001XX
SA4 64Kbytes 10000h-1FFFFh 0001XXX
SA5 64Kbytes 20000h-2FFFFh 0010XXX
SA6 64Kbytes 30000h-3FFFFh 0011XXX
SA7 64Kbytes 40000h-4FFFFh 0100XXX
SA8 64Kbytes 50000h-5FFFFh 0101XXX
SA9 64Kbytes 60000h-6FFFFh 0110XXX
SA10 64Kbytes 70000h-7FFFFh 0111XXX
SA11 64Kbytes 80000h-8FFFFh 1 0 0 0 X X X
SA12 64Kbytes 90000h-9FFFFh 1 0 0 1 X X X
SA13 64Kbytes A0000h-AFFFFh 1010XXX
SA14 64Kbytes B0000h-BFFFFh 1011XXX
SA15 64Kbytes C0000h-CFFFFh 1 1 0 0 X X X
SA16 64Kbytes D0000h-DFFFFh 1101XXX
SA17 64Kbytes E0000h-EFFFFh 1110XXX
SA18 64kbytes F0000h-FFFFFh 1111XXX
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
T able 2. BUS OPERA TION--1
Note:
1. Q0~Q7 are input (DIN) or output (DOUT) pins according to the requests of co mmand sequence, secto r protection,
or data polling algorithm.
Mode Select RE- CE# WE# OE# Address Q0~Q7
SET#
Device Reset L X X X X HighZ
Standby Mo de Vcc±Vcc±X X X HighZ
0.3V 0.3V
Output H L H H X HighZ
Disable
Read Mode H L H L AIN DOUT
Write H L L H AIN DIN
Temporary Vhv X X X AIN DIN
Sector
Unprotect
Sector Vh v L L H Secto r Address, D I N
Protect A6=L, A1=H,
A0=L
Chip V hv L L H Secto r Address, DIN
Unprotect A6=H, A1=H,
A0=L
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
BUS OPERA TION--2
Item Control Input AM A12 A8 A5
CE# WE# OE# to to A9 to A6 to A1 A0 Q0~Q7
A13 A10 A7 A2
Sector Protect L H L SA x Vhv x L x H L 01h or 00h
Verification (Note1)
Read Silico n ID L H L x x Vhv x L x L L C2H
Manufacturer Code
Read Silico n ID L H L x x Vhv x L x L H 59H
MX29LV002CT
Read Silico n ID L H L x x Vhv x L x L H 5AH
MX29LV002CB
Read Silico n ID L H L x x Vhv x L x L H B5H
MX29LV004CT
Read Silico n ID L H L x x Vhv x L x L H B6H
MX29LV004CB
Read Silico n ID L H L x x Vhv x L x L H 3EH
MX29LV008CT
Read Silico n ID L H L x x Vhv x L x L H 37H
MX29LV008CB
Notes:
1. Sector unprotected code:00h. Secto r protected code:01h.
2. AM: MSB of address.
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
WRITE COMMANDS/COMMAND SEQUENCES
To write a co mmand to the de vice, system m ust drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all
address are latched at the later falling edge o f CE# and WE#, and all data are latched at the earlier rising edge of CE#
and WE#.
Figure 1 illustrates the A C timing wavefo rm of a write co mmand, and Table 3 defines all the valid co mmand sets o f the
device. System is not allowed to write invalid co mmands not defined in this datasheet. Writing an invalid command will
bring the device to an undefined state.
REQUIREMENTS FOR READING ARRAY DA T A
Read array action is to read the data stored in the array . While the memo ry device is in powered up o r has been reset,
it will auto matically enter the status of read array. If the microprocesso r wants to read the data stored in array, it has to
drive CE# (device enable control pin) and OE# (Output contro l pin) as Vil, and input the address of the data to be read
into address pin at the same time. After a perio d of read cycle (Tce o r Taa), the data being read o ut will be displa yed
o n output pin fo r microprocessor to access. If CE# o r OE# is Vih, the o utput will be in tri-state, and there will be no data
displa yed on o utput pin at all.
After the memo ry device co mpletes embedded o peratio n (automatic Erase o r Program), it will auto matically return to
the status o f read arra y, and the device can read the data in any address in the arra y. In the pro cess o f erasing, if the
de vice receiv es the Er ase suspend command, erase o peration will be stopped temporarily after a period of time no
more than Tready1 and the device will return to the status of read array. At this time, the device can read the data
sto red in any address except the secto r being erased in the array . In the status o f erase suspend, if user wants to read
the data in the secto rs being erased, the device will o utput status data o nto the output. Similarly, if pro gram co mmand
is issued after erase suspend, after pro g ram o peratio n is co mpleted, system can still read arra y data in any address
e xcept the sectors to be erased
The device needs to issue reset command to enable read array o peration again in order to arbitrarily read the data in
the arra y in the following two situatio ns:
1. In pro gram o r erase o peratio n, the programming o r erasing failure causes Q5 to go high.
2. The device is in auto select mode or CFI mode.
In the two situations above, if reset command is not issued, the device is not in read array mode and system must
issue reset co mmand befo re reading array data.
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RESET# OPERA TION
Driving RESET# pin low fo r a period more than Trp will reset the device back to read mo de. If the device is in pro gram
o r erase o peratio n, the reset operatio n will take at mo st a perio d o f Tready1 fo r the device to return to read array mo de.
Bef o re the de vice returns to read array mo d e, the R Y/BY# pin remains low (b usy status).
When RESET# pin is held at GND±0.3V, the device consumes standby current(Isb).However, device dra ws larger
current if RESET# pin is held at Vil b ut not within GND±0.3V.
It is reco mmended that the system to tie its reset signal to RESET# pin of flash memory , so that the flash memo ry will
be reset during system reset and allows system to read bo ot co de fro m flash memo ry.
SECTOR PROTECT OPERA TION
When a sector is protected, program or erase operation will be disabled on that protected sector. MX29LV002C/
MX29LV004C/MX29L V008C T/B pro vides two metho ds fo r sector protection.
Once the secto r is pro tected, the sector remains pro tected until next chip unprotect, o r is tempo rarily unpro tected by
asserting RESET# pin at Vhv . Ref er to tempo rary secto r unpro tect o peratio n f o r further details.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the
algo rithm f or this metho d.
The o ther method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operatio n begins at the
f alling edge o f WE# and terminates at the rising edge. Co ntact Macro nix f o r details.
CHIP UNPROTECT OPERATION
MX29LV002C/MX29L V004C/MX29LV008C T/B pro vides two methods for chip unprotect. The chip unpro tect operation
unpro tects all sectors within the device. It is reco mmended to protect all sectors befo re activating chip unpro tect mode.
All secto r are unpro tected when shipped from the facto ry.
The first metho d is by applying Vhv o n RESET# pin. Refer to Figure 12 f or timing diagram and Figure 13 for algorithm
o f the operation.
The other method is asserting Vhv o n A9 and OE# pins, with A6 at Vih and CE# at Vil (see Tab le 2). The unprotect
o peratio n begins at the f alling edge o f WE# and terminates at the rising edge. Co ntact Macro nix fo r details.
TEMPORAR Y SECTOR UNPROTECT OPERA TION
System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously
pro tected sectors can be programmed o r erased just as it is unpro tected. The devices returns to normal o peration once
Vhv is remo v ed fro m RESET# pin and previo usly pro tected secto rs are again pro tected.
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AUTOMATIC SELECT OPERA TION
When the device is in Read array mo de, erase-suspended read array mode o r CFI mo de, user can issue read silico n
ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs
continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix
Manufacture ID C2. When A0 is high, device will o utput Device ID. In read silicon ID mode, issuing reset command will
reset device back to read arra y mode or erase-suspended read array mode.
Ano ther way to enter read silicon ID is to apply high vo ltage o n A9 pin with CE#, OE#, A6 and A1 at Vil. While the high
v o ltage o f A9 pin is discharged, device will automatically leav e read silico n ID mo de and go back to read arra y mo de
or erase-suspended read arra y mode. When A0 is Lo w , de vice will output Macro nix Manuf acture ID C2. When A0 is
high, de vice will output De vice ID.
VERIFY SECT OR PROTECT ST ATUS OPERA TION
MX29LV002C/MX29LV004C/MX29L V008C T/B pro vides hardware secto r protection against Program and Erase o p-
eration for protected sectors. The sector protect status can be read through Sector Protect Verify command. This
metho d requires Vhv on A9 pin, Vih o n WE# and A1 pins, Vil o n CE#, OE#, A6 and A0 pins, and secto r address on A13
to AM pins. If the read o ut data is 01H, the designated secto r is pro tected. Oppo sitely, if the read o ut data is 00H, the
designated secto r is no t protected.
DA T A PRO TECTION
To av oid accidental erasure or programming o f the device, the de vice is automatically reset to read array mode during
pow er up. Besides, o nly after successful co mpletio n o f the specified co mmand sets will the de vice begin its erase o r
program o peration.
Other features to protect the data fro m accidental alternatio n are described as followed.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than 1.4V. This prevents data from spur iously
altered. The device automatically resets itself when Vcc is lo w er than 1.4V and write cycles are ignored until Vcc is
greater than 1.4V. System must pro vide proper signals o n contro l pins after Vcc is larger than 1.4V to av oid uninten-
tio nal program o r erase o peration
WRITE PULSE "GLITCH" PRO TECTION
CE#, WE#, OE# pulses sho rter than 5ns are treated as glitches and will no t be regarded as an effectiv e write cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is igno red when either CE# at Vih,
WE# a Vih, or OE# at Vil.
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
POWER-UP SEQUENCE
Upo n power up, MX29L V002C/MX29LV004C/MX29LV008C T/B is placed in read array mo de. Furthermo re, program o r
erase o peratio n will begin o nly after successful completio n o f specified command sequences.
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up , the device igno res the first command on the
rising edge of WE#.
PO WER SUPPLY DECOUPLING
A 0.1uF capacito r sho uld be connected between the Vcc and GND to reduce the no ise effect.
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P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
T ABLE 3. MX29L V002C/MX29LV004C/MX29LV008C T/B COMMAND DEFINITIONS
Notes:
1. Device ID :
29L V002C: 59H/5AH (Top/Bottom)
29L V004C: B5H/B6H (T o p/Bottom)
29L V008C: 3EH/37H (Top/Bottom)
2. For secto r pro tect v erify result, 00H means secto r is no t pro tected, 01H means secto r has been pro tected.
3. Secto r Pro tect co mmand is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus cyc
is for protect verify.
4. Fo r MX29L V002C/002NC and MX29LV004C.
Manufacturer
ID Device
ID Sector Protect
Verify
1s t Bus Cy c A ddr A ddr X XX 555 555 555 555 555 555
Data Data F0 AA AA AA AA AA AA
2nd B us Cy c A ddr 2A A 2A A 2A A 2A A 2A A 2A A
Data 55 55 55 55 55 55
3rd Bus Cyc A ddr 555 555 5 55 555 555 555
Data 90 90 90 A0 80 80
4t h B us Cy c A ddr X 00 X 01 (Sector)X02 Addr 555 555
Data C2 ID 00/01 Data AA AA
5t h B us Cy c A ddr 2AA 2AA
Data 55 55
6t h B us Cy c A ddr 555 Sector
Data 10 30
Command Read
Mode Reset
Mode
Automatic Select
Program Chip
Erase Sector
Erase
1st B us Cy c Ad dr XXX XXX XXX AA
Data B0 30 60 98
2nd B us Cyc A ddr s e ctor
Data 60
3rd B us Cy c A ddr se c tor
Data 40
4t h Bus Cyc A d dr sect or
Data 00/01
5t h Bus Cyc A d dr
Data
6t h Bus Cyc A d dr
Data
Command Erase
Suspend Erase
Resume Sector
Protect CFI
(Note 4)
17
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RESET
In the f ollowing situations, ex ecuting reset command will reset de vice bac k to read arra y mode:
•Amo ng erase command sequence (befo re the full command set is completed)
•Secto r erase time-o ut perio d
•Erase fail (while Q5 is high)
•Among program command sequence (before the full command set is completed, erase-suspended program in-
cluded)
•Pro gram fail (while Q5 is high, and erase-suspended pro gram f ail is included)
•Read silico n ID mo de
•Secto r protect v erify
•CFI mo de
While de vice is at the status o f prog ram fail o r erase f ail (Q5 is high), user must issue reset co mmand to reset device
back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must
issue reset command to reset de vice back to read arr ay mode.
When the device is in the progress o f programming (not pro gram fail) o r erasing (no t erase fail), device will ignore reset
command.
AUTOMA TIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is
protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a
specific command. The fourth cycle is a normal read cycle, and user can read at an y address any number of times
witho ut entering ano ther command sequence. The reset command is necessary to exit the Automatic Select mode and
back to read array. The fo llowing table shows the identificatio n co de with co rresponding address.
Address Data (Hex) Representation
Manufacturer ID X00 C 2
Device ID X0 1 ID To p/Bo tto m Bo o t Sector
Secto r Pro tect Verify (Secto r address) X 02 00/01 Unprotected/protected
There is an alternative metho d to that shown in Table 2, which is intended for EPROM programmers and requires Vhv
o n address bit A9.
Notes:
Device ID : MX29LV002CT: 59, MX29LV002CB: 5A
MX29L V004CT : B5, MX29LV004CB: B6
MX29LV008CT: 3E, MX29L V008CB: 37
18
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AUTOMATIC PROGRAMMING
The MX29LV002C/MX29L V004C/MX29LV008C T/B can provide the user program functio n by the fo rm o f Byte-Mode or
Wo rd-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlo ck cycles and A0H), any
data user inputs will auto matically be pro grammed into the arra y .
Once the pro gram function is executed, the internal write state controller will auto matically execute the algorithms and
timings necessary fo r pro gram and verificatio n, which includes generating suitable pro gram pulse, verifying whether
the threshold vo ltage of the programmed cell is high enough and repeating the program pulse if any o f the cells do es not
pass verificatio n. Meanwhile, the internal co ntro l will pro hibit the pro gramming to cells that pass verificatio n while the
other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device
requires the user to write the pro gram co mmand and data only .
Pro gramming will o nly change the bit status from "1" to "0". That is to say, it is impo ssible to co nvert the bit status fro m
"0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not
successfully pro grammed to "0".
Any co mmand written to the device during pro gramming will be ignored except hardware reset, which will terminate the
pro gram o peration after a perio d of time no mo re than Tready1. When the embedded program algo rithm is complete o r
the pro gram o peratio n is terminated by hardware reset, the device will return to the reading array data mo de.
When the embedded program o peration is on go ing, user can co nfirm if the embedded operation is finished or not by the
fo llowing metho ds:
Status Q7 Q6 Q5 RY/BY#*2
In progress*1 Q7# to gging 0 0
Finished Q7 Sto p toggling 0 1
Exceed time limit Q7# Toggling 1 0
*1: The status "in progress" means both pro gram mo de and erase-suspended program mo de.
*2: R Y/BY# is an o pen drain o utput pin and sho uld be weakly co nnected to Vcc thro ugh a pull-up resisto r .
*3: When an attempt is made to program a protected sector, Q7 will o utput its complement data o r Q6 continues to
toggle f or about 1us o r less and the device returns to read array state without programing the data in the protected
sector.
19
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SECTOR ERASE
Secto r Erase is to erase all the data in a secto r with "1" and "0" as all "1". It requires six command cycles to issue. The
first two cycles are "unlock cycles", the third o ne is a configuratio n cycle, the f o urth and fifth are also "unlo ck cycles"
and the sixth cycle is the secto r erase command. After the sector erase command sequence is issued, there is a time-
o ut period o f 50us counted internally . During the time-o ut period, additional sector address and sector erase co mmand
can be written multiply. Once user enters ano ther sector erase co mmand, the time-o ut perio d of 50us is reco unted. If
user enters any co mmand o ther than sector eras o r erase suspend during time-o ut perio d, the erase co mmand wo uld
be abor ted and the device is reset to read array condition . The number of sectors could be from one sector to all
secto rs. After time-o ut perio d passing by, additio nal erase co mmand is not accepted and erase embedded o peratio n
begins.
During sector erasing, all commands will no t be accepted except hardware reset and erase suspend and user can
check the status as chip erase.
When the embedded chip erase o peratio n is on go ing, user can co nfirm if the embedded operation is finished o r no t by
the fo llowing metho ds:
Status Q7 Q6 Q5 Q2 RY/BY#
In pro gress 0 Togging 0 Toggling 0
Finished 1 Stop toggling 0 1 1
Exceed time limit 0 Toggling 1 Toggling 0
CHIP ERASE
Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the actio n in, and the first two
cycles are "unlo ck" cycles , the third o ne is a co nfiguration cycle, the fourth and fifth are also "unlo ck" cycles , and the
sixth cycle is the chip erase operation.
During chip erasing, all the co mmands will not be accepted except hardware reset or the wo rking vo ltage is too low that
chip erase will be interrupted. After Chip Erase, the chip will return to the state o f Read Array.
*1: The status Q3 is the time-out per iod indicator. When Q3=0, the device is in time-out period and is acceptible to
ano ther secto r address to be erased. When Q3=1, the de vice is in erase o peratio n and o nly er ase suspend is valid.
*2: R Y/BY# is o pen drain o utput pin and sho uld be weakly co nnected to Vcc through a pull-up resisto r.
*3: When an attempt is made to erase a pro tected sector , Q7 will o utput its complement data o r Q6 continues to toggle
f o r 100us o r less and the de vice returned to read arra y status witho ut erasing the data in the pro tected secto r .
When the embedded erase o peration is o n going, user can co nfirm if the embedded operatio n is finished or no t by the
fo llowing metho ds:
Status Q7 Q6 Q5 Q3 Q2 RY/BY#*2
Time-out period 0 To gging 0 0 Toggling 0
In pro gress 0 To gging 0 1 Toggling 0
Finished 1 Sto p toggling 0 1 1 1
Exceed time limit 0 Toggling 1 1 Toggling 0
20
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
When the device has suspended er asing, user can e x ecute the co mmand sets e xcept secto r erase and chip erase ,
such as read silico n ID , secto r pro tect v erify, pro gram, CFI query and erase resume.
SECTOR ERASE RESUME
Secto r erase resume co mmand is valid o nly when the device is in erase suspend state. After erase resume, user can
issue another erase suspend command, but there should be a 400uS interval between er ase resume and the next
erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for
erasing will increase.
Status Q7 Q6 Q5 Q3 Q2 RY/BY#
Erase suspend read in erase suspended secto r 1 No to ggle 0 N/A toggle 1
Erase suspend read in no n-erase suspended secto r Data Data Data Data Data 1
Erase suspend pro gram in no n-erase suspended sector Q7# Toggle 0 N/A N/A 0
SECTOR ERASE SUSPEND
During sector erasure, secto r erase suspend is the o nly valid co mmand. If user issue erase suspend co mmand in the
time-o ut perio d o f sector erasure, device time-o ut perio d will be o ver immediately and the device will go back to erase-
suspended read array mo de. If user issue erase suspend co mmand during the sector erase is being o perated, device
will suspend the o ngo ing erase o peration, and after the Tready1 (<=20uS) suspend finishes and the device will enter
erase-suspended read array mode. User can judge if the device has finished erase suspend thro ugh Q6, Q7, and R Y/
BY#.
After device has entered erase-suspended read array mo de, user can read o ther sectors not at erase suspend by the
speed o f Taa; while reading the secto r in erase-suspend mo de, device will o utput its status. User can use Q6 and Q2
to judge the secto r is erasing or the erase is suspended.
21
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
T able 4-1. CFI mode: Identification Data Values (MX29L V002C/002NC and 004C only)
(All values in these tables are in hexadecimal)
T able 4-2. CFI Mode: System Interface Data V alues
QUER Y COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LV002C/MX29LV004C T/B features CFI mo de. Host system can retrieve the operating characteristics, structure
and vendor-specified infor mation such as identifying information, memory size, byte/word configuration, operating
vo ltages and timing inf o rmatio n o f this device b y CFI mode. The device enters the CFI Query mo de when the system
writes the CFI Query command, 98H, to address 55H any time the device is ready to read array data. The system can
read CFI informatio n at the addresses given in Table 4. A reset co mmand is required to exit CFI mode and go back to
ready arra y mode o r erase suspend mo de. The system can write the CFI Query co mmand only when the de vice is in
read mo de, erase suspend, standby mo de or automatic select mode.
Description Address (h) Data (h)
Query-unique ASCII string "QRY" 1 0 0051
11 0052
12 0059
Primary vendor command set and control interface ID code 1 3 0002
14 0000
Address for primary algorithm extended query table 1 5 0040
16 0000
Alternate vendor command set and control interface ID code 1 7 0000
18 0000
Address for alternate algorithm extended query table 19 0000
1A 0000
Description Address (h) Data (h)
Vcc supply minimum program/erase voltage 1B 0027
Vcc supply maximum program/erase voltage 1 C 0036
VPP supply minimum program/erase voltage 1 D 0000
VPP supply maximum program/erase voltage 1E 0000
Typical timeout per single word/byte write, 2n uS 1F 0004
Typical timeout for maximum-size buffer write, 2n uS 2 0 0000
Typical timeout per individual block erase, 2n mS 2 1 000A
Typical timeout for full chip erase, 2n mS 2 2 0000
Maximum timeout for word/byte write, 2n times typical 23 0005
Maximum timeout for buffer write, 2n times typical 24 0000
Maximum timeout per individual block erase, 2n times typical 25 0004
Maximum timeout for chip erase, 2n times typical 26 0000
22
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
T able 4-3. CFI Mode: Device Geometry Data V alues
Description Address (h) Data (h)
Device size = 2n in number of bytes (MX29LV002C) 2 7 0012
Device size = 2n in number of bytes (MX29LV004C) 2 7 0013
Flash device interface description 2 8 0000
29 0000
Maximum number of bytes in buffer write = 2n (not support) 2A 0000
2B 0000
Number of erase regions within device 2 C 0004
Index for Erase Bank Area 1 2D 0000
[2E,2D] = # of same-size sectors in region 1-1 2E 0000
[30, 2F] = sector size in multiples of 256-bytes 2F 0040
30 0000
Index for Erase Bank Area 2 31 0001
32 0000
33 0020
34 0000
Index for Erase Bank Area 3 35 0000
36 0000
37 0080
38 0000
Index for Erase Bank Area 4 (for MX29LV002C) 3 9 0002
Index for Erase Bank Area 4 (for MX29LV004C) 3 9 0006
3A 0000
3B 0000
3C 0001
23
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
T able 4-4. CFI Mode: Primary V endor-Specific Extended Query Data V alues
Description Address (h) Data (h)
Query - Primary extended table, unique ASCII string, PRI 4 0 0050
41 0052
42 0049
Major version number, ASCII 4 3 0031
Minor version number, ASCII 4 4 0030
Unlock recognizes address (0= recognize, 1= don't recognize) 4 5 0000
Erase suspend (2= to both read and program) 4 6 0002
Sector protect (N= # of sectors/group) 4 7 0001
Temporary sector unprotect (1=supported) 48 0001
Sector protect/Chip unprotect scheme 49 0004
Simultaneous R/W operation (0=not supported) 4A 0000
Burst mode (0=not supported) 4B 0000
Page mode (0=not supported) 4C 0000
24
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ABSOLUTE MAXIMUM STRESS RATINGS
Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC
Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6 5oC to +150oC
V oltage Range
Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
RESET#, A9 and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V
The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to Vcc +0.5 V
Output Short Circuit Current (less than o ne second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade
Surrounding Temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Grade
Surrounding Temperature (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Vcc Supply Voltages
Full Vcc Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
Regulated Vcc Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to 3.6 V
25
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
DC CHARACTERISTICS
Symbol Description Min Typ Max Remark
Iilk Input Leak ± 1.0uA
Iilk9 A9 Leak 35uA A9=12.5V
Iolk Output Leak ± 1.0uA
Icr1 Read Current(5MHz) 7mA 12mA CE#=Vil,
OE#=Vih
Icr2 Read Current(1MHz) 2mA 4mA CE#=Vil,
OE#=Vih
Icw Write Current 15mA 30mA CE#=Vil,
OE#=Vih,
WE#=Vil
Isb Standby Current 0.2uA 5uA Vcc=Vcc max,
other pin disable
Isbr Reset Current 0.2uA 5uA Vcc=Vccmax,
RESET# enable,
other pin disable
Isbs Sleep Mo de Current 0.2uA 5uA
Vil Input Low V oltage -0.5V 0.8V
Vih Input High V oltage 0.7xVcc Vcc+0.3V
Vhv V ery High V oltage fo r hardware 11.5V 12.5V
Protect/Unprotect/Auto Select/
Temporary Unprotect
V o l Output Low V o ltage 0.45V Iol=4.0mA
V oh1 Ouput High V oltage 0.85xVcc Ioh1=-2mA
V oh2 Ouput High V oltage Vcc-0.4V Io h2=-100uA
26
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SWITCHING TEST CIRCUITS
Test Condition
Output Lo ad : 1 TTL gate
Output Lo ad Capacitance,CL : 30pF(45R/55R/70nS)/100pF(90nS)
Rise/Fall Times : 5nS
In/Out reference levels :1.5V
SWITCHING TEST WAVEFORMS
1.5V 1.5V
Test Points
3.0V
0.0V OUTPUT
INPUT
R1=6.2K ohm
R2=2.7K ohm
TESTED DEVICE
DIODES=IN3064
OR EQUIVALENT
CL
R1
Vcc
0.1uF R2 +3.3V
27
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
AC CHARACTERISTICS
MX29LV002C/002NC
Symbol Description Min Typ Max Unit
Ta a V alid data o utput after address 70/90 nS
Tce V alid data o utput after CE# lo w 70/90 nS
Toe V alid data o utput after OE# low 30/35 nS
Tdf Data o utput floating after OE# high 25/30 nS
Toh Output ho ld time fro m the earliest rising edge o f address, 0 nS
CE#, OE#
Trc Read period time 70/90 nS
Twc Write period time 70/90 nS
Tcwc Co mmand write period time 70/90 nS
Tas Address setup time 0 nS
Ta h Address ho ld time 4 5 nS
Tds Data setup time 35/45 nS
Tdh Data ho ld time 0 nS
Tvcs Vcc setup time 50 uS
Tcs Chip enable Setup time 0 nS
Tch Chip enable ho ld time 0 nS
To e s Output enable setup time 0 nS
Toeh Read 0 nS
Toeh Output enable ho ld time Toggle & 10 nS
Data# Polling
Tws WE# setup time 0 nS
Tw h WE# ho ld time 0 nS
Tcep CE# pulse width 3 5 nS
Tceph CE# pulse width high 3 0 nS
Tw p WE# pulse width 3 5 nS
Tw ph WE# pulse width high 3 0 nS
Tbusy Progr am/Erase active time b y RY/BY# 90 nS
Tgh wl Read reco ver time befo re write 0 nS
Tghel Read reco ver time befo re write (CE# Control) 0 nS
Twhwh1 Byte Program o peration 9 300 uS
Twhwh2 Sector Erase Operation 0.7 1 5 sec
Tbal Sector Add ho ld time 5 0 uS
28
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C (Restricated Vcc=3.0V~3.6V for 45R/55R)
Symbol Description Min Typ Max Unit
Ta a V alid data o utput after address 45/55/70/90 nS
Tce V alid data o utput after CE# lo w 45/55/70/90 nS
Toe V alid data o utput after OE# low 30/30/30/35 nS
Tdf Data o utput floating after OE# high 25/25/25/30 nS
Toh Output ho ld time fro m the earliest rising edge o f address, 0 nS
CE#, OE#
Trc Read period time 45/55/70/90 nS
Twc Write period time 45/55/70/90 nS
Tcwc Co mmand write period time 45/55/70/90 nS
Tas Address setup time 0 nS
Ta h Address ho ld time 4 5 nS
Tds Data setup time 35/35/35/45 nS
Tdh Data ho ld time 0 nS
Tvcs Vcc setup time 50 uS
Tcs Chip enable Setup time 0 nS
Tch Chip enable ho ld time 0 nS
To e s Output enable setup time 0 nS
Toeh Read 0 nS
Toeh Output enable ho ld time Toggle & 10 nS
Data# Polling
Tws WE# setup time 0 nS
Tw h WE# ho ld time 0 nS
Tcep CE# pulse width 3 5 nS
Tceph CE# pulse width high 3 0 nS
Tw p WE# pulse width 3 5 nS
Tw ph WE# pulse width high 3 0 nS
Tbusy Progr am/Erase active time b y RY/BY# 90 nS
Tgh wl Read reco ver time befo re write 0 nS
Tghel Read reco ver time befo re write (CE# Control) 0 nS
Twhwh1 Byte Program o peration 9 3 00 uS
Twhwh2 Sector Erase Operation 0.7 1 5 sec
Tbal Sector Add ho ld time 5 0 uS
No tes: Only 40-TSOP pro vide RY/BY# pin.
29
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C (Restricated Vcc=3.0V~3.6V for 55R)
Symbol Description Min Typ Max Unit
Ta a V alid data o utput after address 55/70/90 nS
Tce V alid data o utput after CE# lo w 55/70/90 nS
Toe V alid data o utput after OE# low 30/30/35 nS
Tdf Data o utput floating after OE# high 25/25/30 nS
Toh Output ho ld time fro m the earliest rising edge o f address, 0 nS
CE#, OE#
Trc Read period time 55/70/90 nS
Twc Write period time 55/70/90 nS
Tcwc Co mmand write period time 55/70/90 nS
Tas Address setup time 0 nS
Ta h Address ho ld time 4 5 nS
Tds Data setup time 35/35/45 nS
Tdh Data ho ld time 0 nS
Tvcs Vcc setup time 50 uS
Tcs Chip enable Setup time 0 nS
Tch Chip enable ho ld time 0 nS
To e s Output enable setup time 0 nS
Toeh Read 0 nS
Toeh Output enable ho ld time Toggle & 10 nS
Data# Polling
Tws WE# setup time 0 nS
Tw h WE# ho ld time 0 nS
Tcep CE# pulse width 3 5 nS
Tceph CE# pulse width high 3 0 nS
Tw p WE# pulse width 3 5 nS
Tw ph WE# pulse width high 3 0 nS
Tbusy Pro gr am/Erase active time b y R Y/BY# 90 nS
Tghwl Read reco ver time bef ore write 0 nS
Tghel Read reco ver time befo re write (CE# Control) 0 nS
Twhwh1 Byte Program o peration 9 300 uS
Twhwh2 Sector Erase Operation 0.7 1 5 sec
Tbal Sector Add hold time 50 uS
30
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 1. COMMAND WRITE OPERA TION
Addresses
CE#
OE#
WE#
DIN
Tds
Tah
Data
Tdh
Tcs Tch
Tcwc
Twph
Twp
Toes
Tas
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
VA
V A: Valid Address
31
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
READ/RESET OPERATION
Figure 2. READ TIMING WA VEFORMS
Addresses
CE#
OE#
Taa
WE#
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh
Vol
HIGH Z HIGH Z
D ATA V alid
Toe
Toeh Tdf
Tce
Trc
Outputs
Toh
ADD V alid
32
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 3. RESET# TIMING W AVEFORM
AC CHARACTERISTICS
Item Description Setup Speed Unit
Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 500 nS
Trp2 RESET# Pulse Width (NOT During Automatic Algo rithms) MIN 500 nS
Tr h RESET# High Time Bef ore Read MIN 5 0 nS
Tr b 1 R Y/BY# Recovery Time (to CE#, OE# go low) MIN 0 nS
Tr b2 RY/BY# Reco very Time (to WE# go low) MIN 5 0 nS
Tready1 RESET# PIN Low (During Auto matic Algo rithms) MAX 2 0 uS
to Read or Write
Tready2 RESET# PIN Low (NO T During Auto matic MAX 500 nS
Algo rithms) to Read o r Write
Trh
Trb1
Trp2
Trp1
Tready2
Tready1
RY/BY#
CE#, OE#
RESET#
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY#
CE#, OE#
Trb2
WE#
RESET#
33
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ERASE/PROGRAM OPERATION
Figure 4. AUTOMA TIC CHIP ERASE TIMING W A VEFORM
Twc
Address
OE#
CE#
55h
2AAh SA
10h
In
Progress Complete
VA VA
Tas Tah
SA: 555h for chip erase
Tghwl
Tch
Twp
Tds Tdh
Read Status
Last 2 Erase Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
34
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
NO Data=FFh ?
Write Data 10H Address 555H
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Chip Erase Completed
35
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 6. AUTOMA TIC SECTOR ERASE TIMING W A VEFORM
Twc
Address
OE#
CE#
55h
2AAh Sector
Address 1
Sector
Address 0
30h
In
Progress Complete
VA VA
30h
Sector
Address n
Tas
Tah
Tbal
Tghwl
Tch
Twp
Tds Tdh
Twhwh2
Read Status
Last 2 Erase Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
30h
36
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 7. AUTOMA TIC SECT OR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Sector Erase Completed
NO
Last Sector
to Erase
YES
YES
NO
Data=FFh
37
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
38
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 9. AUTOMA TIC PROGRAM TIMING W A VEFORMS
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Tah
Tghwl
Tch
Twp
Tds Tdh
Twhwh1
Last 2 Read Status CycleLast 2 Program Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
39
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 10. CE# CONTROLLED WRITE TIMING WA VEFORM
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Tah
Tghwl
Tcep
Tds Tdh
Twhwh1 or Twhwh2
Tbusy Trb
Tceph
WE#
Data
RY/BY#
40
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 11. AUTOMA TIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Read Again Data:
Program Data?
YES
Auto Program Completed
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Last Word to be
Programed
No
No
41
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
SECTOR PROTECT/CHIP UNPROTECT
Figure 12. Sector Protect/Chip Unprotect Waveform (RESET# Control)
150uS: Sector Protect
15mS: Chip Unprotect
1us
Vhv
Vih
Data
SA, A6
A1, A0
CE#
WE#
OE#
VA VA VA
Status
VA: valid address
40h60h60h
Verification
RESET#
42
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 13-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
Wait 150us
Reset
PLSCNT=1
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
Device fail
Temporary Unprotect Mode
Retry Count +1
First CMD=60h?
Data=01h?
Retry Count=25?
Yes
YesYes
Yes
No
No
No
No
Protect another
sector?
43
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 13-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv
Write [A6,A1,A0]:[1,1,0]
data: 60h
Write [A6,A1,A0]:[1,1,0]
data: 40h
Read [A6,A1,A0]:[1,1,0]
Wait 15ms
Temporary Unprotect
Write reset CMD
Chip Unprotect Done
Retry Count +1
Device fail
All sectors
protected?
Data=00h?
Retry Count=1000?
Yes
Yes
No
No
Yes
Protect All Sectors
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
First CMD=60h?
Yes
No
No
44
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 14. SECTOR PROTECT TIMING W A VEFORM (A9, OE# Control)
Notes: Tvlht (V o ltage transitio n time)=4uS min.
Twpp1 (Write pulse width fo r sector pro tect)=100nS min, 10uS(Typ.)
Twpp2 (Write pulse width fo r chip unprotected)=100nS min, 12mS(Typ.)
To esp (OE# setup time to WE# activ e)=4uS min.
Toe
Data
OE#
WE#
12V
3V
12V
3V
CE#
A9
A1
A6
Toesp
Twpp1
Tvlht
TvlhtTvlht
Verify
01H F0H
AM-A13 Sector Address
45
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 15. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Write Sector Addr
Retry Count=0
Retry Count+1
Sector Protect
Done
Data=01H?
Yes
.
OE#=Vhv, A9=Vhv, CE#=Vil
A6=Vil
Activate WE# Pulse
Time Out 150us
WE#=Vih, CE#=OE#=Vil
A9=Vhv
Read at Sector Address
with A1=1
Protect Another
Sector?
Remove Vhv from A9
Write Reset Command
Device Failed
PLSCNT=32?
Yes
No
No
46
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 16. TIMING WA VEFORM FOR CHIP UNPROTECTION (A9, OE# Control)
No tes: Tvlht (V o ltage transitio n time)=4uS min.
Twpp1 (Write pulse width fo r secto r protect)=100nS min, 10uS(Typ.)
Twpp2 (Write pulse width fo r chip unpro tected)=100nS min, 12mS(Typ.)
To esp (OE# setup time to WE# activ e)=4uS min.
Toe
Data
WE#
12V
VCC
CE#
A9
A1
Toesp
Twpp2
OE#
12V
VCC
Tvlht Tvlht
Verify
00H
A6
Sector Address
AM-A13
F0H
Tvlht
47
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 17. CHIP UNPRO TECTION ALGORITHM (A9, OE# Control)
START
Protect All Sectors
Retry Count=0
Chip Unprotect
Done
Data=00H?
Yes
OE#=A9=Vhv
CE#=Vil, A6=Vih
Activate WE# Pulse
Time Out 50ms
Sector Protect Verify from
first sector with CE#=OE#=vil,
A9=Vhv, A1=1
All sectors have
been verified?
Remove Vhv from A9
Write Reset Command
Device Failed
PLSCNT=1000?
No
Retry Count +1
No
Yes
Yes
No
go to next sector
* Before chip unprotect, all sectors should be protected.
48
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 18. TEMPORARY SECTOR UNPROTECT WAVEFORMS
T able 5. TEMPORARY SECTOR UNPROTECT
Parameter Alt Description Condition Speed Unit
Trpvhh Tvidr RESET# Rise Time to Vhv and Vhv F all Time to RESET# MIN 500 nS
Tvhhwl Trsp RESET# Vhv to WE# Low MIN 4 uS
RESET#
CE#
WE#
RY/BY#
Trpvhh
12V
Vhv
0 or Vih Vil or Vih
Tvhhwl
Trpvhh
Program or Erase Command Sequence
49
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 19. TEMPORARY SECTOR UNPROTECT FLOWCHART
Notes:
1. Temporary unpro tect all protected sectors Vhv=11.5~12.5V.
2. The pro tected conditio ns o f the pro tected secto rs are the same to tempo rary secto r unprotect mode.
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Mode Operation Completed
50
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 20. SILICON ID READ TIMING W A VEFORM
Taa
Tce
Taa
Toe
Toh Toh
Tdf
DATA OUT
C2H Device ID
Vhv
Vih
Vil
A9
ADD
CE#
A1
OE#
WE#
A0
DATA OUT
DATA
Q0-Q7
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Notes:
Device ID : MX29LV002CT: 59, MX29LV002CB: 5A
MX29L V004CT : B5, MX29LV004CB: B6
MX29LV008CT: 3E, MX29L V008CB: 37
51
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
WRITE OPERATION STATUS
Figure 21. DA T A# POLLING TIMING WA VEFORMS (DURING AUTOMATIC ALGORITHMS)
Tdf
Tce
Tch
Toe
Toeh
Toh
CE#
OE#
WE#
Q7
Q0-Q6
RY/BY#
Tbusy
Status Data Status Data
Status Data Complement True Valid Data
Taa
Trc
Address
VAVA
High Z
High Z
Valid DataTrue
52
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 22. Data# Polling Algorithm
Read Q7~Q0 at valid address
(Note 1)
Read Q7~Q0 at valid address
Start
Q7 = Data# ?
Q5 = 1 ?
Q7 = Data# ?
(Note 2)
FAIL Pass
No
No
No
Yes
Yes
Yes
Notes:
1 . Fo r programming, valid address meas pro gram address.
F o r erasing, valid address meas er ase secto rs address.
2. Q7 sho uld be rechec ked ev en Q5="1" because Q7 ma y change simultaneo usly with Q5.
53
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 23. T OGGLE BIT TIMING W A VEFORMS (DURING AUT OMA TIC ALGORITHMS)
Tdf
Tce
Tch
Toe
Toeh
Taa
Trc
Toh
Address
CE#
OE#
WE#
Q6/Q2
RY/BY#
Tbusy
Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA : Valid Address
VA
Valid Data
54
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Figure 24. Toggle Bit Algorithm
Notes:
1. Read to ggle bit twice to determine whether or no t it is to ggling.
2. Recheck toggle bit because it ma y stop toggling as Q5 changes to "1".
Read Q7-Q0 Twice
Q5 = 1?
Read Q7~Q0 Twice
PGM/ERS fail
Write Reset CMD PGM/ERS Complete
Q6 Toggle ?
Q6 Toggle ?
NO
(Note 1)
YES
NO
NO
YES
YES
Start
55
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is reco mmended fo r the supply vo ltages and the co ntro l signals at device po wer-up.
If the timing in the figure is igno red, the device may not o perate correctly.
Figure A. AC Timing at Device P ower-Up
Symbol Parameter Min. Max. Unit
Tvr Vcc Rise Time 20 500000 uS/V
Tr Input Signal Rise Time 2 0 uS/V
Tf Input Signal F all Time 2 0 uS/V
Vcc
ADDRESS
CE#
WE#
OE#
DATA
Tvr
Taa
Tr or Tf Tr or Tf
Tce
Tf
Vcc(min)
GND
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh High Z
Vol
WP#/ACC
Valid
Ouput
Valid
Address
Tvcs
Tr
Toe
Tf Tr
56
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MIN. MAX.
Input Voltage voltage difference with GND on all pins except I/O pins -1.0V 12.5V
Input Voltage voltage difference with GND on all I/O pins -1.0V Vcc + 1.0V
Vcc Current -100mA +100mA
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
LIMITS
PARAMETER MIN. TYP. MAX. UNITS
Chip Erase Time MX29LV002C 4 32 sec
MX29LV004C 4 32 sec
MX29LV008C 14 sec
Sector Erase Time 0. 7 1 5 sec
Erase/Program Cycles 100,000 Cycles
Chip Programming Time MX29LV002C 4.5 13.5 sec
MX29LV004C 4.5 13.5 sec
MX29LV008C 9 27 sec
Byte Programming Time 9 300 uS
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Parameter Symbol Parameter Description Test Set TYP MAX UNIT
CIN2 Control Pin Capacitance VIN=0 12 pF
COUT Output Capacitance VOUT=0 1 2 pF
CIN Input Capacitance VIN=0 8 pF
TSOP PIN CAPACITANCE
57
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
ORDERING INFORMATION
MX29LV002C
P ART NO. Access Time Operating Current Standby Current PACKA GE Remark
(nS) MAX. (mA) MAX. (uA)
MX29LV002CTTC-70 70 3 0 5 32 Pin TSOP
MX29LV002CBTC-70 70 3 0 5 32 Pin TSOP
MX29LV002CTTC-90 90 3 0 5 32 Pin TSOP
MX29LV002CBTC-90 90 3 0 5 32 Pin TSOP
MX29LV002CTTI-70 7 0 3 0 5 32 Pin TSOP
MX29LV002CBTI-70 7 0 30 5 32 Pin TSOP
MX29LV002CTTI-90 9 0 3 0 5 32 Pin TSOP
MX29LV002CBTI-90 9 0 30 5 32 Pin TSOP
MX29LV002CTQC-70 70 3 0 5 32 Pin PLCC
MX29LV002CBQC-70 7 0 3 0 5 32 Pin PLCC
MX29LV002CTQC-90 70 3 0 5 32 Pin PLCC
MX29LV002CBQC-90 7 0 3 0 5 32 Pin PLCC
MX29LV002CTQI-70 7 0 30 5 32 Pin PLCC
MX29LV002CBQI-70 7 0 30 5 32 Pin PLCC
MX29LV002CTQI-90 7 0 30 5 32 Pin PLCC
MX29LV002CBQI-90 7 0 30 5 32 Pin PLCC
MX29LV002CTTC-70G 70 3 0 5 32 Pin TSOP PB free
MX29LV002CTTC-90G 90 3 0 5 32 Pin TSOP PB free
MX29LV002CBTC-70G 7 0 3 0 5 32 Pin TSOP PB free
MX29LV002CBTC-90G 9 0 3 0 5 32 Pin TSOP PB free
MX29LV002CTTI-70G 7 0 3 0 5 32 Pin TSOP PB free
MX29LV002CTTI-90G 9 0 3 0 5 32 Pin TSOP PB free
MX29LV002CBTI-70G 7 0 30 5 32 Pin TSOP PB free
MX29LV002CBTI-90G 9 0 30 5 32 Pin TSOP PB free
MX29LV002CTQC-70G 70 30 5 32 Pin PLCC PB free
MX29LV002CTQC-90G 90 30 5 32 Pin PLCC PB free
MX29LV002CBQC-70G 70 3 0 5 32 Pin PLCC PB free
MX29LV002CBQC-90G 90 3 0 5 32 Pin PLCC PB free
MX29LV002CTQI-70G 7 0 30 5 32 Pin PLCC PB free
MX29LV002CTQI-90G 9 0 30 5 32 Pin PLCC PB free
MX29LV002CBQI-70G 70 30 5 32 Pin PLCC PB free
MX29LV002CBQI-90G 90 30 5 32 Pin PLCC PB free
58
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PART NO. Access Time Operating Current Standby Current PACKA GE Remark
(nS) MAX. (mA) MAX. (uA)
MX29LV002NCTTC-70 7 0 30 5 32 Pin TSOP
MX29LV002NCBTC-70 7 0 3 0 5 32 Pin TSOP
MX29LV002NCTTC-90 9 0 30 5 32 Pin TSOP
MX29LV002NCBTC-90 9 0 3 0 5 32 Pin TSOP
MX29LV002NCTTI-70 70 30 5 32 Pin TSOP
MX29LV002NCBTI-70 70 30 5 32 Pin TSOP
MX29LV002NCTTI-90 90 30 5 32 Pin TSOP
MX29LV002NCBTI-90 90 30 5 32 Pin TSOP
MX29LV002NCTQC-70 7 0 3 0 5 32 Pin PLCC
MX29LV002NCBQC-70 70 30 5 32 Pin PLCC
MX29LV002NCTQC-90 7 0 3 0 5 32 Pin PLCC
MX29LV002NCBQC-90 70 30 5 32 Pin PLCC
MX29LV002NCTQI-70 7 0 3 0 5 32 Pin PLCC
MX29LV002NCBQI-70 70 30 5 32 Pin PLCC
MX29LV002NCTQI-90 7 0 3 0 5 32 Pin PLCC
MX29LV002NCBQI-90 70 30 5 32 Pin PLCC
MX29LV002NCTTC-70G 7 0 3 0 5 32 Pin TSOP PB free
MX29LV002NCTTC-90G 9 0 3 0 5 32 Pin TSOP PB free
MX29LV002NCBTC-70G 70 3 0 5 32 Pin TSOP PB free
MX29LV002NCBTC-90G 90 3 0 5 32 Pin TSOP PB free
MX29LV002NCTTI-70G 70 3 0 5 32 Pin TSOP PB free
MX29LV002NCTTI-90G 90 3 0 5 32 Pin TSOP PB free
MX29LV002NCBTI-70G 7 0 30 5 32 Pin TSOP PB free
MX29LV002NCBTI-90G 9 0 30 5 32 Pin TSOP PB free
MX29LV002NCTQC-70G 7 0 30 5 32 Pin PLCC PB free
MX29LV002NCTQC-90G 9 0 30 5 32 Pin PLCC PB free
MX29LV002NCBQC-70G 70 3 0 5 32 Pin PLCC PB free
MX29LV002NCBQC-90G 90 3 0 5 32 Pin PLCC PB free
MX29LV002NCTQI-70G 7 0 3 0 5 32 Pin PLCC PB free
MX29LV002NCTQI-90G 9 0 3 0 5 32 Pin PLCC PB free
MX29LV002NCBQI-70G 7 0 3 0 5 32 Pin PLCC PB free
MX29LV002NCBQI-90G 9 0 3 0 5 32 Pin PLCC PB free
59
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV004C
P ART NO. Access Time Operating Current Standby Current PACKA GE Remark
(nS) MAX. (mA) MAX. (uA)
MX29LV004CTTC-55R 5 5 3 0 5 40 Pin TSOP
MX29LV004CBTC-55R 55 30 5 40 Pin TSOP
MX29LV004CTTC-70 7 0 3 0 5 40 Pin TSOP
MX29LV004CBTC-70 7 0 30 5 40 Pin TSOP
MX29LV004CTTC-90 9 0 3 0 5 40 Pin TSOP
MX29LV004CBTC-90 9 0 30 5 40 Pin TSOP
MX29LV004CTTI-55R 55 30 5 40 Pin TSOP
MX29LV004CBTI-55R 5 5 30 5 40 Pin TSOP
MX29LV004CTTI-70 7 0 30 5 40 Pin TSOP
MX29LV004CBTI-70 7 0 30 5 40 Pin TSOP
MX29LV004CTTI-90 9 0 30 5 40 Pin TSOP
MX29LV004CBTI-90 9 0 30 5 40 Pin TSOP
MX29LV004CTQC-55R 5 5 3 0 5 32 Pin PLCC
MX29LV004CBQC-55R 55 3 0 5 32 Pin PLCC
MX29LV004CTQC-70 7 0 3 0 5 32 Pin PLCC
MX29LV004CBQC-70 70 30 5 32 Pin PLCC
MX29LV004CTQC-90 7 0 3 0 5 32 Pin PLCC
MX29LV004CBQC-90 70 30 5 32 Pin PLCC
MX29LV004CTQI-55R 5 5 30 5 32 Pin PLCC
MX29LV004CBQI-55R 55 3 0 5 32 Pin PLCC
MX29LV004CTQI-70 7 0 3 0 5 32 Pin PLCC
MX29LV004CBQI-70 70 30 5 32 Pin PLCC
MX29LV004CTQI-90 7 0 3 0 5 32 Pin PLCC
MX29LV004CBQI-90 70 30 5 32 Pin PLCC
MX29LV004CTTC-55Q 55 30 5 40 Pin TSOP PB free
MX29LV004CBTC-55Q 5 5 30 5 40 Pin TSOP PB free
MX29LV004CTTC-70G 70 30 5 40 Pin TSOP PB free
MX29LV004CBTC-70G 7 0 30 5 40 Pin TSOP PB free
MX29LV004CTTC-90G 90 30 5 40 Pin TSOP PB free
MX29LV004CBTC-90G 9 0 30 5 40 Pin TSOP PB free
MX29LV004CTTI-55Q 5 5 30 5 40 Pin TSOP PB free
MX29LV004CBTI-55Q 5 5 30 5 40 Pin TSOP PB free
MX29LV004CTTI-70G 7 0 30 5 40 Pin TSOP PB free
MX29LV004CBTI-70G 7 0 30 5 40 Pin TSOP PB free
MX29LV004CTTI-90G 9 0 30 5 40 Pin TSOP PB free
MX29LV004CBTI-90G 9 0 30 5 40 Pin TSOP PB free
60
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
P ART NO. Access Time Operating Current Standby Current PACKA GE Remark
(nS) MAX. (mA) MAX. (uA)
MX29LV004CTQC-55Q 5 5 3 0 5 32 Pin PLCC PB free
MX29LV004CBQC-55Q 55 30 5 32 Pin PLCC PB free
MX29LV004CTQC-70G 7 0 3 0 5 32 Pin PLCC PB free
MX29LV004CBQC-70G 70 30 5 32 Pin PLCC PB free
MX29LV004CTQC-90G 9 0 3 0 5 32 Pin PLCC PB free
MX29LV004CBQC-90G 90 30 5 32 Pin PLCC PB free
MX29LV004CTQI-55Q 55 3 0 5 32 Pin PLCC PB free
MX29LV004CBQI-55Q 55 3 0 5 32 Pin PLCC PB free
MX29LV004CTQI-70G 70 3 0 5 32 Pin PLCC PB free
MX29LV004CBQI-70G 70 3 0 5 32 Pin PLCC PB free
MX29LV004CTQI-90G 90 3 0 5 32 Pin PLCC PB free
MX29LV004CBQI-90G 90 3 0 5 32 Pin PLCC PB free
MX29LV004CTTI-45Q 4 5 30 5 40 Pin TSOP PB free
MX29LV004CBTI-45Q 4 5 30 5 40 Pin TSOP PB free
61
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
MX29LV008C
P ART NO. ACCESS OPERA TING ST ANDBY PA CKA GE Remark
TIME (nS) Current MAX. (mA) Current MAX. (uA)
MX29LV008CTTC-55R 5 5 30 5 40 Pin TSOP
MX29LV008CTTC-70 7 0 30 5 40 Pin TSOP
MX29LV008CTTC-90 9 0 30 5 40 Pin TSOP
MX29LV008CBTC-55R 55 3 0 5 40 Pin TSOP
MX29LV008CBTC-70 7 0 30 5 40 Pin TSOP
MX29LV008CBTC-90 9 0 30 5 40 Pin TSOP
MX29LV008CTTI-55R 55 30 5 40 Pin TSOP
MX29LV008CTTI-70 7 0 30 5 40 Pin TSOP
MX29LV008CTTI-90 9 0 30 5 40 Pin TSOP
MX29LV008CBTI-55R 5 5 30 5 40 Pin TSOP
MX29LV008CBTI-70 7 0 3 0 5 40 Pin TSOP
MX29LV008CBTI-90 9 0 3 0 5 40 Pin TSOP
MX29LV008CTTC-55Q 55 30 5 40 Pin TSOP Pb-free
MX29LV008CTTC-70G 70 30 5 40 Pin TSOP Pb-free
MX29LV008CTTC-90G 90 30 5 40 Pin TSOP Pb-free
MX29LV008CBTC-55Q 5 5 30 5 40 Pin TSOP Pb-free
MX29LV008CBTC-70G 7 0 30 5 40 Pin TSOP Pb-free
MX29LV008CBTC-90G 9 0 30 5 40 Pin TSOP Pb-free
MX29LV008CTTI-55Q 5 5 30 5 40 Pin TSOP Pb-free
MX29LV008CTTI-70G 7 0 30 5 40 Pin TSOP Pb-free
MX29LV008CTTI-90G 9 0 30 5 40 Pin TSOP Pb-free
MX29LV008CBTI-55Q 5 5 30 5 40 Pin TSOP Pb-free
MX29LV008CBTI-70G 7 0 30 5 40 Pin TSOP Pb-free
MX29LV008CBTI-90G 9 0 30 5 40 Pin TSOP Pb-free
62
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PART NAME DESCRIPTION
MX 29 LV 70C T T C G
OPTION:
G: Lead-free package
R: Restricted Vcc (3.0V~3.6V)
Q: Restricted Vcc (3.0V~3.6V) with Lead-free package
blank: normal
SPEED:
45: 45nS
55: 55nS
70: 70nS
90: 90nS
TEMPERATURE RANGE:
C: Commercial (0˚CC to 70˚ C)
I: Industrial (-40˚aC to 85˚ C)
PACKAGE:
Q: PLCC
T: TSOP
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
C
DENSITY & MODE:
002/002N: 2Mb, x8 Boot Block
004: 4Mb, x8 Boot Block
008: 8Mb, x8 Boot Block
TYPE:
LV: 3V
DEVICE:
29:Flash
002
63
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
PACKAGE INFORMATION
64
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
65
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
66
P/N:PM1301 REV. 1.2, NOV. 06, 2006
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
REVISION HISTORY
Revision No. Description Page Date
1.1 1. Corrected wrong CFI address data P21~23 AUG/25/2006
1. 2 1. Added statement P67 NOV/06/2006
MACRONIX INTERNATIONAL CO., LTD .
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-512-6258-0888
FAX:+86-512-6258-6799
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
Technical Support Center :
TEL:+81-44-246-9875
FAX:+81-44-246-9951
Singapore Office :
TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
MX29LV002C/002NC T/B
MX29LV004C T/B
MX29LV008C T/B
Macro nix's products are not designed, manufactured, or intended fo r use fo r any high risk applications in which the
failure of a single component could cause death, personal injury, severe physical damage, or other substantial
harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and
military applicatio n. Macronix and its suppliers will no t be liable to yo u and/o r any third party fo r any claims, injuries
o r damages that may be incurred due to use o f Macro nix's pro ducts in the pro hibited applicatio ns.
67
