Data Sheet
V1.6 2015-04
Microcontrollers
XMC1100 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex™-M0
32-bit processor core
Edition 2015-04
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein , any typical values stated herein and/or any
information regard ing the application of t he device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limit ation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements , compone nts may contain dangerous substances. For information on the types in
question, please cont act the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to ca use the failure
of that life-suppo rt device or system or to affect the safety or effectiveness of t hat device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human lif e. If they fa il, it is reasona ble to assume that th e healt h of the user or other per so ns may
be endangered.
Data Sheet
V1.6 2015-04
Microcontrollers
XMC1100 AB-Step
Microcontroller Series
for Industrial Applications
XMC1000 Family
ARM® Cortex™-M0
32-bit processor core
XMC1100 AB-Step
XMC1000 Family
Data Sheet V1.6, 2015-02
Trademarks
C166™, TriCore™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.
Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace
Buffer™ are trademarks of ARM, Limited.
XMC1100 Data Sheet
Revision History: V1.6 2015-02
Previous Version: V1.5
Page Subjects
Page 11 Chip Identification Number Table:
• The Chip Identification Numbers ar e update d with 00000C00 for every
variant.
Page 36 ADC Characteristics Table:
• Footnote 1 is added to indicate the ADC clock frequency.
• Minimum limit is changed to 2.0V, test condition for gain calibration
sample time control is added for lower supply voltage range with
internal reference.
Page 40 Temperature Sensor Charac teristics Table:
• The sensor accuracy parameter limits and test conditions are updated.
Page 50 DCO1 Characteristics Table:
• The accuracy with calibration based on temp erature senso r parameter
is removed.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve th e quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Table of Contents
Data Sheet 5 V1.6, 2015-04
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Pin Configuration and Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.3 Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 22
3 Electrical Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.2 Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.3 Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.4 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.5 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.2 Power-Up and Supply Monitoring Characteristics . . . . . . . . . . . . . . . . 48
3.3.3 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.4 Serial Wire Debug Port (SW- DP) Timing . . . . . . . . . . . . . . . . . . . . . . . 52
3.3.5 SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.3.6 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 54
3.3.6.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.3.6.3 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 59
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table of Contents
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
About this Document
Data Sheet 6 V1.6, 2015-04
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC1100 series devices.
The document describes the characteristics of a superset of the XMC1100 series
devices. For simplicity, the various device types are referred to by the collective term
XMC1100 throughout this document.
XMC1000 Family User Documentation
The set of user documentation includes:
•Reference Manu al
– decribes the functionality of the superset of devices.
•Data Sheets
– list the complete ordering designations, available features and electrical
characteristics of derivative devices.
•Errata Sheets
– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc1000 to get access to the latest versions
of those documents.
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
Data Sheet 7 V1.6, 2015-04
1 Summary of Features
The XMC1100 de vices are members of the XMC1000 famil y of microcontrollers base d
on the ARM Cortex-M0 processor core. The XMC1100 series devices are designed for
general purpose applications.
Figure 1 System Block Diagram
CPU Subsystem
•CPU Core
– High-performance 32-bit ARM Cortex-M0 CPU
– Most 16-bit Thumb and subset of 32-bit Thumb2 instructio n set
– Single cycle 32-bit hardware multiplier
16k
SRAM
64k + 0.5k
1)
Flash
8k ROM
PRNG
Memories
SCU
WDT
PORTS
Fl ash S FRs
RTC
CCU40
1) 0.5kby tes of s ec tor 0 ( r eadable only).
AHB-L i t e Bu s
16-bit APB Bus
AHB to APB
Bridge
PAU
Cortex-M0
CPU
Debug
system SPD
SWD
NVIC
USIC0
VADC
ERU0
EVR
T em per ature s ensor
2 x DCO
A n alog system
ANAC TRL SFRs
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
Data Sheet 8 V1.6, 2015-04
– System timer (SysTick) for Operating System support
– Ultra low power consumption
• Nested Vectored Interrupt Controller (NVIC)
• Event Request Unit (ERU) for processing of external and internal service requests
On-Chip Memories
• 8 kbytes on-chip ROM
• 16 kbytes on-chip high-speed SRAM
• up to 64 kbytes on-chip Flash program and data memory
On-Chip Peripherals
• Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI,
quad-SPI, IIC, IIS and LIN interfaces
• A/D Converters
– up to 12 channels
– 12-bit analog to digital converter
• Capture/Compare Units 4 (CCU4) for use as general purpose timers
• Window Watchdog Timer (WDT) for safety sensitive applications
• Real Time Clock module with alarm supp ort (RT C)
• System Control Unit (SCU) for system configuration and control
• Pseudo random number generator (PRNG) for fast random data generation
• Temperature Sensor (TSE)
Input/Output Li ne s With In div id ual Bit Controllability
• Tri-stated in input mode
• Push/pull or open drain outpu t mode
• Configurable pad hysteresis
Debug System
• Access through the standard ARM serial wire debug (SW D) or the single p in debu g
(SPD) in terface
• A breakpoint un i t (BPU ) sup po rting up to 4 hardware breakpoints
• A watchpoint unit (DW T) supporting up to 2 watchpoints
1.1 Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:
• <DDD> the derivatives function set
• <Z> the package variant
– T: TSSOP
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
Data Sheet 9 V1.6, 2015-04
–Q: VQFN
• <PPP> package pin count
• <T> the temperature range:
– F: -40°C to 85°C
– X: -40°C to 105°C
• <FFFF> the Flash me mo ry size.
For ordering codes for the XMC1100 plea se contact your sales representative or local
distributor.
This document describes several derivatives of the XMC1100 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC1100 is used for all derivatives throughout this document.
1.2 Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
Table 1 Synopsis of XMC1100 Device Types
Derivative Package Flash
Kbytes SRAM
Kbytes
XMC1100-T016F0008 PG-TSSOP-16-8 8 16
XMC1100-T016F0016 PG-TSSOP-16-8 16 16
XMC1100-T016F0032 PG-TSSOP-16-8 32 16
XMC1100-T016F0064 PG-TSSOP-16-8 64 16
XMC1100-T016X0016 PG-TSSOP-16-8 16 16
XMC1100-T016X0032 PG-TSSOP-16-8 32 16
XMC1100-T016X0064 PG-TSSOP-16-8 64 16
XMC1100-T038F0016 PG-TSSOP-38-9 16 16
XMC1100-T038F0032 PG-TSSOP-38-9 32 16
XMC1100-T038F0064 PG-TSSOP-38-9 64 16
XMC1100-T038X0064 PG-TSSOP-38-9 64 16
XMC1100-Q024F0008 PG-VQFN-24-19 8 16
XMC1100-Q024F0016 PG-VQFN-24-19 16 16
XMC1100-Q024F0032 PG-VQFN-24-19 32 16
XMC1100-Q024F0064 PG-VQFN-24-19 64 16
XMC1100-Q040F0016 PG-VQFN-40-13 16 16
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
Data Sheet 10 V1.6, 2015-04
1.3 Device Type Features
The following table lists the available features per device type.
1.4 Chip Identification Number
The Chip Identification Number allows software to identify the markin g. It is a 8 words
value with the most significant 7 words stored in Flash configuration sector 0 (CS0) at
address location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word and
most significant word of the Chip Identification Number are the value of registers
DBGROMID and IDCHIP, respectively.
XMC1100-Q040F0032 PG-VQFN-40-13 32 16
XMC1100-Q040F0064 PG-VQFN-40-13 64 16
Table 2 Features of XMC1100 Device Types1)
1) Features that are not included in this table are available in all the derivatives
Derivative ADC channel
XMC1100-T016 6
XMC1100-T038 12
XMC1100-Q024 8
XMC1100-Q040 12
Table 3 ADC Channels
Package VADC0 G0 VADC0 G1
PG-TSSOP-16 CH0..CH5 -
PG-TSSOP-38 CH0..CH7 CH1, CH5 .. CH7
PG-VQFN-24 CH0..CH7 -
PG-VQFN-40 CH0..CH7 CH1, CH5 .. CH7
Table 1 Synopsis of XMC1100 Device Types (cont’d)
Derivative Package Flash
Kbytes SRAM
Kbytes
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
Data Sheet 11 V1.6, 2015-04
Table 4 XMC1100 Chip Identification Number
Derivative Value Marking
XMC1100-T016F0008 00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00003000 201ED083H
AB
XMC1100-T016F0016 00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
AB
XMC1100-T016F0032 00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
AB
XMC1100-T016F0064 00011032 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
AB
XMC1100-T016X0016 00011033 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
AB
XMC1100-T016X0032 00011033 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
AB
XMC1100-T016X0064 00011033 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
AB
XMC1100-T038F0016 00011012 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
AB
XMC1100-T038F0032 00011012 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
AB
XMC1100-T038F0064 00011012 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
AB
XMC1100-T038X0064 00011013 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
AB
XMC1100-Q024F0008 00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00003000 201ED083H
AB
XMC1100-Q024F0016 00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
AB
XMC1100-Q024F0032 00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
AB
XMC1100-Q024F0064 00011062 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
AB
XMC1100-Q040F0016 00011042 01CF00FF 00001F37 00000000
00000C00 00001000 00005000 201ED083H
AB
Subject to Agreement on the Use of Product Information
XMC1100
XMC1000 Family
Summary of Features
Data Sheet 12 V1.6, 2015-04
XMC1100-Q040F0032 00011042 01CF00FF 00001F37 00000000
00000C00 00001000 00009000 201ED083H
AB
XMC1100-Q040F0064 00011042 01CF00FF 00001F37 00000000
00000C00 00001000 00011000 201ED083H
AB
Table 4 XMC1100 Chip Identification Number (cont’d)
Derivative Value Marking
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 13 V1.6, 2015-04
2 General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC1100 Logic Symbol for TSSOP-38 and TSSOP-16
XMC1100
TSSOP-38
V
DDP
(2)
V
SSP
(2)
Port 0
16 bit
Port 1
6bit
Port 2
4 bi t
XMC1100
TSSOP-16
V
DDP
(1)
V
SSP
(1)
Port 2
8 bi t
Port 0
8 bi t
Port 2
3 bi t
Port 2
3 bi t
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 14 V1.6, 2015-04
Figure 3 XMC1100 Logic Symbol for VQFN-24 and VQFN-40
XMC1100
VQFN-40
V
DD
(1) V
SS
(1)
Port 0
16 bit
Port 1
7 bit
Port 2
4 bit
Port 2
8 bit
V
DDP
(2) V
SSP
(1)
XMC1100
VQFN-24
V
DDP
(1) V
SSP
(1)
Port 0
10 bit
Port 1
4 bit
Port 2
4 bit
Port 2
4 bit
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 15 V1.6, 2015-04
2.2 Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the different
packages.
Figure 4 XMC1100 PG-TSSOP-38 Pin Configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
37
36
35
34
33
32
31
30
29
38
P2.5
P2.6
P2.7
P0.10
V
SSP
/V
SS
V
DDP
/V
DD
P0.13
P0.14
P2.1
P2.0
P2.2
P0.11
P0.12
P1.4 P0.8
P0.9
P2.10
P2.9
P2.3P2.4
P2.11
V
DDP
P1.3
P1.2 V
SSP
15
16
17
18
19
24
23
22
21
20
P2.8
P1.5
P1.0
P0.0
P0.1
P1.1
P0.2
P0.6
P0.7
P0.4
P0.5
P0.3
P0.15
Top View
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 16 V1.6, 2015-04
Figure 5 XMC1100 PG-TSSOP-16 Pin Configuration (top view)
Figure 6 XMC1100 PG-VQFN-24 Pin Configuration (top view)
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
16P2.7/P2.8
V
SSP
/V
SS
V
DDP
/V
DD
P2.10
P2.9
P2.11
P0.5
P0.0
Top View
P0.14
P2.0
P0.8
P0.9
P2.6
P0.6
P0.7
P0.15
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 17 V1.6, 2015-04
Figure 7 XMC1100 PG-VQFN-40 Pin Configuration (top view)
123 45678910
11
13
14
15
24 23 22 21 20
19
18
17
16
36
35
34
33
32
31 30 29 28 27 26 25
37
38
39
40
P0.13
P0.12
P2.0
V
DDP
V
SSP
V
DDP
P1.6
P1.5
P1.4
P0.1
P0.2
P0.0
P1.1
P1.0
P0.11
12
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
V
SS
V
DD
P1.3
P1.2
P0.6
P0.7
P0.5
P0.3
P0.4
P0.10
P0.9
P0.8
P0.15
P0.14
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 18 V1.6, 2015-04
2.2.1 Package Pin Summary
The following general building block is used to describe each pin:
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the supply pins.
The following columns, title d with the supported package variants, lists the pa ckage pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type:
• STD_INOUT (standard bi-directional pads)
• STD_INOUT/AN (standard bi-directional pads with analog input)
• High Current (high current bi-directional pads)
• STD_IN/AN (standard input pads with an alog input)
• Power (power supply)
Details about the pad properties are defined in the Electrical Parameters.
Table 5 Package Pin Mapping Description
Function Package A Package B ... Pad Type
Px.y N N Pad Class
Table 6 Package Pin Mapping
Function VQFN
40 TSSOP
38 VQFN
24 TSSOP
16 Pad Type Notes
P0.0 23 17 15 7 STD_INOUT
P0.1 24 18 - - STD_INOUT
P0.2 25 19 - - STD_INOUT
P0.3 26 20 - - STD_INOUT
P0.4 27 21 - - STD_INOUT
P0.5 28 22 16 8 STD_INOUT
P0.6 29 23 17 9 STD_INOUT
P0.7 30 24 18 10 STD_INOUT
P0.8 33 27 19 11 STD_INOUT
P0.9 34 28 20 12 STD_INOUT
P0.10 35 29 - - STD_INOUT
P0.11 36 30 - - STD_INOUT
P0.12373121- STD_INOUT
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 19 V1.6, 2015-04
P0.13383222- STD_INOUT
P0.1439332313STD_INOUT
P0.1540342414STD_INOUT
P1.0 22 16 14 - High Current
P1.1 21 15 13 - High Current
P1.2 20 14 12 - High Current
P1.3 19 13 11 - High Current
P1.4 18 12 - - High Current
P1.5 17 11 - - High Current
P1.6 16 - - - STD_INOUT
P2.0 1 35 1 15 STD_INOUT/
AN
P2.1 2 36 2 - STD_INOUT/
AN
P2.2 3 37 3 - STD_IN/AN
P2.3 4 38 - - STD_IN/AN
P2.4 5 1 - - STD_IN/AN
P2.5 6 2 - - STD_IN/AN
P2.673416STD_IN/AN
P2.78451STD_IN/AN
P2.89551STD_IN/AN
P2.9 10 6 6 2 STD_IN/AN
P2.10 11 7 7 3 STD_INOUT/
AN
P2.11 12 8 8 4 STD_INOUT/
AN
VSS 13 9 9 5 Power Supply GND, ADC
reference GND
VDD 14 10 10 6 Power Supply VDD, ADC
reference voltage/
ORC reference
voltage
Table 6 Package Pin Mapping
Function VQFN
40 TSSOP
38 VQFN
24 TSSOP
16 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 20 V1.6, 2015-04
2.2.2 Port I/O Function Description
The following general building block is used to describe the I/O functions of each PORT
pin:
VDDP 15 10 10 6 Power When VDD is
supplied, VDDP has
to be supplied with the
same voltage.
VSSP 31 25 - - Power I/O port ground
VDDP 32 26 - - Power I/O port supply
VSSP Exp.
Pad -Exp.
Pad -Power Expo sed Die Pad
The exposed die pad
is connected internally
to VSSP. For proper
operation, it is
mandatory to connect
the exposed pad to
the board ground. For
thermal aspects,
please refer to the
Package and
Reliability chapter.
Table 7 Port I/O Function Description
Function Outputs Inputs
ALT1 ALTn Input Input
P0.0 MODA.OUT MODC.INA
Pn.y MODA.OUT MODA.INA MODC.INB
Table 6 Package Pin Mapping
Function VQFN
40 TSSOP
38 VQFN
24 TSSOP
16 Pad Type Notes
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 21 V1.6, 2015-04
Figure 8 Simplified Port Structure
Pn.y is the port pin name , d efinin g the con t rol and data bi ts/registers associ ated with i t.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single port
pin, selected by Pn_IOCR.PC. The output value is directly driven by the respective
module, with the pi n characteristics controlled by the port registers (wi thin the limits of
the connected pad).
The port pin input can be connected to mult iple peripherals. Most peripherals have an
input multiplexer to select between different possi b l e in put sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
Please refer to the Port I/O Functions table for the complete Port I/O function mapping.
XMC1000
Pn.y
V
DDP
GND
Pn.y
ALT1
...
ALTn
HWO0
HWO1
SW
Control Logi c
Input 0
Input n
...
PAD
HWI0
HWI1
MODB.OUT
MODB
MODA
MODA.INA
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
General Device Information
Data Sheet 22 V1.6, 2015-04
2.2.3 Hardware Controlled I/O Function Description
The following general building block is used to describe the hardware I/O and pull control
functions of each PORT pin:
By Pn_HWSEL, it is possible to select between different hardware “masters”
(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).
Hardware control overrules settings in the respective port pin registers. Additional
hardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by the
peripherals can be used to control the pull devices of the pin.
Please refer to the Hardware Controlled I/O Functions table for the complete hardware
I/O and pull control function mapping.
Table 8 Hardware Controlled I/O Function Description
Function Outputs Inputs Pull Control
HWO0 HWI0 HW0_PD HW0_PU
P0.0 MODB.OUT MODB.INA
Pn.y MODC.OUT MODC.OUT
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Data Sheet 23 V1.6, 2015-04
Table 9 Port I/O Functions
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 Input Input Input Input Input Input Input
P0.0 ERU0.
PDOUT0 ERU0.
GOUT0 CCU40.OUT
0USIC0_CH0.
SELO0 USIC0_CH1.
SELO0 CCU40.IN0C USIC0_CH0.
DX2A USIC0_CH1.
DX2A
P0.1 ERU0.
PDOUT1 ERU0.
GOUT1 CCU40.OUT
1SCU.
VDROP CCU40.IN1C
P0.2 ERU0.
PDOUT2 ERU0.
GOUT2 CCU40.OUT
2VADC0.
EMUX02 CCU40.IN2C
P0.3 ERU0.
PDOUT3 ERU0.
GOUT3 CCU40.OUT
3VADC0.
EMUX01 CCU40.IN3C
P0.4 CCU40.OUT
1VADC0.
EMUX00 WWDT.
SERVICE_O
UT
P0.5 CCU40.OUT
0
P0.6 CCU40.OUT
0USIC0_CH1.
MCLKOUT USIC0_CH1.
DOUT0 CCU40.IN0B USIC0_CH1.
DX0C
P0.7 CCU40.OUT
1USIC0_CH0.
SCLKOUT USIC0_CH1.
DOUT0 CCU40.IN1B USIC0_CH0.
DX1C USIC0_CH1.
DX0D USIC0_CH1.
DX1C
P0.8 CCU40.OUT
2USIC0_CH0.
SCLKOUT USIC0_CH1.
SCLKOUT CCU40.IN2B USIC0_CH0.
DX1B USIC0_CH1.
DX1B
P0.9 CCU40.OUT
3USIC0_CH0.
SELO0 USIC0_CH1.
SELO0 CCU40.IN3B USIC0_CH0.
DX2B USIC0_CH1.
DX2B
P0.10 USIC0_CH0.
SELO1 USIC0_CH1.
SELO1 USIC0_CH0.
DX2C USIC0_CH1.
DX2C
P0.11 USIC0_CH0.
MCLKOUT USIC0_CH0.
SELO2 USIC0_CH1.
SELO2 USIC0_CH0.
DX2D USIC0_CH1.
DX2D
P0.12 USIC0_CH0.
SELO3 CCU40.IN0A CCU40.IN1A CCU40.IN2A CCU40.IN3A USIC0_CH0.
DX2E
P0.13 WWDT.
SERVICE_O
UT
USIC0_CH0.
SELO4 USIC0_CH0.
DX2F
P0.14 USIC0_CH0.
DOUT0 USIC0_CH0.
SCLKOUT USIC0_CH0.
DX0A USIC0_CH0.
DX1A
P0.15 USIC0_CH0.
DOUT0 USIC0_CH1.
MCLKOUT USIC0_CH0.
DX0B
P1.0 CCU40.OUT
0USIC0_CH0.
DOUT0 USIC0_CH0.
DX0C
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Data Sheet 24 V1.6, 2015-04
P1.1 VADC0.
EMUX00 CCU40.OUT
1USIC0_CH0.
DOUT0 USIC0_CH1.
SELO0 USIC0_CH0.
DX0D USIC0_CH0.
DX1D USIC0_CH1.
DX2E
P1.2 VADC0.
EMUX01 CCU40.OUT
2USIC0_CH1.
DOUT0 USIC0_CH1.
DX0B
P1.3 VADC0.
EMUX02 CCU40.OUT
3USIC0_CH1.
SCLKOUT USIC0_CH1.
DOUT0 USIC0_CH1.
DX0A USIC0_CH1.
DX1A
P1.4 VADC0.
EMUX10 USIC0_CH1.
SCLKOUT USIC0_CH0.
SELO0 USIC0_CH1.
SELO1 USIC0_CH0.
DX5E USIC0_CH1.
DX5E
P1.5 VADC0.
EMUX11 USIC0_CH0.
DOUT0 USIC0_CH0.
SELO1 USIC0_CH1.
SELO2 USIC0_CH1.
DX5F
P1.6 VADC0.
EMUX12 USIC0_CH1.
DOUT0 USIC0_CH0.
SCLKOUT USIC0_CH0.
SELO2 USIC0_CH1.
SELO3 USIC0_CH0.
DX5F
P2.0 ERU0.
PDOUT3 CCU40.OUT
0ERU0.
GOUT3 USIC0_CH0.
DOUT0 USIC0_CH0.
SCLKOUT VADC0.
G0CH5 ERU0.0B0 USIC0_CH0.
DX0E USIC0_CH0.
DX1E USIC0_CH1.
DX2F
P2.1 ERU0.
PDOUT2 CCU40.OUT
1ERU0.
GOUT2 USIC0_CH0.
DOUT0 USIC0_CH1.
SCLKOUT VADC0.
G0CH6 ERU0.1B0 USIC0_CH0.
DX0F USIC0_CH1.
DX3A USIC0_CH1.
DX4A
P2.2 VADC0.
G0CH7 ERU0.0B1 USIC0_CH0.
DX3A USIC0_CH0.
DX4A USIC0_CH1.
DX5A
P2.3 VADC0.
G1CH5 ERU0.1B1 USIC0_CH0.
DX5B USIC0_CH1.
DX3C USIC0_CH1.
DX4C
P2.4 VADC0.
G1CH6 ERU0.0A1 USIC0_CH0.
DX3B USIC0_CH0.
DX4B USIC0_CH1.
DX5B
P2.5 VADC0.
G1CH7 ERU0.1A1 USIC0_CH0.
DX5D USIC0_CH1.
DX3E USIC0_CH1.
DX4E
P2.6 VADC0.
G0CH0 ERU0.2A1 USIC0_CH0.
DX3E USIC0_CH0.
DX4E USIC0_CH1.
DX5D
P2.7 VADC0.
G1CH1 ERU0.3A1 USIC0_CH0.
DX5C USIC0_CH1.
DX3D USIC0_CH1.
DX4D
P2.8 VADC0.
G0CH1 VADC0.
G1CH0 ERU0.3B1 USIC0_CH0.
DX3D USIC0_CH0.
DX4D USIC0_CH1.
DX5C
P2.9 VADC0.
G0CH2 VADC0.
G1CH4 ERU0.3B0 USIC0_CH0.
DX5A USIC0_CH1.
DX3B USIC0_CH1.
DX4B
P2.10 ERU0.
PDOUT1 CCU40.OUT
2ERU0.
GOUT1 USIC0_CH1.
DOUT0 VADC0.
G0CH3 VADC0.
G1CH2 ERU0.2B0 USIC0_CH0.
DX3C USIC0_CH0.
DX4C USIC0_CH1.
DX0F
P2.11 ERU0.
PDOUT0 CCU40.OUT
3ERU0.
GOUT0 USIC0_CH1.
SCLKOUT USIC0_CH1.
DOUT0 VADC0.
G0CH4 VADC0.
G1CH3 ERU0.2B1 USIC0_CH1.
DX0E USIC0_CH1.
DX1E
Table 9 Port I/O Functions (cont’d)
Function Outputs Inputs
ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 Input Input Input Input Input Input Input
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Data Sheet 25 V1.6, 2015-04
Table 1 0 Hardware Controlled I/O Functions
Function Outputs Inputs Pull Control
HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.10
P0.11
P0.12
P0.13
P0.14
P0.15
P1.0 USIC0_CH0. DOUT0 USIC0_CH0. HWIN0
P1.1 USIC0_CH0. DOUT1 USIC0_CH0. HWIN1
P1.2 USIC0_CH0. DOUT2 USIC0_CH0. HWIN2
P1.3 USIC0_CH0. DOUT3 USIC0_CH0. HWIN3
P1.4
P1.5
P1.6
P2.0
P2.1
P2.2 CCU40.OUT3 CCU40.OUT3
P2.3
P2.4
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Data Sheet 26 V1.6, 2015-04
P2.5
P2.6 CCU40.OUT3 CCU40.OUT3
P2.7 CCU40.OUT3 CCU40.OUT3
P2.8 CCU40.OUT2 CCU40.OUT2
P2.9 CCU40.OUT2 CCU40.OUT2
P2.10
P2.11
Table 1 0 Hardware Controlled I/O Functions (cont’d)
Function Outputs Inputs Pull Control
HWO0 HWO1 HWI0 HWI1 HW0_PD HW0_PU HW1_PD HW1_PU
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 27 V1.6, 2015-04
3 Electrical Parameter
This section provides the electrical parameter which are implementation-specific for the
XMC1100.
3.1 General Parameters
3.1.1 Parameter Interpretation
The parameters listed in this section represent partly the characteristics of the XMC1100
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are indicated by the abbreviations in the
“Symbol” column:
•CC
Such parameters indicate Controller Characteristics, wh ich ar e distinctive feature of
the XMC1100 and must be regarded for a system design.
•SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC1100 is designed in.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 28 V1.6, 2015-04
3.1.2 Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
3.1.3 Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 12 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
• full operation life-time is not exceeded
•Operating Co nditions are met for
– pad supply levels (VDDP)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
Table 11 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Cond
ition
Min. Typ. Max.
Junction temperature TJ SR -40 – 115 °C–
Storage temperature TST SR -40 – 125 °C–
Voltage on power supply pin
with respect to VSSP
VDDP SR -0.3 – 6 V –
Voltage on any pin with
respect to VSSP
VIN SR -0.5 – VDDP + 0.5
or max. 6 V whichever
is lower
Voltage on any analog input
pin with respect to VSSP
VAIN
VAREF SR -0.5 – VDDP + 0.5
or max. 6 V–
Input current on any pin
during overload condition IIN SR -10 – 10 mA –
Absolute maximum sum of all
input currents during overload
condition
ΣIIN SR -50 – +50 mA –
Analog comparator input
voltage VCM SR -0.3 – VDDP + 0.3 V
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 29 V1.6, 2015-04
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations li ke short to battery.
Figure 9 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Figure 9 Input Overload Current via ESD structur es
Table 13 and Table 14 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as de fined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 12 Overload Para meters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin
during overload condition IOV SR -5 – 5 mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR – – 25 mA
Pn.y IOVx
GND
ESD Pad
GND
VDDP
VDDP
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 30 V1.6, 2015-04
Table 13 PN-Junction Characterisitics for positive Overload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=115°C
Standard,
High-current,
AN/DIG_IN
VIN =VDDP +0.5V VIN =VDDP +0.5V
Table 14 PN-Junction Characterisitics for negative Ov erload
Pad Type IOV =5mA, TJ=-40°C IOV =5mA, TJ=115°C
Standard,
High-current,
AN/DIG_IN
VIN =VSS -0.5V VIN =VSS -0.5V
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 31 V1.6, 2015-04
3.1.4 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC1100. All parameters specified in the following tables
refer to these operating conditions, unless noted otherw ise.
Table 15 Operating Conditions Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Ambient Temperature TA SR -40 −85 °C Temp. Range F
-40 −105 °C Temp. Range X
Digital supply voltage1)
1) See also the Supply Monitoring thresholds, Chapter 3.3.2.
VDDP SR 1.8 −5.5 V
MCLK Frequency fMCLK CC −−33.2 MHz CPU clock
PCLK Frequency fPCLK CC −−66.4 MHz Peripherals
clock
Short circuit current of
digital outputs ISC SR -5 −5mA
Absolute sum of short
circuit currents of the
device
ΣISC_D SR −−25 mA
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 32 V1.6, 2015-04
3.2 DC Parameters
3.2.1 Input/Output Characteristics
Table 16 provides the characteristics of the input/output pins of the XMC1100.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 16 Input/Output Characteristics (Operating Conditions ap ply)
Parameter Symbol Limit Values Unit Test Conditions
Min. Max.
Output low voltage on
port pins
(with standard pads)
VOLP CC – 1.0 V IOL = 11 mA (5 V)
IOL = 7 mA (3.3 V)
–0.4V
IOL = 5 mA (5 V)
IOL = 3.5 mA (3.3 V)
Output low voltage on
high current pads VOLP1 CC – 1.0 V IOL = 50 mA (5 V)
IOL = 25 mA (3.3 V)
–0.32V
IOL = 10 mA (5 V)
–0.4V
IOL = 5 mA (3.3 V)
Output high voltage on
port pins
(with standard pads)
VOHP CC VDDP -
1.0 –VIOH = -10 mA (5 V)
IOH = -7 mA (3.3 V)
VDDP -
0.4 –VIOH =-4.5mA (5V)
IOH =-2.5mA (3.3V)
Output high voltage on
high current pads VOHP1 CC VDDP -
0.32 –VIOH = -6 mA (5 V)
VDDP -
1.0 –VIOH = -8 mA (3.3 V)
VDDP -
0.4 –VIOH = -4 mA (3.3 V)
Input low voltage on port
pins
(Standard Hysteresis)
VILPS SR – 0.19 ×
VDDP
V CMOS Mode
(5 V, 3.3 V & 2.2 V)
Input high voltage on
port pins
(Standard Hysteresis)
VIHPS SR 0.7 ×
VDDP
–VCMOS Mode
(5 V, 3.3 V & 2.2 V)
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 33 V1.6, 2015-04
Input low voltage on port
pins
(Large Hysteresis)
VILPL SR – 0.08 ×
VDDP
V CMOS Mode
(5 V, 3.3 V & 2.2 V)10)
Input high voltage on
port pins
(Large Hysteresis)
VIHPL SR 0.85 ×
VDDP
–VCMOS Mode
(5 V, 3.3 V & 2.2 V)10)
Rise time on High
Current Pad1) tHCPR CC – 9 ns 50 pF @ 5 V2)
– 12 ns 50 pF @ 3.3 V3)
– 25 ns 50 pF @ 1.8 V4)
Fall time on High
Current Pad1) tHCPF CC – 9 ns 50 pF @ 5 V2)
– 12 ns 50 pF @ 3.3 V3)
– 25 ns 50 pF @ 1.8 V4)
Rise time on Standard
Pad1) tRCC – 12 ns 50 pF @ 5 V5)
– 15 ns 50 pF @ 3.3 V6)
– 31 ns 50 pF @ 1.8 V7)
Fall time on Standard
Pad1) tFCC – 12 ns 50 pF @ 5 V5)
– 15 ns 50 pF @ 3.3 V6)
– 31 ns 50 pF @ 1.8 V7)
Input Hysteresis8) HYS CC 0.08 ×
VDDP
– V CMOS Mode (5 V),
Standard Hysteresis
0.03 ×
VDDP
– V CMOS Mode (3.3 V),
Standard Hysteresis
0.02 ×
VDDP
– V CMOS Mode (2.2 V),
Standard Hysteresis
0.5 ×
VDDP
0.75 ×
VDDP
V CMOS Mode(5 V),
Large Hysteresis
0.4 ×
VDDP
0.75 ×
VDDP
V CMOS Mode(3.3 V),
Large Hysteresis
0.2 ×
VDDP
0.65 ×
VDDP
V CMOS Mode(2.2 V),
Large Hysteresis
Table 16 Input/Output Characteristics (Operating Conditions ap ply) (cont’d)
Parameter Symbol Limit Values Unit Test Conditions
Min. Max.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 34 V1.6, 2015-04
Pin capacitance (digital
inputs/outputs) CIO CC – 10 pF
Pull-up resistor on port
pins RPUP CC 20 50 kohm VIN = VSSP
Pull-down resistor on
port pins RPDP CC 20 50 kohm VIN = VDDP
Input leakage current9) IOZP CC -1 1 μA0 < VIN < VDDP,
TA≤105 °C
Voltage on any pin
during VDDP power off VPO SR – 0.3 V 10)
Maximum current per
pin (excluding P1, VDDP
and VSS)
IMP SR -10 11 mA –
Maximum current per
high currrent pins IMP1A SR -10 50 mA –
Maximum current into
VDDP (TSSOP28/16,
VQFN24)
IMVDD1 SR – 130 mA 10)
Maximum current into
VDDP (TSSOP38,
VQFN40)
IMVDD2 SR – 260 mA 10)
Maximum current out of
VSS (TSSOP28/16,
VQFN24)
IMVSS1 SR – 130 mA 10)
Maximum current out of
VSS (TSSOP38,
VQFN40)
IMVSS2 SR – 260 mA 10)
1) Rise/Fall time parameters are taken with 10% - 90% of supply.
2) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.150 ns/pF at 5 V supply voltage.
3) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.
4) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.
5) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.225 ns/pF at 5 V supply voltage.
6) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.
7) Additional rise/fall time valid for CL=50pF-C
L= 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.
Table 16 Input/Output Characteristics (Operating Conditions ap ply) (cont’d)
Parameter Symbol Limit Values Unit Test Conditions
Min. Max.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 35 V1.6, 2015-04
8) Hysteresis is implemented to avoid meta stable st ates a nd switching due to intern al g round bo unce. It cannot
be guaranteed that it suppresses switch ing due to external system noise.
9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.
10)However, for applications with strict low power-down current requirements, it is mandatory that no active
voltage source is supplied at any GPIO pin when VDDP is powere d off.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 36 V1.6, 2015-04
3.2.2 An a lo g to Dig ita l Co n ve r te rs (ADC )
Table 17 shows the Analog to Digital Converter (ADC) characteristics.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 17 ADC Characteristics (Operating Conditions apply) 1)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Supply voltage range
(internal reference) VDD_int SR 2.0 – 3.0 V SHSCFG.AREF =
11B
CALCTR.CALGN
STC = 0CH
3.0 – 5.5 V SHSCFG.AREF =
10B
Supply voltage range
(external reference) VDD_ext SR 3.0 – 5.5 V SHSCFG.AREF =
00B
Analog input voltage
range VAIN SR VSSP
- 0.05 –VDDP
+ 0.05 V
Auxiliary analog
reference ground VREFGND SR VSSP
- 0.05 – 1.0 V G0CH0
VSSP
- 0.05 – 0.2 V G1CH0
Internal reference
voltage (full scale
value)
VREFINT CC 5 V
Switched capacitance
of an analog input CAINS CC – 1.2 2 pF GNCTRxz.GAINy
= 00B (unity gain)
– 1.2 2 pF GNCTRxz.GAINy
= 01B (gain g1)
– 4.5 6 pF GNCTRxz.GAINy
= 10B (gain g2)
– 4.5 6 pF GNCTRxz.GAINy
= 11B (gain g3)
Total capacitance of an
analog input CAINT CC – – 10 pF
Total capaci tance of
the reference input CAREFT CC – – 10 pF
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 37 V1.6, 2015-04
Gain settings GIN CC 1 – GNCTRxz.GAINy
= 00B (unity gain)
3 – GNCTRxz.GAINy
= 01B (gain g1)
6 – GNCTRxz.GAINy
= 10B (gain g2)
12 – GNCTRxz.GAINy
= 11B (gain g3)
Sample Time tsample CC 3 – – 1 /
fADC
VDD = 5.0 V
3 – – 1 /
fADC
VDD = 3.3 V
30 – – 1 /
fADC
VDD = 2.0 V
Sigma delta loop hold
time tSD_hold CC 20 – – μs Residual charge
stored in an active
sigma delta lo op
remains available
Conversion time
in fast compare mode tCF CC 9 1 /
fADC
2)
Conversion time
in 12-bit mode tC12 CC 20 1 /
fADC
2)
Maximum sample rate
in 12-bit mode 3) fC12 CC – – fADC /
42.5 –1 sample
pending
––
fADC /
62.5 – 2 samples
pending
Conversion time
in 10-bit mode tC10 CC 18 1 /
fADC
2)
Maximum sample rate
in 10-bit mode 3) fC10 CC – – fADC /
40.5 –1 sample
pending
––
fADC /
58.5 – 2 samples
pending
Conversion time
in 8-bit mode tC8 CC 16 1 /
fADC
2)
Table 17 ADC Characteristics (Operating Conditions apply) (cont’d)1)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 38 V1.6, 2015-04
Maximum sample rate
in 8-bit mode 3) fC8 CC – – fADC /
38.5 –1 sample
pending
––
fADC /
54.5 – 2 samples
pending
RMS noise 4) ENRMS CC – 1.5 – LSB
12 DC input,
VDD = 5.0 V,
VAIN = 2.5 V,
25°C
DNL error EADNL CC – ±2.0 – LSB
12
INL error EAINL CC – ±4.0 – LSB
12
Gain error with external
reference EAGAIN CC – ±0.5 – % SHSCFG.AREF =
00B (calibrated)
Gain error with internal
reference 5) EAGAIN CC – ±3.6 – % SHSCFG.AREF =
1XB (calibrated),
-40°C - 105°C
– ±2.0 – % SHSCFG.AREF =
1XB (calibrated),
0°C - 85°C
Offset error EAOFF CC – ±8.0 – mV Calibrated,
VDD = 5.0 V
1) The parameters are defined for ADC clock frequency fSH = 32MHz.
2) No pending samples assumed, excluding sampling time and calibration.
3) Includes synchronization and calibration (average of gain and offset calibration).
4) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(AMAXeff / NRMS).
With AMAXeff = 2N / 2, SNR[dB] = 20 × log ( 2048 / NRMS) [N = 12].
NRMS = 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.
5) Includes error from the reference voltage.
Table 17 ADC Characteristics (Operating Conditions apply) (cont’d)1)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 39 V1.6, 2015-04
Figure 10 ADC Voltage Supply
MC_VADC_AREFPATHS
AREF
:
V
AGND
SAR
Converter
V
CAL
VSS
VDD Internal
Reference
REFSEL
0 1
00 1X
V
DD
CH7
.
.
CH0
V
DDint
/
V
DDext
V
AIN
V
REFGND
V
REFINT
CHNR
V
AREF
V
REF
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 40 V1.6, 2015-04
3.2.3 Temperature Sensor Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 18 Temperature Sensor Characteristics
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Measurement time tM CC −−10 ms
Temperature sensor range TSR SR -40 −115 °C
Sensor Accuracy1)
1) The temperature sensor accuracy is independent of the supply voltage.
TTSAL CC -6 – 6 °C TJ > 20°C
-10 – 10 °C 0°C ≤ TJ ≤ 20°C
-18 – 18 °C -25°C ≤ TJ < 0°C
-31 – 31 °C -40°C ≤ TJ < -25°C
Start-up time after enabling tTSSTE SR −−15 μs
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 41 V1.6, 2015-04
3.2.4 Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lowe r than those given in the followi ng tables,
and depend on the custo mer's system operat ing condi tions (e.g . thermal connecti on or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19 Power Supply Parameters; VDDP = 5V
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ.1) Max.
Active mode current
Peripherals enabled
fMCLK / fPCLK in MH z 2)
IDDPAE CC −8.4 11.0 mA 32 / 64
−7.3 −mA 24 / 48
−6.1 −mA 16 / 32
−5.1 −mA 8 / 16
−3.7 −mA 1 / 1
Active mode current
Peripherals disabled
fMCLK / fPCLK in MH z 3)
IDDPAD CC −4.7 −mA 32 / 64
−4.1 −mA 24 / 48
−3.3 −mA 16 / 32
−2.6 −mA 8 / 16
−1.5 −mA 1 / 1
Active mode current
Code execution from RAM
Flash is powered down
fMCLK / fPCLK in MH z
IDDPAR CC −6.3 −mA 32 / 64
−5.4 −mA 24 / 48
−4.6 −mA 16 / 32
−3.8 −mA 8 / 16
−3.0 −mA 1 / 1
Sleep mode current
Peripherals clock enabled
fMCLK / fPCLK in MH z 4)
IDDPSE CC −5.9 −mA 32 / 64
5.4 −mA 24 / 48
4.8 −mA 16 / 32
4.3 −mA 8 / 16
3.7 −mA 1 / 1
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 42 V1.6, 2015-04
Sleep mode current
Peripherals clock disa bled
Flash active
fMCLK / fPCLK in MH z 5)
IDDPSD CC −1.8 −mA 32 / 64
1.7 −mA 24 / 48
1.6 −mA 16 / 32
1.5 −mA 8 / 16
1.4 −mA 1 / 1
Sleep mode current
Peripherals clock disa bled
Flash powered down
fMCLK / fPCLK in MH z 6)
IDDPSR CC −1.2 −mA 32 / 64
1.1 −mA 24 / 48
1.0 −mA 16 / 32
0.8 −mA 8 / 16
0.7 −mA 1 / 1
Deep Sleep mode current7) IDDPDS CC −0.24 −mA
Wake-up time from Sleep to
Active mode8) tSSA CC −6−cycles
Wake-up time from Deep
Sleep to Active mode9) tDSA CC −280 −μsec
1) The typical values are measured at TA=+25°C and VDDP =5V.
2) CPU and all peripherals clock enabled, Flash is in active mode.
3) CPU enabled, all peripherals clock disabled, Flash is in active mode.
4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.
5) CPU in sleep, Flash is in active mode.
6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.
7) CPU in sleep, peripherals cl ock disabled, Flash is powered down and code e xecuted from RAM after wake-up.
8) CPU in sleep, Flash is in active mode during sleep mode.
9) CPU in sleep, Flash is in powered down mode during deep sleep mode.
Table 19 Power Supply Parameters; VDDP = 5V (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ.1) Max.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 43 V1.6, 2015-04
Figure 11 shows typical graphs for active mode supply current for VDDP = 5V, VDDP =
3.3V, VDDP = 1.8V across different clock frequencies.
Figure 11 Active mode, a) peripherals clocks enabled, b) peripherals clocks
disabled: Supply current IDDPA over supply voltage VDDP for different
clock frequencies
Condition:
1. TA=+25°C
0
1
2
3
4
5
6
7
8
9
1/1 8/16 16/32 24/48 32/64
I (mA)
MCLK / PCLK (MHz)
IDDPAE 5 V /3 .3 V
IDDPAE 1 .8 V
IDDPAD
5V/3.3V/1.8V
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 44 V1.6, 2015-04
Figure 12 shows typical graphs for sleep mode current for VDDP = 5V, VDDP = 3.3V, VDDP
= 1.8V across different clock frequencies.
Figure 12 Sleep mode, peripherals clocks disabled, Fla sh powered down:
Supply current IDDPSR over supply voltage VDDP for different clock
frequencies
Conditions:
1. TA=+25°C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1/1 8/16 16/32 24/48 32/64
I (mA )
MCLK / PCLK (MHz)
IDDPSR
5V/3.3V/1.8V
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 45 V1.6, 2015-04
Table 20 provides the active current consumption of some modules operating at 5 V
power supply at 25
°
C. The typical values shown are used as a reference guide on the
current consumption when these modules are enabled.
Table 20 Typical Active Current Consumption
Active Current
Consumption Symbol Limit
Values Unit Test Condition
Typ.
Baseload current ICPUDDC 5.04 mA Modules including Core, SCU,
PORT, memories, ANATOP1)
1) Baseload current is measured with device run ning in user mode, MCLK =PCLK=32 MHz, with an endless loop
in the flash memory. The clock to the modules stated in CGATSTAT0 are gated.
VADC and SHS IADCDDC 3.4 mA Set CGATCLR0.VADC to 12)
2) Active current is measured with: module enab led, MCLK=32 MHz, running in auto-scan conversion mode
USIC0 IUSIC0DDC 0.87 mA Set CGATCLR0.USIC0 to 13)
3) Active current is measured with: module enabled, al ternating messages sent to PC at 57.6kbaud every 200ms
CCU40 ICCU40DDC 0.94 mA Set CGATCLR0.CCU40 to 14)
4) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switching
from 1500Hz and 1000Hz at regula r intervals, 1 CCU4 slice in capture mod e for reading period and duty cycle
WDT IWDTDDC 0.03 mA Set CGATCLR0.WDT to 15)
5) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB =
0x00008000; WDT serviced every 1s
RTC IRTCDDC 0.01 mA Set CGATCLR0.RTC to 16)
6) Active current is measured with: module enabled, MCL K=32 MHz, Periodic interrupt enabled
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 46 V1.6, 2015-04
3.2.5 Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 21 Flash Memory Parameters
Parameter Symbol Valu e s Unit Note /
Test Condition
Min. Typ. Max.
Erase Time per page tERASE CC 6.8 7.1 7.6 ms
Program time per block tPSER CC 102 152 204 μs
Wake-Up time tWU CC −32.2 −μs
Read time per word ta CC −50 −ns
Data Retention Time tRET CC 10 −− years Max. 100 erase /
program cycles
Flash Wait States 1)
1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typical
values are calculated from the execution of the Dhrystone benchmark program.
NWSFLASH CC 0 0 0 fMCLK = 8 MHz
011 fMCLK = 16 MHz
11.32 fMCLK = 32 MHz
Erase Cycles per page NECYC CC −−5*104cycles
Total Erase Cycles NTECYC CC −−2*106cycles
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 47 V1.6, 2015-04
3.3 AC Parameters
3.3.1 Testing Waveforms
Figure 13 Rise/Fall Time Parameters
Figure 14 Testing Waveform, Output Delay
Figure 15 Testing Waveform, Output High Imp ed ance
10%
90%
V
SS
V
DDP
t
R
t
F
10%
90%
V
DDP
/ 2 V
DDP
/ 2
V
DDP
V
SS
Test Points
VLOAD + 0.1 V Timing
Reference
Points
VLOAD -0.1V
VOH -0.1V
VOL + 0.1V
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 48 V1.6, 2015-04
3.3.2 Power-Up and Supply Monitoring Characteristics
Table 22 provides th e characteristics of the supply monitoring in XMC1100.
The guard band between the lowest valid operating voltage and the brownout reset
threshold provides a margin for noise immunity and hysteresis. The electrical
parameters may be violated while VDDP is outside its operating range.
The brownout detection triggers a reset within the defined range. The prewarning
detection can be used to trigger an early warning and issue corrective and/or fail-safe
actions in case of a critical supply voltage drop.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 22 Power-Up and Supply Monitoring Parameters (Operating Conditions
apply) 1)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
VDDP ramp-up time tRAMPUP SR VDDP/
SVDDPrise
−107μs
VDDP slew rate SVDDPOP SR 0 −0.1 V/μs Slope during
normal operation
SVDDP10 SR 0 −10 V/μs Slope during fast
transient within +/-
10% of VDDP
SVDDPrise SR 0 −10 V/μs Sl ope during
power-on or
restart after
brownout event
SVDDPfall2) SR 0 −0.25 V/μs Slope during
supply falling out
of the +/-10%
limits3)
VDDP prewarning
voltage VDDPPW CC 2.1 2.25 2.4 V ANAVDEL.VDEL_
SELECT = 00B
2.85 3 3.15 V ANAVDEL.VDEL_
SELECT = 01B
4.2 4.4 4.6 V ANAVDEL.VDEL_
SELECT = 10B
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 49 V1.6, 2015-04
Figure 16 Supply Threshold Parameters
VDDP brownout reset
voltage VDDPBO CC 1.55 1.62 1.75 V calibrated, before
user code starts
running
VDDP voltage to
ensure defined pad
states
VDDPPA CC −1.0 −V
Start-up time from
power-on reset tSSW SR −320 – μs Time to the first
user code
instruction in all
start-up modes4)
BMI program time tBMI SR −8.25 – ms Time taken from a
user-triggered
system reset after
BMI installation is
is requested
1) Not all parameters are 100% tested, but are verified by design/characterisation.
2) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as stated for
this parameter.
3) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forward ed only to
the chip. A larger capacitor value has to be chosen if the power source sink a current.
4) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHz
and the clocks to peripheral as specified in register CGATSTAT0 are gated.
Table 22 Power-Up and Supply Monitoring Parameters (Operating Conditions
apply) (cont’d)1)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
VDDP }
5.0V
V
DDPPW
V
DDPBO
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 50 V1.6, 2015-04
3.3.3 On-Chip Oscillator Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 23 provides the characteristics of the 64 MHz clock output from the digital
controlled oscillator, DCO1 in XMC1100.
Table 23 64 MHz DCO1 Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Condition s
Min. Typ. Max.
Nominal frequency fNOM CC – 64 – MHz under nominal
conditions1) after
trimming
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA=+25 °C.
Accuracy2)
2) The accuracy of the DCO1 oscill at or can be further improved through alte rnat ive methods, ref er to XMC1000
Oscillator Handling Application Note.
ΔfLT CC -1.7 – 3.4 % with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9 – 4.0 % with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 51 V1.6, 2015-04
Figure 17 shows the typical curves for the accuracy of DCO1, with and without
calibration based on temperature sensor, respectively.
Figure 17 Typical DCO1 accuracy over temperatu re
Table 24 provides the characteristics of the 32 kHz clock ou tput from digital controlled
oscillators, DCO2 in XMC1100.
Table 24 32 kHz DCO2 Characteristics (Operating Conditions apply)
Parameter Symbol Limit Values Unit Test Conditions
Min. Typ. Max.
Nominal frequency fNOM CC – 32.75 – kHz under nominal
conditions1) after trimming
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA=+25 °C.
Accuracy ΔfLT CC -1.7 – 3.4 % with respect to fNOM(typ),
over temperature
(0 °C to 85 °C)
-3.9 – 4.0 % with respect to fNOM(typ),
over temperature
(-40 °C to 105 °C)
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Accuracy [%]
Temperature [ C]
Without calibration based
on temperature sensor
With calibration based on
temperature sensor
°
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 52 V1.6, 2015-04
3.3.4 Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 18 SWD Timing
Table 25 SWD Interface Timing Parameters(Opera ting Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SWDCLK high time t1 SR 50 – 500000 ns –
SWDCLK low time t2 SR 50 – 500000 ns –
SWDIO input setup
to SWDCLK rising edge t3 SR 10 – – ns –
SWDIO input hold
after SWDCLK rising edge t4 SR 10 – – ns –
SWDIO output valid time
after SWDCLK rising edge t5 CC – – 68 ns CL=50pF
– – 62 ns CL=30pF
SWDIO output hold time
from SWDCLK rising edge t6 CC 4 – – ns
SWDCLK
SWDIO
(Output)
t
1
t
2
t
6
t
5
SWDIO
(Input)
t
3
t
4
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 53 V1.6, 2015-04
3.3.5 SPD Timing Requirements
The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value the
system has maximum robustness against frequency deviations of the sampling clock on
tool and on device side. However it is not always possible to exactly match this value
with the given constraints fo r the sample clock. For instance for a o versampling rate of
4, the sample clock will be 8 MHz and in this case the closest possible effective decision
time is 5.5 clock cycles (0.69 µs).
For a balanced distribution of the timing robustness of SPD between tool and device, the
timing requirements for the tool are:
• Frequency devi ation of the sample clock is +/- 5%
• Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Table 26 Optimum Number of Sample Clocks for SPD
Sample
Freq. Sampling
Factor Sample
Clocks 0B
Sample
Clocks 1B
Effective
Decision
Time1)
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks)
Remark
8 MHz 4 1 to 5 6 to 12 0.69 µs The other closes t option
(0.81 µs) for the effective
decision time is less robust.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 54 V1.6, 2015-04
3.3.6 Peripheral Timings
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: Operating Conditions apply.
Table 27 USIC SSC Master Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SCLKOUT master clock
period tCLK CC 62.5 −− ns
Slave select output SELO
active to first SCLKOUT
transmit edg e
t1 CC 80 −− ns
Slave select output SELO
inactive afte r last
SCLKOUT receive edge
t2 CC 0 −− ns
Data output DOUT[3:0]
valid time t3 CC -10 −10 ns
Receive data input
DX0/DX[5:3] setup time to
SCLKOUT receive edge
t4 SR 80 −− ns
Data input DX0/DX[5:3]
hold time from SCLKOU T
receive edg e
t5 SR 0 −− ns
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 55 V1.6, 2015-04
Table 28 USIC SSC Slave Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DX1 slave clock period tCLK SR 125 −− ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
1) These input timings are valid for asynchron ous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
t10 SR 10 −− ns
Select input DX2 hold after
last clock input DX1 receive
edge1)
t11 SR 10 −− ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
t12 SR 10 −− ns
Data input DX0/DX[5:3] hold
time from clock input DX1
receive edg e1)
t13 SR 10 −− ns
Data output DOUT[3:0] valid
time t14 CC - −80 ns
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 56 V1.6, 2015-04
Figure 19 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock O utput
SCLKOUT
Data Output
DOUT[3:0]
t
3
t
3
t
5
Data
valid
t
4
First Transmit
Edge
Data Input
DX0/DX[5:3]
Sel ect Ou tput
SELOx
Active
Master Mode Ti m ing
S l ave Mode Tim i ng
t
11
t
10
Clock I nput
DX1
Data Output
DOUT[3:0]
t
14
t
14
Data
valid
Data Input
DX0/DX[5:3]
Select Input
DX2
Active
t
13
t
12
Transmit Edge: with this clock edge, transmit data is shifted to transm it da ta output.
Receive Edge: with this clock edge, receive data at receive data input i s latched.
Receive
Edge Last Receive
Edge
InactiveInactive
Trans mit
Edge
InactiveInactive
Firs t Transm it
Edge Receive
Edge Transm it
Edge Last Receive
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH.SCLK CFG = 00B. Also val id for for SCLKCFG = 01B with inverted SCLKOUT s ignal.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 57 V1.6, 2015-04
3.3.6.2 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: Operating Conditions apply.
Table 29 USIC IIC Standard Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open -drain mode. The high level on th ese lines must be held by an extern al pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR --300ns
Rise time of both SDA and
SCL t2
CC/SR - - 1000 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 250 - - ns
LOW period of SCL clock t5
CC/SR 4.7 - - µs
HIGH period of SCL clock t6
CC/SR 4.0 - - µs
Hold time for (repeated)
START condition t7
CC/SR 4.0 - - µs
Set-up time for repeated
START condition t8
CC/SR 4.7 - - µs
Set-up time for STOP
condition t9
CC/SR 4.0 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 4.7 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 58 V1.6, 2015-04
Table 30 USIC IIC Fast Mode Timing 1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open -drain mode. The high level on th ese lines must be held by an extern al pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL t1
CC/SR 20 +
0.1*Cb
2)
2) Cb refers to the total capacitance of one bus line in pF.
- 300 ns
Rise time of both SDA and
SCL t2
CC/SR 20 +
0.1*Cb
- 300 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 100 - - ns
LOW period of SCL clock t5
CC/SR 1.3 - - µs
HIGH period of SCL clock t6
CC/SR 0.6 - - µs
Hold time for (repeated)
START condition t7
CC/SR 0.6 - - µs
Set-up time for repeated
START condition t8
CC/SR 0.6 - - µs
Set-up time for STOP
condition t9
CC/SR 0.6 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 1.3 - - µs
Capacitive load for each
bus line Cb SR - - 400 pF
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 59 V1.6, 2015-04
Figure 20 USIC IIC Stand and Fast Mode Timing
3.3.6.3 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: Operating Conditions apply.
Table 31 USIC IIS Master Tr an sm itter Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t1 CC 2/fMCLK --nsVDDP ≥ 3 V
4/fMCLK --nsVDDP < 3 V
Clock HIGH t2 CC 0.35 x
t1min
--ns
Clock Low t3 CC 0.35 x
t1min
--ns
Hold time t4 CC 0 - - ns
Clock rise time t5 CC - - 0.15 x
t1min
ns
SCL
SDA
SCL
SDA
t
1
t
2
t
1
t
2
t
10
t
9
t
7
t
8
t
7
t
3
t
4
t
5
t
6
PSSr
S
70%
30%
9
th
clock
9
th
clock
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Electrical Parameter
Data Sheet 60 V1.6, 2015-04
Figure 21 USIC IIS Master Tr an smitter Timing
Figure 22 USIC IIS Slave Receiver Timing
Table 32 USIC IIS Slave Receiver Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t6 SR 4/fMCLK --ns
Clock HIGH t7 SR 0.35 x
t6min
--ns
Clock Low t8 SR 0.35 x
t6min
--ns
Set-up time t9 SR 0.2 x
t6min
--ns
Hold time t10 SR 10 - - ns
SCK
WA/
DOUT
t
1
t
5
t
3
t
2
t
4
SCK
WA/
DIN
t
6
t
10
t
8
t
7
t
9
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Data Sheet 61 V1.6, 2015-04
4 Package and Reliability
The XMC1100 is a member of the XMC1000 Derivatives of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the exposed die pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1 Package Parameters
Table 33 provides th e thermal characteristics of the packages used in XMC1100.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSSP, independent of EMC and thermal requirements.
4.1.1 Thermal Considerations
When operating the XMC1100 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting the rma l
damage.
The maximum heat that can be dissipated depend s on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 115 °C.
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
Table 33 Thermal Characteristics of the Packages
Parameter Symbol Limit Values Unit Package Types
Min. Max.
Exposed Die Pad
Dimensions Ex × Ey
CC -2.7×2.7 mm PG-VQFN-24-19
-3.7×3.7 mm PG-VQFN-40-13
Thermal resistance
Junction-Ambient RΘJA CC - 104.6 K/W PG-TSSOP-16-81)
1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered .
- 70.3 K/W PG-TSSOP-38-91)
- 46.0 K/W PG-VQFN-24-191)
- 38.4 K/W PG-VQFN-40-131)
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Data Sheet 62 V1.6, 2015-04
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage curren t).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
• Reduce VDDP, if possible in the system
• Reduce the system frequency
• Reduce the number of output pins
• Reduce the load on active output drivers
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Data Sheet 63 V1.6, 2015-04
4.2 Package Outlines
Figure 23 PG-TSSOP-38-9
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Data Sheet 64 V1.6, 2015-04
Figure 24 PG-TSSOP-16-8
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Data Sheet 65 V1.6, 2015-04
Figure 25 PG-VQFN-24-19
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Package and Reliability
Data Sheet 66 V1.6, 2015-04
Figure 26 PG-VQFN-40-13
All dimensions in mm.
Subject to Agreement on the Use of Product Information
XMC1100 AB-Step
XMC1000 Family
Quality Declaration
Data Sheet 67 V1.6, 2015-04
5 Quality Declaration
Table 34 shows the characteristics of the quality parameters in the XMC1100.
Table 34 Quality Parameters
Parameter Symbol Limit Values Unit Notes
Min. Max.
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
SR - 2000 V Conforming to
EIA/JESD22-
A114-B
ESD susceptibility
according to Charged
Device Model (CDM) pins
VCDM
SR - 500 V Conforming to
JESD22-C101-C
Moisture sensitivity level MSL
CC - 3 - JEDEC
J-STD-020D
Soldering te mp erature TSDR
SR - 260 °C Profile according
to JEDEC
J-STD-020D
Subject to Agreement on the Use of Product Information
www.infineon.com
Published by Infineon Technologies AG