Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. E
01/29/08
IS62WV5128ALL
IS62WV5128BLL
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
512K x 8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation
36 mW (typical) operating
9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
1.65V – 2.2V VDD (IS62WV5128ALL)
2.5V – 3.6V VDD (IS62WV5128BLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial temperature available
• Lead-free available
DESCRIPTION
The ISSI IS62WV5128ALL / IS62WV5128BLL are high-
speed, 4M bit static RAMs organized as 512K words by 8
bits. It is fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-
performance and low power consumption devices.
When CS1 is HIGH (deselected) the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE) controls both writing and reading of the memory.
The IS62WV5128ALL and IS62WV5128BLL are packaged
in the JEDEC standard 32-pin TSOP (TYPE I), 32-pin
sTSOP (TYPE I), 32-pin TSOP (Type II), 32-pin SOP and
36-pin mini BGA.
FUNCTIONAL BLOCK DIAGRAM
JANUARY 2008
A0-A18
CS1
OE
WE
512K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
PIN DESCRIPTIONS
A0-A18 Address Inputs
CS1 Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
NC No Connection
VDD Power
GND Ground
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0
I/O4
I/O5
GND
VDD
I/O6
I/O7
A9
A1
A2
OE
A10
NC
WE
NC
A18
CS1
A11
A3
A4
A5
A17
A16
A12
A6
A7
A15
A13
A8
I/O0
I/O1
VDD
GND
I/O2
I/O3
A14
36-pin mini BGA (B) (6mm x 8mm)
(Package Code B)
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
32-pin TSOP (TYPE I), (Package Code T)
32-pin sTSOP (TYPE I) (Package Code H)
32-pin SOP (Package Code Q)
32-pin TSOP (TYPE II) (Package Code T2)
PIN DESCRIPTIONS
A0-A18 Address Inputs
CS1 Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
VDD Power
GND Ground
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
A18
A15
V
DD
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A15
A18
WE
A13
A8
A9
A11
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
V
DD
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions VDD Min. Max. Unit
VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V
IOH = -1 mA 2.5-3.6V 2.2 — V
VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V
IOL = 2.1 mA 2.5-3.6V — 0.4 V
VIH Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V
2.5-3.6V 2.2 VDD + 0.3 V
VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V
2.5-3.6V –0.2 0.6 V
ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA
Notes:
1. VIL (min.) = –1.0V for pulse width less than 10 ns.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.2 to VDD+0.3 V
VDD VDD Related to GND –0.2 to VDD+0.3 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
OPERATING RANGE (VDD)
Range Ambient Temperature IS62WV5128ALL IS62WV5128BLL
Commercial 0°C to +70°C 1.65V - 2.2V 2.5V - 3.6V
Industrial –40°C to +85°C 1.65V - 2.2V 2.5V - 3.6V
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
AC TEST LOADS
Figure 1 Figure 2
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Input/Output Capacitance VOUT = 0V 10 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter IS62WV5128ALL IS62WV5128BLL
(Unit) (Unit)
Input Pulse Level 0.4V to VDD-0.2V 0.4V to VDD-0.3V
Input Rise and Fall Times 5 ns 5ns
Input and Output Timing VREF VREF
and Reference Level
Output Load See Figures 1 and 2 See Figures 1 and 2
IS62WV5128ALL IS62WV5128BLL
1.65 - 2.2V 2.5V - 3.6V
R1(Ω) 3070 3070
R2(Ω) 3150 3150
VREF 0.9V 1.5V
VTM 1.8V 2.8V
R1
30 pF
Including
jig and
scope
R2
OUTPUT
VTM
R1
5 pF
Including
jig and
scope
R2
OUTPUT
VTM
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV5128ALL (1.65V - 2.2V)
Symbol Parameter Test Conditions Max. Unit
70 ns
ICC VDD Dynamic Operating VDD = Max., Com. 25 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 30
ICC1Operating Supply VDD = Max., CS1 = 0.2V Com. 10 mA
Current WE = VDD-0.2V Ind. 10
f=1MHZ
ISB1TTL Standby Current VDD = Max., Com. 0.35 mA
(TTL Inputs) VIN = VIH or VIL Ind. 0.35
CS1 = VIH,
f = 1 MHZ
ISB2CMOS Standby VDD = Max., Com. 15 µA
Current (CMOS Inputs) CS1
≥
V DD – 0.2V, Ind. 15
VIN
≥
V DD – 0.2V, or
VIN
≤
0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
62WV5128BLL (2.5V - 3.6V)
Symbol Parameter Test Conditions Max. Unit
55 ns
ICC VDD Dynamic Operating VDD = Max., Com. 40 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. 45
ICC1Operating Supply VDD = Max., CS1 = 0.2V Com. 15 mA
Current WE = VDD-0.2V Ind. 15
f=1MHZ
ISB1TTL Standby Current VDD = Max., Com. 0.35 mA
(TTL Inputs) VIN = VIH or VIL Ind. 0.35
CS1 = VIH,
f = 1 MHZ
ISB2CMOS Standby VDD = Max., Com. 15 µA
Current (CMOS Inputs) CS1 ≥ VDD – 0.2V, Ind. 15
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, WE = VIH)
DATA VALID
PREVIOUS DATA VALID
tAA
tOHA tOHA
tRC
D
OUT
ADDRESS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
55 ns 70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 55 — 70 — ns
tAA Address Access Time — 55 — 70 ns
tOHA Output Hold Time 10 — 10 — ns
tACS1 CS1 Access Time — 55 — 70 ns
tDOE OE Access Time — 25 — 35 ns
tHZOE(2) OE to High-Z Output — 20 — 25 ns
tLZOE(2) OE to Low-Z Output 5 — 5 — ns
tHZCS1 CS1 to High-Z Output 0 20 0 25 ns
tLZCS1 CS1 to Low-Z Output 10 — 10 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS1, OE Controlled)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS1= VIL. WE=VIH.
3. Address is valid prior to or coincident with CS1 LOW transition.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS1
t
LZCS1
t
HZOE
HIGH-Z DATA VALID
t
HZCS
ADDRESS
OE
CS1
DOUT
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
55 ns 70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 55 — 70 — ns
tSCS1 CS1 to Write End 45 — 60 — ns
tAW Address Setup Time to Write End 45 — 60 — ns
tHA Address Hold from Write End 0 — 0 — ns
tSA Address Setup Time 0 — 0 — ns
tPWE WE Pulse Width 40 — 50 — ns
tSD Data Setup to Write End 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE(3) WE LOW to High-Z Output — 20 — 20 ns
tLZWE(3) WE HIGH to Low-Z Output 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4V to
VDD-0.2V/VDD-0.3V and output loading specified in Figure 1.
2.
The internal write time is defined by the overlap of CS1 LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CS1
WE
DOUT
DIN
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCS1
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
OE
CS1
WE
DOUT
DIN
DATA-IN VALID
DATA UNDEFINED
t
WC
tSCS1
tAW
tHA
tPWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
OE
CS1
WE
DOUT
DIN
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Test Condition Min. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 1.2 3.6 V
IDR Data Retention Current VDD = 1.2V, CS1 ≥ VDD – 0.2V — 15 µA
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
DATA RETENTION WAVEFORM (CS1CS1
CS1CS1
CS1 Controlled)
VDD
CS1 ≥ VDD - 0.2V
t
SDR
t
RDR
V
DR
CS1
GND
Data Retention Mode
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
01/29/08
IS62WV5128ALL, IS62WV5128BLL
ORDERING INFORMATION
IS62WV5128ALL (1.65V-2.2V)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
70 IS62WV5128ALL-70TI TSOP, TYPE I
70 IS62WV5128ALL-70T2I TSOP, TYPE II
70 IS62WV5128ALL-70HI sTSOP, TYPE I
70 IS62WV5128ALL-70BI mini BGA (6mmx8mm)
ORDERING INFORMATION
IS62WV5128BLL (2.5V - 3.6V)
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
55 IS62WV5128BLL-55H sTSOP, TYPE I
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
55 IS62WV5128BLL-55TI TSOP, TYPE I
55 IS62WV5128BLL-55TLI TSOP, TYPE I, Lead-free
55 IS62WV5128BLL-55QLI SOP, Lead-free
55 IS62WV5128BLL-55T2I TSOP, TYPE II
55 IS62WV5128BLL-55T2LI TSOP, TYPE II, Lead-free
55 IS62WV5128BLL-55HI sTSOP, TYPE I
55 IS62WV5128BLL-55HLI sTSOP, TYPE I, Lead-free
55 IS62WV5128BLL-55BI mini BGA (6mmx8mm)
55 IS62WV5128BLL-55BLI mini BGA (6mmx8mm), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
06/18/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
eC
1N/2
N/2+1N
E1
A1
A
E
Lα
ZD
.
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 32 44 50
A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830
E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471
e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024
ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF
α0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°
PACKAGING INFORMATION
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
06/13/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic TSOP-Type I
Package Code: T (32-pin)
D
SEATING PLANE
B
eC
1
N
E
A1
A
S
H
Lα
Notes:
1. Controlling dimension: millimeters, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect
to one another within 0.004 inches at the
seating plane.
MILLIMETERS INCHES
Symbol Min. Max. Min. Max.
No. Leads 32
A — 1.20 — 0.047
A1 0.05 0.25 0.002 0.010
B 0.17 0.23 0.007 0.009
C 0.12 0.17 0.005 0.007
D 7.90 8.10 0.311 0.319
E 18.30 18.50 0.720 0.728
H 19.80 20.20 0.780 0.795
e 0.50 BSC 0.020 BSC
L 0.40 0.60 0.016 0.024
α0° 8° 0° 8°
S 0.25 REF 0.010 REF
PACKAGING INFORMATION
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
06/13/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
450-mil Plastic SOP
Package Code: Q (32-pin)
D
SEATING PLANE
B
eC
1
N
E1
A1
A
E
Lα
S
MILLIMETERS INCHES
Symbol Min. Max. Min. Max.
No. Leads 32
A — 3.00 — 0.118
A1 0.10 — 0.004 —
B 0.36 0.51 0.014 0.020
C 0.15 0.30 0.006 0.012
D 20.14 20.75 0.793 0.817
E 13.87 14.38 0.546 0.566
E1 11.18 11.43 0.440 0.450
e 1.27 BSC 0.050 BSC
L 0.58 0.99 0.023 0.039
α0° 10° 0° 10°
S — 0.86 — 0.034
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
Integrated Silicon Solution, Inc.
PACKAGING INFORMATION
Plastic STSOP - 32 pins
Package Code: H (Type I)
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
Plastic STSOP (H - Type I)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
N 32
A — 1.25 — 0.049
A1 0.05 — 0.002 —
A2 0.95 1.05 0.037 0.041
b 0.17 0.23 0.007 0.009
C 0.14 0.16 0.0055 0.0063
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.50 BSC 0.020 BSC
L 0.30 0.70 0.012 0.028
S 0.28 Typ. 0.011 Typ.
α0° 5° 0° 5°
PK13197H32 Rev. B 04/21/03
D1
SEATING PLANE
C
D
1N
e
S
b
A1
A
A2
E
Lα
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. E
01/15/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
PACKAGING INFORMATION
Mini Ball Grid Array
Package Code: B (36-pin)
Notes:
1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 36 36
A — — 1.20 — — 0.047
A1 0.24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 7.90 8.00 8.10 0.311 0.315 0.319
D1 5.25BSC 0.207BSC
E 5.90 6.00 6.10 0.232 0.236 0.240
E1 3.75BSC 0.148BSC
e 0.75BSC 0.030BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
mBGA - 8mm x 10mm
MILLIMETER INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
N0.
Leads 36 36
A — — 1.20 — — 0.047
A1 0.24 — 0.30 0.009 — 0.012
A2 0.60 — — 0.024 — —
D 9.90 10.00 10.10 0.390 0.394 0.398
D1 5.25BSC .207BSC
E 7.90 8.00 8.10 0.311 0.315 0.319
E1 3.75BSC 0.148BSC
e 0.75BSC 0.030BSC
b 0.30 0.35 0.40 0.012 0.014 0.016
SEATING PLANE
A
A1
A2
A
B
C
D
E
F
G
H
e
e
D1
E1E
D
φ b (36x)
Top View Bottom View
6 5 4 3 2 11 2 3 4 5 6
A
B
C
D
E
F
G
H
