NCP81243 Dual Output 3 & 2 Phase Controller with Single Intel Proprietary Interface for Desktop and Notebook CPU Applications The NCP81243 dual output three plus two phase buck solutions are optimized for Intel(R)'s IMVP8 CPUs. The NCP81243 offer five PWM drive signals that can be configured in multiple setups. The controller combines true differential voltage sensing, differential inductor DCR current sensing, input voltage feed-forward, and adaptive voltage positioning to provide accurately regulated power for both desktop and notebook applications. The control system is based on Dual-Edge pulse-width modulation (PWM) combined with DCR current sensing providing an ultra fast initial response to dynamic load events and reduced system cost. The NCP81243 provides the mechanism to shed phases during light load operation and can auto frequency scale in light load conditions while maintaining excellent transient performance. Dual high performance operational error amplifiers are provided to simplify compensation of the complete system. Patented Dynamic Reference Injection further simplifies loop compensation by eliminating the need to compromise between closed-loop transient response and Dynamic VID performance. Patented Total Current Summing provides highly accurate current monitoring for droop and digital current monitoring. Features * Meets Intel's IMVP8 Specification * Current Mode Dual Edge Modulation for Fast Initial Response to * * * * * * * * * * * * Transient Loading Dual High Performance Operational Error Amplifier One Digital Soft Start Ramp for Both Rails Dynamic Reference Injection Accurate Total Summing Current Amplifier DAC with Droop Feed-forward Injection Dual High Impedance Differential Voltage and Total Current Sense Amplifiers Phase-to-Phase Dynamic Current Balancing "Lossless" DCR Current Sensing for Current Balancing Summed Compensated Inductor Current Sensing for Droop True Differential Current Balancing Sense Amplifiers for Each Phase Adaptive Voltage Positioning (AVP) Switching Frequency Range of 300 kHz - 1.4 MHz (c) Semiconductor Components Industries, LLC, 2017 June, 2017 - Rev. 2 www.onsemi.com MARKING DIAGRAM 1 52 NCP81243 FAWLYYWW G QFN52 MN SUFFIX CASE 485BE NCP81243 = Specific Device Code F = Wafer Fab A = Assembly Site WL = Lot ID YY = Year WW = Work Week G = Pb-Free Package ORDERING INFORMATION Device Package Shipping NCP81243MNTXG QFN52 (Pb-Free) 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. * Startup into Pre-Charged Loads while Avoiding False OVP * Pin Programmable Power Saving Phase Shedding * Vin Feed Forward Ramp Slope * Over Voltage Protection (OVP) & Under Voltage * * * Protection (UVP) Over Current Protection (OCP) Dual Power Good Output with Internal Delays These Devices are Pb-Free and are RoHS Compliant Applications * Desktop & Notebook Processors * Gaming 1 Publication Order Number: NCP81243/D VCCGT {5} VCCGT_SENSE {5} VSSGT_SENSE VCCCORE {5} VCCCORE_SENSE {5} VSSCORE_SENSE LABEL AS "DIGITAL INTERFACE" 130 2 R155 1 2 2 VCCGT 2 1 J80 1 J82 ILIMA R251 R248 1 2PIN 2 1 R250 1 1 100 2 0.0 2 0.0 2 100 2 100 R48 0.0 R257 23K 2 0.0 2 100 2 2 R249 1 R3 1 2PIN J13 R2 1 R34 1 1 VSENSEGT VSENSE CORE DNP 1 2 J81 C240 1nF C341 1nF C51 2.2nF 1 1 VSP 220K RT132 R252 75.0K {4} 2 {4} VSNA {4} VSN place close to L1 C241 360pF VSPA{4} 1nF 2 2.10K 2 2 2.10K 2 C237 2.2nF C342 R304 1 1 R303 1 1 R253 165K CSSUMA C94 0.1uF CSP1A 2 R263 1 1 7 RT126 220K 136K 2 1 R256 4.7K 2 1 FSW=400K J32 J45 {4} VR_RDY C86 1uF 2 0.1uF C242 1 R309 2 {4} VR_HOT R154 32K 1 2 34.2K 2 J26 2 21.5K 2 C235 0.1uF DNP 1 R261 1 10.0 2 C236 0.1uF 1 C82 VCC J61 J63 J62 C79 1uF 1 IOUTA R245 0.0 DNP C346 ILIM J8 1 2 3 4 5 6 7 8 9 10 11 12 13 R18 40K VSPA VSNA IOUT EN SDIO ALERT SCLK VR_RDY VCC ROSC VRMP PROG PIN TSENSEA VRHOT IOUTA 1 CSCOMP CSSUM CSREF CSP3 CSN3 CSP2 CSN2 U6 NCP81243-DNP 2 J42 C155 1.2nF place close to L1 Auxiliary rail R246 15K TSENSEA SWN1A{4} CSN1A{4} J79 VSN COMP FB DIFFOUT VSP TSENSEA VCC SR=10mV/us, 4+1 config R244 75K 1 SDIO 1 ALERT# 1 SCLK R40 1.0K +VDC_IN RT131 220K 1 ROSC VRMP 10nF R247 1 2 1 IOUT R71 2.2 J56 1 +5V_IN C61 0.1uF 1 R38 1 place close to L1 MAIN RAIL R32 15K TSENSE R125 0.0 1000pF C340 +5V_IN 1 CSREFA {4} ENABLE J47 U16A NL37WZ07 SER_EN R187 390 VCCIO 1 220K RT130 2 39 38 37 36 35 34 33 32 31 30 29 28 27 R300 1 0 2 1 R184 20K DRON 1 R241 20K ICCMAXA J28 PWM1 PWM2 PWM3 PWM2A PWM1A VBOOT/ADD VBOOTA/ADDA CSP1 CSN1 TSENSE J76 R242 47k {3} J21 R297 DNP 1 R132 165K R262 1 CSP3 CSP2 124K 2 124K 2 124K 2 R139 1 R140 1 124K 2 R138 1 CSSUM CSP1 2 CSREF C69 1000pF J40 2 R9 2 R10 2 R27 2 J78 2 R260 2 R243 68k 1.00K 2 C232 680pF 1.00K 2 C56 680F 2 1 R238 1 49.9 ICCMAX 1 Vboot=1V; Address main rail=0, Address AUX=1 CSP2A place close to L1 C156 620pF R131 75.0K CSP1 CSN1 TSENSE ICCMAX DRVON PWM1 PWM2 PWM3 PWM2A PWM1A ICCMAXA VBOOT/ADDR VBOOTA/ADDRA R240 1 DIFFOUT J39 R37 1 R50 49.9 1 2 1 1 FB 1 FBA 75 R158 2 R156 54.9 1 DNP 1 R159 2 R157 1 DNP 1 R160 2 VCCCORE {4} V_1P05_VCCP 1 2 SER_EN SER_VR_RDY SDIO {5} SCLK {5} ALERT# {5} 1 2 1 2 1 3 5 7 9 11 13 15 17 19 1 8 4 2 4 6 8 10 12 14 16 18 20 1 2 CSCOMPA 1 2 1 2 J59 20PIN 2ROW 1 2 1 2 1 2 2 1 2 2 J1 5PIN 1 2 1 2 1 2 1 1 1 1 2 CSP2A CSP3 1 0.1uF C239 10.0 2 1 DNP R296 1 R308 2 0.1uF C80 R307 2 1 R306 2 1 R305 2 CSP1A 0.1uF C83 J29 2 DNP 1 1 1 1 DNP R4 1 DNP R8 1 DNP R12 1 JP5 ETCH 10.0 2 10.0 2 10.0 2 R127 DNP J77 2 1 J41 2 C233 2.2nF CSP2 0.1uF C85 5.1K 10pF 2 2 1 C234 1 C55 2.2nF 10pF 2 2 1 R255 1 2 2 2 R239 1 ICCMAXA 4.7K 4.7K 4.7K 4.7K C57 1 R43 5.1K 1 1 V_1P05_VCCP 1 2 1 2 1 2 1 1 1 DIFFA 1 2 1 1 2 2 1 2 1 2 +5V_IN 1 2 J27 R16 DNP DNP C347 DNP C345 DNP C344 DNP C343 R272 DNP 2PIN 2 1 PSYS feed for NCP81203A J95 SWN2A{4} {3} {3} {3} {3} {3} {3} CSN2A{4} SWN1 CSN1 SWN2 CSN2 SWN3 CSN3 R19 DNP Phase detection 1 ILIM 1 2 1 2 53 52 51 50 49 48 47 46 45 44 43 42 41 40 1 1 2 GND VSN VSP DIFF FB COMP CSCOMP ILIM CSCUM CSREF CSP3 CSN3 CSP2 CSN2 CSCOMP 1 2 VSNA VSPA DIFFA FBA COMPA CSCOMPA ILIMA CSSUMA CSREFA CSP2A CSN2A CSP1A CSN1A 14 15 16 17 18 19 20 21 22 23 24 25 26 DIFFA FBA COMPA CSCOMPA ILIMA CSSUMA CSREFA CSP2A CSN2A CSP1A CSN1A 1 2 1 2 1 2 2 www.onsemi.com 1 Figure 1. 2 COMPA 1 COMP 2 J2 5PIN NCP81243 VCCGT {5} VCCGT_SENSE 130 2 R155 1 2 2 VCCGT 2 1 J80 1 J82 ILIMA R251 R248 1 2PIN 2 1 R250 1 1 100 2 0.0 2 0.0 2 100 2 100 R48 R257 23K 0.0 2 0.0 2 100 2 2 R249 1 R3 1 2PIN J13 R2 1 R34 1 1 VSENSEGT VSENSE CORE DNP 1 2 J81 C240 1nF C341 1nF 1 2 1 220K RT132 R252 75.0K 2 VSNA {4} VSP {4} VSN {4} place close to L1 C241 360pF VSPA{4} 1nF C237 2.2nF C342 2.10K 2 2 2.10K 2 C51 2.2nF R304 1 1 R303 1 1 R253 165K CSSUMA C94 0.1uF CSP1A 2 1 7 R187 390 VCCIO RT126 220K 136K 2 1 R256 4.7K 2 1 FSW=400K J32 J45 {4} VR_RDY C86 1uF 1 0.1uF C242 1 R309 2 {4} VR_HOT R154 32K 2 2 34.2K 2 C61 0.1uF 1 R38 1 J26 2 1 C235 0.1uF DNP R261 1 10.0 2 C236 0.1uF 1 21.5K 2 10nF R247 1 J61 J63 J62 C79 1uF 1 IOUTA R245 0.0 DNP C346 J8 R18 40K VSPA VSNA IOUT EN SDIO ALERT SCLK VR_RDY VCC ROSC VRMP PROG PIN TSENSEA VRHOT IOUTA 1 CSCOMP CSSUM CSREF CSP3 CSN3 CSP2 CSN2 J42 C155 1.2nF 2 1 220K RT130 2 39 38 37 36 35 34 33 32 31 30 29 28 27 R300 1 0 2 1 R184 20K DRON 1 J76 R241 20K ICCMAXA J28 PWM1 PWM2 PWM3 PWM2A PWM1A VBOOT/ADD VBOOTA/ADDA CSP1 CSN1 TSENSE R240 J39 1 DIFFOUT R242 47k {3} J21 R297 DNP 1 R132 165K R262 1 R140 1 CSP3 CSP2 124K 2 124K 2 124K 2 R139 1 CSSUM CSP1 2 124K 2 R138 1 CSREF C69 1000pF 2 J40 2 R9 2 R10 2 R27 2 R260 2 R243 68k 2 J78 C232 680pF 1.00K 2 1 R238 1 49.9 ICCMAX 1 2 1.00K Vboot=1V; Address main rail=0, Address AUX=1 CSP2A place close to L1 C156 620pF R131 75.0K CSP1 CSN1 TSENSE ICCMAX DRVON PWM1 U6 PWM2 NCP81243-DNP PWM3 PWM2A PWM1A ICCMAXA VBOOT/ADDR VBOOTA/ADDRA place close to L1 Auxiliary rail R246 15K TSENSEA SWN1A{4} CSN1A{4} J79 1 2 3 4 5 6 7 8 9 10 11 12 13 ILIM TSENSEA VCC VSN COMP FB DIFFOUT VSP SR=10mV/us, 4+1 config R244 75K 1 SDIO 1 ALERT# 1 SCLK R40 1.0K +VDC_IN RT131 220K 1 ROSC VRMP C82 VCC 1 IOUT R71 2.2 2 J56 1 +5V_IN place close to L1 MAIN RAIL R32 15K TSENSE R125 0.0 1000pF C340 +5V_IN 1 CSREFA {4} ENABLE J47 U16A NL37WZ07 SER_EN R263 1 V_1P05_VCCP R37 1 1 1 1 1 2 CSP2A CSP3 1 0.1uF C239 10.0 2 1 DNP R296 1 R308 2 0.1uF C80 R307 2 1 R306 2 1 R305 2 CSP1A 0.1uF C83 J29 2 2 DNP 1 1 1 1 DNP R4 1 DNP R8 1 DNP R12 1 JP5 ETCH 10.0 2 10.0 2 10.0 2 R127 DNP J77 C233 2.2nF CSP2 0.1uF C85 5.1K 10pF 2 2 1 C234 1 2 J41 C55 2.2nF 10pF 2 2 1 R255 1 2 2 2 R239 1 ICCMAXA 4.7K 4.7K 4.7K 4.7K C57 1 R43 5.1K 1 1 C56 R50 49.9 680F 1 2 1 1 FB 1 FBA 75 R158 2 R156 54.9 1 DNP 1 R157 1 DNP 1 R160 2 R159 2 VCCCORE {4} {5} VSSGT_SENSE VCCCORE {5} VCCCORE_SENSE {5} VSSCORE_SENSE LABEL AS "DIGITAL INTERFACE" SER_VR_RDY SDIO {5} SCLK {5} ALERT# {5} 1 2 SER_EN 1 2 1 2 1 3 5 7 9 11 13 15 17 19 1 8 4 2 4 6 8 10 12 14 16 18 20 1 2 CSCOMPA 1 2 1 2 J59 20PIN 2ROW 1 2 1 2 1 2 2 1 2 2 J1 5PIN 1 2 1 2 1 2 1 V_1P05_VCCP 1 2 1 2 1 2 1 1 1 DIFFA 1 2 1 1 2 2 1 2 1 2 +5V_IN 1 2 J27 R16 DNP DNP C347 DNP C345 DNP C344 DNP C343 R272 DNP 2PIN 2 1 PSYS feed for NCP81203A J95 SWN2A{4} {3} {3} {3} {3} {3} {3} CSN2A{4} SWN1 CSN1 SWN2 CSN2 SWN3 CSN3 R19 DNP Phase detection 1 ILIM 1 2 1 2 53 52 51 50 49 48 47 46 45 44 43 42 41 40 1 1 2 GND VSN VSP DIFF FB COMP CSCOMP ILIM CSCUM CSREF CSP3 CSN3 CSP2 CSN2 CSCOMP 1 2 VSNA VSPA DIFFA FBA COMPA CSCOMPA ILIMA CSSUMA CSREFA CSP2A CSN2A CSP1A CSN1A 14 15 16 17 18 19 20 21 22 23 24 25 26 DIFFA FBA COMPA CSCOMPA ILIMA CSSUMA CSREFA CSP2A CSN2A CSP1A CSN1A 1 2 1 2 1 3 2 www.onsemi.com 1 Figure 2. 2 COMPA 1 COMP 2 J2 5PIN NCP81243 NCP81243 VCC ENABLE GND TSENSEA TSENSE VRHOT THERMAL MONITOR VRDY ENABLE UVLO & EN VSNA VSN DAC GND DIFFAMP CSREF ENABLE VSP VSN DAC VSPA VSNA AUX DAC + DIFFOUT ERROR AMP DIFFOUTA COMP CSSUM CSREF CURRENT MEASUREMENT & LIMIT OVP OVP AUX OVP VSPA VSNA ERROR AMP OVPA - IOUT VSP VSN + ILIM AUX DIFFAMP - FB VR READY COMPARATOR CURRENT MEASUREMENT & LIMIT VSP-VSN VSPA-VSNA TSENSE TSENSEA ENABLE SDIO Intel proprietary FACE interface INTER DATA REGISTERS ADDRA ADC DAC DAC AUX DAC AUX DAC MUX AUX CS AMP IMAX IMAXA IOUT IOUTA ADDR ADDRA ENABLE RAMP GENERATORS OVP COMPA ENABLE NCP81243 POWER STATE STAGE POWER STATE STAGE Figure 3. 3 + 2 Block Diagram www.onsemi.com 4 DRON PWM GENERATORS RAMP1 RAMP2 RAMP3 PWM GENERATORS PWM2A PWM1A COMP ENABLE RAMP1A RAMP2A IOUTA CSSUMA CSREFA VBOOTA VBOOT VRMP ROSC OVP IPH3 IPH2 IPH1 PH_CONFIG CURRENT BALANCE ILIMA CSCOMPA CURRENT IPH2A BALANCE IPH1A PWM1 PWM2 PWM3 CSN3 CSP3 CSN2 CSP2 CSN1 CSP1 FBA COMPA CS AMP CSCOMP ALERT SCLK ADDR VSPA DAC GND CSREFA VSP CSN2A CSP2A CSN1A CSP1A NCP81243 VCC ENABLE GND TSENSEA TSENSE VRHOT THERMAL MONITOR VRDY ENABLE UVLO & EN VSNA VSN DAC GND DIFFAMP CSREF ENABLE VSP VSN DAC VSPA VSNA AUX DAC + DIFFOUT ERROR AMP DIFFOUTA COMP CSSUM CSREF CURRENT MEASUREMENT & LIMIT OVP OVP AUX OVP VSPA VSNA ERROR AMP OVPA - IOUT VSP VSN + ILIM AUX DIFFAMP - FB VR READY COMPARATOR CURRENT MEASUREMENT & LIMIT VSP-VSN VSPA-VSNA TSENSE TSENSEA ENABLE SDIO Intel proprietary FACE interface INTER DATA REGISTERS AUX DAC AUX DAC IPH2A RAMP1A RAMP1 RAMP2 RAMP3 RAMP2A ENABLE PWM GENERATORS PWM GENERATOR CURRENT Sense OVP COMPA ENABLE RAMP GENERATORS NCP81243 Figure 4. 4 + 1 Block Diagram www.onsemi.com 5 DRON POWER STATE STAGE POWER STATE STAGE IOUTA CSSUMA CSREFA VBOOTA VBOOT IPH1A IPH3 IPH2 IPH1 ILIMA CSCOMPA PWM1A COMP ENABLE DAC AUX CS AMP IMAX IMAXA IOUT IOUTA ADDR ADDRA VRMP ROSC OVP DAC MUX PH_CONFIG CURRENT BALANCE ADC PWM1 PWM2 PWM3 PWM2A ADDRA CSN2A CSP2A CSN3 CSP3 CSN2 CSP2 CSN1 CSP1 FBA COMPA CS AMP CSCOMP ALERT SCLK ADDR VSPA DAC GND CSREFA VSP CSN1A CSP1A NCP81243 5V VCC 12V VRMP SDA ALERT SCLK TSENSE VR_RDY ENABLE VRHOT ROSC PH_CONFIG PWM1 Vcore PWM2 COMP FB PWM3 DIFFOUT ILIM DRON CSCOMP CSSUM CSREF V Auxiliary PWM1A IOUT COMP PWM2A FB DIFFOUT ILIM CSCOMP TSENSEA CSSUM CSREFA IOUTA GND Figure 5. Pinout www.onsemi.com 6 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 NCP81243 39 38 37 36 35 34 33 32 31 30 29 28 13 27 CSP1 CSN1 TSENSE ICCMAX DRVON PWM1 PWM2 PWM3 PWM2A PWM1A ICCMAXA VBOOT/ADDR VBOOTA/ADDRA VSNA VSPA DIFFA FBA COMPA CSCOMPA ILIMA CSSUMA CSREFA CSP2A CSN2A CSP1A CSN1A IOUT EN SDIO ALERT# SCLK VRDY VCC ROSC VRMP PH/FDm/FDa/SR TSENSEA VRHOT IOUTA 52 51 50 49 48 47 46 45 44 43 42 41 40 VSN VSP DIFF FB COMP CSCOMP ILIM CSSUM CSREF CSP3 CSN3 CSP2 CSN2 NCP81243 Figure 6. Table 1. QFN52 PIN LIST DESCRIPTION Pin No. Symbol 1 IOUT 2 EN 3 SDIO 4 ALERT# Description Total output current for Main Rail. Logic input. Logic high enables both rail output and logic low disables both rail output. Serial VID data interface Serial VID ALERT#. 5 SCLK Serial VID clock 6 VRDY Open drain output. High output on this pin indicates that the Main Rail output is regulating. 7 VCC 8 ROSC A resistor to ground on this pin will set the oscillator frequency 9 VRMP Feed-forward input of Vin for the ramp slope compensation. The current fed into this pin is used to control of the ramp of PWM slope 10 PH/FDm/FDa/SR A resistor to ground on startup is used to set the phase configuration per rail of the NCP81243 as well as the Fast slew rate 11 TSenseA Temp Sense input for Auxiliary rail 12 VR_HOT Open drain output. Signals an over temperature event has occurred 13 IOUTA Total output current for the Auxiliary rail. 14 VSNA Differential Output Voltage Sense Negative for auxiliary rail 15 VSPA Differential Output Voltage Sense Positive for auxiliary rail 16 DIFFA Output of the auxiliary rail differential remote sense amplifier. Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground. 17 FBA 18 COMPA Error amplifier voltage feedback for auxiliary rail output 19 CSCOMPA 20 ILIMA 21 CSSUMA Inverting input of total current sense amplifier for auxiliary rail output. 22 CSREFA Total output current sense amplifier reference voltage input for auxiliary rail 23 CSP2A Non-inverting input to current balance sense amplifier for phase 2 A 24 CSN2A Inverting input to current balance sense amplifier for phase 2 A 25 CSP1A Non-inverting input to current balance sense amplifier for phase 1 A 26 CSN1A Inverting input to current balance sense amplifier for phase 1 A Output of the error amplifier and the inverting inputs of the PWM comparators for the auxiliary rail output. Output of total current sense amplifier for auxiliary rail output. Over current shutdown threshold setting for auxiliary rail l output. Resistor to CSCOMP to set threshold. www.onsemi.com 7 NCP81243 Table 1. QFN52 PIN LIST DESCRIPTION Pin No. Symbol 27 VBOOTA/ADDRA VBOOT and Address AUX rail Input Pin. A resistor to ground on startup is used to VBOOT and address of the auxiliary rail 28 VBOOT/ADDR VBOOT and Address main rail Input Pin. A resistor to ground on startup is used to VBOOT and address of the main rail 29 ICCMAXA ICCMAX Input for auxiliary rail Pin. During start up it is used to program configuration of Internal register with a resistor to ground 30 PWM1A PWM 1 Auxiliary rail output. 30 PWM1A PWM 1 Auxiliary rail output. ICCMAX Input for auxiliary rail Pin. 31 PWM2A PWM 2 Auxiliary rail output. 32 PWM3 PWM 3 Main rail output. 33 PWM2 PWM 2 Main rail output. 34 PWM1 PWM 1 Main output. 35 DRVON Bidirectional gate driver enable for external drivers for both Main and Auxiliary Rails. It should be left floating if unused. 36 ICCMAX ICCMAX Main rail Input Pin. During start up it is used to program configuration of Internal register with a resistor to ground 37 Tsense Temp Sense input for main rail 38 CSN1 Non-inverting input to current balance sense amplifier for Main Rail phase 1 39 CSP1 Non-inverting input to current balance sense amplifier for Main Rail phase 1 40 CSN2 Non-inverting input to current balance sense amplifier for Main rail phase 2 41 CSP2 Non-inverting input to current balance sense amplifier for Main Rail phase 2 42 CSN3 Non-inverting input to current balance sense amplifier for Main Rail phase 2 43 CSP3 Non-inverting input to current balance sense amplifier for Main Rail phase 2 44 CSREF Total output current sense amplifier reference voltage input for Main Rail 45 CSSUM Inverting input of total current sense amplifier for Main Rail output 46 ILIM 47 CSCOMP 48 COMP Description Over current shutdown threshold setting for Main Rail output. Resistor to CSCOMP to set threshold. Output of total current sense amplifier for Main Rail output Output of the Main Rail error amplifier and the inverting input of the PWM comparator for Main Rail output 49 FB 50 DIFF Error amplifier voltage feedback for Main Rail output Output of the Main Rail differential remote sense amplifier. 51 VSP Differential Output Voltage Sense Positive for mail rail 52 VSN Differential Output Voltage Sense Negative for main rail 53 AGND www.onsemi.com 8 NCP81243 Table 2. ABSOLUTE MAXIMUM RATINGS Pin Symbol VMAX VMIN ISOURCE ISINK COMP,COMPA VCC + 0.3 V -0.3 V 2 mA 2 mA CSCOMP, CSCOMPA VCC + 0.3 V -0.3 V 2 mA 2 mA 2 mA 2 mA DIFF, DIFFA VCC + 0.3 V -0.3 V PWM1, PWM2, PWM3, PWM1A, PWM2A VCC + 0.3 V -0.3 V VSN, VSNA GND + 300 mV GND-300 mV 1 mA 1 mA VRDY VCC + 0.3 V -0.3 V 2 mA 2 mA VCC 6.5 V -0.3 V VRMP +25 V -0.3 V All Other Pins VCC + 0.3 V -0.3 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *All signals referenced to GND unless noted otherwise. Table 3. THERMAL INFORMATION Description Thermal Characteristic QFN Package (Note 1) Operating Junction Temperature Range (Note 2) Symbol Value Unit RJA 68 C/W TJ -40 to +125 C -40 to +100 C Maximum Storage Temperature Range TSTG -40 to +150 C Moisture Sensitivity Level QFN Package MSL 1 Operating Ambient Temperature Range *The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 LFM 2. JESD 51-7 (1S2P Direct-Attach Method) with 0 LFM www.onsemi.com 9 NCP81243 Table 4. NCP81243 (3+2) ELECTRICAL CHARACTERISTICS Unless otherwise stated: -40C < TA < 100C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF Test Conditions Parameter Min Typ Max Unit 400 nA ERROR AMPLIFIER Input Bias Current -400 Open Loop DC Gain CL = 20 pF to GND, RL = 10 KW to GND 80 dB Open Loop Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 KW to GND 20 MHz Slew Rate DVin = 100 mV, G = -10 V/V, DVout = 0.75 V - 1.52 V, CL = 20 pF to GND, DC Load = 10 k to GND 20 V/ms Maximum Output Voltage ISOURCE = 2.0 mA Minimum Output Voltage ISINK = 0.5 mA 3.5 - - V - - 1 V Input Bias Current -400 - 400 nA VSP Input Voltage Range -0.3 - 3.0 V VSN Input Voltage Range -0.3 - 0.3 V DIFFERENTIAL SUMMING AMPLIFIER -3 dB Bandwidth CL = 20 pF to GND, RL = 10 KW to GND 12 Closed Loop DC gain VS to DIFF VS+ to VS- = 0.5 to 1.3 V Droop Accuracy CSREF-DROOP = 80 mV DAC = 0.8 V to 1.2 V -82 Maximum Output Voltage ISOURCE = 2 mA 3.0 Minimum Output Voltage ISINK = 0.5 mA - MHz 1.0 V/V -78 mV - - V - 0.5 V 500 mV CURRENT SUMMING AMPLIFIER Offset Voltage (Vos) Input Bias Current -500 CSSUM = CSREF = 1 V -7.5 Open Loop Gain 7.5 mA 80 dB 10 MHz Current Sense Unity Gain Bandwidth CL = 20 pF to GND, RL = 10 KW to GND Maximum CSCOMP (A) Output Voltage Isource = 2 mA 3.5 - - V Minimum CSCOMP(A) Output Voltage Isink = 500 mA - - 0.1 V -50 - 50 nA CURRENT BALANCE AMPLIFIER Input Bias Current CSPX = CSNX = 1.2 V Common Mode Input Voltage Range CSPx = CSNx 0 - 2.0 V Differential Mode Input Voltage Range CSNx = 1.2 V -100 - 100 mV Closed loop Input Offset Voltage Matching CSPx = 1.2 V, Measured from the average -2 - 2 mV Current Sense Amplifier Gain 0 V < CSPx < 0.1 V 5.7 6.0 6.3 V/V Multiphase Current Sense Gain Matching CSNX = CSPX = 10 mV to 30 mV -4.5 4.5 % -3 dB Bandwidth Guaranteed by simulation 8 MHz BIAS SUPPLY Supply Voltage Range 4.75 5.25 V VCC Quiescent Current PS0 50 mA VCC Quiescent Current PS1 50 mA www.onsemi.com 10 NCP81243 Table 4. NCP81243 (3+2) ELECTRICAL CHARACTERISTICS Unless otherwise stated: -40C < TA < 100C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF Parameter Test Conditions Min Typ Max Unit 50 mA BIAS SUPPLY VCC Quiescent Current PS2 VCC Quiescent Current PS3 20 VCC Quiescent Current PS4 (25C only) 230 VCC Quiescent Current Enable low 45 mA UVLO Threshold VCC rising 4.5 V VCC falling mA mA 4 VCC UVLO Hysteresis 200 mV VRMP Supply Range UVLO Threshold 4.5 VRMP rising VRMP falling 20 V 4.2 V 3 VCC UVLO Hysteresis 700 mV Soft Start Slew Rate 1/2 SR Fast mv/ms Slew Rate Slow 1/2 SR Fast mv/ms DAC SLEW RATE Slew Rate Fast >10 mv/ms AUX Soft Start Slew Rate 1/2 SR Fast mv/ms AUX Slew Rate Slow 1/2 SR Fast mv/ms AUX Slew Rate Fast >10 mv/ms ENABLE INPUT 0 1.0 mA Enable High Input Leakage Current Enable = 0 -1 Upper Threshold VUPPER 0.8 Lower Threshold VLOWER 0.3 V Enable Delay Time Measure time from Enable transitioning HI, VBOOT is not 0 V 2.5 ms - - V - 0.1 V DRON Output High Voltage Sourcing 500 mA Output Low Voltage Sinking 500 mA 3.0 - Pull Up Resistances Rise/Fall Time CL (PCB) = 20 pF, DVo = 10% to 90% Internal Pull Down Resistance VCC = 0 V - V 2.0 kW 160 ns 70 kW IOUT /IOUTA OUTPUT Input Referred Offset Voltage Ilimit to CSREF Output current max Ilimit sink current 80 mA Current Gain (Iout current)/(Ilimit Current) Rlim = 20 K, Riout = 5 K DAC = 0.8 V, 1.25 V, 1.52 V -3 +3 mV mA - - 800 9.5 10 10.5 300 - 1400 KHz -10 - 10 % 350 390 430 kHz OSCILLATOR Switching Frequency Range Switching Frequency Accuracy 300 KHz < Fsw < 1.4 MHz 3 Phase Operation OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP) Over Voltage Threshold During Soft-Start 2.5 www.onsemi.com 11 V NCP81243 Table 4. NCP81243 (3+2) ELECTRICAL CHARACTERISTICS Unless otherwise stated: -40C < TA < 100C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF Parameter Test Conditions Min Typ Max Unit 375 400 425 mV OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP) Over Voltage Threshold Above DAC VSS rising Over Voltage Delay VSS rising to PWMx low Under Voltage Threshold Below DAC-DROOP VSS falling Under-voltage Hysteresis VSS rising 50 275 Under-Voltage Delay 300 ns 325 mV 25 mV 5 mS OVERCURRENT PROTECTION ILIM Threshold Current (OCP shutdown after 50 us delay) Main Rail, Rlim = 20 kW 8.0 10 12 mA ILIM Threshold Current (immediate OCP shutdown) Main Rail, Rlim = 20 k 13 15 16.5 mA ILIM Threshold Current (OCP shutdown after 50 ms delay) Main Rail, RLIM = 20 K (N = number of phases in PS0 mode) 10/N mA ILIM Threshold Current (immediate OCP shutdown) Main Rail, RLIM = 20 K (N= number of phases in PS0 mode) 15/N mA ILIM Threshold Current (OCP shutdown after 50 ms delay) Auxiliary Rail, Rlim = 20 k 8.0 10 11 mA ILIM Threshold Current (immediate OCP shutdown) Auxiliary Rail, Rlim = 20 k 13 15 16.5 mA ILIM Threshold Current (OCP shutdown after 50 ms delay) Auxiliary Rail RLIM = 20 K 10/N mA ILIM Threshold Current (immediate OCP shutdown) Auxiliary Rail, RLIM = 20 K 15/N mA ns MODULATORS (PWM COMPARATORS) FOR MAIN RAIL & AUXILIARY RAIL Minimum Pulse Width Fsw = 350 KHz 60 0% Duty Cycle COMP voltage when the PWM outputs remain LO 1.3 - V 100% Duty Cycle COMP voltage when the PWM outputs remain HI VRMP = 12.0 V 2.5 - V PWM Ramp Duty Cycle Matching COMP = 2 V, PWM Ton matching 1 % PWM Phase Angle Error Between adjacent phases 5 deg Ramp Feed-forward Voltage range - 4.5 20 V TSENSE/TSENSEA VRHOT Assert Threshold 440 mV VRHOT Rising Threshold 460 mV Alert Rising Threshold 480 mV Alert Assertion Threshold 460 mV TSENSE Bias Current -57.5 -60 -1.0 - -62.5 mA VRHOT Output Low Voltage Output Leakage Current High Impedance State 0.3 V 1.0 mA ADC Voltage Range Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) 0 2 V -1.25 +1.25 % 1 LSB 8-bit Power Supply Sensitivity 1 % Conversion Time 30 ms www.onsemi.com 12 NCP81243 Table 4. NCP81243 (3+2) ELECTRICAL CHARACTERISTICS Unless otherwise stated: -40C < TA < 100C; 4.75 V < VCC < 5.25 V; CVCC = 0.1 mF Parameter Test Conditions Min Typ Max Unit ADC ms 90 Round Robin VRDY OUTPUT Output Low Saturation Voltage IVDD(A)_VRDY = 4 mA 0.3 V Rise Time External pull-up of 1KW to 3.3V, CTOT = 45 pF, DVo = 10% to 90% 150 ns Fall Time External pull-up of 1 KW to 3.3 V, CTOT = 45 pF, DVo = 90% to 10% 150 ns Output Voltage at Power-up VRDY pulled up to 5 V via 2 KW enable low Output Leakage Current When High VRDY = 5.0 V VRDY Delay (falling) From OCP - - - - 0.1 V -1.0 - 1.0 mA 50 - - From OVP 300 ms ns PWM (A), OUTPUTS Output High Voltage Sourcing 500 mA Output Mid Voltage No load Output Low Voltage Sinking 500 mA Rise and Fall Time CL (PCB) = 50 pF, DVo =10% to 90% of VCC Tri-State Output Leakage Gx = 2.0V, x = 1-2, EN=Low VCC - 0.2V - - V 1.9 2.0 2.1 V - - 0.7 - 10 -1.0 - V ns 1.0 mA PHASE DETECTION CSP2, CSP3, CSP1A, CSP2A Pin Threshold Voltage 4.7 Phase Detect Timer V 100 3. Guaranteed by design or characterization. Not in production testing www.onsemi.com 13 ms NCP81243 Table 5. STATE TRUTH TABLE STATE VR_RDY Pin Error AMP Comp Pin OVP & UVP DRON PIN POR N/A N/A N/A Resistive pull down Low Low Disabled Low Low Low Disabled Low Low Low Disabled Resistive pull up Low Operational Active / No latch High High Operational Active / Latching High Low N/A DAC+OVP High Method of Reset 0<VCC<UVLO Disabled EN < threshold UVLO >threshold Start up Delay & Calibration EN> threshold UVLO>threshold DRON Fault EN> threshold UVLO>threshold DRON<threshold Soft Start Driver must release DRON to high EN > threshold UVLO >threshold DRON > High Normal Operation EN > threshold UVLO >threshold DRON > High Over Voltage Over Current Low Operational Last DAC Code Low VOUT = 0 V Low: if Reg34h:bit0=0; High:if Reg34h:bit0=1; Clamped at 0.9 V Disabled High, PWM outputs in low state www.onsemi.com 14 N/A NCP81243 VCC > UVLO Controller POR Disable EN = 1 EN = 0 VCC < UVLO Calibrate Drive Off 3.5 VDRP > ILIM NO _ CPU INVALID VID ms and CAL DONE Phase Detect VCCP > UVLO and DRON HIGH Soft Start Ramp DAC = Vboot Soft Start Ramp OVP DAC = VID VS > OVP Normal VR _ RDY VS > UVP VS < UVP UVP General Phase Configuration: The NCP81243 is a dual rail three plus two phase dual edge modulated multiphase PWM controller, with a single serial Intel proprietary interface control interface. The NCP81243 has 5 external PWM signals which can be configured across the two rail. A resistor to ground on pin10, is used to configure Phase configuration, Frequency double on main/Auxiliary rail and SR. Available configuration options from pin10 are shown below: Ultrasonic Mode: The Switching frequency of a rail in DCM will decrease at very light loads. Ultrasonic Mode forces the switching frequency to stay above the audible frequency range. www.onsemi.com 15 NCP81243 Table 6. PHASE CONFIGURATION SELECTION Resistor LEVEL PH_config BOOST Main Rail BOOST AUX Rail SR 10000 1 3+2 NO NO 10 13000 2 3+2 NO NO 30 16000 3 3+2 NO NO 10 19200 4 3+2 NO NO 30 22500 5 3+2 NO YES(*2) 10 26000 6 3+2 NO YES(*2) 30 29600 7 3+2 NO YES(*2) 10 33500 8 3+2 NO YES(*2) 30 37400 9 3+2 YES(*2) NO 10 41500 10 3+2 YES(*2) NO 30 45800 11 3+2 YES(*2) NO 10 50200 12 3+2 YES(*2) NO 30 54800 13 3+2 YES(*2) YES(*2) 10 59500 14 3+2 YES(*2) YES(*2) 30 64500 15 3+2 YES(*2) YES(*2) 10 69600 16 3+2 YES(*2) YES(*2) 30 75000 17 4+1 NO NO 10 80600 18 4+1 NO NO 30 86500 19 4+1 NO NO 10 92600 20 4+1 NO NO 30 99000 21 4+1 NO YES(*2) 10 105500 22 4+1 NO YES(*2) 30 112500 23 4+1 NO YES(*2) 10 119600 24 4+1 NO YES(*2) 30 127000 25 4+1 YES (*1.5) NO 10 134800 26 4+1 YES(*1.5) NO 30 143000 27 4+1 YES(*1.5) NO 10 151400 28 4+1 YES(*1.5) NO 30 160300 29 4+1 YES(*1.5) YES(*2) 10 169500 30 4+1 YES(*1.5) YES(*2) 30 180000 31 4+1 YES(*1.5) YES(*2) 10 210000 32 4+1 YES(*1.5) YES(*2) 30 www.onsemi.com 16 NCP81243 Phase Interleaving PWM1 o 0 PWM2A o 270 PWM3 240 o 3+2 PWM1 o 0 PWM1A o 90 PWM2A o 270 2+2 PWM2 120o PWM2 o 120 PWM1 PWM2 PWM1 PWM3 PWM2 PWM1A PWM1A PWM2A PWM2A Serial VID Interface (Intel proprietary interface) Information regarding Intel proprietary interface can be obtained from Intel. www.onsemi.com 17 PWM1A o 90 NCP81243 VBOOT and Intel proprietary interface Address Programming (VBOOT/ADDR) is used to set the address for the main rail, pin 29 (VBOOTA/ADDRA) is used to address the Auxiliary rail. On power up a 10 mA current is sourced from these pins through a resistor connected to this pin and the resulting voltage is measured. Table 7 shows the resistor values that should be used and the corresponding Intel proprietary interface and VBOOT options for each rail. The NCP81243 has a VBOOT voltage register that can be externally programmed for both core and Auxiliary boot-up output voltages. The VBOOT voltage for main and auxiliary rails can be programmed with a resistor from VBOOT and VBOOTA pin to GND. In addition to VBOOT level, pin 28 and pin 29 also support Intel proprietary interface bus address programming. The NCP81243 support multiple Intel proprietary interface Device Addresses per rail. Pin 28 Pin 28 (VBOOT/ADDR) Resistor LEVEL VBOOT Address Auto Phase Shedding Disabling 10000 1 0 0 No 15000 2 0 0 Yes 21000 3 1.2 0 no 26700 4 0.9 0 No 33200 5 0 1 No 41200 6 0 1 Yes 49900 7 1.2 1 No 60400 8 0.9 1 No 71500 9 0 2 No 84500 10 0 2 Yes 97600 11 1.2 2 No 115000 12 1.5 2 No 133000 13 0 4 No 154000 14 0 4 Yes 178000 15 1.2 4 No 210000 16 1.5 4 No Table 7. VBOOT, ADDRESS PROGRAMMABILITY MAIN AND AUX RAILS Pin 27 (VBOOTA/ADDRA) Resistor LEVEL VBOOT AUX Address AUX 10000 1 0 1 13000 2 1.05 1 15800 3 1.2 1 20000 4 0.9 1 23700 5 0 0 28000 6 1.05 0 33200 7 1.2 0 38300 8 0.9 0 45000 9 0 2 52300 10 1.05 2 60400 11 1.2 2 69800 12 1.5 2 80600 13 0 3 93100 14 1.05 3 107000 15 1.2 3 121000 16 1.5 3 137000 17 0.8 2 158000 18 0.95 2 180000 19 0.8 3 210000 20 0.95 3 www.onsemi.com 18 NCP81243 Remote Sense Amplifier signal. This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions. The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP and CSREF. The Ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground. The amplifier actively filters and gains up the voltage applied across the inductors to recover the voltage drop across the inductor series resistance (DCR). Rth is placed near an inductor to sense the temperature of the inductor. This allows the filter time constant and gain to be a function of the Rth NTC resistor and compensate for the change in the DCR with temperature. A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of the regulator. The VSP and VSN inputs should be connected to the regulator's output voltage sense points. The remote sense amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to VDIFOUT = VVSP * VVSN ) 1.3 V * VDAC ) VDROOP * VCSREF This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The non-inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier output bias. High Performance Voltage Error Amplifier A high performance error amplifier is provided for high bandwidth transient performance. A standard type III compensation circuit is normally used to compensate the system. Differential Current Feedback Amplifiers The DC gain equation for the current sensing: V CSCOMP-CSREF + * CCSN SWNx VOUT DCR LPHASE 1 R CSN + Rcs2 ) Rcs1@Rth Rcs1)Rth @ Iout Total @ DCR Rph Set the gain by adjusting the value of the Rph resistors. The DC gain should be set to the output voltage droop. If the voltage from CSCOMP to CSREF is less than 100 mV at ICCMAX then it is recommend increasing the gain of the CSCOMP amp. This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain of the amplifier should be set to provide ~100 mV across the current limit programming resistor at full load. The values of Rcs1 and Rcs2 are set based on the 220k NTC and the temperature effect of the inductor and should not need to be changed. The NTC should be placed near the closest inductor. The output voltage droop should be set with the droop filter divider. The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time constant using commonly available values. It is best to fine tune this filter during transient testing. CSNx RCSN CSPx Each phase has a low offset differential amplifier to sense that phase current for current balance. The inputs to the CSNx and CSPx pins are high impedance inputs. It is recommended that any external filter resistor RCSN does not exceed 10 kW to avoid offset issues with leakage current. It is also recommended that the voltage sense element be no less than 0.5 kW for accurate current balance. Fine tuning of this time constant is generally not required. The individual phase current is summed into the PWM comparator feedback this way current is balanced via a current mode control approach. 2 L PHASE C CSN @ DCR Total Current Sense Amplifier The NCP81243 uses a patented approach to sum the phase currents into a single temperature compensated total current www.onsemi.com 19 NCP81243 FZ + NCP81243 and projects the loadline is produced by adding a signal proportional to output load current (Vdroop) to the output voltage feedback signal- thereby satisfying the voltage regulator at an output voltage reduced proportional to load current. The loadline is programmed by setting the gain of the Total Current Sense Amplifier such that the total current signal is equal to the desired output voltage droop.The signals CSCOMP and CSREF are differentially summed with the output voltage feedback to add precision voltage droop to the output voltage. DCR@25C 2 @ PI @ L Phase Programming the Current Limit The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on the CSCOMP-CSREF voltage as shown below. Rcs2) Rcs1@Rth Rcs1)Rth @ Iout LIMIT @ DCR Rph R LIMIT + 10 m Droop = DCR * (RCS / Rph) or R LIMIT + V CSCOMP-CSREF @ ILIMIT Programming IOUT 10 m The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates a 2 V signal on IOUT. A pull-up resistor from 5 V VCC can be used to offset the IOUT signal positive if needed. Programming DAC Feed-Forward Filter The DAC feed-forward implementation is realized by having a filter on the VSN pin. Programming Rvsn sets the gain of the DAC feed-forward and Cvsn provides the time constant to cancel the time constant of the system per the following equations. Cout is the total output capacitance and Rout is the output impedance of the system. R IOUT + 2.0 V @ R LIMIT Rcs2) Rcs1@Rth Rcs1)Rth @ Iout 10 @ ICC_MAX @ DCR Rph Programming ICC_MAX A resistor to ground on the IMAX pin programs these registers at the time the part is enabled. 10 uA is sourced from these pins to generate a voltage on the program resistor. ICC_MAX 21h + Rvsn + Cout @ Rout @ 453.6 @ 10 6 Cvsn + Rout @ Cout Rvsn R @ 10 mA @ 255 A 2V Programming TSENSE A temperature sense input per rail is provided. A precision current is sourced out the output of the TSENSE pin to generate a voltage on the temperature sense network. The voltage on the temperature sense inputs are sampled by the internal A/D converter. A 100 k NTC similar to the VISHAY ERT-J1VS104JA should be used. Rcomp1 is optional to the user, and can be used to slightly change the hysteresis. See the specification table for the thermal sensing voltage thresholds and source current. Programming DROOP An output loadline is a power supply characteristic wherein the regulated (DC) output voltage decreases proportional to the load current. This characteristic can reduce the output capacitance required to maintain output voltage within limits during load transient faster than those to which the regulation loop can respond. With the www.onsemi.com 20 NCP81243 Precision Oscillator TSENSE A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit. This oscillator is programmed by a resistor to ground on the ROSC pin. The oscillator frequency range is between 300 KHz/phase to 1.4 MHz/phase. The ROSC pin provides approximately 2 V out and the source current is mirrored into the internal ramp oscillator. The oscillator frequency is approximately proportional to the current flowing in the ROSC resistor. Rcomp1 0.0 Cfilter 0.1uF Rcomp2 8.2K AGND RNTC 100K AGND Figure 7. NCP81243 Operating Frequency vs. Rosc Programming the Ramp Feed-Forward Circuit The oscillator generates triangle ramps that are 1.3~2.5 V in amplitude depending on the VRMP pin voltage to provide input voltage feed forward compensation. The ramps are equally spaced out of phase with respect to each other and the signal phase rail is set half way between phases 1 and 2 of the multi phase rail for minimum input ripple current. For use with On Semiconductors phase doubler the NCP81243 offers the user the ability to double the frequency of each rail independently or simultaneously. This will allow the rail that is being doubled to maintain a higher system switching frequency. The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage feed-forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4V UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when the controller is disabled. The PWM ramp time is changed according to the following, V RAMPpk+pk PP + 0.1 @ V VRMP Vin Vramp _pp Comp -IL Duty www.onsemi.com 21 NCP81243 PWM Comparators operate in a hysteretic mode with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps. The noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (COMP) and each phase current (IL*DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage with a 1.3 V offset. The operating input voltage range of the comparators is from 0 V to 3.0 V and the output of the comparator generates the PWM output. During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty cycle is still calculated by approximately Vout/Vin. During a transient event, the controller will Phase Configuration Configuration Phase Detection Sequence Normally, NCP81243 operates as a 3-phase VCORE/ 2-phase Auxiliary PWM controller however the NCP81243 can also be configures as a 4+1-phase controller. During start-up, the number of operational phases and their phase relationship is determined by the internal circuitry monitoring the CSP outputs. Programming Pin Phase Config (30 mv/us slew rate) Programming Pin CSPx Unused Pins 1 4+1 80k6 All CSP pins connected normally 2 4+0 80k6 Connect CSP1A to VCC through a 2 k resistor. All other CSP pins connected normally Float:PWM1A, ILIMA, DIFFOUTA,COMPA,CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA,VSPA, TsenseA 3 3+2 13k All CSP pins connected normally No unused pins 4 3+1 13k Connect CSP2A to VCC through a 2k resistor. All other CSP pins connected normally Float: PWM2A 5 3+0 13k Connect CSP2A and CSP1A to VCC through a 2k resistor. All other CSP pins connected normally Float: PWM2A, PWM1A, ILIMA, DIFFOUTA, COMPA, CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA, VSPA, TsenseA 6 2+2 13k Connect CSP3 to VCC through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM3 7 2+1 13k Connect CSP2A to VCC through a 2k resistor. All other CSP pins connected normally Float PWM3, PWM2A 8 2+0 13K Connect CSP3, CSP2A and CSP1A to VCC through a 2k resistor. All other CSP pins connected normally Float PWM3, PWM1A, PWM2A, PWM3ILIMA, DIFFOUTA, COMPA, CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA, VSPA, TsenseA 9 1+2 13K Connect CSP3 and CSP2 through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM2 and PWM3 10 1+1 13K Connect CSP3, CSP2 and CSP2A through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM2, PWM3, PWM2A 11 1+0 13K Connect CSP3, CSP2, CSP2A and CSP1A through a 2k resistor pulled to VCC. All other CSP pins connected normally Float: PWM2, PWM3, PWM1A, PWM2A, ILIMA, DIFFOUTA, COMPA, CSCOMPA Ground: IOUTA, FBA, CSSUMA, CSREFA, VSPA, VSNA The PWM outputs are logic-level devices intended for driving fast response external gate drivers such as the NCP81151 and NCP81161. As each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one PWM output can be on at the same time to allow overlapping phases. www.onsemi.com 22 NCP81243 Protection Features When the voltage on the gate driver is insufficient it will pull DRON low and prevents the controller from being enabled. The gate driver will hold DRON low for a minimum period of time to allow the controller to hold off it's startup sequence. In this case the PWM is set to the MID state to begin soft start. Under Voltage Lockouts There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81243 monitors the 5 V VCC supply. The gate driver monitors both the gate driver VCC and the BST voltage. If DRON is pulled low the controller will hold off its startup DAC Gate Driver Pulls DRON Low during driver UVLO and Calibration Figure 8. Gate Driver UVLO Restart Start Up Sequence main and Auxiliary rail is enabled at this time. A digital counter steps the DAC up from Zero to the target voltage level based on the soft start slew rate selected. As the DAC ramps the PWM outputs for each rail will begin to fire. Each phase will move out of the MID state when the first PWM pulse is produced. When the controller is disabled the PWM signal will return to the MID state. When the controller is disabled, the PWM signals will return to Mid - level. Following the rise of Vcc and VRMP above the UVLO thresholds, externally programmed data is collected. After the configuration data is collected, the PWMs will be set to 2.0 V MID state to indicate that the drivers should be in diode mode. When the device is enabled DRON will then be asserted high to activate the gates, please note that there is only one Enable pin, once this enable is pulled high both the Figure 9. Startup Operation www.onsemi.com 23 NCP81243 Over Current Latch-Off Protection Input Under-Voltage Lockouts The NCP81243 compares a programmable current-limit set point to the voltage from the output of the current-summing amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external resistor connected between ILIM and CSCOMP is then compared to the internal current limit current ICL. If the current generated through this resistor into the ILIM pin (Ilim) exceeds the internal current-limit threshold current (ICL), an internal latch-off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150% load current) after which the outputs will remain disabled until the Vcc voltage or EN is toggled. The voltage swing of CSCOMP cannot go below ground. This limits the voltage drop across the DCR through the current balance circuitry. An inherent per-phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. The over-current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following equations. Equation related to the NCP81243: NCP81243 monitors the 5 V VCC supply as well as the VRMP pin. Hysteresis is incorporated within these comparators. If either the Vcc or the VRMP UVLO requirements are not met the VR will fail to startup and the Intel proprietary interface interface will be unresponsive to all commands. I LIM @ DCR @ R ILIM + Under Voltage Monitor The output voltage is monitored at the output of each differential amplifier for UVLO. If the output falls more than 300 mV below the DAC-DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low. Over Voltage Protection The output voltage for each rail is also monitored for OVP at the output of the differential amplifier and also at the CSREF pin. During normal operation, if the output voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the output voltage will be ramped down to 0 V, the ramp to 0 V is controlled to avoid producing negative output voltage. At the same time, the PWMs of the OVP rail are sent low. The PWM outputs will pulse to mid level during the DAC ramp down period if the output decreases below the DAC+OVP threshold as DAC decreases. When the DAC reaches 0 V, the PWMs will be held low, the high side gate drivers are all turned off and the low side gate drivers are all turned on. The part will stay in this mode until the Vcc voltage or EN is toggled. RCS RPH I CL Where ICL = 10 mA CSSUM RCS RPH RPH R PH CSCOMP RLIM ILIM CSREF www.onsemi.com 24 NCP81243 Figure 10. OVP Behavior at Startup Figure 11. OVP During Normal Operation Mode During start up, the OVP threshold is set to 2.5 V. This allows the controller to start up without false triggering the OVP www.onsemi.com 25 NCP81243 PACKAGE DIMENSIONS QFN52 6x6, 0.4P CASE 485BE ISSUE B PIN ONE LOCATION EEE EEE EEE EEE 0.10 C L1 DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS TOP VIEW A (A3) DETAIL B 0.10 C DIM A A1 A3 b D D2 E E2 e K L L1 L2 EEE EEE EXPOSED Cu 0.10 C L L A B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION 0.08 C A1 NOTE 4 SIDE VIEW C D2 DETAIL C SEATING PLANE K 14 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.15 0.25 6.00 BSC 4.60 4.80 6.00 BSC 4.60 4.80 0.40 BSC 0.30 REF 0.25 0.45 0.00 0.15 0.15 REF L2 DETAIL A L2 DETAIL C 27 8 PLACES SOLDERING FOOTPRINT* E2 52X 6.40 4.80 L 52X 0.63 1 52 40 52X e BOTTOM VIEW b 0.07 C A B 0.05 C NOTE 3 4.80 6.40 0.11 0.49 DETAIL D PKG OUTLINE 8 PLACES 0.40 PITCH 52X DETAIL D 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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