May 2009 Rev 9 1/65
1
M29W320ET
M29W320EB
32 Mbit (4Mbx8 or 2Mbx16, Uniform Parameter Blocks, Boot Block)
3V supply Flash memory
Features
Supply voltage
–V
CC = 2.7V to 3.6V for Program, Erase and
Read
–V
PP =12V for Fast Program (optional)
Access times: 70, 90ns
Programming time
–10μs per byte/word typical
– Double word/ Quadruple byte Program
Memory Blocks
– Memory Array: 63 Main Blocks
– 8 Parameter Blocks (Top or Bottom
Location)
Erase Suspend and Resume modes
– Read and Program another Block during
Erase Suspend
Unlock Bypass Program command
– Faster Production/Batch Programming
VPP/WP pin for fast Program and Write Protect
Temporary Block Unprotection mode
Common Flash Interface
– 64 bit Security code
Extended memory Block
– Extra block used as security block or to
store additional information
Low power consumption
– Standby and Automatic Standby
100,000 Program/Erase cycles per block
Electronic signature
– Manufacturer code: 0020h
– Top Device code M29W320ET: 2256h
– Bottom Device code M29W320EB: 2257h
RoHS® packages available
FBGA BGA
TSOP48 (N)
12 x 20 mm
TFBGA48 (ZE)
6 x 8 mm
FBGA64 (ZS)
11 x 13 mm
www.numonyx.com
Contents M29W320ET, M29W320EB
2/65
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1 Address Inputs (A0-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 14
2.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11 Byte/word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12 VCC Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.1 Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.2 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M29 W320ET , M29W320EB Con tents
3/65
4.5 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.1 Quadruple byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.2 Double word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.9 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.12 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.13 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.14 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.15 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . 26
5 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4 Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5 Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Appendix A Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Ap pe n d ix B C ommon Fla s h In t e r f ace (CFI ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Appendix C Extended memory Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Contents M29W320ET, M29W320EB
4/65
Appendix D Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
D.2 In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
M29 W320ET , M29W320EB List of tables
5/65
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. Bus operations, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Write ac characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. Write ac characteristics, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Toggle and alternative Toggle bits ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 16. Reset/Block Temporary Unprotect ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, package mechanical data . . . . . . . 43
Table 18. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, package mechanical data. . . . . . . . . . . 44
Table 19. FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package mechanical data . . . 45
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Top Boot Block Addresses, M29W320ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22. Bottom Boot Block Addresses, M29W320EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 27. Primary Algorithm-specific extended Query table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 28. Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 29. Extended Block Address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 30. Programmer technique Bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 31. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
List o f figu res M29 W320 ET, M29 W320EB
6/65
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. FBGA64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 10. AC measurement Load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. Write ac waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 13. Write ac waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Toggle and alternative Toggle bits mechanism, Chip Enable controlled . . . . . . . . . . . . . . 41
Figure 15. Toggle and alternative Toggle bits mechanism, Output Enable controlled. . . . . . . . . . . . . 41
Figure 16. Reset/Block Temporary Unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm package outline, top view. . . . . . . . 43
Figure 19. TFBGA48 6x8mm-6x8 Ball Array, 0.8mm Pitch, package outline, bottom view . . . . . . . . . 44
Figure 20. FBGA64 11 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline, bottom view . 45
Figure 21. Programmer Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 22. Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 23. In-system Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 24. In-system Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
M29 W320ET , M29W32 0E B Descri ption
7/65
1 Description
The M29W320E is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.
The device features an asymmetrical block architecture. The M29W320E has an array of 8
parameter and 63 main blocks. M29W320ET locates the Parameter Blocks at the top of the
memory address space while the M29W320EB locates the Parameter Blocks starting from
the bottom.
M29W320E has an extra 32 Kword (x16 mode) or 64 Kbyte (x8 mode) block, the Extended
Block, that can be accessed using a dedicated command. The Extended Block can be
protected and so is useful for storing security information. However the protection is
irreversible, once protected the protection cannot be undone.
Each block can be erased independently so it is possible to preserve valid data while old
data is erased. The blocks can be protected to prevent accidental Program or Erase
commands from modifying the memory. Program and Erase commands are written to the
Command interface of the memory. An on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase
operation can be detected and any error conditions identified. The command set required to
control the memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12x20mm), and TFBGA48 (6x8mm, 0.8mm pitch)
packages. In order to meet environmental requirements, Numonyx offers the M29W320E in
RoHS packages, which are are Lead-free. The category of second Level Interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
The memory is supplied with all the bits erased (set to ’1’).
Description M29W320ET, M29W320EB
8/65
Figure 1. Logic diagram
Table 1. Signal n ames
A0-A20 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/word Organization Select
VCC Supply voltage
VPP/WP VPP/Write Protect
VSS Ground
NC Not Connected Internally
AI09346
21
A0-A20
W
DQ0-DQ14
VCC
M29W320ET
M29W320EB
E
VSS
15
G
RP
DQ15A–1
BYTE
RB
VPP/WP
M29 W320ET , M29W32 0E B Descri ption
9/65
Figure 2. TSO P connec tions
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
A7
DQ7
VPP/WP
NC
AI09347
M29W320ET
M29W320EB
12
1
13
24 25
36
37
48
DQ8
A20
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14 VSS
E
A0
RP
VSS
Description M29W320ET, M29W320EB
10/65
Figure 3. TFBGA 48 conne ctions (top view through package)
654321
VSS
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
VPP
/
WP
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 A20
A16
BYTE
C
B
A
E
D
F
G
H
DQ15
A–1
AI08084
M29 W320ET , M29W32 0E B Descri ption
11/65
Figure 4. FBGA 64 conne ctions (top view through pa cka ge)
654321
VSS
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
VPP
/
WP
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 A20
A16
BYTE
C
B
A
E
D
F
G
H
DQ15
A–1
AI12719_bis
87
NC
VCC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
Description M29W320ET, M29W320EB
12/65
Fig u re 5. Bl o ck Addr esse s (x8)
1. See also Appendix A: Block Addresses, Table 21 and Table 22 for a full listing of the Block Addresses.
AI0934
8
64 KByte or
32 KWord
000000h
00FFFFh
64 KByte or
32 KWord
3E0000h
3EFFFFh
Top Boot Block (x8)
Address lines A20-A0, DQ15A-1
64 KByte or
32 KWord
2F0000h
2FFFFFh
64 KByte or
32 KWord
300000h
30FFFFh
8 KByte or
4 KWord
3FE000h
3FFFFFh
8 KByte or
4 KWord
3F0000h
3F1FFFh
Total of 63
Main Blocks
Total of 8
Parameter
Blocks
(1)
8 KByte or
4 KWord
000000h
001FFFh
64 KByte or
32 KWord
0F0000h
0FFFFFh
Bottom Boot Block (x8)
Address lines A20-A0, DQ15A-1
8 KByte or
4 KWord
00E000h
00FFFFh
Total of 8
Parameter
Blocks
(1)
64 KByte or
32 KWord
010000h
01FFFFh
64 KByte or
32 KWord
3F0000h
3FFFFFh
64 KByte or
32 KWord
100000h
10FFFFh
Total of 63
Main Blocks
Note 1. Used as Extended Block Addresses in Extended Block mode.
M29 W320ET , M29W32 0E B Descri ption
13/65
Fig u re 6. Bl o ck Addr esse s (x16)
1. See also Appendix A: Block Addresses, Table 21 and Table 22 for a full listing of the Block Addresses.
AI09349
64 KByte or
32 KWord
000000h
007FFFh
64 KByte or
32 KWord
1F0000h
1F7FFFh
Top Boot Block (x16)
Address lines A20-A0
64 KByte or
32 KWord
178000h
17FFFFh
64 KByte or
32 KWord
180000h
187FFFh
8 KByte or
4 KWord
1FF000h
1FFFFFh
8 KByte or
4 KWord
1F8000h
1F8FFFh
Total of 63
Main Blocks
Total of 8
Parameter
Blocks
(1)
8 KByte or
4 KWord
000000h
000FFFh
64 KByte or
32 KWord
078000h
07FFFFh
Bottom Boot Block (x16)
Address lines A20-A0
8 KByte or
4 KWord
007000h
007FFFh
Total of 8
Parameter
Blocks
(1)
64 KByte or
32 KWord
008000h
00FFFFh
64 KByte or
32 KWord
1F8000h
1FFFFFh
64 KByte or
32 KWord
080000h
087FFFh
Total of 63
Main Blocks
Note 1. Used as Extended Block Addresses in Extended Block mode.
Si gnal descri pt i o n s M2 9W320E T, M2 9W320E B
14/65
2 Signal descriptions
See Figure 1: Lo gi c diagr am, and Ta bl e 1: S i gnal nam es, for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A20)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
interface of the Program/Erase Controller.
2.2 Data Inputs /Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command interface
of the Program/Erase Controller.
2.3 Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status register these bits should be ignored.
2.4 Data Input/Output or Address Input (DQ15A–1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
LSB of the addressed word, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data Input/Output to include this pin when BYTE is High and
references to the Address Inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
2.5 Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6 Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
M29 W320ET , M 29W32 0EB Sig n al des cri p tion s
15/65
2.7 Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command interface.
2.8 VPP/Write Pro tect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Program
operations. This is achieved by bypassing the unlock cycles and/or using the Double word
or Quadruple byte Program commands.
The Write Protect function provides a hardware method of protecting the two outermost boot
blocks. When VPP/Write Protect is Low, VIL, the memory protects the two outermost boot
blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect
is Low, even when RP is at VID.
When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status
of the two outermost boot blocks. Program and Erase operations can now modify the data
in these blocks unless the blocks are protected using Block Protection.
When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock
Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes.
During Unlock Bypass Program operations the memory draws IPP from the pin to supply the
programming circuits. See the description of the Unlock Bypass command in the Command
interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than
tVHVPP
, see Figure 17
Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating or unconnected or the device may
become unreliable. A 0.1μF capacitor should be connected between the VPP/Write Protect
pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during Unlock Bypass Program,
IPP
.
2.9 Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if VPP/WP is at VIL, then the two outermost boot blocks will remain protected even
if RP is at VID.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last.
See the Ready/Busy Output section, Table 16 and Figure 16: Reset/Block Temporary
Unprotect ac waveforms, for more details.
Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
Si gnal descri pt i o n s M2 9W320E T, M2 9W320E B
16/65
2.10 Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 16 and Figure 16: R eset/ Bl ock Tem po rary Unprote c t
ac waveforms.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11 Byte/word Organization Select (BYTE)
The byte/word Organization Select pin is used to switch between the x8 and x16 Bus modes
of the memory. When byte/word Organization Select is Low, VIL, the memory is in x8 mode,
when it is High, VIH, the memory is in x16 mode.
2.12 VCC Supply voltage
VCC provides the power supply for all operations (Read, Program and Erase).
The Command interface is disabled when the VCC Supply voltage is less than the Lockout
voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1μF capacitor should be connected between the VCC Supply voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, ICC3.
2.13 VSS Ground
VSS is the reference for all voltage measurements. The device features two VSS pins which
must be both connected to the system ground.
M29 W320ET , M29W320EB Bus o p erat ions
17/65
3 Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby.
See Table 2 and Table 3, Bus operations, for a summary. Typically glitches of less than 5ns
on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11: Read mode
ac waveforms, and Table 12: Read ac characteristics, for details of when the output
becomes valid.
3.2 Bus Write
Bus Write operations write to the Command interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure 12 and Figure 13, Write ac waveforms,
and Table 13 and Table 14, Write ac characteristics, for details of the timing requirements.
3.3 Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4 Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply current to
the Standby Supply current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the
Standby current level see Table 11: DC characteri stic s.
During program or erase operations the memory will continue to use the Program/Erase
Supply current, ICC3, for Program or Erase operations until the operation completes.
Bus operations M29W320ET, M29W320EB
18/65
3.5 Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply current is reduced to
the Standby Supply current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read
operation is in progress.
3.6 Special bus operations
Additional bus operations can be performed to read the Electronic signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.6.1 Electronic signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2
and Table 3, Bus operations.
3.6.2 Block Protect and Chip Unprotect
Groups of blocks can be protected against accidental Program or Erase. The Protection
groups are shown in Append i x A: Blo ck Ad dres ses, Table 21 and Table 22, Block
Addresses. The whole chip can be unprotected to allow the data inside the blocks to be
changed.
The VPP/Write Protect pin can be used to protect the two outermost boot blocks. When
VPP/Write Protect is at VIL the two outermost boot blocks are protected and remain
protected regardless of the Block Protection Status or the Reset/Block Temporary
Unprotect pin status.
Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.
M29 W320ET , M29W320EB Bus o p erat ions
19/65
Table 2. Bus operations, BYTE = VIL(1)
Operation E G W Address Input s
DQ15A–1, A0-A2 0
Data Inputs/Outputs
DQ14-
DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read Manufacturer
code VIL VIL VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
Hi-Z 20h
Read Device code VIL VIL VIH
A0 = VIH, A1 = VIL,
A9 = VID, Others VIL or VIH
Hi-Z 56h (M29W320ET)
57h (M29W320EB)
Extended memory
Block Verify code VIL VIL VIH
A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH
Hi-Z 81h (factory locked)
01h (factory unlocked)
1. X = VIL or VIH.
Bus operations M29W320ET, M29W320EB
20/65
Table 3. Bus operations, BYTE = VIH(1)
Operation E G W Address Inputs
A0-A20 Data Inputs/ Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH X Hi-Z
Standby VIH X X X Hi-Z
Read Manufacturer
code VIL VIL VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
0020h
Read Device code VIL VIL VIH
A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH
2256h (M29W320ET)
2257h (M29W320EB)
Extended memory
Block Verify code VIL VIL VIH
A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH
81h (factory locked)
01h (factory unlocked)
1. X = VIL or VIH.
M29 W320ET , M 29W32 0EB Comm and interf ace
21/65
4 Command interface
All Bus Write operations to the memory are interpreted by the Command interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-
bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being
used, for a summary of the commands.
4.1 Read/Reset command
The Read/Reset command returns the memory to its Read mode. It also resets the errors in
the Status register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the time-out of a Block erase operation then the memory will take up to
10μs to abort. During the abort period no valid data can be read from the memory. The
Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
4.2 Auto Select command
The Auto Select command is used to read the Manufacturer code, the Device code, the
Block Protection Status and the Extended memory Block Verify code. Three consecutive
Bus Write operations are required to issue the Auto Select command. The memory remains
in Auto Select mode until a Read/Reset or CFI Query command is issued.
In Auto Select mode the Manufacturer code can be read using a Bus Read operation with
A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH.
The Device code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The
other address bits may be set to either VIL or VIH.
The Block Protection Status of each block can be read using a Bus Read operation with A0
= VIL, A1 = VIH and A12-A20 specifying the block address. The other address bits may be
set to either VIL or VIH. If the addressed block is protected then 01h is output on Data
Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
Co m mand interface M29W32 0ET, M29W320E B
22/65
4.3 Read CFI Query command
The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Auto Select mode.
One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Auto Select mode). A second Read/Reset command would be needed
if the device is to be put in the Read Array mode from Auto Select mode.
See Appendix B : Common Flas h Interfa ce (CFI), Table 23, Table 24, Table 25, Table 26,
Table 27 and Table 28 for details on the information contained in the Common Flash
Interface (CFI) memory area.
4.4 Program command
The Program command can be used to program a value to one address in the memory
array at a time. The command requires four Bus Write operations, the final write operation
latches the address and data, and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. After programming has started, Bus
Read operations output the Status register content. See Sect i on 5: Status regi ster for more
details. Typical program times are given in Table 6
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations will continue to output
the Status register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
M29 W320ET , M 29W32 0EB Comm and interf ace
23/65
4.5 Fast Program commands
There are two Fast Program commands available to improve the programming throughput,
by writing several adjacent words or bytes in parallel. The Quadruple byte Program
command is available for x8 operations, while the Double word Program command is
available for x16 operations.
Fast Program commands should not be attempted when VPP/WP is not at VPP
. Care must
be taken because applying a 12V VPP voltage to the VPP/WP pin will temporarily unprotect
any protected block.
After programming has started, Bus Read operations output the Status register content.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations will continue to output
the Status register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical Program times are given in Table 6: Progr am , Erase times and Program , Eras e
Endurance cycles
4.5.1 Quadruple byte Program command
The Quadruple byte Program command is used to write a page of four adjacent bytes in
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles
are necessary to issue the Quadruple byte Program command.
1. The first bus cycle sets up the Quadruple byte Program command.
2. The second bus cycle latches the Address and the Data of the first byte to be written.
3. The third bus cycle latches the Address and the Data of the second byte to be written.
4. The fourth bus cycle latches the Address and the Data of the third byte to be written.
5. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and
starts the Program/Erase Controller.
4.5.2 Double word Program command
The Double word Program command is used to write a page of two adjacent words in
parallel. The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double word Program command.
1. The first bus cycle sets up the Double word Program command.
2. The second bus cycle latches the Address and the Data of the first word to be written.
3. The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
Co m mand interface M29W32 0ET, M29W320E B
24/65
4.6 Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory enters Unlock Bypass
mode. The Unlock Bypass Program command can then be issued to program addresses or
the Unlock Bypass Reset command can be issued to return to Read mode. In Unlock
Bypass mode the memory can be read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin the memory automatically enters the
Unlock Bypass mode and the Unlock Bypass Program command can be issued
immediately. Care must be taken because applying a 12V VPP voltage to the VPP/WP pin
will temporarily unprotect any protected block.
4.7 Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two Bus Write operations, the final write operation
latches the address and data, and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. The operation cannot be aborted, a
Bus Read operation outputs the Status register. See the Program command for details on
the behavior.
4.8 Unlock Bypass Reset comm and
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass mode.
4.9 Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100μs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 6. All Bus Read operations during the Chip Erase
operation will output the Status register on the Data Inputs/Outputs. See the section on the
Status register for more details.
After the Chip Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
M29 W320ET , M 29W32 0EB Comm and interf ace
25/65
Status register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.10 Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is
lost.
Six Bus Write operations are required to select the first block in the list. Each additional
block in the list can be selected by repeating the sixth Bus Write operation using the address
of the additional block. The Block Erase operation starts the Program/Erase Controller after
a time-out period of 50μs after the last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any more blocks. Each additional block must
therefore be selected within 50μs of the last block. The 50μs timer restarts when an
additional block is selected. After the sixth Bus Write operation a Bus Read operation will
output the Status register. See the Status register section for details on how to identify if the
Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100μs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the 50μs
time-out period. Typical block erase times are given in Table 6.
After the Erase operation has started all Bus Read operations will output the Status register
on the Data Inputs/Outputs. See the section on the Status register for more details.
After the Block Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs Bus Read operations will continue to
output the Status register. A Read/Reset command must be issued to reset the error
condition and return to Read mode.
4.11 Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.
The Program/Erase Controller will suspend within the Erase Suspend Latency time of the
Erase Suspend Command being issued. Once the Program/Erase Controller has stopped
the memory will be set to Read mode and the Erase will be suspended. If the Erase
Suspend command is issued during the period when the memory is waiting for an additional
block (before the Program/Erase Controller starts) then the Erase is suspended immediately
and will start immediately when the Erase Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase Resume.
Co m mand interface M29W32 0ET, M29W320E B
26/65
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
During Erase Suspend a Bus Read operation to the Extended Block will output the
Extended Block data.
4.12 Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller after an
Erase Suspend. The device must be in Read Array mode before the Resume command will
be accepted. An erase can be suspended and resumed more than once.
4.13 Ente r Exten ded Blo ck comm and
The M29W320E has an extra 64Kbyte block (Extended Block) that can only be accessed
using the Enter Extended Block command. Three Bus write cycles are required to issue the
Extended Block command. Once the command has been issued the device enters
Extended Block mode where all Bus Read or Program operations to the Boot Block
addresses access the Extended Block. The Extended Block (with the same address as the
boot block) cannot be erased, and can be treated as one-time programmable (OTP)
memory. In Extended Block mode the Boot Blocks are not accessible.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Block can be protected, however once protected the protection cannot be
undone.
4.14 Exit Extended Block command
The Exit Extended Block command is used to exit from the Extended Block mode and return
the device to Read mode. Four Bus Write operations are required to issue the command.
4.15 Block Pro tect and Chip Unprot ect comm ands
Groups of blocks can be protected against accidental Program or Erase. The Protection
groups are shown in Append i x A: Blo ck Ad dres ses, Table 21 and Table 22, Block
Addresses. The whole chip can be unprotected to allow the data inside the blocks to be
changed.
Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.
M29 W320ET , M 29W32 0EB Comm and interf ace
27/65
Table 4. Comm ands , 16-bit mode , BYTE = VIH(1)(2)
Command
Length
Bus Write operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3555 AA2AA 55 X F0
Auto Select 3 555 AA 2AA 55 (BA)
555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Double word Program 3 555 50 PA0 PD0 PA1 PD1
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2X A0PAPD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 BA B0
Erase Resume 1 BA 30
Read CFI Query 1 55 98
Enter Extended Block 3 555 AA 2AA 55 555 88
Exit Extended Block 4 555 AA 2AA 55 555 90 X 00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.
2. The Command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Co m mand interface M29W32 0ET, M29W320E B
28/65
Table 5. Comm ands , 8-bit mode, BYTE = VIL(1)(2)
Command
Length
Bus Write operations
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 (BA)
AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Quadruple byte Program 5 AAA 55 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 BA B0
Erase Resume 1 BA 30
Read CFI Query 1 AA 98
Enter Extended Block 3 AAA AA 555 55 AAA 88
Exit Extended Block 4 AAA AA 555 55 AAA 90 X 00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.
2. The Command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
M29 W320ET , M 29W32 0EB Comm and interf ace
29/65
Table 6. Program, Erase times and Progra m , Erase Endurance cycles
Parameter Min Typ(1)(2) Max(2) Unit
Chip Erase 40 200(3) s
Block Erase (64 Kbytes) 0.8 6(3) s
Erase Suspend Latency time 50(4) μs
Program (byte or word) 10 200(4) μs
Double word Program (byte or word) 10 200(3) μs
Chip Program (byte by byte) 40 200(3) s
Chip Program (word by word) 20 100(3) s
Chip Program (Quadruple byte or Double word) 10 100(3) s
Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and VCC.
Status register M29W320ET, M29W320EB
30/65
5 Status register
The M29W320E has one Status register. It provides information on the current or previous
Program or Erase operations. The various bits convey information and errors on the
operation. Bus Read operations from any address, always read the Status register during
Program and Erase operations. It is also read during Erase Suspend when an address
within a block being erased is accessed.
The bits in the Status register are summarized in Table 7: Status reg ist er bits.
5.1 Data Polling bit (DQ7)
The Data Polling bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling bit is output on DQ7 when the Status register is read.
During Program operations the Data Polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
mode.
In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 7: Data Polling flowchart, gives an example of how to use the Data Polling bit. A Valid
Address is the address being programmed or an address within the block being erased.
5.2 Togg le bit (DQ6)
The Toggle bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
bit is output on DQ6 when the Status register is read.
During Program and Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle bit will output when addressing a cell within a block
being erased. The Toggle bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 8: Toggle flowchart, gives an example of how to use the Data Toggle bit. Figure 14
and Figure 15 describe Toggle bit timing waveform.
M29 W320ET , M29W320EB Sta tu s regi ster
31/65
5.3 Error bit (DQ5)
The Error bit can be used to identify errors detected by the Program/Erase Controller. The
Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
5.4 Erase Timer bit (DQ3)
The Erase Timer bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer bit
is set to ’0’ and additional blocks to be erased may be written to the Command interface.
The Erase Timer bit is output on DQ3 when the Status register is read.
5.5 Alternative Toggle bit (DQ2)
The alternative Toggle bit can be used to monitor the Program/Erase controller during Erase
operations. The alternative Toggle bit is output on DQ2 when the Status register is read.
During Chip Erase and Block Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased.
A protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error bit to be set the alternative Toggle bit can be
used to identify which block or blocks have caused the error. The alternative Toggle bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The alternative Toggle bit does not change if
the addressed block has erased correctly.
Status register M29W320ET, M29W320EB
32/65
Table 7. Status reg ister bits(1)
1. Unspecified data bits should be ignored.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Any Address DQ7 Toggle0––0
Program during
Erase Suspend Any Address DQ7 Toggle0––0
Program Error Any Address DQ7 Toggle 1 – – Hi-Z
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout
Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No
To g g le 0
Block Erase
Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No
To g g le 0
Erase Suspend
Erasing Block 1 No
To g g le 0 – Toggle Hi-Z
Non-Erasing Block Data read as normal Hi-Z
Erase Error
Good Block
Address 0 Toggle 1 1 No
To g g le Hi-Z
Faulty Block
Address 0 Toggle 1 1 Toggle Hi-Z
M29 W320ET , M29W320EB Sta tu s regi ster
33/65
Figure 7. Data Pol ling flowc har t
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI90194
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
Status register M29W320ET, M29W320EB
34/65
Figure 8. Togg le flowcha rt
1. BA = Address of Block being Programmed or Erased.
READ DQ6
ADDRESS = BA
START
READ DQ6
TWICE
ADDRESS = BA
FAIL PASS
AI08929b
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
ADDRESS = BA
M29 W320ET , M29W320EB Ma ximum rating
35/65
6 Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the Numonyx SURE
Program and other relevant quality documents.
Table 8. Absol u te ma xi mum ra tings
Symbol Parameter Min Max Unit
TBIAS Temperature under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
VIO Input or Output voltage (1)(2)
1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
–0.6 VCC +0.6 V
VCC Supply voltage –0.6 4 V
VID Identification voltage –0.6 13.5 V
VPP(3)
3. VPP must not remain at 12V for more than a total of 80hrs.
Program voltage –0.6 13.5 V
DC and ac p arameters M29W320ET, M29W320EB
36/65
7 DC and ac parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 9: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Fig u re 9. AC measureme nt I/ O waveform
Figure 10. AC measureme nt Load circuit
Table 9. Operating and ac measure m ent conditions
Parameter
M29W320ET, M29W320EB
Unit70 90
Min Max Min Max
VCC Supply voltage 2.7 3.6 2.7 3.6 V
Ambient operating temperature –40 85 –40 85 °C
Load capacitance (CL)3030pF
Input Rise and Fall times 10 10 ns
Input Pulse voltages 0 to VCC 0 to VCC V
Input and Output Timing Ref. voltages VCC/2 VCC/2 V
AI05557
VCC
0V
VCC/2
AI05558
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25kΩ
VCC
25kΩ
VCC
0.1µF
VPP
0.1µF
