1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature Write Leveling 1.5V 0.075V (JEDEC Standard Power Supply) OCD Calibration 8 Internal memory banks (BA0- BA2) Dynamic ODT (Rtt_Nom & Rtt_WR) Differential clock input (CK, ) Auto Self-Refresh Programmable Latency: 5, 6, 7, 8, 9 Self-Refresh Temperature Programmable Additive Latency: 0, CL-1, CL-2 Partial Array Self-Refresh Programmable Sequential / Interleave Burst Type RoHS Compliance Programmable Burst Length: 4, 8 Packages: 8 bit prefetch architecture Output Driver Impedance Control 78-Ball BGA for x4 & x8 components 96-Ball BGA for x16 components Description The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 1,073,741,824 bits. It is internally configured as an octal-bank DRAM. The 1Gb chip is organized as 32Mbit x 4 I/O x 8, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V 0.75V power supply and are available in BGA packages. 1 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Pin Configuration - 78 balls BGA Package (x4) < TOP View> See the balls through the package x4 1 2 3 7 8 9 VSS VDD NC A NC VSS VDD VSS VSSQ DQ0 B DM VSSQ VDDQ VDDQ DQ2 DQS C DQ1 DQ3 VSSQ VSSQ NC D VDD VSS VSSQ VREFDQ VDDQ NC E NC NC VDDQ NC VSS F CK VSS NC ODT VDD G NC H VSS BA0 BA2 VDD A3 VSS VDD CKE A10/AP ZQ NC J NC VERFCA VSS A0 K A12/ BA1 VDD A5 A2 L A1 A4 VSS VDD A7 A9 M A11 A6 VDD VSS A13 N NC A8 VSS 2 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Pin Configuration - 78 balls BGA Package (x8) < TOP View> See the balls through the package x8 1 2 3 7 8 9 VSS VDD NC A NU/ VSS VDD VSS VSSQ DQ0 B DM/TDQS VSSQ VDDQ VDDQ DQ2 DQS C DQ1 DQ3 VSSQ VSSQ DQ6 D VDD VSS VSSQ VREFDQ VDDQ DQ4 E DQ7 DQ5 VDDQ NC VSS F CK VSS NC ODT VDD G NC H VSS BA0 BA2 VDD A3 VSS VDD CKE A10/AP ZQ NC J NC VERFCA VSS A0 K A12/ BA1 VDD A5 A2 L A1 A4 VSS VDD A7 A9 M A11 A6 VDD VSS A13 N NC A8 VSS 3 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Pin Configuration - 96 balls BGA Package (x16) < TOP View> See the balls through the package x 16 1 2 3 7 8 9 VDDQ DQU5 DQU7 A DQU4 VDDQ VSS VSSQ VDD VSS B DQU6 VSSQ VDDQ DQU3 DQU1 C DQSU DQU2 VDDQ VSSQ VDDQ DMU D DQU0 VSSQ VDD VSS VSSQ DQL0 E DML VSSQ VDDQ VDDQ DQL2 DQSL F DQL1 DQL3 VSSQ VSSQ DQL6 G VDD VSS VSSQ VREFDQ DQL4 H DQL7 DQL5 VDDQ NC VSS J CK VSS NC ODT VDD K VDD CKE NC L A10/AP ZQ NC VSS BA0 BA2 M NC VREFCA VSS VDD A3 A0 N A12 BA1 VDD VSS A5 A2 P A1 A4 VSS VDD A7 A9 R A11 A6 VDD VSS NC T NC A8 VSS 4 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Input / Output Functional Description Symbol Type CK, Input Function Clock: CK and are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of . Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for CKE Input Self-Refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must maintain to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when is registered high. provides for external rank Input selection on systems with multiple memory ranks. , , Input is considered part of the command code. Command Inputs: , and (along with ) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges DM, (DMU, DML) Input of DQS. For x8 device, the function of DM or TDQS / is enabled by Mode Register A11 setting in MR1 Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or BA0 - BA2 Input Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Address Inputs: Provide the row address for Activate commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. A0 - A13 Input (A10/AP and A12/BC# have additional function as below. The address inputs also provide the op-code during Mode Register Set commands. A13 did not apply on x16 device. Burst Chop: A12/ is sampled during Read and Write commands to determine if burst chop (on A12 / BC# Input the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped). DQ Input/output Data Inputs/Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge aligned with read data, centered with write data. For the x16, DQSL corresponds to the data on DQL0 - DQL7; DQSU corresponds to DQU, DQL the data on DQU0-DQU7. The data strobes DQS, DQSL, DQSU are paired with differential signals DQS, () Input/output , , , respectively, to provide differential pair signaling to the system during both DQSL, (), reads and writes. DDR3 SDRAM supports differential data strobe only and does not support DQSU,() single-ended. 5 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Symbol Type Function On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS# and DM/TDQS, NU/TDQS# ODT Input (when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. For x16 configuration ODT is applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU and DML signal. The ODT pin will be ignored if MR1and MR2 are programmed to disable RTT. Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when Input RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.5V 0.075V VDD Supply Power Supply: VSSQ Supply DQ Ground Vss Supply Ground VREFCA Supply Reference voltage for CA VREFDQ Supply Reference voltage for DQ ZQ Supply Reference pin for ZQ calibration. 1.5V 0.075V Note: Input only pins (BA0-BA2, A0-A13, , , , , CKE, ODT, and ) do not supply termination. DDR3 SDRAM Addressing Configuration NT5CB256M4AN NT5CU128M8AN NT5CB64M16AP 8 8 8 BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A10 / AP A10 / AP A10 / AP BL switch on the fly A12 / A12 / A12 / Row Address A0 - A13 A0 - A13 A0 - A12 A0 - A9, A11 A0 - A9 A0 - A9 1KB 1KB 2KB # of Bank Bank Address Column Address Page size Note: Page size is the number of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: Page size = 2 COLBITS * ORG / 8 COLBITS = the number of column address bits ORT = the number of I/O (DQ) bits 6 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Ordering Information Green Speed Organization Part Number Package Clock (Mbp/s) Data Rate (Mb/s) CL-TRCD-TRP NT5CB256M4AN-AC 400 DDR3-800 5-5-5 NT5CB256M4AN-AD 400 DDR3-800 6-6-6 NT5CB256M4AN-BE 533 DDR3-1066 7-7-7 NT5CB256M4AN-BF 533 DDR3-1066 8-8-8 NT5CB256M4AN-CF 667 DDR3-1333 8-8-8 NT5CB256M4AN-CG 667 DDR3-1333 9-9-9 800 DDR3-1600 9-9-9 800 DDR3-1600 10-10-10 400 DDR3-800 5-5-5 NT5CB128M8AN-AD 400 DDR3-800 6-6-6 NT5CB128M8AN-BE 533 DDR3-1066 7-7-7 NT5CB128M8AN-BF 533 DDR3-1066 8-8-8 NT5CB128M8AN-CF 667 DDR3-1333 8-8-8 NT5CB128M8AN-CG 667 DDR3-1333 9-9-9 NT5CB128M8AN-DG 800 DDR3-1600 9-9-9 NT5CB128M8AN-DH 800 DDR3-1600 10-10-10 NT5CB64M16AP-AC 400 DDR3-800 5-5-5 NT5CB64M16AP-AD 400 DDR3-800 6-6-6 533 DDR3-1066 7-7-7 533 DDR3-1066 8-8-8 667 DDR3-1333 8-8-8 NT5CB64M16AP-CG 667 DDR3-1333 9-9-9 NT5CB64M16AP-DG 800 DDR3-1600 9-9-9 NT5CB64M16AP-DH 800 DDR3-1600 10-10-10 256M x 4 NT5CB256M4AN-DG NT5CB256M4AN-DH 78-Ball wBGA 0.8mmx0.8mm NT5CB128M8AN-AC Pitch 128M x 8 NT5CB64M16AP-BE NT5CB64M16AP-BF 64M x 16 96-Ball wBGA 0.8mmx0.8mm NT5CB64M16AP-CF Pitch 7 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Simplified State Diagram Power Applied Power ON Reset Procedure MRS, MPR, Write Levelizing Initialization Self Refresh SRE From any State ZQCL MRS SRX RESET ZQCL ZQCS ZQ Calibration Idle REF Refreshing PDX ACT PDE Precharge Power Down Activating Active Power Down PDE PDX Bank Active Write Read Read Write Read Writing Reading Write Write A Automatic Sequence Read A Write A Read A Read A Write A Command Sequence PRE, PREA Writing PRE, PREA Reading PRE, PREA Precharging Abbreviation ACT PRE PREA MRS REF ZQCL Function Abbreviation Function Abbreviation Function Active Read RD, RDS4, RDS8 PED Enter Power-down Precharge Read A RDA, RDAS4, RDAS8 PDX Exit Power-down Precharge All Write WR, WRS4, WRS8 SRE Self-Refresh entry Mode Register Set Write A WRA, WRAS4, WRAS8 SRX Self-Refresh exit Refresh RESET# Start RESET Procedure MPR Multi-Purpose Register ZQ Calibration Long ZQCS ZQ Calibration Short - 8 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Basic Functionality The DDR3 SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and continue for a burst length of eight or a chopped burst of four in a programmed sequence. Operation begins with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A13 select the row). The address bit registered coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BC8 mode on the fly (via A12) if enabled in the mode register. Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions and device operation. DRAM Initialization and RESET Power-up Initialization sequence The Following sequence is required for POWER UP and Initialization 1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). RESET# needs to be maintained for minimum 200us with stable power. CKE is pulled "Low" anytime before RESET# being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be no greater than 200ms; and during the ramp, VDD>VDDQ and (VDD-VDDQ)<0.3 Volts. - VDD and VDDQ are driven from a single power converter output, AND - The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once power ramp is finished, AND - Vref tracks VDDQ/2. OR - Apply VDD without any slope reversal before or at the same time as VDDQ. - Apply VDDQ without any slope reversal before or at the same time as VTT & Vref. - The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After RESET# is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 9 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP 3. Clock (CK, CK#) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meet. Also a NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered "High" after Reset, CKE needs to be continuously registered "High" until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3 DRAM will keep its on-die termination in high impedance state as long as RESET# is asserted. Further, the DRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up initialization sequence is finished, including the expiration of tDLLK and tZQinit. 5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command to load mode register. [tXPR=max(tXS, 5tCK)] 6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide "Low" to BA0 and BA2, "High" to BA1) 7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide "Low" to BA2, "High" to BA0 and BA1) 8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to BA1 and BA2) 9. Issue MRS Command to load MR0 with all application settings and "DLL reset". (To issue DLL reset command, provide "High" to A8 and "Low" to BA0-BA2) 10. Issue ZQCL command to starting ZQ calibration. 11. Wait for both tDLLK and tZQinit completed. 12. The DDR3 SDRAM is now ready for normal operation. 10 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DDR3 Reset and Initialization Sequence at Power-on Ramping Ta Tb Tc Td tCKSRX Te Tf Tg Th Ti Tj Tk CK CK RESET 10ns tIS Valid CKE Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW ODT NOP* Command BA0-BA2 MRS MRS MRS MRS MR2 MR3 MR1 MR0 ZQCL Valid NOP* Valid Valid VDD, VDDQ tDLLK T=200us Do Not Care tMRD tXPR T=500us Time break tMRD tMRD tMOD tZQinit. * From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads. DDR3 Reset Procedure at Power Stable Condition The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100ns. CKE is pulled "Low" before RESET being de-asserted (min. time 10ns). 2. Follow Power-up Initialization Sequence step 2 to 11. 3. The Reset sequence is now completed. DDR3 SDRAM is ready for normal operation. Ta Tb Tc Td tCKSRX Te Tf Tg Th Ti Tj Tk CK CK RESET 10ns tIS Valid CKE Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW ODT NOP* Command BA0-BA2 MRS MRS MRS MRS MR2 MR3 MR1 MR0 ZQCL Valid NOP* Valid Valid VDD, VDDQ tDLLK T=100ns Do Not Care T=500us Time break tXPR tMRD tMRD tMRD tMOD tZQinit. * From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads. 11 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Register Definition Programming the Mode Registers For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the DDR3 SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, contents of Mode Registers must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands shown as below. CK CK CMD MRS NOP NOP NOP NOP MRS tMRD ADDR VAL VAL CKE Do not Care Time break The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the following figure. CK CK CMD MRS NOP NOP NOP NOP Non MRS tMOD ADDR VAL VAL CKE VAL Old Setting Updating Setting New Setting The mode register contents can be changed using the same command and timing requirements during normal operation as long as 12 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the functionality and/or modes. The mode register MR0 stores data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins according to the following figure. MR0 Definition Address Filed BA2 * BA1 BA0 A13 * A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Burst Length MRS mode BA1 BA0 0 A1 A0 BL 0 0 8 (Fixed) 0 1 BC4 or 8 (on the fly) 1 0 BC4 (Fixed) 1 1 Reserved MRS mode 0 MR0 0 1 MR1 1 0 MR2 1 1 MR3 Burst Type Precharge Power Down DLL Control for Precharge PD A12 0 Slow Exit (Low Power) 1 Fast Exit (Normal) A3 Burst Type 0 Nibble Sequential 1 Interleave CAS Latency Write recovery for autoprecharge** A11 A10 A9 WR(cycles) 0 0 0 Reserved 0 0 1 5 0 1 0 6 0 1 1 7 1 0 0 8 1 0 1 10 1 1 0 12 1 1 1 Reserved A6 A5 A4 A2 CAS Latency 0 0 0 0 Reserved 0 0 1 0 5 0 1 0 0 6 0 1 1 0 7 1 0 0 0 8 1 0 1 0 9 1 1 0 0 10 1 1 1 0 Reserved Mode DLL Reset A8 DLL Reset 0 NO 1 YES * BA2 and A13 are reserved for future use and must be set to 0 when programming the MR. **WR(write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR (ns) by tCK (ns) and rounding up to the next integer: Wrmin[cycles] = Roundup(tWR/tCK). The value in the mode register must be programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL. A7 Mode 0 Normal 1 TEST 13 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Burst Length, Type, and Order Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst length options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write command via A12/. Burst Type and Burst Order Burst Length Read/ Write 4 Chop Read Write 8 Read Write Starting Column Address (A2,A1,A0) 000 001 010 011 100 101 110 111 0,V,V 1,V,V 0 1 10 11 100 101 110 111 V,V,V Burst type = Sequential Burst type = Interleaved (decimal) (decimal) A3 = 0 A3 = 1 0,1,2,3,T,T,T,T 0,1,2,3,T,T,T,T 1,2,3,0,T,T,T,T 1,0,3,2,T,T,T,T 2,3,0,1,T,T,T,T 2,3,0,1,T,T,T,T 3,0,1,2,T,T,T,T 3,2,1,0,T,T,T,T 4,5,6,7,T,T,T,T 4,5,6,7,T,T,T,T 5,6,7,4,T,T,T,T 5,4,7,6,T,T,T,T 6,7,4,5,T,T,T,T 6,7,4,5,T,T,T,T 7,4,5,6,T,T,T,T 7,6,5,4,T,T,T,T 0,1,2,3,x,x,x,x 0,1,2,3,x,x,x,x 4,5,6,7,x,x,x,x 4,5,6,7,x,x,x,x 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 Note 1,2,3 1,2,4,5 2 2,4 Note: 1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on-th-fly via A12/, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks. 2. 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst. 3. T: Output driver for data and strobes are in high impedance. 4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. 5. X: Do not Care. 14 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP CAS Latency The CAS Latency is defined by MR0 (bit A9~A11) as shown in the MR0 Definition figure. CAS Latency is the delay, in clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3 SDRAM does not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. Test Mode The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0 definition figure. Programming bit A7 to a 1 places the DDR3 SDRAM into a test mode that is only used by the DRAM manufacturer and should not be used. No operations or functionality is guaranteed if A7=1. DLL Reset The DLL Reset bit is self-clearing, meaning it returns back to the value of 0 after the DLL reset function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK must be met before any functions that require the DLL can be used. (i.e. Read commands or ODT synchronous operations) Precharge PD DLL MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or slow-exit, the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12=1), or fast-exit, the DLL is maintained after entering precharge power-down and upon exiting power-down requires tXP to be met prior to the next valid command. Write Recovery The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be equal or larger than tWR(min). 15 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Mode Register MR1 The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on , , , high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to the following figure. Address Filed BA2 * BA1 BA0 A13 * A12 A11 A10 * A9 A8 * A7 A6 A5 * A4 A3 A2 A1 A0 DLL Mode Register MR BA1 BA0 0 0 MR0 0 1 MR1 1 0 MR2 1 1 MR3 Qoff ** 0 Output buffer enabled 1 Output buffer disabled DLL Enable 0 Enable 1 Disable Output Driver Impedance Control Qoff A12 A0 A5 A1 D.I.C. 0 0 Reserved for RZQ/6 0 1 RZQ/7 1 0 RZQ/TBD 1 1 RZQ/TBD Note: RZQ=240ohms TDQS A11 ODT value TDQS enable 0 Disabled 1 Enabled Rtt_Nom*** A9 A6 A2 0 0 0 ODT Disable 0 0 1 RZQ/4 0 1 0 RZQ/2 0 1 1 RZQ/6 1 0 0 RZQ/12 1 0 1 RZQ/8 1 1 0 Reserved 1 1 1 Reserved Write Levelization A7 Write leveling enable 0 Disabled 1 Enabled Additive Latency A4 A3 AL 0 0 0 (AL disable) 0 1 CL-1 1 0 CL-2 1 1 Reserved **** **** * BA2, A5, A8, A10, and A13 are reserved for future use and must be set to 0 when programming the MR. ** Outputs disabled - DQs, DQSs, DQSs. *** In Write leveling Mode (MR1[bit7]=1) with MR1[bit12]=1, all RTT_Nom settings are allowed; in Write Leveling Mode (MR1[bit7]=1) with MR1[bit12]=0, only RTT_Nom settin gof RZQ/2, RZQ/4, and RZQ/6 are allowed. **** If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4, RZQ/6 are allowed. 16 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-Refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation, expect when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable operation in DLL-off Mode. The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode. The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2{A10,A9}={0,0}, to disable Dynamic ODT externally. Output Driver Impedance Control The output driver impedance of the DDR3 SDRAM device is selected by MR1(bit A1 and A5) as shown in MR1 definition figure. ODT Rtt Values DDR3 SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to enable a unique Rtt value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. Additive Latency (AL) Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3 SDRAM. In this operation, the DDR3 SDRAM allows a read or write command (either with or without auto-precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL register options are shown as the following table. Additive Latency (AL) Settings A4 0 0 1 1 A3 0 1 0 1 AL 0 (AL Disable) CL-1 CL-2 Reserved 17 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Write leveling For better signal integrity, DDR3 memory module adopted fly by topology for the commands, addresses, control signals, and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support write leveling in DDR3 SDRAM to compensate for skew. Output Disable The DDR3 SDRAM outputs maybe enable/disabled by MR1 (bit12) as shown in MR1 definition. When this feature is enabled (A12=1) all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device removing any loading of the output drivers. This feature may be useful when measuring modules power for example. For normal operation A12 should be set to 0. TDQS, TDQS (Termination Data Strobe) is a feature of x8 DDR3 SDRAM that provides additional termination resistance outputs that may be useful in some system configurations. TDQS is not supported in x4 and x16 configurations. When enabled via the mode register, the same termination resistance function is applied to be TDQS/ pins that are applied to the DQS/ pins. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data strobe function of RDQS is not provided by TDQS. The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided and the pin is not used. The TDQS function is available in x8 DDR3 SDRAM only and must be disabled via the mode register A11=0 in MR1 for x4 and x16 configurations. TDQS, Function Matrix MR1 (A11) DM / TDQS NU / TDQS 0 (TDQS Disabled) DM Hi-Z 1 (TDQS Enabled) TDQS TDQS Note: 1. If TDQS is enabled, the DM function is disabled. 2. When not used, TDQS function can be disabled to save termination power. 3. TDQS function is only available for x8 DRAM and must be disabled for x4 and x16 18 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Mode Register MR2 The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency. The Mode Register 2 is written by asserting low on , , , high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the table below. Address Filed BA 2 * BA 1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 PASR MRS mode BA1 BA0 MRS mode 0 0 MR0 0 1 MR1 1 0 MR2 1 1 MR3 A2 A1 A0 PASR 0 0 0 Full Array 0 0 1 Half Array (000,001,010,011 ) 0 1 0 Quarter Array (000,001) 0 1 1 1/8 Array (000) 1 0 0 3/4 array (010, 011, 100, 101, 110 , 111) 1 0 1 Half array (100, 101, 110, 111) Rtt_WR** Rtt _WR th A10 A9 0 0 Dynamic ODT off (Write does not affect RTT value ) 1 1 0 Quarter array (110, 111) 0 1 RZQ/4 1 1 1 1/8 array (111) 1 0 RZQ /2 1 1 Reserved th CAS Write Latency Self-Refresh Temperature Range A7 A5 A4 A3 CAS Write Latency 0 0 0 5 (tCK(avg)>=2.5ns) 0 0 1 6 (2.5ns >tCK(avg)>=1.875ns) 0 1 0 7 (1.875ns>tCK(avg) >=1.5ns) 0 1 1 8 (1.5ns>tCK(avg)>=1.25ns) 1 0 0 Reserved SRT 0 Normal Operating temperature range 1 Extended operating temperature range Auto Self Refresh A6 ASR 1 0 1 Reserved 0 Manual Self Refresh Reference 1 1 0 Reserved 1 ASR Enable 1 1 1 Reserved * BA2, A5, A8, A13 are reserved for future use and must be set to 0 when programming the MR . ** The Rtt _WR value can be applied during writes even when Rtt _Nom is disabled . During write leveling , Dynamic ODT is not available . 19 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Partial Array Self-Refresh (PASR) If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in MR2 will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-Refresh command is issued. CAS Write Latency (CWL) The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3 DRAM does not support any half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL); WL=AL+CWL. Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT) DDR3 SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately. Dynamic ODT (Rtt_WR) DDR3 SDRAM introduces a new feature "Dynamic ODT". In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. 20 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Mode Register MR3 The Mode Register MR3 controls Multi purpose registers. The Mode Register 3 is written by asserting low on , , , high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below. Address Filed BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MPR Location MRS mode BA1 BA0 MRS mode 0 0 MR0 0 1 MR1 1 0 MR2 1 1 MR3 A1 A0 MPR Loc. 0 0 Predefined pattern 0 1 RFU 1 0 RFU 1 1 Thermal Sensor Readout MPR A2 MPR 0 Normal Operation 1 Dataflow from MPR Note: BA2, A3-A13 are reserved for future use and must be set to 0 when programming the MR. Multi-Purpose Register (MPR) The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power down mode, Self-Refresh, and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. 21 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DDR3 SDRAM Command Description and Operation Command Truth Table 22 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP CKE Truth Table No Operation (NOP) Command The No operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP ( low and , , and high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Deselect Command The Deselect function ( HIGH) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected. 23 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DLL-off Mode DDR3 DLL-off mode is entered by setting MR1 bit A0 to "1"; this will disable the DLL for subsequent operations until A0 bit set back to "0". The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off Mode operations listed below are an optional feature for DDR3. The maximum clock frequency for DLL-off Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI. Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6. DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain. Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command, the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8) DLL-off mode READ Timing Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK CK CMD Address READ Bank, Col b RL = AL+CL = 6 (CL=6, AL=0) DQSdiff_DLL_on Din b DQ_DLL_on RL(DLL_off) = AL+(CL-1) = 5 Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tDQSCKDLL_diff_min DQSdiff_DLL_off DQ_DLL_off Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 Din b+3 Din b+4 Din b+5 Din b+6 DQSdiff_DLL_off tDQSCKDLL_diff_max DQ_DLL_off Din b Din b+1 Din b+2 Din b+7 Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same way and the skew between all DQ, DQS, and DQS# signals will still be tDQSQ. 24 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DLL on/off switching procedure DDR3 DLL-off mode is entered by setting MR1 bit A0 to "1"; this will disable the DLL for subsequent operation until A0 bit set back to "0". DLL "on" to DLL "off" Procedure To switch from DLL "on" to DLL "off" requires te frequency to be changed during Self-Refresh outlined in the following procedure: 1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL). 2. Set MR1 Bit A0 to "1" to disable the DLL. 3. Wait tMOD. 4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied. 5. Change frequency, in guidance with "Input Clock Frequency Change" section. 6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. 8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. A ZQCL command may also be issued after tXS). 9. Wait for tMOD, and then DRAM is ready for next command. DLL Switch Sequence from DLL-on to DLL-off T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 SRX 6) NOP Te 0 Te1 Tf0 CK CK tMOD CMD 1) MRS 2) NOP tCKSRE SRE 3) 4) tCKSRX 5) NOP tXS tMOD MRS 7) NOP Valid8) tCKESR CKE Valid8) ODT Valid 8) Time break Do not Care Note: ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High 1) Starting with Idle State, RTT in Hi-Z State. 2) Disable DLL by setting MR1 Bit A0 to 1. 3) Enter SR. 4) Change Frequency. 5) Clock must be stable at least tCKSRX. 6) Exit SR. 7) Update Mode registers with DLL off parameters setting. 8) Any valid command. 25 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DLL "off" to DLL "on" Procedure To switch from DLL "off" to DLL "on" (with requires frequency change) during Self-Refresh: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high impedance state before Self-Refresh mode is entered). 2. Enter Self Refresh Mode, wait until tCKSRE satisfied. 3. Change frequency, in guidance with "Input clock frequency change" section. 4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs. 5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh mode was entered. the ODT signal must continuously be registered LOW until tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered LOW or HIGH. 6. Wait tXS, then set MR1 Bit A0 to "0" to enable the DLL. 7. Wait tMRD, then set MR0 Bit A8 to "1" to start DLL Reset. 8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK). 9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued. T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf1 Tg0 Th0 SRX 5) MRS 6) MRS 7) MRS 8) Valid CK CK CMD 1) NOP SRE 2) ODTLoff + 1tck NOP tCKSRE 3) tCKSRX 4) tXS tMRD tMRD tDLLK CKE Valid tCKESR ODT Note: ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High 1) Starting from Idle State. 2) Enter SR. 3) Change Frequency. 4) Clock must be stable at least tCKSRX. 5) Exit SR. 6) Set DLL-on by MR1 A0="0" 7) Start DLL Reset 8) Any valid command Time break Do not Care 26 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Input Clock frequency change Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be "stable" during almost all states of normal operation. This means once the clock frequency has been set and is to be in the "stable state", the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specification. The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to change the clock frequency. For the first condition, once the DDR3 SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has been satisfied, the state of the clock becomes a dont care. Once a dont care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode of the sole purpose of changing the clock frequency. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. The second condition is when the DDR3 SDRAM is in Precharge Power-Down mode (either fast exit mode or slow exit mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was disabled in the mode register prior to engering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before precharge Power Down may be exited; after Precharge Power Down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock period, ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate with new clock frequency. 27 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Change Frequency during Precharge Power-down Previous Clock Frequency T0 T1 New Clock Frequency T2 Ta0 Tb0 Tc0 Tc1 tCKb tCHb tCLb tCK Td0 Td1 NOP MRS Te0 Te1 NOP Valid CK CK tCH tCL tCKSRE tCKSRX CKE tIH tIS tIS tIH tCPDED tCKE Command NOP NOP NOP NOP DLL Reset Address tAOFPD/tAOF Valid tXP ODT tIH DQS, DQS High-Z DQ High-Z tIS tDLLK DM Enter Precharge Power-Down mode Exit Precharge Power-Down mode Frequency Change Write Leveling For better signal integrity, DDR3 memory adopted fly by topology for the commands, addresses, control signals, and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support "write leveling" in DDR3 SDRAM to compensate the skew. The memory controller can use the "write leveling" feature and feedback from the DDR3 SDRAM to adjust the DQS - to CK - relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS - to align the rising edge of DQS - with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK - , sampled with the rising edge of DQS - , through the DQ bus. The controller repeatedly delays DQS - until a transition from 0 to 1 is detected. The DQS - delay established though this exercise would ensure tDQSS specification. Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS- signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in "AC Timing Parameters" section in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is show as below figure. Diff _ CK Source Diff _DQS Diff _ CK Destination Diff _ DQS DQ 0 or 1 0 0 Push DQS to capture 0 -1 transition DQ 0 or 1 1 1 28 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DQS/ driven by the controller during leveling mode must be determined by the DRAM based on ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. One or more data bits should carry the leveling feedback to the controller across the DRAM configurations x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be able for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS (diff_UDQS) to clock relationship whereas the lower data bits would indicate the lower diff_DQS (diff_LDQS) to clock relationship. DRAM setting for write leveling and DRAM termination unction in that mode DRAM enters into Write leveling mode if A7 in MR1 set "High" and after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set "Low". Note that in write leveling mode, only DQS/ terminations are activated and deactivated via ODT pin not like normal operation. MR setting involved in the leveling procedure Function Write leveling enable Output buffer mode (Qoff) MR1 A7 A12 Enable 1 0 Disable 0 1 DRAM termination function in the leveling mode ODT pin at DRAM De-asserted Asserted DQS/DQS termination off on DQs termination off off Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2, RZQ/4, and RZQ/6 are allowed. Procedure Description Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed. As well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal. Controller may drive DQS low and high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, edge which is used by the DRAM to sample CK - driven from controller. tWLMRD(max) timing is controller dependent. DRAM samples CK - status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes (DQS/DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS - delay setting and launches the next DQS/ pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS - delay setting and write leveling is achieved for the device. The following figure describes the timing diagram and parameters for the overall Write leveling procedure. 29 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Timing details of Write Leveling sequence [DQS - is capturing CK - low at T1 and CK high at T2 T1 tWLS T2 t WLH tWLS t WLH CK CK CMD M RS NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tMOD ODT t DQSL tWLDQSEN tDQSH tDQSL tDQSH Di ff_ DQS tWLMR D On e Pri me DQ: tWLO t WLO Prime DQ t WLO Late Re ma ini ng DQs Earl y Re ma ini ng DQs tWLO All DQs are Prime : tWLMRD tWLOE t WLO tWLO Late Re ma ini ng DQs t WLOE Earl y Re ma ini ng DQs tWLO tWLOE t WLO Undefined Driving Mode Do not Care Time break Note: 1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state through out the leveling procedure. 2. MRS: Load MR1 to enter write leveling mode 3. NOP: NOP or deselect 4. diff_DQS is the differential data strobe (DQS, ). Timing reference points are the zero crossings. DQS is shown with solid line, is shown with dotted line. 6. DQS/ needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent. Write Leveling Mode Exit The following sequence describes how Write Leveling Mode should be exited: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1). 2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0). 3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2). 4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1). Timing detail of Write Leveling exit T0 T1 NOP NOP T2 Ta0 Tb0 Tc0 Tc1 NOP NOP Tc2 Td0 Td1 Te0 Te1 NOP Valid NOP Valid CK CK CMD NOP NOP NOP MRS tMOD MR1 BA Valid Valid tMRD ODT tIS tWLO RTT_DQS_DQS tODTLoff tAOFmin RTT _Nom tAOFmax DQS_DQS DQ Result = 1 Time Break Transitioning Do not Care Undefined Driving Mode 30 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Extended Temperature Usage a. Auto Self-refresh supported b. Extended Temperature Range supported c. Double refresh required for operation in the Extended Temperature Range. Mode Register Description Field Bits ASR MR2(A6) SRT MR2(A7) Description Auto Self-Refresh (ASR) When enabled, DDR3 SDRAM automatically provides Self-Refresh power management functions for all supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation. 0 = Manual SR Reference (SRT) 1 = ASR enable Self-Refresh Temperature (SRT) Range If ASR = 0, the SRT bit must be programmed to indicate TOPER during subsequent Self-Refresh operation. If ASR = 1, SRT bit must be set to 0. 0 = Normal operating temperature range 1 = Extended operating temperature range Auto Self-Refresh mode - ASR mode DDR3 SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6=1 and MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended Temperature Ranges. In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by DRAM, MR2 bit A6 must set to 0. If the ASR option is not enabled (MR2 bit A6=0), the SRT bit (MR2 bit A7) must be manually programmed with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Self-Refresh Temperature Range - SRT SRT applies to devices supporting Extended Temperature Range only. If ASR=0, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh operation. If SRT=0, then the DRAM will set an appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT=1, then the DRAM will set an appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to IDD table for details. Self-Refresh mode summary MR2 A[6] MR2 A[7] 0 0 0 1 1 0 1 0 1 1 Self-Refresh operation Self-Refresh rate appropriate for the Normal Temperature Range Self-Refresh appropriate for either the Normal or Extended Temperature Ranges. The DRAM must support Extended Temperature Range. The value of the SRT bit can effect self-refresh power consumption, please refer to the IDD table for details. ASR enabled (for devices supporting ASR and Normal Temperature Range). Self-Refresh power consumption is temperature dependent. ASR enabled (for devices supporting ASR and Extended Temperature Range). Self-Refresh power consumption is temperature dependent. Illegal Allowed Operating Temperature Range for Self-Refresh mode Normal (0 ~ 85C) Normal and Extended (0 ~ 95C) Normal (0 ~ 85C) Normal and Extended (0 ~ 95C) 31 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] 0 don't care (0 or 1) 1 See the following table Function Normal operation, no MPR transaction. All subsequent Reads will come from DRAM array. All subsequent Writes will go to DRAM array. Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0]. MPR Functional Description One bit wide logical interface via all DQ pins during READ operation. Register Read on x4: DQ [0] drives information from MPR. DQ [3:1] either drive the same information as DQ [0], or they drive 0. Register Read on x8: DQ [0] drives information from MPR. DQ [7:1] either drive the same information as DQ [0], or they drive 0. Register Read on x16: DQL [0] and DQU [0] drive information from MPR. DQL [7:1] and DQU [7:1] either drive the same information as DQL[0], or they drive 0. Addressing during for Multi Purpose Register reads for all MPR agents: BA [2:0]: dont care. A [1:0]: A [1:0] must be equal to "00". Data read burst order in nibble is fixed. A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is switched on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *) A [9:3]: dont care. A10/AP: dont care. A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0 A11, A13: dont care. Regular interface functionality during register reads: Support two Burst Ordering which are switched with A2 and A[1:0]=00. Support of read burst chop (MRS and on-the-fly via A12/BC). All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the DDR3 SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR READs. Note *): Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. 32 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP MPR Register Address Definition The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read. MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function Burst Length Read Address A[2:0] Burst Order and Data Pattern Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] Read Predefined Burst order 0,1,2,3 1 00 Pattern for System BC4 000 Pre-defined Data Pattern [0,1,0,1] Calibration Burst order 4,5,6,7 BC4 100 Pre-defined Data Pattern [0,1,0,1] BL8 000 Burst order 0,1,2,3,4,5,6,7 1 01 RFU BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 BL8 000 Burst order 0,1,2,3,4,5,6,7 1 10 RFU BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 BL8 000 Burst order 0,1,2,3,4,5,6,7 1 11 RFU BC4 000 Burst order 0,1,2,3 BC4 100 Burst order 4,5,6,7 Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent. BL8 000 ACTIVE Command The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A13 selects the row. These rows remain active (or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. PRECHARGE Command The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle bank) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. 33 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP READ Operation Read Burst Operation During a READ or WRITE command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled). A12=0, BC4 (BC4 = burst chop, tCCD=4) A12=1, BL8 A12 will be used only for burst length control, not a column address. Read Burst Operation RL=5 (AL=0, CL=5, BL=8) T0 T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T145 NOP NOP NOP NOP CK CK CMD READ Address Bank Col n NOP NOP tRPRE tRPST DQS, DQS Dout n DQ CL=5 RL = AL + CL Dout n +1 Dout n +2 Dout n +3 Dout n +4 Dout n +5 Dout n +6 Dout n +7 READ Burst Operation RL = 9 (AL=4, CL=5, BL=8) T0 T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T145 NOP NOP NOP NOP CK CK CMD READ Address Bank Col n NOP NOP AL = 4 tRPRE DQS, DQS CL=5 DQ RL = AL + CL Dout n Dout n +1 Dout n +2 Dout n +3 Dout n +4 Dout n +5 READ Timing Definitions Read timing is shown in the following figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK. tDQSCK is the actual position of a rising strobe edge relative to CK, CK. tQSH describes the DQS, differential output high time. tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalide transition of the associated DQ pins. Falling data strobe edge parameters: tQSL describes the DQS, differential output low time. tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. 34 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Read Timing Definition CK CK tDQSK, min tDQSK, max Rising Strobe Region tDQSK Rising Strobe Region tQSH tQSL tQH tQH tDQSK DQS DQS tDQSQ tDQSQ Associated DQ pins Read Timing; Clock to Data Strobe relationship Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and . tDQSCK is the actual position of a rising strobe edge relative to CK and . tQSH describes the data strobe high pulse width. Falling data strobe edge parameters: tDSL describes the data strobe low pulse width. Clock to Data Strobe Relationship RL Measured to this point CK CK tLZ(DQS)min tDQSCKmin tQSH tRPRE tQSL tRPST tHZ(DQS)min DQS, DQS Early Strobe tHZ(DQS)max tDQSCKmax tLZ(DQS)max tRPST DQS, DQS Late Strobe tRPRE 35 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Read Timing; Data Strobe to Data Relationship The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and locked. Rising data strobe edge parameters: tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins. Data Strobe to Data Relationship T0 T1 T2 T3 NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 NOP NOP CK CK CMD READ Address Bank Col n NOP tRPRE NOP tDQSQmax tQH tRPST DQS, DQS tLZ(DQ)min RL = AL + CL DQ (Last data valid) DQ (First data no longer valid) tDQSQmin Dout n Dout n Dout n +1 Dout n +1 tHZ(DQ)min tQH Dout n +2 Dout n +2 Dout n +3 Dout n +3 Dout n +4 Dout n +4 Dout n +5 Dout n +5 Dout n +6 Dout n +6 Dout n +7 Dout n +7 All DQ collectively Valid data Valid data 36 REV 1.2 01 / 2009 REV 1.2 01 / 2009 Bank Col n Address Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP NOP T1 tCCD NOP tCCD NOP T2 RL = 5 RL = 5 NOP NOP T3 READ READ Bank Col b READ Bank Col b READ T4 tRPRE tRPRE NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP NOP T6 Dout n +2 NOP tRPST Dout n +3 Dout n +3 RL = 5 Dout n +2 RL = 5 NOP T7 Dout n +5 Dout n +6 Dout n +7 NOP T9 tRPRE NOP READ (BL4) to READ (BL4) NOP READ (BL8) to READ (BL8) Dout n +4 NOP T8 Dout b Dout b Dout b +1 Dout b +1 NOP NOP T10 Dout b +2 Dout b +2 NOP Dout b +3 tRPST Dout b +3 NOP T11 Dout b +4 Dout b +5 NOP NOP T12 Dout b +6 Dout b +7 NOP tRPST NOP T13 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Read to Read (CL=5, AL=0) 37 REV 1.2 01 / 2009 Bank Col n Address Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP T3 NOP T4 tRPRE NOP NOP READ RL = 5 Bank Col b WRITE tRPRE READ to Write Command delay = RL +tCCD + 2tCK -WL RL = 5 NOP T2 READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL NOP NOP T1 NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP Bank Col b Dout n +2 Dout n +3 Dout n +5 Dout n +6 Dout n +7 WL = 5 tRPST NOP T9 NOP tWPRE Dout b NOP READ (BL8) to WRITE (BL8) Dout n +4 NOP T8 READ (BL4) to WRITE (BL4) NOP NOP T7 tRPST Dout n +3 WL = 5 Dout n +2 WRITE T6 Dout b +1 Dout b +2 NOP NOP T10 NOP Dout b Dout b +3 tBL = 4 clocks tWPST tWRPRE NOP T11 Dout b +1 NOP Dout b +2 NOP T12 Dout b +3 NOP Dout b +4 NOP T13 Dout b +5 NOP Dout b +6 NOP T14 tWR tWTR Dout b +7 NOP tWPST NOP T15 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP READ to WRITE (CL=5, AL=0; CWL=5, AL=0) 38 REV 1.2 01 / 2009 Bank Col n Address Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP NOP T1 tCCD NOP tCCD NOP T2 RL = 5 RL = 5 NOP NOP T3 READ READ Bank Col b READ Bank Col b READ T4 tRPRE tRPRE NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP NOP T6 Dout n +2 NOP tRPST Dout n +3 Dout n +3 RL = 5 Dout n +2 RL = 5 NOP T7 Dout n +5 Dout n +6 Dout n +7 NOP T9 tRPRE NOP READ (BC4) to READ (BL8) NOP READ (BL8) to READ (BC4) Dout n +4 NOP T8 Dout b Dout b Dout b +1 Dout b +1 NOP NOP T10 Dout b +2 Dout b +2 Dout b +3 Dout b +3 NOP tRPST NOP T11 Dout b +4 Dout b +5 NOP NOP T12 Dout b +6 Dout b +7 tRPST NOP NOP T13 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP READ to READ (CL=5, AL=0) 39 REV 1.2 01 / 2009 Bank Col n Address Bank Col n Address DQ DQS, DQS READ CMD DQ DQS, DQS READ CMD CK CK T0 NOP T3 READ NOP T4 tRPRE NOP RL = 5 NOP READ RL = 5 Bank Col b WRITE tRPRE READ to WRITE Command delay = RL + tCCD +2tCK - WL NOP T2 READ to WRITE Command delay = RL + tCCD/2 +2tCK - WL NOP NOP T1 NOP NOP T5 Dout n Dout n Dout n +1 Dout n +1 NOP Bank Col b Dout n +2 NOP NOP T7 tRPST Dout n +3 Dout n +3 WL = 5 Dout n +2 WRITE T6 Dout n +5 Dout n +6 Dout n +7 WL = 5 tRPST NOP T9 tWPRE Dout b NOP READ (BL4) to WRITE (BL8) NOP READ (BL8) to WRITE (BC4) Dout n +4 NOP T8 Dout b +1 Dout b +2 NOP NOP T10 Dout b +3 tWPRE Dout b +4 NOP Dout b NOP T11 Dout b +5 Dout b +1 Dout b +6 NOP Dout b +2 NOP T12 NOP Dout b +7 tWPST Dout b +3 tWPST NOP T13 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP READ to WRITE (CL=5, AL=0; CWL=5, AL=0) 40 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Write Operation During a READ or WRITE command, DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (Auto Precharge can be enabled or disabled). A12=0, BC4 (BC4 = Burst Chop, tCCD=4) A12=1, BL8 A12 is used only for burst length control, not as a column address. WRITE Timing Violations Motivation Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to "hang up" and errors be limited to that particular operation. For the following, it will be assumed that there are no timing violations w.r.t. to the Write command itself (including ODT, etc.) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly otherwise. Strobe to Strobe and Strobe to Clock Violations Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. Write Timing Parameters This drawing is for example only to enumerate the strobe edges that "belong" to a write burst. No actual timing violations are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge - as shown). 41 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Write Timing Definition T0 T1 T2 T3 CMD Write NOP NOP NOP Address Bank Col n T4 T5 T6 NOP NOP T7 T8 T9 Tn NOP NOP NOP CK CK NOP NOP tDSH tDSH tDSH tDQSS tDSH tWPST(min) tDSS tWPRE(min) DQS, DQS (tDQSS min) tDQSH tDQSL tDQSH Din n DQ tDQSH tDSS tDSS Din n +1 tDQSL(min) tDSS Din n +2 Din n +3 Din n +4 Din n +5 Din n +6 Din n +7 tDSS WL = AL + CWL tWPST(min) tDSH tDSH tDSH tDSH tDSS tWPRE(min) DQS, DQS (tDQSS nominal) tDQSH tDQSL tDQSH Din n DQ tDQSH tDSS tDSS Din n +1 tDQSL(min) tDSS Din n +2 Din n +3 Din n +4 Din n +5 Din n +6 Din n +7 tDSS tDSH tDQSS tDSH tWPRE(min) tWPST(min) tDSH tDSH DQS, DQS (tDQSS max) tDSS tDQSH tDQSL DQ tDSS tDSS tDQSH Din n Din n +1 Din n +2 Din n +3 Din n +4 Din n +5 tDQSH Din n +6 tDQSL(min) Din n +7 tDSS tDSS Note: 1. BL=8, WL=5 (AL=0, CWL=5). 2. Din n = data in from column n. 3. NOP commands are shown for ease of illustration; other command may be valid at these times. 4. BL8 setting activated by either MR0 [A1:0=00] or MR0 [A1:0=01] and A12 = 1 during WRITE command at T0. 4. tDQSS must be met at each rising clock edge. 42 REV 1.2 01 / 2009 REV 1.2 01 / 2009 Bank Col n Address Bank Col n Address DQ DQS, DQS WRITE CMD DQ DQS, DQS WRITE CMD CK CK T0 NOP NOP T1 WL = 5 NOP T3 WL = 5 NOP READ WRITE (BC4) to WRITE (BC4) tCCD NOP WRITE (BL8) to WRITE (BL8) tCCD NOP T2 Bank Col b WRITE Bank Col b WRITE T4 tRPRE tWPRE Dout n NOP Dout n NOP T5 Dout n +1 Dout n +1 Dout n +2 NOP Dout n +2 NOP T6 NOP Dout n +4 Dout n +3 WL = 5 tWPST WL = 5 Dout n +3 NOP T7 Dout n +5 NOP Dout n +6 NOP T8 tWPRE Dout n +7 Dout b NOP Dout b NOP T9 Dout b +1 Dout b +1 Dout b +2 NOP Dout b +2 NOP T10 tBL=4 NOP Dout b +4 Dout b +3 tWPST Dout b +3 tBL=4 NOP T11 Dout b +5 NOP Dout b +6 NOP T12 Dout b +7 NOP tWPST NOP T13 tWTR tWR tWTR tWR 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP WRITE to WRITE (WL=5; CWL=5, AL=0) 43 REV 1.2 01 / 2009 Bank Col n Address Bank Col n Address DQ DQS, DQS WRITE CMD DQ DQS, DQS WRITE CMD CK CK T0 NOP NOP T1 WL = 5 NOP T3 WL = 5 NOP WRITE (BC4) to READ (BC4/BL8) NOP WRITE (BL8) to READ (BC4/BL8) NOP T2 NOP NOP T4 tRPRE tWPRE NOP Dout n NOP T5 Dout n Dout n +1 Dout n +1 NOP Dout n +2 NOP T6 Dout n +2 NOP Dout n +4 tBL=4 Dout n +3 tWPST Dout n +3 NOP T7 Dout n +5 NOP Dout n +6 NOP T8 Dout n +7 NOP tWPST NOP T9 NOP NOP T10 tWTR NOP tWTR NOP T11 NOP NOP T12 Bank Col b READ Bank Col b READ T13 RL=5 RL=5 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP WRITE to READ (RL=5, CL=5, AL=0; WL=5, CWL=5, AL=0; BL=4) 44 REV 1.2 01 / 2009 Bank Col n Address Bank Col n Address DQ DQS, DQS WRITE CMD DQ DQS, DQS WRITE CMD CK CK T0 NOP NOP T1 WL = 5 NOP T3 WL = 5 NOP READ WRITE (BC4) to WRITE (BL8) tCCD NOP WRITE (BL8) to WRITE (BC4) tCCD NOP T2 Bank Col b WRITE Bank Col b WRITE T4 tRPRE tWPRE Dout n NOP Dout n NOP T5 Dout n +1 Dout n +1 Dout n +2 NOP Dout n +2 NOP T6 NOP Dout n +4 Dout n +3 WL = 5 tWPST WL = 5 Dout n +3 NOP T7 Dout n +5 NOP Dout n +6 NOP T8 tWPRE Dout n +7 Dout b NOP Dout b NOP T9 Dout b +1 Dout b +1 Dout b +2 NOP Dout b +2 NOP T10 Dout b +3 Dout b +3 Dout b +3 tBL=4 NOP tWPST tBL=4 NOP T11 Dout b +4 Dout b +5 NOP NOP T12 Dout b +6 Dout b +7 tWPST NOP NOP T13 tWTR tWR tWTR tWR 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP WRITE to WRITE (WL=5, CWL=5, AL=0) 45 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Self-Refresh Operation The Self-Refresh command can be used to retain data in the DDR3 SDRAM, even if the reset of the system is powered down. When in the Self-Refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by having , , , and held low with WE high at the rising edge of the clock. Before issuing the Self-Refreshing-Entry command, the DDR3 SDRAM must be idle with all bank precharge state with tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering ODT pin low "ODTL + 0.5tCK" prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically enabled (including a DLL-RESET) upon exiting Self-Refresh. When the DDR3 SDRAM has entered Self-Refresh mode, all of the external control signals, execpt CKE and , are "dont care". For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within tCKE period once it enters Self-Refresh mode. The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3 SDRAM must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device can exit Self-Refresh mode. The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements [TBD] must be satisfied. CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry. Upon exit from Self-Refresh, the DDR3 SDRAM can be put back into Self-Refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3 SDRAM requires a minimum of one extra refresh command before it is put back into Self-Refresh mode. 46 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Self-Refresh Entry/Exit Timing T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Te0 Tf Valid Valid CK, CK tCKSRE tCKSRX tCPDED CKE tCKESR Valid ODT ODTL CMD NOP SRE NOP SRX Note: 1. Only NOP or DES commands 2. Valid commands not requiring a locked DLL 3. Valid commands requiring a locked DLL Valid 2) Valid 3) Valid Valid tXS tXSDLL tRF Enter Self Refresh NOP 1) Exit Self Refresh Do Not Care Time Break Refresh Command The Refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command is not persistent, so it must be issued each time a refresh is required. The DDR3 SDRAM requires Refresh cycles at an average periodic interval of tREFI. When , , and are held Low and WE High at the rising edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Dont Care" during a Refresh command. An internal address counter suppliers the address during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as shown in the following figure. In general, a Refresh command needs to be issued to the DDR3 SDRAM regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 Refresh commands can be postponed during operation of the DDR3 SDRAM, meaning that at no point in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A maximum of 8 additional Refresh commands can be issued in advance ("pulled in"), with each one reducing the number of regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh commands must be executed. 47 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Self-Refresh Entry/Exit Timing T0 T1 REF NOP Ta0 Ta1 REF NOP Tb0 Tb1 Tb2 Tb3 Valid Valid Valid Valid Tc0 Tc1 REF Valid CK CK CMD NOP tRFC NOP Valid tRFC(min) DRAM must be idle tREFI (max, 9 x tREFI) DRAM must be idle Time Break Postponing Refresh Commands (Example) tREFI 9 x tREFI t tREFI 8 REF-Command postponed Pulled-in Refresh Commands (Example) tREFI 9 x tREFI t tREFI 8 REF-Commands pulled-in 48 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Power-Down Modes Power-Down Entry and Exit Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write operation are in progress. CKE is allowed to go low while any of other operation such as row activation, precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operation. The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in precharge Power-Down mode; if any bank is open after in progress commands are completed, the device will be in active Power-Down mode. Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, , and . To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed during the CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED has expired. Power-Down Entry Definitions Status of DRAM MRS bit A12 DLL PD Exit Don't Care On Fast Relevant Parameters Active tXP to any valid command. (A Bank or more open) tXP to any valid command. Since it is in precharge state, Precharged commands here will be ACT, AR, MRS/EMRS, PR, or PRA. 0 Off Slow (All Banks Precharged) tXPDLL to commands who need DLL to operate, such as RD, RDA, or ODT control line. Precharged 1 On Fast tXP to any valid command. (All Banks Precharged) Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, high, and a stable clock signal must be maintained at the inputs of the DDR3 SDRAM, and ODT should be in a valid state but all other input signals are "Dont care" (If goes low during Power-Down, the DRAM will be out of PD mode and into reset state). CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet. 49 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Active Power Down Entry and Exit timing diagram T0 T1 T2 Valid NOP NOP Ta0 Ta1 Tb0 Tb1 Tc0 NOP NOP NOP Valid Valid CK CK CMD tIS NOP tPD tIH CKE tIH tIS Address tCKE Valid Valid tCPDED tXP Enter Power-Down Exit Power-Down Do not care Time Break Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge, Activate, Precharge, Refresh, MRS: Power-Down Entry after Read and Read with Auto Precharge T0 T1 Ta0 Ta1 Ta2 RD or RDA NOP NOP NOP NOP Ta3 Ta4 Ta5 Ta6 NOP NOP NOP NOP Ta7 Ta8 Tb0 Tb1 NOP NOP NOP Valid CK CK CMD tIS tCPDED CKE Valid tPD Address Valid Valid RL = AL + CL DQS BL8 Din b Din b+1 Din b+2 Din b+3 BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tRDPDEN Power-Down Entry Do not care Time Break Power-Down Entry after Write with Auto Precharge T0 T1 Ta0 Ta1 Ta2 WRITE NOP NOP NOP NOP Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tc0 NOP NOP Valid CK CK CMD NOP tIS CKE Address tCPDED Bank, Col n WL=AL+CWL WR (1) tPD DQS BL8 Din b Din b+1 Din b+2 Din b+3 BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 Start Internal Precharge tWRAPDEN Power-Down Entry Do not care Time Break 50 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Power-Down Entry after Write T0 T1 Ta0 Ta1 Ta2 WRITE NOP NOP NOP NOP Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tc0 CK CK CMD NOP tIS CKE Address NOP NOP tCPDED Bank, Col n WL=AL+CWL WR tPD DQS BL8 Din b Din b+1 Din b+2 Din b+3 BC4 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 tWRPDEN Power-Down Entry Do not care Time Break Precharge Power-Down (Fast Exit Mode) Entry and Exit T0 T1 WRITE NOP T2 Ta0 Ta1 NOP NOP Tb0 Tb1 Tc0 NOP NOP NOP CK CK CMD NOP tCPDED T0 tCKE tIS tIH CKE NOP CK Valid tIS tPD tXP Enter Power-Down Mode CK Exit Power-Down Mode Do not care Time Break CMD Precharge Power-Down (Slow Exit Mode) Entry and Exit T0 T1 T2 Ta0 Ta1 WRITE NOP NOP NOP NOP Tb0 Tb1 Tc0 NOP NOP Valid Td0 Address CK CK CMD tCPDED Valid CKE tCKE tIS tIH CKE NOP Valid Valid tIS tXP tPD tXPDLL Enter Power-Down Mode Exit Power-Down Mode Do not care Time Break Refresh Command to Power-Down Entry T0 T1 T2 T3 Ta0 CMD REF NOP NOP NOP Address Valid Ta1 CK CK Valid Valid tIS tCPDED tPD CKE Valid tREFPDEN Do not care Time Break 51 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Active Command to Power-Down Entry T0 T1 T2 T3 Ta0 CMD Active NOP NOP NOP Address Valid Ta1 CK CK Valid Valid tCPDED tIS tPD CKE Valid tACTPDEN Do not care Time Break Precharge/Precharge all Command to Power-Down Entry T0 T1 T2 T3 Ta0 CMD PRE PREA NOP NOP NOP Address Valid Ta1 CK CK Valid Valid tIS tCPDED tPD CKE Valid tPREPDEN Do not care Time Break MRS Command to Power-Down Entry T0 T1 Ta0 Ta1 CMD MRS NOP NOP NOP Address Valid Tb0 Tb1 CK CK Valid Valid tIS tCPDED tPD CKE Valid tMRSPDEN Do not care Time Break 52 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP On-Die Termination (ODT) ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination resistance for each DQ, DQS, , and DM for x4 and x8 configuration (and TDQS, for x8 configuration, when enabled via A11=1 in MR1) via the ODT control pin. For x16 configuration, ODT is applied to each DQU, DQL, DQSU, , DQSL, , DMU, and DML signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT feature is turned off and not supported in Self-Refresh mode. A simple functional representation of the DRAM ODT feature is shown as below. ODT To other circuitry like RCV, ... VDDQ / 2 RTT Switch DQ , DQS, DM, TDQS The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1 and MR2 are programmed to disable ODT and in self-refresh mode. ODT Mode Register and ODT Truth Table The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is determined by the settings of those bits. Application: Controller sends WR command together with ODT asserted. One possible application: The rank that is being written to provides termination. DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR) DRAM does not use any write or read command decode information. Termination Truth Table ODT pin DRAM Termination State 0 OFF 1 ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general) 53 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes are: Any bank active with CKE high Refresh with CKE high Idle mode with CKE high Active power down mode (regardless of MR0 bit A12) Percharge power down mode if DLL is enabled during precharge power down by MR0 bit A12 The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode. In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write latency (WL) by: ODTLonn = WL - 2; ODTLoff = WL-2. ODT Latency and Posted ODT In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3 SDRAM latency definitions. ODT Latency Symbol Parameter DDR3 SDRAM Unit ODTLon ODT turn on Latency WL - 2 = CWL + AL - 2 tCK ODTLoff ODT turn off Latency WL - 2 = CWL + AL - 2 tCK Timing Parameters In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, AOF min/max. Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from ODTLoff. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered low. 54 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6; ODTLoff=AL+CWL-2=6 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T14 T13 T15 CK CK CKE ODT AL=3 AL=3 tAONmax CWL - 2 tAONmax ODTH4, min ODTLon = CWL + AL -2 tAONmin tAONmin ODTLoff = CWL + AL -2 RTT_NOM DRAM_RTT Transitioning Do not care Synchronous ODT example with BL=4, WL=7 T0 T1 T2 NOP NOP NOP T3 T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK NOP NOP WRS4 NOP ODTH4 ODTH4 ODT ODTH4min ODTLoff = CWL -2 tAONmin ODTLoff = WL - 2 tAOFmax tAONmax tAOFmax tAONmax tAONmin tAOFmin tAOFmin RTT_NOM DRAM_RTT ODTLon = CWL -2 ODTLon = CWL -2 Transitioning Do not care ODT must be held for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8 (BL=8) after Write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of Write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the Write command at T7. ODT during Reads: As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example. ODT must be disabled externally during Reads by driving ODT low. (Example: CL=6; AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CMD Read Address Valid NOP NOP NOP NOP NOP NOP NOP RL = AL + CL ODT ODTLon = CWL + AL - 2 ODTLoff = CWL + AL - 2 tAONmax tAOFmin DRAM ODT RTT_NOM RTT RTT_NOM tAOFmax DQSdiff DQ Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 55 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by the "Dynamic ODT" feature as described as follows: Functional Description The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to 1. The function is described as follows: Two RTT values are available: RTT_Nom and RTT_WR. The value for RTT_Nom is preselected via bits A[9,6,2] in MR1. The value for RTT_WR is preselected via bits A[10,9] in MR2. During operation without write commands, the termination is controlled as follows: Nominal termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff. When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termination is controlled as follows: A latency ODTLcnw after the write command, termination strength RTT_WR is selected. A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the write command, termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff. The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic ODT mode. The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9 = [0,0], to disable Dynamic ODT externally. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of Write command until ODT is register low. 56 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Latencies and timing parameters relevant for Dynamic ODT Name and Description Abbr. ODT turn-on Latency ODTLon ODT turn-off Latency ODTLoff ODT Latency for changing from RTT_Nom to RTT_WR ODT Latency for change from RTT_WR to RTT_Nom (BL=4) ODT Latency for change from RTT_WR to RTT_Nom (BL=8) Minimum ODT high time after ODT assertion Minimum ODT high time after Write (BL=4) Minimum ODT high time after Write (BL=8) Defined from registering external ODT signal high registering external ODT signal low ODTLcnw registering external write command ODTLcwn4 registering external write command ODTLcwn8 registering external write command ODTH4 registering ODT high ODTH8 RTT change skew tADC Unit turning termination on ODTLon=WL-2 tCK turning termination off ODTLoff=WL-2 tCK ODTLcnw=WL-2 tCK ODTLcwn4=4+ODTLoff tCK ODTLcwn8=6+ODTLoff tCK(avg) ODT registered low ODTH4=4 tCK(avg) ODT registered low ODTH4=4 tCK(avg) ODT register low ODTH8=6 tCK(avg) RTT valid tADC(min)=0.3tCK(avg) tADC(max)=0.7tCK(avg) tCK(avg) change RTT strength from RTT_Nom to RTT_WR change RTT strength from RTT_WR to RTT_Nom change RTT strength from RTT_WR to RTT_Nom registering write with ODT high registering write with ODT high ODTLcnw ODTLcwn ODTH4 Definition for all DDR3 speed pin Defined to Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn) ODT Timing Diagrams Dynamic ODT: Behavior with ODT being asserted before and after the write T0 T1 T2 T3 NOP NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CMD WRS4 Address NOP Valid ODT ODTLoff ODTH4 ODTLcwn4 tADCmin tAONmin RTT_Nom RTT RTT_WR tAONmax ODTLon tAOFmin tADCmin RTT_Nom tADCmax tADCmax tAOFmax ODTLcnw ODTH4 DQS/DQS WL DQ Din n Din n+1 Din n+2 Din n+3 Do not care Transitioning Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write command. In tihs example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command). 57 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Dynamic ODT: Behavior without write command, AL=0, CWL=5 T0 T1 T2 T3 T4 Valid Valid Valid Valid T5 T6 Valid Valid T7 T8 T9 T10 T11 Valid Valid Valid Valid CK CK CMD Valid Valid Address ODTLoff ODT ODTH4 ODTLoff tADCmin tAONmin RTT_Nom RTT tADCmax tAONmax ODTLon DQS/DQS DQ Do not care Transitioning Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration of 6 clock cycles. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK CMD NOP WRS8 NOP NOP NOP NOP NOP NOP ODTLcnw Address Valid ODT ODTH8 ODTLoff ODTLon tAOFmin tAONmin RTT_WR RTT tAOFmax tAONmax ODTLcwn8 DQS/DQS WL DQ Din h Din h+1 Din h+2 Din h+3 Din h+4 Din h+5 Din h+6 Din h+7 Do not care Transitioning Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied. 58 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF), AL=0, CWL=5. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK CMD ODTLcnw NOP WRS4 NOP NOP NOP NOP NOP NOP Valid Address ODT ODTH4 tAONmin ODTLoff tADCmin RTT_WR RTT tAOFmin RTT_Nom tAONmax tAOFmax tADCmax ODTLon ODTLcwn4 DQS/DQS WL Din n DQ Din n+1 Din n+2 Din n+3 Do not care Transitioning Dynamic ODT: Behavior with ODT pin being asserted together with write command for the duration of 4 clock cycles. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP CK CK# CMD ODTLcnw NOP Address WRS4 NOP NOP NOP NOP NOP NOP Valid ODT ODTH4 tAONmin ODTLoff tAOFmin RTT_WR RTT tAONmax tAOFmax ODTLon ODTLcwn4 DQS/DQS WL DQ Din n Din n+1 Din n+2 Din n+3 Do not care Transitioning 59 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power down mode if DLL is disabled during precharge power down by MR0 bit A12. In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the external ODT command. In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max. Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in time when the ODT resistance is fully on. tAONPDmin and tAONPDmax are measured from ODT being sampled high. Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low. Asynchronous ODT Timings on DDR3 SDRAM with fast ODT transition: AL is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK CK# CKE tIS tIH ODT tIS tIH tAONPDmax tAOFPDmin RTT tAONPDmin tAOFPDmax Do not care Transitioning In Precharge Power Down, ODT receiver remains active, however no Read or Write command can be issued, as the respective ADD/CMD receivers may be disabled. Asynchronous ODT Timing Parameters for all Speed Bins Symbol Description min max Unit tAONPD Asynchronous RTT turn-on delay (Power-Down with DLL frozen) 1 9 ns tAOFPD Asynchronous RTT turn-off delay (Power-Down with DLL frozen) 1 9 ns ODT timing parameters for Power Down (with DLL frozen) entry and exit transition period Description min max ODT to RTT min{ ODTLon * tCK + tAONmin; tAONPDmin } max{ ODTLon * tCK + tAONmax; tAONPDmax } turn-on delay min{ (WL - 2) * tCK + tAONmin; tAONPDmin } max{ (WL - 2) * tCK + tAONmax; tAONPFmax } ODT to RTT min{ ODTLoff * tCK + tAOFmin; tAOFPDmin } max{ ODTLoff * tCK + tAOFmax; tAOFPDmax } turn-off delay min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin } max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax } tANPD WL-1 60 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to "0", there is a transition period around power down entry, where the DDR3 SDRAM may show either synchronous or asynchronous ODT behavior. The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where CKE is first registered low. The transition period begins with the starting point of tANPD and terminates at the end point of tCPDED(min). If there is a Refresh command in progress while CKE goes low, then the transition period ends at the later one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please note that the actual starting point at tANPD is excluded from the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are included in the transition period. ODT assertion during the transition period may result in an RTT changes as early as the smaller of tAONPDmin and (ODTLon*tck+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK+tAOFmax). Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition period. Synchronous to asynchronous transition during Precharge Power Down (with DLL frozen) entry (AL=0; CWL=5; tANPD=WL-1=4) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK CK CMD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CKE tANPD tCPDEDmin tCPDED PD entry transition period Last sync. ODT tAOFmin RTT RTT ODTLoff tAOFmax Sync. Or async. ODT RTT RTT tAOFPDmin tAOFPDmax ODTLoff+tAOFPDmin ODTLoff+tAOFPDmax First async. ODT tAOFPDmax RTT RTT tAOFPDmin Transitioning Do not care Time Break 61 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Asynchronous to Synchronous ODT Mode transition during Power-Down Exit If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to "0", there is also a transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM. This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and (ODTLon*tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition period with synchronous response. Asynchronous to synchronous transition during Precharge Power Down (with DLL frozen) exit (CL=6; AL=CL-1; CWL=5; tANPD=WL-1=9) T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Td0 Td1 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK CKE CMD NOP NOP NOP NOP NOP tANPD tXPDLL PD exit transition period ODT_C _sync tAOFPDmin DRAM _RTT_ C_sync RTT tAOFPDmax ODT_B _tran tAOFPDmin DRAM _RTT_ B_tran RTT tAOFPDmax ODTLoff + tAOFmin ODTLoff + tAOFmax ODTLoff ODT_A _async tAOFmax tAOFmin DRAM_ RTT_A_ async RTT Transitioning Do not care Time Break 62 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit may overlap. In this case, the response of the DDR3 SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period (even if the entry ends later than the exit period). If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the response of the DDR3 SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from the state of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is assumed that there was no Refresh command in progress when Idle state was entered. Transition period for short CKE cycles with entry and exit period overlapping (AL=0; WL=5; tANPD=WL-1=4) T0 T1 T2 T3 REF NOP NOP NOP T4 T5 T6 NOP NOP T7 T8 T9 T10 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP NOP CK CK CMD NOP NOP CKE tANPD tANPD PD exit transition period PD entry transition period tRFC(min) tXPDLL CKE Short CKE high transition period tXPDLL Do not care Transitioning ZQ Calibration Commands ZQ Calibration Description ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3 SDRAM needs longer time to calibrate output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations. ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO which gets reflected as updated output driver and on-die termination values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing period of tZQoper. ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after self refresh exit is tXS. In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or tZQCS between ranks. 63 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP ZQ Calibration Timing T0 T1 Ta0 Ta1 ZQCL NOP NOP NOP Ta2 Ta3 Tb0 Tb1 Valid Valid ZQCS Address Valid Valid A10 Valid Valid Tc0 Tc1 Tc2 NOP NOP Valid CK CK CMD NOP Valid CKE (1) Valid Valid (1) Valid ODT (2) Valid Valid (2) Valid DQ Bus (3) Hi-Z Activities (3) Hi-Z tZQCS Activities tZQCS Do not care Time Break Note: 1. CKE must be continuously registered high during the calibration procedure. 2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure. 3. All devices connected to the DQ bus should be high impedance during the calibration procedure. ZQ External Resistor Value, Tolerance, and Capacitive loading In order to use the ZQ calibration function, a 240 ohm +/- 0.1% tolerance external resistor connected between the ZQ pin and ground. The single resistor can be used for each SDRAM or one resistor can be shared between two SDRAMs if the ZQ calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin must be limited. Absolute Maximum Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Vin, Vout Tstg Parameter Rating Units Note Voltage on VDD pin relative to Vss -0.4 ~ 1.975 V 1,3 Voltage on VDDQ pin relative to Vss -0.4 ~ 1.975 V 1,3 Voltage on any pin relative to Vss -0.4 ~ 1.975 V 1 -55 ~ 100 C 1,2 Storage Temperature Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when VDD and VDDQ are less than 500mV; Vref may be equal to or less than 300mV. 64 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Temperature Range Symbol Parameter Rating Units Notes Normal Operating Temperature Range 0 to 85 C 1,2 Extended Temperature Range 85 to 95 C 1,3 Toper Note: 1. Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the following additional apply: a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. It is also possible to specify a component with 1x refresh (tREFI to 7.8us) in the Extended Temperature Range. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable the optional Auto Self-Refresh mode (MR2 A6=1 and MR2 A7=0). AC & DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Parameter Rating Unit Note 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.5 Supply Voltage for Output 1.425 1.5 Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 65 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP AC & DC Input Measurement Levels AC and DC Logic Input Levels for Single-Ended Signals & Command and Address Symbol Parameter DDR3-800/1066 DDR3-1333/1600 Min. Max. Min. Max. Unit Note VIH.CA(DC) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1 VIL.CA(DC) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.CA(AC) AC input logic high Vref + 0.175 Note2 Vref + 0.175 Note2 V 1,2 VIL.CA(AC) AC input logic low Note2 Vref - 0.175 Note2 Vref - 0.175 V 1,2 VIH.CA(AC150) AC input logic high - - Vref + 0.150 Note2 V 1,2 VIL.CA(AC150) AC input logic low - - - Vref - 0.150 V 1,2 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4 Unit Note Reference Voltage for VREFCA(DC) ADD, CMD inputs Note: 1. For input only pins except RESET.Vref=VrefCA(DC) 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 0.1% VDD. 4. For reference: approx. VDD/2 +/- 15mV. AC and DC Logic Input Levels for Single-Ended Signals & DQ and DM Symbol Parameter DDR3-1066 DDR3-1333 Min. Max. Min. Max. VIH.DQ(DC) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1 VIL.DQ(DC) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1 VIH.DQ(AC) AC input logic high Vref + 0.175 Note2 Vref + 0.150 Note2 V 1,2,5 VIL.DQ(AC) AC input logic low Note2 Vref - 0.175 Note2 Vref - 0.150 V 1,2,5 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4 Reference Voltage for VREFDQ(DC) DQ, DM inputs Note: 1. For input only pins except RESET.Vre=VrefDQ(DC) 2. See "Overshoot and Undershoot Specifications" 3. The ac peak noise on Vref may not allow Vref to deviate from Vref(DC) by more than +/- 0.1% VDD. 4. For reference: approx. VDD/2 +/- 15mV. 5. Single-ended swing requirement for DQS, DQS is 350mV (peak to peak). Differential swing requirement for DQS, DQS is 700mV (peak to peak) 66 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Vref Tolerances The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise). Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than +/-1% VDD. The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref. "Vref" shall be understood as Vref(DC). The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for Vref(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (+/-1% of VDD) are included in DRAM timing and their associated deratings. Illustration of Vref(DC) tolerance and Vref ac-noise limits Voltage VDD Vref ac-noise Vref(DC)max Vref(DC) VDD/2 Vref(DC)min VSS time AC and DC Logic Input Levels for Differential Signals Symbol Parameter Min. Max. Unit Notes VIHdiff Differential input logic high 0.2 note3 V 1 VILdiff Differential input logic low note3 -0.2 V 1 VIHdiff(ac) Differential input high ac 2 x (VIH(ac) - Vref) note3 V 2 VILdiff(ac) Differential input low ac note3 2 x (Vref - VIL(ac)) V 2 Note: 1. Used to define a differential signal slew-rate. 2. For CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also there. 3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot. 67 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Differential Input Voltage (i.e. DQS - DQS, CK - CK) Definition of differential ac-swing and "time above ac-level" tDVAC VIH.Diff.AC.min VIH.Diff. DC min 0 Half cycle VIL. Diff. DC max VIL.Diff.AC.max tDVAC Time Allowed time before ringback (tDVAC) for CK - and DQS - Slew Rate [V/ns] > 4.0 4 3 2 1.8 1.6 1.4 1.2 1 < 1.0 tDVAC [ps] @IVIH/Ldiff(ac)I = 350mV min 75 57 50 38 34 29 22 13 0 0 max - tDVAC [ps] @IVIH/Ldiff(ac)I = 300mV min 175 170 167 163 162 161 159 155 150 150 max - Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, , , , or ) has also to comply with certain requirements for single-ended signals. CK and have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH(ac) / VIL(ac)) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH(ac) / VIL(ac)) for DQ signals) in every half-cycle proceeding and following a valid transition. 68 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Single-ended levels for CK, DQS, DQSL, DQSU, , , , or Symbol Parameter Min Max Unit Notes Single-ended high-level for strobes (VDDQ/2) + 0.175 note3 V 1, 2 Single-ended high-level for CK, CK (VDDQ/2) + 0.175 note3 V 1, 2 Single-ended low-level for strobes note3 (VDDQ/2) - 0.175 V 1, 2 Single-ended Low-level for CK, CK note3 (VDDQ/2) - 0.175 V 1, 2 VSEH VSEL Note: 1. For CK, CK use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) use VIH/VIL(ac) of DQs. 2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also there. 3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot. Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in the following table. The differential input cross point voltage Vix is measured from the actual cross point of true and completement signal to the midlevel between of VDD and VSS. Vix Definition Cross point voltage for differential input signals (CK, DQS) Symbol Vix Parameter Differential Input Cross Point Voltage relative to VDD/2 for CK, CK Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS Min. -150 -175 Max. 150 175 Unit mV mV -150 150 mV Note 1 Note1: Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 250mV, and when the differential slew rate of CK - CK is larger than 3V/ns. 69 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Slew Rate Definition for Differential Input Signals Differential Input Slew Rate Definition Measured Description Defined by From To VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff Differential input slew rate for rising edge (CK-CK & DQS-DQS) Differential input slew rate for falling edge (CK-CK & DQS-DQS) The differential signal (i.e., CK-CK & DQS-DQS) must be linear between these thresholds. Input Nominal Slew Rate Definition for single ended signals Delta TRdiff VIHdiffMin 0 VILdiffMax Delta TFdiff 70 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP AC and DC Output Measurement Levels Single Ended AC and DC Output Levels Symbol Parameter Value Unit Notes VOH(DC) DC output high measurement level (for IV curve linearity) 0.8xVDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5xVDDQ V VOL(DC) DC output low measurement level (fro IV curve linearity) 0.2xVDDQ V VOH(AC) AC output high measurement level (for output SR) VTT+0.1xVDDQ V 1 VOL(AC) AC output low measurement level (for output SR) VTT-0.1xVDDQ V 1 Note: 1. The swing of 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT = VDDQ/2. Differential AC and DC Output Levels Symbol Parameter DDR3 Unit Notes VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x VDDQ V 1 VOLdiff(AC) AC differential output low measurement level (for output SR) -0.2 x VDDQ V 1 Note: 1. The swing of 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 and an effective test load of 25 to VTT=VDDQ/2 at each of the differential outputs. Single Ended Output Slew Rate Measured Description Defined by From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Single Ended Output Slew Rate Definition Delta TRse VOH(AC) VTT VOL(AC) Delta TFse 71 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Output Slew Rate (single-ended) Parameter Symbol Single-ended Output Slew Rate SRQse DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 (-AC/-AD) (-BE/-BF) (-CF/-CG) (-DG/-DH) Min. Max. Min. Max. 2.5 5 2.5 5 Max. Max. 2.5 5 Unit Min. Max. TBD 5 V/ns Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). se: Single-ended signals. For Ron = RZQ/7 setting. Differential Output Slew Rate Measured Description Defined by From To Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTRdiff Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / DeltaTFdiff Note: Output slew rate is verified by design and characterization, and may not be subject to production test. Differential Output Slew Rate Definition Delta TRdiff VOHdiff(AC) 0 VOLdiff(AC) Delta TFdiff Differential Output Slew Rate Symbol SRQdiff Parameter Differential Output Slew Rate DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 (-AC/-AD) (-BE/-BF) (-CF/CG) (-DG/-DH) Min. Max. Min. Max. Min. Max. Min. Max. 5 10 5 10 5 10 TBD 10 Units V/ns Note: SR: Slew Rate. Q: Query Output (like in DQ, which stands for Data-in, Query -Output). diff: Differential Signals. For Ron = RZQ/7 setting. 72 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Reference Load for AC Timing and Output Slew Rate The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK, CK DUT DQ DQS DQS RDQS RDQS 25 Ohm Vtt = VDDQ / 2 Timing Reference Points 73 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins (A0-A13, BA0-BA2, , , , , CKE, ODT Item DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 V Maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD 0.67 0.5 0.4 0.33 V-ns Maximum undershoot area below VSS 0.67 0.5 0.4 0.33 V-ns Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask (CK, , DQ, , DQS, DM) Item DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 V Maximum peak amplitude allowed for undershoot area 0.4 0.4 0.4 0.4 V Maximum overshoot area above VDD 0.25 0.19 0.15 0.13 V-ns Maximum undershoot area below VSS 0.25 0.19 0.15 0.13 V-ns Maximum Amplitude Volts (V) Overshoot Area VDDQ VSSQ Maximum Amplitude Undershoot Area Time (ns) 74 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP 34 Ohm Output Driver DC Electrical Characteristics A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value of the external reference resistor RZQ as follows: RON34 = RZQ / 7 (nominal 34.4ohms +/-10% with nominal RZQ=240ohms) The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu = [VDDQ-Vout] / l Iout l ------------------- under the condition that RONPd is turned off (1) RONPd = Vout / I Iout I -------------------------------under the condition that RONPu is turned off (2) Chip in Drive Mode Output Driver VDDQ I Pu To other circuitry like RCV, ... RONPu DQ I Pd I Out V Out RONPd VSSQ Output Driver DC Electrical Characteristics, assuming RZQ = 240ohms; entire operating temperature range; after proper ZQ calibration RONNom Resistor Vout min nom max Unit Notes VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1 1.1 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ / 7 1,2,3 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ / 7 1,2,3 VOMdc = 0.5 x VDDQ 0.9 1 1.1 RZQ / 7 1,2,3 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ / 7 1,2,3 Mismatch between pull-up and pull-down, MMPuPd VOMdc = 0.5 x VDDQ -10 10 % 1,2,4 RON34Pd 34 ohms RON34Pu Note: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above. e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPd, but at 0.5 x VDDQ: MMPuPd = [RONPu - RONPd] / RONNom x 100 75 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Output Driver Temperature and Voltage sensitivity If temperature and/or voltage after calibration, the tolerance limits widen according to the following table. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. Items Min. Max. 0.6 - dRONdTH*lDelta Tl - 1.1 + dRONdTH*lDelta Tl - dRONdVH*lDelta Vl dRONdVH*lDelta Vl 0.9 - dRONdTM*lDelta Tl - 1.1 + dRONdTM*lDelta Tl - dRONdVM*lDelta Vl dRONdVM*lDelta Vl 0.6 - dRONdTL*lDelta Tl - 1.1 + dRONdTL*lDelta Tl - dRONdVL*lDelta Vl dRONdVL*lDelta Vl RONPU@VOHdc Unit RZQ/7 RON@VOMdc RZQ/7 RONPD@VOLdc RZQ/7 Output Driver Voltage and Temperature Sensitivity Items Min. Max Unit dRONdTM 0 1.5 %/C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/C dRONdVL 0 TBD %/mV dRONdTH 0 1.5 %/C dRONdVH 0 TBD %/mV Note: These parameters may not be subject to production test. They are verified by design and characterization. 76 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register. ODT is applied to the DQ, DM, DQS/DQS, and TDQS/TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows: RTTPu = [VDDQ - Vout] / I Iout I ------------------ under the condition that RTTPd is turned off (3) RTTPd = Vout / I Iout I ------------------------------ under the condition that RTTPu is turned off (4) Chip in Termination Mode ODT VDDQ I Pu I Out = I To other circuitry like RCV, ... RTT -I Pd Pu Pu DQ I Pd RTT I Out V Out Pd VSSQ ODT DC Electrical Characteristics The following table provides an overview of the ODT DC electrical characteristics. The values for RTT 60Pd120, RTT60Pu120, RTT120Pd240, RTT120Pu240, RTT40Pd80, RTT40Pu80, RTT30Pd60, RTT30Pu60, RTT20Pd40, RTT20Pu40 are not specification requirements, but can be used as design guide lines: ODT DC Electrical Characteristics, assuming RZQ = 240ohms +/- 1% entire operating temperature range; after proper ZQ calibration MR1 A9, A6, A2 0,1,0 RTT Resistor Vout min nom max Unit Notes RTT120Pd240 VOLdc = 0.2 x VDDQ 0.5 x VDDQ VOHdc = 0.8 x VDDQ 0.6 0.9 0.9 1 1 1 1.1 1.1 1.4 RZQ RZQ RZQ 1,2,3,4 1,2,3,4 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ 1,2,3,4 0.5 x VDDQ 0.9 1 1,1 RZQ 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ /2 1,2,5 120 RTT120Pu240 RTT120 77 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP RTT60Pd120 0, 0, 1 60 RTT60Pu120 RTT60 RTT40Pd80 0, 1, 1 40 RTT40Pu80 RTT40 RTT30Pd60 1, 0, 1 30 RTT30Pu60 RTT30 RTT20Pd40 1, 0, 0 20 RTT20Pu40 RTT20 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/2 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/2 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/2 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/4 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/3 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/3 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/3 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/6 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/4 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/4 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/4 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/8 1,2,5 VOLdc = 0.2 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4 VOLdc = 0.2 x VDDQ 0.9 1 1.4 RZQ/6 1,2,3,4 0.5 x VDDQ 0.9 1 1.1 RZQ/6 1,2,3,4 VOHdc = 0.8 x VDDQ 0.6 1 1.1 RZQ/6 1,2,3,4 VIL(ac) to VIH(ac) 0.9 1 1.6 RZQ/12 1,2,5 +5 % 1,2,5,6 Deviation of VM w.r.t. VDDQ/2, DVm -5 Note: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration may be used to achieve the linearity spec shown above. 4. Not a specification requirement, but a design guide line. 5. Measurement definition for RTT: Apply VIH(ac) to pin under test and measure current / (VIH(ac)), then apply VIL(ac) to pin under test and measure current / (VIL(ac)) respectively. RTT = [VIH(ac) - VIL(ac)] / [I(VIH(ac)) - I(VIL(ac))] 6. Measurement definition for VM and DVM: Measure voltage (VM) at test pin (midpoint) with no lead: Delta VM = [2VM / VDDQ -1] x 100 78 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP ODT Temperature and Voltage sensitivity If temperature and/or voltage after calibration, the tolerance limits widen according to the following table. Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ ODT Sensitivity Definition min max RTT 0.9 - dRTTdT*lDelta Tl - dRTTdV*lDelta Vl Unit 1.6 + dRTTdT*lDelta Tl - dRTTdV*lDelta Vl RZQ/2,4,6,8,12 ODT Voltage and Temperature Sensitivity min max Unit dRTTdT 0 1.5 %/C dRTTdV 0 0.15 %/mV Note: These parameters may not be subject to production test. They are verified by design and characterization. Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in the following figure. VDDQ DUT DQ DQS DQS RDQS RDQS 25Ohm Vtt = VSSQ VSSQ Timing Reference Points ODT Timing Definitions Definitions for tAON, tAONPD, tAOF, tAOFPD, and tADC are provided in the following table and subsequent figures. Symbol tAON Begin Point Definition End Point Definition Rising edge of CK - CK defined by the end point of ODTLon Extrapolated point at VSSQ tAONPD Rising edge of CK - CK with ODT being first registered high Extrapolated point at VSSQ tAOF Rising edge of CK - CK defined by the end point of ODTLoff End point: Extrapolated point at VRTT_Nom tAOFPD Rising edge of CK - CK with ODT being first registered low End point: Extrapolated point at VRTT_Nom Rising edge of CK - CK defined by the end point of ODTLcnw, End point: Extrapolated point at VRTT_Wr and ODTLcwn4, or ODTLcwn8 VRTT_Nom respectively tADC Reference Settings for ODT Timing Measurements Measured Parameter RTT_Nom Setting RTT_Wr Setting VSW1[V] VSW2[V] RZQ/4 NA 0.05 0.1 RZQ/12 NA 0.1 0.2 RZQ/4 NA 0.05 0.1 RZQ/12 NA 0.1 0.2 RZQ/4 NA 0.05 0.1 RZQ/12 NA 0.1 0.2 RZQ/4 NA 0.05 0.1 RZQ/12 NA 0.1 0.2 RZQ/12 RZQ/2 0.2 0.3 tAON tAONPD tAOF tAOFPD tADC 79 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Definition of tAON Begin point: Rising edge of CK - CK# Defined by the end point of ODTLon CK VTT CK# tAON Tsw2 Tsw1 DQ, DM DQS, DQS# TDQS, TDQS# Vsw2 Vsw1 VSSQ End point: Extrapolated point at VSSQ Definition of tAONPD Begin point: Rising edge of CK - CK# with ODT being first register high CK VTT CK# tAONPD Tsw2 Tsw1 DQ, DM DQS, DQS# TDQS, TDQS# Vsw2 Vsw1 VSSQ End point: Extrapolated point at VSSQ Definition of tAOF Begin point: Rising edge of CK - CK# defined by the end point of ODTLoff CK VTT CK# tAOF VRTT_Nom End point: Extrapolated point at VRTT_Nom Tsw2 DQ, DM DQS, DQS# TDQS, TDQS# Tsw1 Vsw2 Vsw1 VSSQ 80 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Definition of tAOFPD Begin point: Rising edge of CK - CK# with ODT being first registered low CK VTT CK# tAOFPD VRTT_Nom End point: Extrapolated point at VRTT_Nom Tsw2 DQ, DM DQS, DQS# TDQS, TDQS# Tsw1 Vsw2 Vsw1 VSSQ Definition of tADC Begin point: Rising edge of CK - CK# defined by the end of ODTLcnw CK Begin point: Rising edge of CK - CK# defined by the end of ODTLcwn4 or ODTLcwn8 CK VTT CK# CK# tADC VRTT_Nom tADC End point: Extrapolated point at VRTT_Nom Tsw22 Tsw21 DQ, DM DQS, DQS# TDQS, TDQS# VRTT_Nom Tsw12 Tsw11 Vsw2 VRTT_Wr Vsw1 End point: Extrapolated point at VRTT_Wr VSSQ 81 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Input / Output Capacitance Symbol CIO CCK CDCK CDDQS CI CDI_CTRL CDI_ADD_CMD CDIO CZQ Parameter Input/output capacitance (DQ, DM, DQS, , TDQS, ) Input capacitance, CK and CK Input capacitance delta, CK and Input/output capacitance delta, DQS and Input capacitance, CTRL, ADD, CMD input-only pins Input capacitance delta, all CTRL input-only pins Input capacitance delta, all ADD/CMD input-only pins Input/output capacitance delta, DQ, DM, DQS, , TDQS, Input/output capacitance of ZQ pin DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 (-AC/-AD) (-BE/-BF) (-CF/-CG) (-DG/-DH) Units Notes Min. Max Min. Max Min. Max Min. Max 1.5 3 1.5 3 1.5 2.5 1.5 2.3 pF 1,2,3 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pF 2,3 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4 0 0.2 0 0.2 0 0.15 0 0.15 pF 2,3,5 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pF 2,3,7,8 -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pF 2,3,7,8 -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pF 2,3,9,10 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pF 2,3,11 - 3 - 3 - 3 - 3 pF 2,3,12 1. Although the DM, TDQS and pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-C 5. Absolute value of CIO(DQS)-CIO() 6. CI applies to ODT, , CKE, A0-A13, BA0-BA2, , , . 7. CDI_CTRL applies to ODT, and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI()) 9. CDI_ADD_CMD applies to A0-A13, BA0-BA2, , and 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI()) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO()) 12. Maximum external load capacitance on ZQ pin: 5 pF. 82 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DD Specifications and Measurement Conditions IDD Specifications DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Symbol Parameter/Condition IDD3N Operating Current 0 -> One Bank Activate -> Precharge Operating Current 1 -> One Bank Activate -> Read -> Precharge Precharge Power-Down Current Slow Exit - MR0 bit A12 = 0 Precharge Power-Down Current Fast Exit - MR0 bit A12 = 1 Precharge Standby Current Precharge Quiet Standby Current Active Power-Down Current Always Fast Exit Active Standby Current IDD4R Operating Current Burst Read IDD4W Operating Current Burst Write IDD5B Burst Refresh Current Self-Refresh Current Normal Temperature Range (0-85C) IDD0 IDD1 IDD2P(0) IDD2P(1) IDD2N IDD2Q IDD3P IDD6 IDD7 All Bank Interleave Read Current I/O Unit (-AC/-AD) (-BE/-BF) (-CF/-CG) (-DG/-DH) x4 x8/x16 75 100 85 110 95 120 TBD mA x4 x8 x16 90 115 115 100 125 135 100 135 155 TBD mA all 16 16 16 TBD mA all 30 30 30 TBD mA all all 55 50 65 55 70 60 TBD TBD mA mA all 35 40 45 TBD mA all x4/x8 x16 x4/x8 x16 all 60 130 190 140 220 230 65 160 230 160 270 250 70 200 370 200 330 270 TBD mA TBD mA TBD mA TBD mA all 14 14 14 TBD mA x4 x8 x16 250 280 300 280 300 330 330 360 400 TBD mA 83 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP IDD Measurement Conditions Symbol Parameter/Condition Operating Current - One bank Active - Precharge current CKE: High; External clock: On; tCK, tRC, tRAS: see table in the next page; CS: High between ACT and PRE; Command 1 IDD0 Inputs: SWITCHING (except for ACT and PRE); Row, Column Address, Data I/O: SWITCHING1 (A10 Low 2 3 permanently); Bank Address: fixed (Bank 0); Output Buffer: off ; ODT: disabled ; Active Banks: one (ACT-PRE loop); 4 Idle Banks: all other; Pattern example: A0 D DD DD DD DD DD DD D P0 (DDR3-800: tRAS=37.5ns) Operating One bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, tRC, tRAS, tRCD, CL, AL: see table in the next page; CS: High between ACT, RD, 1 and PRE; Command Inputs: SWITCHING (except ACT, RD, and PRE Commands); Row, Column Address: IDD1 SWITCHING1 (A10 Low permanently); Bank Address: fixed (Bank 0); Data I/O: switching every clock (RD Data stable 2 3 during one Clock cycle); floating when no burst activity; Output Buffer: Off ; ODT: disabled ; Burst Length: BL85; Active 4 Banks: one (ACT-RD-PRE loop); Idle Banks: all other; Pattern example: A0 D DD D R0 DD DD DD DD D P0 (DDR3-800-5-5-5: tRCD=12.5ns). Precharge Standby Current IDD2N CKE=High; External Clock=On; tCK: see table in the next page; CS: High; Command Inputs, Row, Column, Bank 1 2 3 Address, Data I/O: SWITCHING ; Output Buffer: Off ; ODT: disabled ; Active / Idle Banks: none / all. Precharge Power-Down Current - (Slow Exit) CKE=Low; External Clock=On; tCK: see table in the next page; CS: Stable; Command Inputs: Stable; Row, Column / IDD2P(0) 2 3 Bank Address: Stable; Data I/O: floating; Output Buffer: Off ; ODT: disabled ; Active / Idle Banks: none / all. Precharge 6 Power Down Mode: Slow Exit (RD and ODT must satisfy tXPDLL - AL) Precharge Power-Down Current - (Fast Exit) CKE=Low; External Clock=On; tCK: see table in the next page; CS: Stable; Command Inputs, Row, Column, Bank IDD2P(1) 2 3 Address: Stable; Data I/O: floating; Output Buffer: Off ; ODT: disabled ; Active / Idle Banks: none / all. Precharge Power 7 Down Mode: Fast Exit 6(any valid Command after tXP) Precharge Quiet Standby Current IDD2Q CKE=High; External Clock=On; tCK: see table in the next page; CS=High; Command Inputs, Row, Column, Bank 3 Address: Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled ; Active / Idle Banks: none / all. Active Standby Current IDD3N CKE=High; External Clock=On; tCK: see table in the next page; CS=High; Command Inputs, Row, Column, Bank 1 3 Address, Data I/O: SWITCHING ; Output Buffer: Off2; ODT: disabled ; Active / Idle Banks: All / none. Active Power-Down Current IDD3P CKE=Low; External Clock=On; tCK: see table in the next page; CS, Command Inputs, Row, Column, Bank Address: 3 Stable; Data I/O: floating; Output Buffer: Off2; ODT: disabled ; Active / Idle Banks: All / none. Operating Burst Read Current CKE=High; External Clock=On; tCK, CL: see table in the next page; AL: 0; CS: High between valid Commands; 1 1 Command Inputs: SWITCHING (except RD Commands); Row, Column Address: SWITCHING (A10: Low permanently); IDD4R 10 Bank Address: cycling ; Data I/O: Seamless Read Data Burst : Output Data switches every clock cycle (i.e. data stable 2 3 5 10 during one clock cycle); Output Buffer: Off ; ODT: disabled ; Burst Length: BL8 ; Active / Idle Banks: All / none ; 4 Pattern: R0 D DD R1 D DD R2 D DD R3 D DD R4 Operating Burst Write Current CKE=High; External Clock=On; tCK, CL: see table in the next page; AL: 0; CS: High between valid Commands; 1 1 Command Inputs: SWITCHING (except WR Commands); Row, Column Address: SWITCHING (A10: Low IDD4W 10 permanently); Bank Address: cycling ; Data I/O: Seamless Write Data Burst : Input Data switches every clock cycle (i.e. 2 3 5 data stable during one clock cycle); DM: L permanently; Output Buffer: Off ; ODT: disabled ; Burst Length: BL8 ; Active 10 4 / Idle Banks: All / none ; Pattern: W0 D DD W1 D DD W2 D DD W3 D DD W4 Burst Refresh Current CKE=High; External Clock=On; tCK, tRFC: see table in the next page; CS: High between valid Commands; Command IDD5B 1 2 3 Inputs, Row, Column, Bank Addresses, Data I/O: SWITCHING ; Output Buffer: Off ; ODT: disabled ; Active Banks: Refresh Command every tRFC=tRFC(IDD); Idle banks: none. Self-Refresh Current 9 11 Tcase=0-85C; Auto Self Refresh =Disable; Self Refresh Temperature Range=Normal ; PASR: full array ; CKE=Low; IDD6 External Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating; 2 3 Output Buffer: off ; ODT: disabled ; Active Banks: All (during Self-Refresh action); Idle Banks: all (between Self-Rerefresh actions) 84 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP IDD6ET IDD6TC IDD7 Self-Refresh Current: extended temperature range 9 11 Tcase=0-95C; Auto Self Refresh =Disable; Self Refresh Temperature Range=Extended ; PASR: full array ; CKE=Low; External Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating; 2 3 Output Buffer: off ; ODT: disabled ; Active Banks: All (during Self-Refresh action); Idle Banks: all (between Self-Rerefresh actions) Auto Self-Refresh Current 8 9 11 Tcase=0-95C; Auto Self Refresh =Enable ; Self Refresh Temperature Range=Normal ; PASR: full array ; CKE=Low; External Clock=Off (CK and CK: Low); CS, Command Inputs, Row, Column Address, Bank Address, Data I/O: Floating; 2 3 Output Buffer: off ; ODT: disabled ; Active Banks: All (during Self-Refresh action); Idle Banks: all (between Self-Rerefresh actions) Operating Bank Interleave Read Current CKE=High; External Clock=On; tCK, tRC, tRAS, tRCD, tRRD, CL: see table as below; AL=tRCD.min-tCK; CS=High between valid commands; Command Input: see table; Row, Column Address: Stable during DESELECT; Bank Address: 10 cycling ; Data I/O: Read Data: Output Data switches every clock cycle (i.e. data stable during one clock cycle); Output 2 3 10 Buffer: Off ;ODT: disabled ; Burst Length: BL8; Active / Idle Banks: All / none. Note1: SWITCHING for Address and Command Input Signals as described in Definition of SWITCHING for Address and Command Input Signals Table. Note2: Output Buffer off: set MR1 A[12] = 1 Note3: ODT disable: set MR1 A[9,6,2]=000 and MR2 A[10,9]=00 Note4: Definition of D and D: described in Definition of SWITCHING for Address and Command Input Signals Table; Ax/Rx/Wx: Activate/Read/Write to Bank x. Note5: BL8 fixed by MRS: set MR0 A[1,0]=00 Note6: Precharge Power Down Mode: set MR0 A12=0/1 for Slow/Fast Exit Note7: Because it is an exit after precharge power down, the valid commands are: ACT, REF, MRS, Enter Self-Refresh. Note8: Auto Self-Refresh(ASR): set MR2 A6 = 0/1 to disable/enable feature Note9: Self-Refresh Temperature Range (SRT): set MR2 A7 = 0/1 for normal/extended temperature range Note10: Cycle banks as follows: 0,1,2,3,...,7,0,1,... Note11: Partial Array Self-Refresh (PASR) disabled: set MR2 A[2,1,0] = 000 85 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP For ID testing the following parameters are utilized. For testing the IDD parameters, the following timing parameters are used: Parameter Symbol DDR3-800 DDR3-800 (-AC) (-AD) 5-5-5 6-6-6 2.5 2.5 ns 5 6 CK 12.5 15 ns 50 52.5 ns Unit Clock Cycle Time tCKmin(IDD) CAS Latency CL(IDD) Active to Read or Write delay tRCDmin(IDD) Active to Active / Auto-Refresh command period tRCmin(IDD) Active to Precharge Command tRASmin(IDD) 37.5 37.5 ns Precharge Command Period tRPmin(IDD) 12.5 15 ns 40 40 ns 50 50 ns 10 10 ns 10 10 ns 110 110 ns DDR3-1066 DDR3-1066 (-BE) (-BF) 7-7-7 8-8-8 1.875 1.875 ns 7 8 CK x4/x8 Four activate window tFAW(IDD) x16 x4/x8 Active to Active command period tRRD(IDD) x16 Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) Parameter Symbol Unit Clock Cycle Time tCKmin(IDD) CAS Latency CL(IDD) Active to Read or Write delay tRCDmin(IDD) 13.125 15 ns Active to Active / Auto-Refresh command period tRCmin(IDD) 50.63 52.5 ns Active to Precharge Command tRASmin(IDD) 37.5 37.5 ns Precharge Command Period tRPmin(IDD) 13.13 15 ns 37.5 37.5 ns 50 50 ns 7.5 7.5 ns 10 10 ns 110 110 ns x4/x8 Four activate window tFAW(IDD) x16 x4/x8 Active to Active command period tRRD(IDD) x16 Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) 86 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Parameter Symbol DDR3-1333 DDR3-1333 (-CF) (-CG) 8-8-8 9-9-9 Unit Clock Cycle Time tCKmin(IDD) 1.5 1.5 ns Active to Read or Write delay tRCDmin(IDD) 12 13.5 ns Active to Active / Auto-Refresh command period tRCmin(IDD) 48 49.5 ns Active to Precharge Command tRASmin(IDD) 36 36 ns Precharge Command Period tRPmin(IDD) 12 13.5 ns 30 30 ns 45 45 ns 6 6 ns 7.5 7.5 ns 110 110 ns DDR3-1600 DDR3-1600 (-DG) (-DH) 9-9-9 10-10-10 x4/x8 Four activate window tFAW(IDD) x16 x4/x8 Active to Active command period tRRD(IDD) x16 Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) Parameter Symbol Unit Clock Cycle Time tCKmin(IDD) 1.25 1.25 ns Active to Read or Write delay tRCDmin(IDD) 11.25 12.5 ns Active to Active / Auto-Refresh command period tRCmin(IDD) 46.25 47.5 ns Active to Precharge Command tRASmin(IDD) 35 35 ns Precharge Command Period tRPmin(IDD) 11.25 12.5 ns 30 30 ns 40 40 ns 6 6 ns 7.5 7.5 ns 110 110 ns x4/x8 Four activate window tFAW(IDD) x16 x4/x8 Active to Active command period tRRD(IDD) x16 Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) 87 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Definition of SWITCHING for Address and Command Input Signals SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks Address and change then to the opposite value (row, column) (e.g. Ax Ax Ax Ax Ax Ax Ax Ax... Please see each IDDx definition for details If not otherwise mentioned the bank addresses should be switched like the Bank Address row/column address - please see each IDDx for details Define D = {, , , } := {HIGH, LOW, LOW, LOW} Define D = {, , , } := {HIGH, HIGH, HIGH, HIGH} Command Define Command Background Pattern = D D D D D D .... (CS, RAS, CAS, WE) If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background Pattern Command is substituted by the respective , , , levels of the necessary command. See each IDDx definition for details. Standard Speed Bins Speed Bin DDR3-800 CL-nRCD-nRP DDR3-1066 5-5-5 (-AC) 6-6-6 (-AD) Symbol Min Max Min Max Min Max Min Max. tAA 12.5 20 15 20 13.125 20 15 20 ns tRCD 12.5 - 15 - 13.125 - 15 - ns tRP 12.5 - 15 - 13.125 - 15 - ns tRC 50 - 52.2 - 50.625 - 52.5 - ns tRAS 37.5 9*tREFI 37.5 9*tREFI 37.5 9*tREFI 37.5 9*tREFI ns CL=5; CWL =5 tCK(AVG) 2.5 3.3 CL=6; CWL =5 tCK(AVG) 2.5 3.3 CL=7; CWL =6 tCK(AVG) Reserved CL=8; CWL =6 tCK(AVG) Parameter 7-7-7 (-BE) 8-8-8 (-BF) Unit Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period Reserved 2.5 3.3 Reserved Reserved 2.5 3.3 ns 2.5 3.3 Reserved 1.875 <2.5 Reserved Reserved 1.875 <2.5 Supported CL Settings 5,6 6 6,7,8 6,8 nCK Supported CWL Settings 5 5 5,6 5,6 nCK Reserved 1.875 <2.5 ns ns ns 88 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Speed Bin DDR3-1333 CL-nRCD-nRP Parameter 8-8-8 (-CF) DDR3-1600 9-9-9 (-CG) 9-9-9 (-DG) 10-10-10 (-DH) Unit Symbol Min Max Min Max Min Max Min Max. tAA 12 20 13.5 20 11.25 20 12.5 20 ns tRCD 12 - 13.5 - 11.25 - 12.5 - ns tRP 12 - 13.5 - 11.25 - 12.5 - ns tRC 48 - 49.5 - 46.25 - 47.5 - ns tRAS 36 9*tREFI 36 9*tREFI 35 9*tREFI 35 9*tREFI ns CL=5; CWL =5 tCK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 ns CL=6; CWL =5 tCK(AVG) 2.5 3.3 2.5 3.3 2.5 3.3 ns CL=6; CWL =6 tCK(AVG) Reserved 1.875 <2.5 CL=7; CWL =6 tCK(AVG) 1.875 <2.5 Reserved 1.875 <2.5 1.875 <2.5 ns CL=8; CWL =6 tCK(AVG) 1.875 <2.5 1.875 <2.5 1.875 <2.5 ns CL=8; CWL =7 tCK(AVG) 1.5 <1.875 1.5 <1.875 CL=9; CWL =7 tCK(AVG) 1.5 <1.875 1.25 <1.5 CL=9; CWL =8 tCK(AVG) 1.25 <1.5 1.5 <1.875 1.5 <1.875 ns 1.25 <1.5 1.25 <1.5 ns Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period Reserved 2.5 Reserved 1.875 1.5 1 <1.875 <2.5 Reserved 1.5 Reserved 1 3.3 <1.875 Reserved 1 1.5 1 <1.875 Reserved Reserved 1.25 <1.5 Reserved ns ns ns ns CL10; CWL=7 tCK(AVG) CL10; CWL=8 tCK(AVG) Reserved Reserved CL11; CWL=8 tCK(AVG) Reserved Reserved Supported CL Settings 5,6,7,8,9 6,8,9 6,7,8,9,10 6,8,10,11 nCK Supported CWL Settings 5,6,7 5,6,7 5,6,7,8 5,6,7,8 nCK 1 1.25 1 <1.5 1 1.25 1 <1.5 ns Note: 1. Optional 89 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Electrical Characteristics & AC Timing Timing Parameter by Speed Bin Symbol Parameter Clock Timing tCK(DLL_OFF) tCK(avg) Minimum Clock Cycle Time (DLL off mode) Average Clock Period(Refer to "Standard Speed Bins") tCH(avg) tCL(avg) Average high pulse width Average low pulse width tCK(abs) Absolute Clock Period tCH(abs) tCL(abs) JIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) Absolute high pulse width Absolute low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Clcyle Period Jitter Cycle to Cycle Period Jitter Cumulative error accross 2 cycles Cumulative error accross 3 cycles Cumulative error accross 4cycles Cumulative error accross 5cycles Cumulative error accross 6 cycles Cumulative error accross 7 cycles Cumulative error accross 8 cycles Cumulative error accross 9 cycles Cumulative error accross 10 cycles Cumulative error accross 11 cycles Cumulative error accross 12 cycles tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles Data Timing tDQSQ tQH tLZ(DQ) tHZ(DQ) DQS, DQS to DQ skew per group, per access DQ output hold time from DQS, DQS DQ low-impedence time from CK / DQ high-impedence time from CK / Data Setup time to DQS, DQS referenced to Vih(ac)/ tDS(base) Vil(ac) levels Data Hold time to DQS, DQS referenced to Vih(dc)/ tDH(base) Vil(dc) levels DQ and DM Input pulse width for each tDIPW input Data Strobe Timing tRPRE DQS, DQS differential READ Preamble tRPST DQS, DQS differential READ Postamble tQSH DQS, DQS differential output high time tQSL DQS, DQS differential output low time tWPRE DQS, DQS differential WRITE Preamble tWPST DQS, DQS differential WRITE Postamble DQS, DQS rising edge output access time from rising tDQSCK CK, tLZ(DQS) DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from tHZ(DQS) RL+BL/2) tDQSL DQS, DQS differential input low pulse width tDQSH DQS, DQS differential input high pulse width tDQSS DQS, DQS rising edge to CK, rising edge DQS, DQS falling edge setup time to CK, rising tDSS edge tDSH DQS, DQS falling edge hold time to CK, rising edge DDR3-800 (-AC/-AD) min max 8 DDR3-1066 (-BE/-BF) min max 8 Refer to "Standard Speed Bins) - 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max 0.43 0.43 0.43 0.43 -100 100 -90 90 -90 90 -80 80 200 180 180 160 -147 147 -132 132 -175 175 -157 157 -194 194 -175 175 -209 209 -188 188 -222 222 -200 200 -232 232 -209 209 -241 241 -217 217 -249 249 -224 224 -257 257 -231 231 -263 263 -237 237 -269 269 -242 242 tERR(npr)max tERR(npr)min tERR(npr)min = tERR(npr)max = (1+ = (1+ 0.68In(n)) (1+ 0.68In(n)) * = (1+ 0.68In(n)) 0.68In(n)) * * tJIT(per)min tJIT(per)min * tJIT(per)max tJIT(per)max 0.38 -800 - 200 400 400 0.38 -600 - 150 300 300 Unit ns tCK(avg) tCK(avg) ps tCK(avg) tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) ps ps 75 25 ps 150 100 ps 600 490 ps 0.9 0.3 0.38 0.38 0.9 0.3 Note 19 Note 11 - 0.9 0.3 0.38 0.38 0.9 0.3 Note 19 Note 11 - tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) -400 400 -300 300 ps -800 400 -600 300 ps - 400 - 300 ps 0.4 0.4 -0.25 0.6 0.6 0.25 0.4 0.4 -0.25 0.6 0.6 0.25 tCK(avg) tCK(avg) tCK(avg) 0.2 - 0.2 - tCK(avg) 0.2 - 0.2 - tCK(avg) 90 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Symbol Parameter Command and Address Timing tDLLK DLL Locking time Internal READ command to PRECHARGE Command tRTP delay Delay from start of internal write transaction to internal tWTR read command tWR WRITE recovery time tMRD Mode Register Set command cycle time DDR3-800 (-AC/-AD) min max tMOD Mode Register Set command update delay tCCD CAS to CAS command delay 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 tDAL Auto Precharge write recovery + precharge time WR + roundup (tRP/tCK(avg)) tMPRR End of MPR Read burst to MSR for MPR (exit) ACTIVE to PRECHARGE command period Refer to "Standard Speed Bins" ACTIVE to ACTIVE command period (1k page size x4/x8) tRAS 1 max(4nCK, 10ns) max(4nCK, tRRD ACTIVE to ACTIVE command period (2k page size -x16) 10ns) tFAW Four activate window (1k page size - x4/x8) 40 tFAW Four activate window (2k page size - x16) 50 Command and Address setup time to CK, tIS(base) 200 referenced Vih(ac) / Vil(ac) levels Command and Address hold time from CK, tIH(base) 275 referenced Vih(ac) / Vil(ac) levels Commad and Address setup time to CK, referenced tIS(base) AC150 to Vih(ac) / Vil(ac) levels Calibration Timing tZQinit Power-up and RESET calibration time 512 tZQoper Normal operation Full calibration time 256 tZQCS normal operation Short calibration time 64 Reset Timing max(5nCK, tXPR Exit Reset from CKE HIGH to a valid command tRFC(min) +10ns) Self RefreshTimings max(5nCK, Exit Self Refresh to Commands not requiring a locked tXS tRFC(min) DLL +10ns) tXSDLL Exit Self Refresh to Commands requiring a locked DLL tDLLK(min) Minimum CKE low width for Self Refresh entry to exit tCKE(min)+1n tCKESR timing CK Valid Clock Requirement after Self Refresh Entry (SRE) max(5nCK, tCKSRE or Power Down Entry (PDE) 10ns) Valid Clock Requirement before Self Refresh Exit(SRX) max(5nCK, tCKSRX or Power-Down Exit (PDX) or Reset Exit 10ns) Power Down Timings Exit Power Down with DLL on to any valid command; max(3nCK, tXP Exit Precharge Power Down with DLL frozen to 7.5ns) commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to max(10nCK, tXPDLL commands requiring a locked DLL 24ns) max(3nCK, tCKE CKE minimm pulse width 7.5ns) tCPDED Command Pass disable delay 1 tPD Power Down Entry to Exit Timing tCKE(min) tACTPDEN Timing of ACT command to Power Down entry 1 tPRPDEN Timing of PRE or PREA command to Power Down entry 1 tRRD - DDR3-1066 (-BE/-BF) min max 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 - 1 - max(4nCK, 7.5ns) max(4nCK, 10ns) 37.5 50 nCK - ns nCK - WR + roundup (tRP/tCK(avg)) - Unit - nCK nCK nCK - ns ns 125 ps 200 ps - - - ps - 512 256 64 - nCK nCK nCK - max(5nCK, tRFC(min) +10ns) - - 9tREFI - max(5nCK, tRFC(min) +10ns) tDLLK(min) tCKE(min)+1nC K max(5nCK, 10ns) max(5nCK, 10ns) max(3nCK, 7.5ns) max(10nCK, 24ns) max(3nCK, 5.625ns) 1 tCKE(min) 1 1 - nCK - 9tREFI - nCK nCK nCK 91 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Symbol Parameter DDR3-800 (-AC/-AD) min max DDR3-1066 (-BE/-BF) min max Unit tWRPDEN Timing of WR command to Power Down entry (BL8OTF, WL + 4 + BL8MRS, BC4OTF) (tWR/tCK(avg)) - WL + 4 + (tWR/tCK(avg)) - nCK tWRAPDEN Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) WL + 4 + WR +1 - WL + 4 + WR + 1 - nCK tWRPDEN Timing of WR command to Power Down entry (BC4MRS) WL + 2 + (tWR/tCK(avg)) - WL + 2 + (tWR/tCK(avg)) - nCK Timing of WRA command to Power Down entry (BC4MRS) Timing of REF command to Power Down entry Timing of MRS command to Power Down entry WL + 2 + WR +1 1 tMOD(min) - nCK - nCK tWRAPDEN tREFPDEN tMRSPDEN ODT Timings ODT high time without write command or with write command and BC4 tODTH8 ODT high time without write command oand BL8 Asynchronous RTT turn-on delay (Power-Down with DLL tAONPD frozen) Asynchronous RTT turn-off delay (Power Down with DLL tAOFPD frozen) tAON RTT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff tAOF reference tADC RTT dynamic change skew Write Leveling Timings First DQS/DQS rising edge after write leveling mode is tWLMRD programmed tWLDQSEN DQS/DQS delay after write leveling mode is porgramed Write leveling setup time from rising CK, CK crossing to tWLS rising DQS, DQS crossing Write leveling hold time from rising DQS, DQS crossing tWLH to rising CK, CK crossing tWLO Write leveling output delay tWLOE Write levleing output error tRFC REF command to ACT or REF command time tREFI Average period refresh interval (0CtCASE85C) tREFI Average period refresh interval (85C<t CASE95C) tODTH4 - WL + 2 + WR + 1 1 tMOD(min) 4 - 4 - nCK 6 - 6 - nCK 1 9 1 9 ns 1 9 1 9 ns -400 400 -300 300 ps 0.3 0.7 0.3 0.7 tCK(avg) 0.3 0.7 0.3 0.7 tCK(avg) 40 - 40 - nCK 25 - 25 - nCK 325 - 245 - ps 325 - 245 - ps 0 0 9 2 0 0 9 2 ns ns ns us us 110 7.8 3.9 - 110 7.8 3.9 92 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Symbol Parameter Clock Timing tCK(DLL_OFF) tCK(avg) Minimum Clock Cycle Time (DLL off mode) Average Clock Period(Refer to "Standard Speed Bins") tCH(avg) tCL(avg) Average high pulse width Average low pulse width tCK(abs) Absolute Clock Period tCH(abs) tCL(abs) JIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6per) tERR(7per) tERR(8per) tERR(9per) tERR(10per) tERR(11per) tERR(12per) Absolute high pulse width Absolute low pulse width Clock Period Jitter Clock Period Jitter during DLL locking period Cycle to Clcyle Period Jitter Cycle to Cycle Period Jitter Cumulative error accross 2 cycles Cumulative error accross 3 cycles Cumulative error accross 4cycles Cumulative error accross 5cycles Cumulative error accross 6 cycles Cumulative error accross 7 cycles Cumulative error accross 8 cycles Cumulative error accross 9 cycles Cumulative error accross 10 cycles Cumulative error accross 11 cycles Cumulative error accross 12 cycles tERR(nper) Cumulative error accross n=13,14,..,49,50 cycles Data Timing tDQSQ tQH tLZ(DQ) tHZ(DQ) DQS, DQS to DQ skew per group, per access DQ output hold time from DQS, DQS DQ low-impedence time from CK / DQ high-impedence time from CK / Data Setup time to DQS, DQS referenced to Vih(ac)/ tDS(base) Vil(ac) levels Data Hold time to DQS, DQS referenced to Vih(dc)/ tDH(base) Vil(dc) levels DQ and DM Input pulse width for each tDIPW input Data Strobe Timing tRPRE DQS, DQS differential READ Preamble tRPST DQS, DQS differential READ Postamble tQSH DQS, DQS differential output high time tQSL DQS, DQS differential output low time tWPRE DQS, DQS differential WRITE Preamble tWPST DQS, DQS differential WRITE Postamble DQS, DQS rising edge output access time from rising tDQSCK CK, tLZ(DQS) DQS, DQS low-impedance time (Referenced from RL-1) DQS, DQS high-impedance time (Referenced from tHZ(DQS) RL+BL/2) tDQSL DQS, DQS differential input low pulse width tDQSH DQS, DQS differential input high pulse width tDQSS DQS, DQS rising edge to CK, rising edge DQS, DQS falling edge setup time to CK, rising tDSS edge tDSH DQS, DQS falling edge hold time to CK, rising edge DDR3-1333 (-CF/-CG) DDR3-1600 (-DG/-DH) min max min max Refer to "Standard Speed Bins" 8 8 Refer to "Standard Speed Bins) - 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tCK(avg)min + tCK(avg)max tCK(avg)min + tCK(avg)max + tJIT(per)min + tJIT(per)max tJIT(per)min tJIT(per)max 0.43 0.43 0.43 0.43 -80 80 -70 70 -70 70 -60 60 160 140 140 120 -118 118 -103 103 -140 140 -122 122 -155 155 -136 136 -168 168 -147 147 -177 177 -155 155 -186 186 -163 163 -193 193 -169 169 -200 200 -175 175 -205 205 -180 180 -210 210 -184 184 -215 215 -188 188 tERR(npr)max tERR(npr)min = tERR(npr)min = tERR(npr)max = = (1+ (1+ 0.68In(n)) * (1+ 0.68In(n)) * (1+ 0.68In(n)) * 0.68In(n)) * tJIT(per)min tJIT(per)min tJIT(per)max tJIT(per)max 0.38 -500 - 125 250 250 0.38 -500 - 100 225 225 Unit ns tCK(avg) tCK(avg) ps tCK(avg) tCK(avg) ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK(avg) ps ps 30 10 ps 65 45 ps 400 360 ps 0.9 0.3 0.4 0.4 0.9 0.3 Note 19 Note 11 - 0.9 0.3 0.4 0.4 0.9 0.3 Note 19 Note 11 - tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) -255 255 -255 255 ps -500 250 -450 225 ps - 250 - 225 ps 0.4 0.4 -0.25 0.6 0.6 0.25 0.4 0.4 -0.25 0.6 0.6 0.25 tCK(avg) tCK(avg) tCK(avg) 0.2 - 0.2 - tCK(avg) 0.2 - 0.2 - tCK(avg) 93 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Symbol Parameter Command and Address Timing tDLLK DLL Locking time Internal READ command to PRECHARGE Command tRTP delay Delay from start of internal write transaction to internal tWTR read command tWR WRITE recovery time tMRD Mode Register Set command cycle time tMOD Mode Register Set command update delay tCCD CAS to CAS command delay tDAL Auto Precharge write recovery + precharge time tMPRR End of MPR Read burst to MSR for MPR (exit) ACTIVE to PRECHARGE command period Refer to "Standard Speed Bins" ACTIVE to ACTIVE command period (1k page size x4/x8) tRAS tRRD tRRD 512 - max(4nCK, 7.5ns) - max(4nCK, 7.5ns) - 15 4 max(12nCK, 15ns) 4 - Four activate window (1k page size - x4/x8) Four activate window (2k page size - x16) Command and Address setup time to CK, tIS(base) referenced Vih(ac) / Vil(ac) levels Command and Address hold time from CK, tIH(base) referenced Vih(ac) / Vil(ac) levels Commad and Address setup time to CK, referenced tIS(base) AC150 to Vih(ac) / Vil(ac) levels Calibration Timing tZQinit Power-up and RESET calibration time tZQoper Normal operation Full calibration time tZQCS normal operation Short calibration time Reset Timing Exit Reset from CKE HIGH to a valid command - DDR3-1600 (-DG/-DH) min max 512 max(4nCK, 7.5ns) max(4nCK, 7.5ns) 15 4 max(12nCK, 15ns) 4 - 1 - 1 Unit nCK - ns nCK - WR + roundup (tRP/tCK(avg)) nCK nCK - nCK Refer to Standard Speed Bin" max(4nCK, 6ns) ACTIVE to ACTIVE command period (2k page size -x16) max(4nCK, 7.5ns) tFAW tFAW tXPR DDR3-1333 (-CF/-CG) min max 30 45 - max(4nCK, 6ns) max(4nCK, 7.5ns) 30 40 - ns ns 65 45 ps 140 120 ps 65+125 45+125 ps 512 256 64 - 512 256 64 - max(5nCK, tRFC(min) +10ns) - max(5nCK, tRFC(min) +10ns) - max(5nCK, tRFC(min) +10ns) - nCK nCK nCK Self RefreshTimings tXS tXSDLL Exit Self Refresh to Commands not requiring a locked DLL Exit Self Refresh to Commands requiring a locked DLL tDLLK(min) Minimum CKE low width for Self Refresh entry to exit tCKESR tCKE(min)+1nCK timing Valid Clock Requirement after Self Refresh Entry (SRE) tCKSRE max(5nCK, 10ns) or Power Down Entry (PDE) Valid Clock Requirement before Self Refresh Exit(SRX) tCKSRX max(5nCK, 10ns) or Power-Down Exit (PDX) or Reset Exit Power Down Timings Exit Power Down with DLL on to any valid command; tXP Exit Precharge Power Down with DLL frozen to max(3nCK, 6ns) commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to max(10nCK, tXPDLL commands requiring a locked DLL 24ns) max(3nCK, tCKE CKE minimm pulse width 5.625ns) tCPDED Command Pass disable delay 1 tPD Power Down Entry to Exit Timing tCKE(min) tACTPDEN Timing of ACT command to Power Down entry 1 tPRPDEN Timing of PRE or PREA command to Power Down entry 1 - 9tREFI - max(5nCK, tRFC(min) +10ns) tDLLK(min) tCKE(min)+1nC K max(5nCK, 10ns) max(5nCK, 10ns) max(3nCK, 6ns) max(10nCK, 24ns) max(3nCK, 5.625ns) 1 tCKE(min) 1 1 - nCK - 9tREFI - nCK nCK nCK 94 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Symbol tWRPDEN tWRAPDEN tWRPDEN tWRAPDEN tREFPDEN tMRSPDEN ODT Timings Parameter Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry WL + 4 + WR + 1 (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry WL + 2 + (BC4MRS) (tWR/tCK(avg)) Timing of WRA command to Power Down entry WL + 2 + WR + 1 (BC4MRS) Timing of REF command to Power Down entry 1 Timing of MRS command to Power Down entry tMOD(min) ODT high time without write command or with write command and BC4 tODTH8 ODT high time without write command oand BL8 Asynchronous RTT turn-on delay (Power-Down with DLL tAONPD frozen) Asynchronous RTT turn-off delay (Power Down with DLL tAOFPD frozen) tAON RTT turn-on RTT_NOM and RTT_WR turn-off time from ODTLoff tAOF reference tADC RTT dynamic change skew Write Leveling Timings First DQS/DQS rising edge after write leveling mode is tWLMRD programmed tWLDQSEN DQS/DQS delay after write leveling mode is porgramed Write leveling setup time from rising CK, CK crossing to tWLS rising DQS, DQS crossing Write leveling hold time from rising DQS, DQS crossing tWLH to rising CK, CK crossing tWLO Write leveling output delay tWLOE Write levleing output error tRFC REF command to ACT or REF command time tREFI Average period refresh interval (0CtCASE85C) tODTH4 DDR3-1333 (-CF/-CG) min max WL + 4 + (tWR/tCK(avg)) - DDR3-1600 (-DG/-DH) min max WL + 4 + (tWR/tCK(avg)) WL + 4 + WR + 1 WL + 2 + (tWR/tCK(avg)) WL + 2 + WR + 1 1 tMOD(min) - Unit nCK nCK nCK nCK nCK 4 - 4 - nCK 6 - 6 - nCK 1 9 1 9 ns 1 9 1 9 ns -250 250 -225 225 ps 0.3 0.7 0.3 0.7 tCK(avg) 0.3 0.7 0.3 0.7 tCK(avg) 40 - 40 - nCK 25 - 25 - nCK 195 - TBD - ps 195 - TBD - ps 0 0 9 2 0 0 7.5 2 ns ns ns us 110 7.8 110 7.8 95 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Jitter Notes Specific Note a Unit "tCK(avg)" represents the actual tCK(avg) of the input clock under operation. Unit "nCK" represents one clock cycle of the input clock, counting the actual clock edges. ex) tMRD=4 [nCK] means; if one Mode Register Set command is registered at Tm, anther Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x tCK(avg) + tERR(4per), min. Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc) transition edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe signal (DQS(L/U), DQS(L/U)) crossing. Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{tPARAM[ns] / tCK(avg)[ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP/tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP/tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6-Tm) is less than 15ns due to input clock jitter. Specific Note e When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper), act of the input clock, where 2 <= m <=12. (output derating are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = -172ps and tERR(mper),act,max = 193ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = -400ps - 193ps = -593ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400ps + 172ps = 572ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = -800ps - 193ps = -993ps and tLZ(DQ),max(derated) = 400ps + 172ps = 572ps. (Caution on the min/max usage!) Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12. Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act=2500ps, tJIT(per),act,min = -72ps and tJIT(per),act,max = 93ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500ps - 72ps = 2178ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500ps - 72ps = 878ps. (Caution on the min/max usage!) 96 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Timing Parameter Notes 1. Actual value dependent upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register. 5. Value must be rouned-up to next higher integer value. 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. For definition of RTT-on time tAON See "Timing Parameters". 8. For definition of RTT-off time tAOF See "Timing Parameters". 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer. 10. WR in clock cycles are programmed in MR0. 11. The maximum read postamble is bonded by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD. 13. Value is only valid for RON34. 14. Single ended signal parameter. 15. tREFI depends on TOPER. 16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC). 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals, VREF(DC)=VRefDQ(DC). For input only pins except RESET, VRef(DC)=VRefCA(DC). 18. Start of internal write transaction is defined as follows: For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL. 19. The maximum preamble is bound by tLZ(DQS)max on the left side and tDQSCK(max) on the right side. 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 97 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP 23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the "Output Driver Voltage and Temperature Sensitivity" and "ODT Voltage and Temperature Sensitivity" tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. the interval could be defined by the following formula: ZQCorrection / [(TSens x Tdriftrate) + (VSens x Vdriftrate)] where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1 C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms 24. n = from 13 cycles to 50 cycles. This row defines 38 parameters. 25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to accommodate for the lower altemate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV 150mV) / 1V/ns]. 98 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Address / Command Setup, Hold, and Derating For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively. Example: tIS (total setup time) = tIS(base) + delta tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded Vref(dc) to ac region, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded Vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line between shaded dc to Vref(dc) region, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to Vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). ADD/CMD Setup and Hold Base-Values for 1V/ns DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 (-AC/-AD) (-BE/-BF) (-CF/-CG) (-CF/-CG) tIS(base) 200 125 65 45 VIH/L(ac) tIH(base) 275 200 140 120 VIH/L(dc) - 65+125 45+125 VIH/L(dc) Unit [ps] tIH(base) AC150 reference Note: 1. (ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate. 2. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV - 150mV) / 1V/ns]. 99 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Derating values DDR3-800/1066/1333/1600 tIS/tIH - ac/dc based CMD/ADD Slew rate V/ns tIS, tIH derating in [ps] AC/DC based Alternate AC150 Threshold -> VIH(ac)=VREF(dc)+175mV, VIL(ac)=VREF(dc)-175mV 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 CK, Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 Derating values DDR3-1333/1600 tIS/tIH - ac/dc based - Alternate CMD/ADD Slew rate V/ns AC150 Threshold tIS, tIH derating in [ps] AC/DC based Alternate AC150 Threshold -> VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)-150mV 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 CK, Differential Slew Rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition tVAC@175mV [ps] tVAC@175mV [ps] Slew Rate [V/ns] min max min max >2.0 75 - 175 - 2 57 - 170 - 1.5 50 - 167 - 1 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - <0.5 0 - 150 - 100 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Data Setup, Hold, and Slew Rate Derating For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDH(base) and tDH(base) value to the delta tDS and delta tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + delta tDS Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded Vref(dc) to ac region, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded Vref(dc) to ac region, the slew rate of the tangent line to the actual signal from the ac level to dc level is used for derating value. Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line between shaded dc level to Vref(dc) region, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded dc to Vref(dc) region, the slew rate of a tangent line to the actual signal from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac). For slew rates in between the values listed in the following tables, the derating values may be obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. Data Setup and Hold Base-Values DDR3-800 DDR3-1066 DDR3-1333 (-AC/-AD) (-BE/-BF) (-CF/-CG) tDS(base) 75 25 -10 tDH(base) 150 100 65 Note: ac/dc referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate Unit [ps] DDR3-1600 (-DG/-DH) reference VIH/L(ac) VIH/L(dc) 101 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP DQ Slew rate (V/ns) Derating values DDR3-800/1066 tDS/tDH - ac/dc based 4.0 V/ns D tDS D tDH 88 50 59 34 0 0 - 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 3.0 V/ns D tDS D tDH 88 50 59 34 0 0 -2 -4 - Delta tDS, Delta tDH derating in AC/DC based DQS, DQS Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH 88 50 59 34 67 42 0 0 8 8 16 16 -2 -4 6 4 14 12 22 20 -6 -10 2 -2 10 6 18 14 -3 -8 5 0 13 8 -1 -10 7 -2 -11 -16 - 1.2 V/ns D tDS D tDH 26 24 21 18 15 8 -2 -6 -30 -26 1.0 V/ns D tDS D tDH 29 34 23 24 5 10 -22 -10 DQ Slew rate (V/ns) Derating values DDR3-1333/1600 tDS/tDH - ac/dc based 2 1.5 1 0.9 0.8 0.7 0.6 0.5 0.4 4.0 V/ns D tDS D tDH 75 50 50 34 0 0 - 3.0 V/ns D tDS D tDH 75 50 50 34 0 0 0 -4 - Delta tDS, Delta tDH derating in AC/DC based DQS, DQS Differential Slew Rate 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns D tDS D tDH D tDS D tDH D tDS D tDH D tDS D tDH 75 50 50 34 58 42 0 0 8 8 16 16 0 -4 8 4 16 12 24 20 0 -10 8 -2 16 6 24 14 8 -8 16 0 24 8 15 -10 23 -2 14 -16 - 1.2 V/ns D tDS D tDH 32 24 32 18 31 8 22 -6 7 -26 1.0 V/ns D tDS D tDH 40 34 39 24 30 10 15 -10 Required time tVAC above VIH(ac) {below VIL(ac)} for valid transition Slew Rate [V/ns] DDR3-800/1066 DDR3-1333/1600 min max min max >2.0 75 - 175 - 2 57 - 170 - 1.5 50 - 167 - 1 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - <0.5 0 - 150 - 102 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Package Dimensions (x4/x8; 78 balls; 0.8mmx0.8mm Pitch; BGA) BOTTOM VIEW TOP VIEW 6.4 0.8 9.0 +/- 0.1 Pin A1 Index 9.6 13.0 +/- 0.1 0.8 Pin A1 Index 78Balls Min. 0.42 Max. 0.52 Min. 0.30 Max. 0.40 Max. 1.39 Units: mm 103 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Package Dimensions (x16; 96 balls; 0.8mmx0.8mm Pitch; BGA) BOTTOM VIEW TOP VIEW 6.4 9 . 0 +/ - 0 . 1 0.8 Pin A 1 Index 12 1 3 . 0 +/- 0 . 1 0.8 Pin A 1 Index 96 Balls Min. 0 . 42 Max. 0 .52 Min. 0 . 30 Max. 0 .40 Max . 1. 39 Units : mm 104 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Revision Log Rev Date 0.1 04/2008 Modification Preliminary Release Updated Simplified State Diagram (P.7) Updated MR2 Definition (P.18) Updated Timing Details of Write Leveling Sequence (P.30) Updated Timing Details of Write Leveling Exit (P.31) Added Refresh Command (P.50) Updated MRS Command to Power Down Entry (P.54) Updated Sync ODT Timing example (P.57) Updated Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry (P.63) Updated Sync to async transition during Precharge Power Down (with DLL frozen) (P.63) Updated AC and DC Logic Input Levels for Single-Ended Signals(P.67) Added Vref Tolerances (P.68) Added Definition of differential ac-swing and "time above ac-level" (P.69) Updated Single-ended levels table (P.70) 0.2 05/2008 Updated Cross point voltage for differential input signals. (P.70) Replaced Single-Ended Input Slew Rate Definition Table Input Nominal Slew Rate Definition for Single-Ended Signals Figure Input Slew Rate for Input Setup Time and Data Setup Time Section Input Slew Rate for Input Hold Time and Data Hold time Section with reference to existing definitions of single-ended signals Section (P.102) Updated Differential Input Slew Rate Definition (P. 71) Updated IDD Measurement Conditions(P.87/88) Updated Input/Output Capacitance table (P.85) Updated DDR3-1333 standard speed pins table (P.90) Updated Timing Parameters by Speed Bin (P.90) Updated and reordered Jitter Notes (P.99) Updated Timing Parameter Notes 11 and 19 for read tRPRE and tRPST Added IDD currents 1.0 06/2008 Official Release Added tDIPW data on Timing Parameters on (P. 90 & P. 93) 1.1 08/2008 Add DDR2-1600-CL9/CL10 Item Spec. 1.2 01/2009 Updated IDD4R/IDD4W burst read/write typo (P.83) 105 REV 1.2 01 / 2009 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP (R) Nanya Technology Corporation. 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Nor does NTC warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. NANYA TECHNOLOGY CORPORATION HWA YA Technology Park 669, FU HSING 3rd Rd., Kueishan, Taoyuan, Taiwan, R.O.C. The NANYA TECHNOLOGY CORPORATION Home page can be found at http:\\www.nanya.com 106 REV 1.2 01 / 2009