TDA9962HL - NXP - Product.Network

TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD

cameras

Rev. 03 — 12 September 2002 Preliminary data

1. Description

The TDA9962 is a 12-bit analog-to-digital interface for CCD cameras. The device

includes a correlated double sampling circuit, PGA, clamp loops and a low-power

12-bit ADC together with its reference voltage regulator.

An internal CDS input buffer is incorporated in order to avoid using an external buffer

that would consume more power and therefore optimizing the application for low

noise, low power working.

The PGA gain and the ADC input clamp level are controlled via the serial interface.

An additional DAC is provided for additional system controls; its output voltage range

is 1.0 V (p-p) which is available at pin OFDOUT.

2. Features

■Internal CDS input buffer, Correlated Double Sampling (CDS), Programmable

Gain Ampliﬁer (PGA), 12-bit Analog-to-Digital Converter (ADC) and reference

regulator included

■Fully programmable via a 3-wire serial interface

■Sampling frequency up to 30 MHz

■PGA gain range of 36 dB (in steps of 0.1 dB)

■Low power consumption of only 115 mW at 2.7 V

■Power consumption in standby mode of 4.5 mW (typ.)

■3.0 V operation and 2.2 to 3.6 V operation for the digital outputs

■All digital inputs accept 5 V signals

■Active control pulses polarity selectable via serial interface

■8-bit DAC included for analog settings

■TTL compatible inputs, CMOS compatible outputs.

3. Applications

■Low-power, low-voltage CCD camera systems.

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 2 of 24

4. Quick reference data

5. Ordering information

Table 1: Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

VCCA analog supply voltage 2.7 3.0 3.6 V

VCCD digital supply voltage 2.7 3.0 3.6 V

VCCO digital outputs supply voltage 2.2 2.5 3.6 V

ICCA analog supply current all clamps active −41 −mA

ICCD digital supply current −2.0 −mA

ICCO digital outputs supply current fpix = 30 MHz; CL= 10 pF; input ramp of

800 µs duration −0.5 −mA

ADCres ADC resolution −12 −bits

Vi(CDS)(p-p) maximum CDS input voltage

(peak-to-peak value) VCC = 2.85 V 650 −−mV

VCC ≥3.0 V 800 −−mV

fpix(max) maximum pixel rate 25 −−MHz

fpix(min) minimum pixel rate OCCD(max) =±100 mV −−1 MHz

OCCD(max) =±200 mV −−2 MHz

DRPGA PGA dynamic range −24 −dB

Ntot(rms) total noise from CDS input to

ADC output PGA code = 00; see Figure 8 −1.4 −LSB

Ein(rms) equivalent input noise

(RMS value) PGA code = 255 −125 −µV

Ptot total power consumption VCCA =V

CCD =3V; V

CCO = 2.5 V −130 −mW

VCCA =V

CCD = 2.7 V; VCCO = 2.2 V −115 −mW

Table 2: Ordering information

Type number Package

Name Description Version Pixel frequency

TDA9962HL LQFP48 plastic low proﬁle quad ﬂat package; 48 leads;

body 7 ×7×1.4 mm SOT313-2 30 MHz

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Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 3 of 24

6. Block diagram

Fig 1. Block diagram.

FCE504

12-bit ADC

REGULATOR

CDS CLOCK GENERATOR

BLANKING OUTPUT

BUFFER

D11

D10

OGND2

26 D1

VCCO1

10 DCLPC

21 VCCD1

VCCO2

22 DGND1

AGND2

VCCA2

CPCDS2

CPCDS1

AGND3

OFDOUT

VCCA3

VCCA4 VCCA5

25,

n.c.

BLK

CLK

AGND6

AGND1

VCCA1

VCCA6

CLPDM

CLPOB

SHP

SHIFT

CORRELATED

DOUBLE

SAMPLING

7-BIT

9-BIT

8-BIT

12 6 13

TEST AGND4 AGND5

SHD

SERIAL

INTERFACE

SEN SCLK SDATA

VSYNC

STDBY

PGA

CLAMP

input buffer

Vref

OFD DAC

DATA

FLIP-

FLOP

CLAMP TDA9962

OGND1

BLACK

LEVEL

SHIFT

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 4 of 24

7. Pinning information

7.1 Pinning

7.2 Pin description

Fig 2. Pin conﬁguration.

24 37

TDA9962HL

FCE505

D10

D11

VCCA1

VCCA2

AGND1

AGND2

AGND3

AGND4

CPCDS1

CPCDS2

OFDOUT

TEST

CLK

SHD

SHP

CLPOB

BLK

STDBY

AGND6

OGND2

CLPDM

VCCA6

VCCO2

DCLPC

AGND5

VCCA3

VCCA4

VCCA5

VCCD1

VCCO1

DGND1

SCLK

SEN

OGND1

VSYNC

SDATA

Table 3: Pin description

Symbol Pin Description

VCCA1 1 analog supply voltage 1

AGND1 2 analog ground 1

AGND2 3 analog ground 2

IN 4 input signal from CCD

AGND3 5 analog ground 3

AGND4 6 analog ground 4

VCCA2 7 analog supply voltage 2

CPCDS1 8 clamp storage capacitor pin 1

CPCDS2 9 clamp storage capacitor pin 2

DCLPC 10 regulator decoupling pin

OFDOUT 11 analog output of the additional 8-bit control DAC

TEST 12 test mode input pin (should be connected to AGND5)

AGND5 13 analog ground 5

VCCA3 14 analog supply voltage 3

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 5 of 24

VCCA4 15 analog supply voltage 4

VCCA5 16 analog supply voltage 5

SDATA 17 serial data input for serial interface control

SCLK 18 serial clock input for serial interface

SEN 19 strobe pin for serial interface

VSYNC 20 vertical sync pulse input

VCCD1 21 digital supply voltage 1

DGND1 22 digital ground 1

VCCO1 23 digital outputs supply voltage 1

OGND1 24 digital output ground 1

D0 25 ADC digital output 0 (LSB)

D1 26 ADC digital output 1

D2 27 ADC digital output 2

D3 28 ADC digital output 3

D4 29 ADC digital output 4

D5 30 ADC digital output 5

D6 31 ADC digital output 6

D7 32 ADC digital output 7

D8 33 ADC digital output 8

D9 34 ADC digital output 9

D10 35 ADC digital output 10

D11 36 ADC digital output 11 (MSB)

OGND2 37 digital output ground 2

VCCO2 38 digital outputs supply voltage 2

OE 39 output enable control input (LOW = outputs active;

HIGH = outputs in high-impedance)

AGND6 40 analog ground 6

VCCA6 41 analog supply voltage 4

STDBY 42 standby mode control input (LOW = TDA9962 active;

HIGH = TDA9962 standby)

BLK 43 blanking control input

CLPOB 44 clamp pulse input at optical black

SHP 45 preset sample-and-hold pulse input

SHD 46 data sample-and-hold pulse input

CLK 47 data clock input

CLPDM 48 clamp pulse input at dummy pixel

Table 3: Pin description

…continued

Symbol Pin Description

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 6 of 24

8. Limiting values

[1] All supplies are connected together.

9. Thermal characteristics

Table 4: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VCCA analog supply voltage [1] −0.3 +4.5 V

VCCD digital supply voltage [1] −0.3 +4.5 V

VCCO digital outputs supply voltage [1] −0.3 +4.5 V

∆VCC supply voltage difference

between VCCA and VCCD −0.5 +0.5 V

between VCCA and VCCO −0.5 +1.2 V

between VCCD and VCCO −0.5 +1.2 V

Viinput voltage referenced to AGND −0.3 +6.5 V

Iodata output current −±10 mA

Tstg storage temperature −55 +150 °C

Tamb ambient temperature −20 +75 °C

Tjjunction temperature −+150 °C

Table 5: Thermal characteristics

Symbol Parameter Conditions Value Unit

Rth(j-a) thermal resistance from junction to ambient in free air 76 K/W

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 7 of 24

10. Characteristics

Table 6: Characteristics

CCA

CCD

= 3.0 V; V

CCO

= 2.5 V; f

pix

= 30 MHz; T

amb

−

20 to +75

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VCCA analog supply voltage 2.7 3.0 3.6 V

VCCD digital supply voltage 2.7 3.0 3.6 V

VCCO digital outputs supply

voltage 2.2 2.5 3.6 V

ICCA analog supply current all clamps active −41 −mA

ICCD digital supply current −2.0 −mA

ICCO digital outputs supply

current CL= 10 pF on all data

outputs; input ramp of

800 µs duration

−0.5 −mA

Digital inputs

Pins SHP, SHD and CLK (referenced to DGND)

VIL LOW-level input voltage 0 −0.8 V

VIH HIGH-level input voltage 2.0 −5.5 V

Iiinput current 0 ≤Vi≤5.5 V −3−+3µA

Ciinput capacitance −− 2pF

Pins CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK and VSYNC

VIL LOW-level input voltage 0 −0.8 V

VIH HIGH-level input voltage 2.0 −5.5 V

Iiinput current 0 ≤Vi≤5.5 V −2−+2µA

Clamps

Global characteristics of the clamp loops

tW(clamp) clamp active pulse width

in number of pixels PGA code = 255 for

maximum 8 LSB error;

CCPCDS =1µF

15 −−pixels

Input clamp (driven by CLPDM)

gm(CDS) CDS input clamp

transconductance −15 −mS

Correlated Double Sampling (CDS)

Vi(CDS)(p-p) maximum peak-to-peak

CDS input amplitude

(video signal)

VCC = 2.85 V 650 −−mV

VCC ≥3.0 V 800 −−mV

Vreset(max) maximum CDS input

reset pulse amplitude −− 1.5 V

Ii(IN) input current into pin IN at ﬂoating gate level −− 3µA

Ciinput capacitance −2−pF

tCDS(min) CDS control pulses

minimum active time Vi(CDS)(p-p) = 800 mV

black-to-whitetransitionin

1 pixel with 98.5% Vi

recovery

11 −−ns

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 8 of 24

th(IN;SHP) CDS input hold time

(pin IN) compared to

control pulse SHP

see Figure 3 and 43−−ns

th(IN;SHD) CDS input hold time

(pin IN) compared to

control pulse SHD

see Figure 3 and 43−−ns

Ampliﬁer

DRPGA PGA dynamic range see Figure 7 and Table 7 −24 −dB

∆GPGA PGA gain step 0.08 0.10 0.12 dB

Analog-to-Digital Converter (ADC)

DNL differential non linearity fpix = 30 MHz; ramp input −±0.5 ±0.9 LSB

Total chain characteristics (CDS +PGA +ADC)

fpix(max) maximum pixel frequency 30 −−MHz

fpix(min) minimum pixel rate OCCD(max) =±100 mV −− 1 MHz

OCCD(max) =±200 mV −− 2 MHz

tCLKH CLK pulse width HIGH 15 −−ns

tCLKL CLK pulse width LOW 15 −−ns

td(SHD;CLK) time delay between

SHD and CLK see Figure 3 and 4−10 −ns

tsu(BLK;SHD) set-up time of BLK

compared to SHD see Figure 3 and 45−−ns

Vi(IN)(FS) video input dynamic

signal for ADC full-scale

output

PGA code = 00 −800 −mV

PGA code = 255 −50 −mV

Ntot(rms) total noise from CDS

input to ADC output

(RMS value)

see Figure 8 [1]

PGA code = 00 −1.4 −LSB

PGA code = 96 −2.3 −LSB

Ein(rms) equivalent input noise

voltage (RMS value) PGA code = 255 −125 −µV

PGA code = 96 −150 −µV

OCCD(max) maximum offset between

CCD ﬂoating level and

CCD dark pixel level

−200 −+200 mV

Digital-to-analog converter (OFDOUT DAC)

VOFDOUT(p-p) additional 8-bit control

DAC(OFD)output voltage

(peak-to-peak value)

Ri=1MΩ−1.0 −V

VOFDOUT(0) DC output voltage for

code 0 −AGND −V

VOFDOUT(255) DC output voltage for

code 255 −AGND +1.0 −V

TCDAC DAC output range

temperature coefﬁcient −250 −ppm/°C

ZOFDOUT DAC output impedance −2000 −Ω

IOFDOUT DAC output current drive static −− 100 µA

Table 6: Characteristics

…continued

CCA

CCD

= 3.0 V; V

CCO

= 2.5 V; f

pix

= 30 MHz; T

amb

−

20 to +75

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 9 of 24

[1] Noise ﬁgure includes the internal input buffer circuit.

Digital outputs (fpix = 30 MHz; CL= 10 pF); see Figure 3 and 4

VOH HIGH-level output voltage IOH =−1mA V

CCO −0.5 −VCCO V

VOL LOW-level output voltage IOL = 1 mA 0 −0.5 V

IOZ output current in 3-state

mode 0.5 V < Vo<V

CCO −20 −+20 µA

th(o) output hold time 5 −−ns

td(o) output delay time CL= 10 pF;VCCO = 3.6 V;

VCCD = 3.6 V −10 13 ns

CL= 10 pF;VCCO = 2.5 V;

VCCD =3V −12 15 ns

CL= 10 pF;VCCO = 2.2 V;

VCCD = 2.7 V −13 16 ns

CLoutput load capacitance −− 20 pF

Serial interface

fSCLK(max) maximum frequency of

serial clock interface 10 −−MHz

Table 6: Characteristics

…continued

CCA

CCD

= 3.0 V; V

CCO

= 2.5 V; f

pix

= 30 MHz; T

amb

−

20 to +75

C; unless otherwise speciﬁed.

Symbol Parameter Conditions Min Typ Max Unit

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Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 10 of 24

SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at the falling edge.

Recommended placement for CLK rising edge is between the falling edge of SHD and the rising edge of SHP.

Fig 3. Pixel frequency timing diagram; all polarities active HIGH.

0.8 V

2.0 V

N + 1

N − 4 N − 3 N − 2 N − 1

N + 2 N + 3 N + 4 N + 5

tCDS(min)

tCLKH

th(IN;SHP)

0.8 V

0.8 V 0.8 V

0.8 V

th(IN;SHD)

2.0 V

tCDS(min)

td(SHD;CLK)

tsu(BLK;SHD)

2.0 V

MCE028

SHP

SHD

CLK

DATA

BLK

th(o) td(o)

50%

2.0 V

NADC CLAMP

CODE

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Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 11 of 24

SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at the rising edge.

Recommended placement for CLK falling edge is between the rising edge of SHD and the falling edge of SHP.

Fig 4. Pixel frequency timing diagram; all polarities active LOW.

2.0 V

tCDS(min)

tCLKL

th(IN;SHP)

0.8 V

0.8 V 0.8 V

th(IN;SHD)

0.8 V

tCDS(min)

td(SHD;CLK)

tsu(BLK;SHD)

2.0 V

2.0 V 2.0 V

MCE029

SHP

SHD

CLK

DATA

BLK

th(o) td(o)

50% ADC CLAMP

CODE

N + 1

N − 4 N − 3 N − 2 N − 1

N + 2 N + 3 N + 4 N + 5

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 12 of 24

Fig 5. DAC voltage output as a function of DAC input code.

FCE508

OFDOUT DAC

voltage

output

(V)

1.0

0255

OFDOUT control DAC input code

Fig 6. Line frequency timing diagram.

MCE025

BLK

(active HIGH)

CLPOB

(active HIGH)

CLPDM

(active HIGH)

PGAOUT VIDEO OPTICAL BLACK

CLPOB

WINDOW

HORIZONTAL FLYBACK DUMMY VIDEO

BLK window

CLPDM

WINDOW

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 13 of 24

Full-scale at the ADC input is reached at Vi(CDS)(p-p) = 800 mV; PGA code 0.

To use 36 dB gain range refer to Table 7, address 0100.

Fig 7. Total gain from CDS input to ADC input as a function of PGA control code.

0 64 192 320 448

PGA input code

128

TOTAL

gain

(dB)

256 384 511

MCE026

1.9

37.9

Gain dB() 1.9 36 PGAcode

383

-------------------------





dB[]×+=

Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is

evaluated. Front-end works at 30 Mpixels with line of 1024 pixels whose ﬁrst 40 are used to run CLPOB and the last 40 for

CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this, the standard deviation of the codes

statistic is computed, resulting in the noise. No quantization noise is taken into account.

Fig 8. Typical total noise performance as a function of PGA gain.

640 192128 PGA code

255

MCE027

Ntot(rms)

(LSB)

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 14 of 24

First logic layer (DFF) is clocked by the ﬁrst falling SCLK edge after the rising SEN edge.

Second logic layer is clocked by the LOAD signal; this signal depends on the VSYNC signal.

If vertical sync is not available, VSYNC should be connected to SEN.

Fig 9. Serial interface block diagram.

OFDOUT DAC

LATCHES PGA GAIN

LATCHES ADC CLAMP

LATCHES

CONTROL PULSE

POLARITY

LATCHES

LOAD

LATCH

SELECTION

SD0

SDATA

SCLK

SEN

LSB MSB

8-bit DAC

MCE030

PGA control ADC clamp

control control pulses

polarity settings

SD2SD1 SD3 SD4 SD5

SD6

SHIFT REGISTER

SD7 SD8 SD9 SD10 SD11

8 9 7 10

A0 A1 A2 A3

VSYNC

FLIP-FLOP FLIP-FLOP FLIP-FLOP

CONDITIONING

VSYNC

tsu1 =t

su2 =t

su3 = 10 ns (min.); thd4 =t

hd5 =t

hd6 10 ns (min.).

Fig 10. Loading sequence of control input data via the serial interface.

MCE031

SDATA

SCLK

SEN

VSYNC

SD11

A1A2

A3 A0 SD9

SD10 SD7 SD6 SD5 SD4 SD3

MSB LSB

SD2 SD1 SD0

thd5

tsu3

tsu1

thd6

thd4

tsu2

SD8

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 15 of 24

Table 7: Serial interface programming

Address bits Data bits SD11 to SD0

A3 A2 A1 A0

0 0 0 0 PGA gain control (SD7 to SD0)

0001DAC OFDOUT output control (SD7 to SD0)

0 0 1 0 ADC clamp reference control (SD6 to SD0); from code 0 to 127

0 0 1 1 control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK)

polarity settings; SD2, SD6, SD7 and SD9 should be set to logic 1; for

SD6 and SD7 see Table 9 and 10

0 1 0 0 SD7 = 0 by default; SD7 = 1 for 36 dB PGA gain range but noise and

clamp behaviour are not guaranteed

other addresses test modes (do not use in normal application)

Table 8: Polarity settings

Symbol Pin Serial control bit Active edge or level

SHP and SHD 45 and 46 SD4 1 = HIGH; 0 = LOW

CLK 47 SD5 1 = rising; 0 = falling

CLPDM 48 SD0 1 = HIGH; 0 = LOW

CLPOB 44 SD1 1 = HIGH; 0 = LOW

BLK 43 SD3 1 = HIGH; 0 = LOW

VSYNC 20 SD8 0 = rising; 1 = falling

Table 9: Standby control using pin STDBY

Bit SD7 of register

0011 STDBY ADC digital outputs

SD11 to SD0 ICCA +ICCD (typ.)

1 1 last logic state 1.5 mA

0 active 43 mA

0 1 active 43 mA

0 test logic state 1.5 mA

Table 10: Output enable selection using output enable pin (OE)

Bit SD6 of register 0011 OE ADC digital outputs SD9 to SD0

1 0 active binary

1 high-impedance

0 0 high-impedance

1 active binary

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 16 of 24

11. Application information

(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.

(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN;SHP) and th(IN;SHD) (see Section 10

“Characteristics”).

(3) As an internal buffer is incorporated, depending on the CCD output impedance, an external input buffer may not be

necessary and consequently power savings can be made.

Fig 11. Application diagram.

FCE514

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

12 25

TDA9962

D11

D10

VCCO

VCCA1

VCCA2

AGND1

AGND2

AGND3

CPCDS1

OFDOUT

TEST

SHP

SHD

CLPOB

BLK

VCCA6

AGND6

STDBY

CLPDM

OGND2

VCCO2

CLK

CPCDS2

DCLPC

AGND5

VCCA3

VCCA4

VCCA5

VCCD1

VCCO1

SCLK

SEN

VSYNC

SDATA

AGND4

DGND1

OGND1

serial

interface

VCCA

CCD(2)(3)

VCCA VCCO

100 nF

VCCD

100 nF

VCCA

100 nF

VCCD

100 nF

1 µF

(1)

(2) (2)

VCCD

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 17 of 24

(1) The external input buffer can be omitted for CCDs with low output impedance, for CCDs with high output impedance, a

small current (around 1 mA) is needed.

Fig 12. Typical imaging application.

CCD 12-bit

data bus

TDA9962

(1)

clamp

signals clock

signals

MCE032

DIGITAL

SIGNAL

PROCESSOR

PULSE

PATTERN

GENERATOR

HORIZONTAL

AND VERTICAL

DRIVER

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 18 of 24

11.1 Power and grounding recommendations

Care should be taken to minimize the noise when designing a printed-circuit board for

applications such as PC cameras, surveillance cameras, camcorders and digital still

cameras.

For the front-end integrated circuit, the basic rules of printed-circuit board design and

implementation of analog components (such as classical operational ampliﬁers) must

be taken into account, particularly with respect to power and ground connections.

The connections between the CCD interface and the CDS input should be as short as

possible and a ground ring protection around these connections can be beneﬁcial.

Separate analog and digital supplies provide the best performance. If it is not possible

to do this on the board then the analog supply pins must be decoupled effectively

from the digital supply pins. The decoupling capacitors must be placed as close as

possible to the IC package.

In a two-ground system, in order to minimize the noise through package and die

parasitics, the following recommendation must be implemented.

•The ground pin associated with the digital outputs must be connected to the digital

ground plane and special care should be taken to avoid feedthrough in the analog

ground plane. The analog and digital ground planes must be connected together

with an inductor as closely as possible to the IC in order for them to have the same

DC voltage.

•The digital output pins and their associated lines should be shielded by the digital

ground plane which can then be used as a return path for digital signals.

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 19 of 24

12. Package outline

Fig 13. SOT313-2.

UNIT A

max. A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 1.60 0.20

0.05 1.45

1.35 0.25 0.27

0.17 0.18

0.12 7.1

6.9 0.5 9.15

8.85 0.95

0.55 7

0.12 0.10.21.0

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2 MS-026136E05 99-12-27

00-01-19

D(1) (1)(1)

7.1

6.9

9.15

8.85

0.95

0.55

vMB

vMA

36 25

detail X

(A )

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 20 of 24

13. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling.

However, to be completely safe, it is desirable to take normal precautions appropriate

to handling integrated circuits.

14. Soldering

14.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our

Data Handbook IC26; Integrated Circuit

Packages

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne

pitch SMDs. In these situations reﬂow soldering is recommended.

14.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 250 °C. The top-surface

temperature of the packages should preferable be kept below 220 °C for thick/large

packages, and below 235 °C small/thin packages.

14.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

•Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

–larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

–smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 21 of 24

The footprint must incorporate solder thieves at the downstream end.

•For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated ﬂux will eliminate the

need for removal of corrosive residues in most applications.

14.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

14.5 Package related soldering information

[1] For more detailed information on the BGA packages refer to the

(LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the

Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods

[3] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[4] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[5] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[6] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

Table 11: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package[1] Soldering method

Wave Reﬂow[2]

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable

HBCC, HBGA, HLQFP, HSQFP, HSOP,

HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[3] suitable

PLCC[4], SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended[4][5] suitable

SSOP, TSSOP, VSO not recommended[6] suitable

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 22 of 24

15. Revision history

Table 12: Revision history

Rev Date CPCN Description

03 20020912 - Preliminary speciﬁcation; third version

02 20000804 - Objective speciﬁcation; second version

01 20000501 - Objective speciﬁcation; initial version

9397 750 10167

Philips Semiconductors TDA9962

12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras

Preliminary data Rev. 03 — 12 September 2002 23 of 24

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.Fax: +31 40 27 24825

16. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

17. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

18. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to

make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve

design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Data sheet status[1] Product status[2] Deﬁnition

Objective data Development This data sheet contains data from the objectivespeciﬁcation for product development. Philips Semiconductors

reserves the right to change the speciﬁcation in any manner without notice.

Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a

later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to

improve the design and supply the best possible product.

Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to

make changes at any time in order to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change Notiﬁcation (CPCN) procedure

SNW-SQ-650A.

© Koninklijke Philips Electronics N.V. 2002.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 12 September 2002 Document order number: 9397 750 10167
Contents
Philips Semiconductors TDA9962
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
4 Quick reference data . . . . . . . . . . . . . . . . . . . . .  2
5 Ordering information. . . . . . . . . . . . . . . . . . . . .  2
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .  3
7 Pinning information. . . . . . . . . . . . . . . . . . . . . .  4
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .  6
9 Thermal characteristics. . . . . . . . . . . . . . . . . . .  6
10 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .  7
11 Application information. . . . . . . . . . . . . . . . . .  16
11.1 Power and grounding recommendations . . . .  18
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . .  19
13 Handling information. . . . . . . . . . . . . . . . . . . .  20
14 Soldering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
14.1 Introduction to soldering surface mount
 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
14.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .  20
14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .  20
14.4 Manual soldering  . . . . . . . . . . . . . . . . . . . . . .  21
14.5 Package related soldering information . . . . . .  21
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . .  22
16 Data sheet status. . . . . . . . . . . . . . . . . . . . . . .  23
17 Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
18 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .  23