TDA9962 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Rev. 03 -- 12 September 2002 Preliminary data 1. Description The TDA9962 is a 12-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, PGA, clamp loops and a low-power 12-bit ADC together with its reference voltage regulator. An internal CDS input buffer is incorporated in order to avoid using an external buffer that would consume more power and therefore optimizing the application for low noise, low power working. The PGA gain and the ADC input clamp level are controlled via the serial interface. An additional DAC is provided for additional system controls; its output voltage range is 1.0 V (p-p) which is available at pin OFDOUT. 2. Features Internal CDS input buffer, Correlated Double Sampling (CDS), Programmable Gain Amplifier (PGA), 12-bit Analog-to-Digital Converter (ADC) and reference regulator included Fully programmable via a 3-wire serial interface Sampling frequency up to 30 MHz PGA gain range of 36 dB (in steps of 0.1 dB) Low power consumption of only 115 mW at 2.7 V Power consumption in standby mode of 4.5 mW (typ.) 3.0 V operation and 2.2 to 3.6 V operation for the digital outputs All digital inputs accept 5 V signals Active control pulses polarity selectable via serial interface 8-bit DAC included for analog settings TTL compatible inputs, CMOS compatible outputs. 3. Applications Low-power, low-voltage CCD camera systems. TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 4. Quick reference data Table 1: Quick reference data Symbol Parameter VCCA Min Typ Max Unit analog supply voltage 2.7 3.0 3.6 V VCCD digital supply voltage 2.7 3.0 3.6 V VCCO digital outputs supply voltage ICCA analog supply current ICCD digital supply current ICCO digital outputs supply current ADCres ADC resolution Vi(CDS)(p-p) maximum CDS input voltage (peak-to-peak value) fpix(max) maximum pixel rate fpix(min) minimum pixel rate Conditions 2.2 2.5 3.6 V - 41 - mA - 2.0 - mA fpix = 30 MHz; CL = 10 pF; input ramp of 800 s duration - 0.5 - mA - 12 - bits VCC = 2.85 V 650 - - mV VCC 3.0 V 800 - - mV 25 - - MHz OCCD(max) = 100 mV - - 1 MHz OCCD(max) = 200 mV - - 2 MHz - 24 - dB all clamps active DRPGA PGA dynamic range Ntot(rms) total noise from CDS input to ADC output PGA code = 00; see Figure 8 - 1.4 - LSB Ein(rms) equivalent input noise (RMS value) PGA code = 255 - 125 - V Ptot total power consumption VCCA = VCCD = 3 V; VCCO = 2.5 V - 130 - mW VCCA = VCCD = 2.7 V; VCCO = 2.2 V - 115 - mW 5. Ordering information Table 2: Ordering information Type number TDA9962HL Package Name Description LQFP48 plastic low profile quad flat package; 48 leads; SOT313-2 body 7 x 7 x 1.4 mm Pixel frequency 30 MHz (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Version Rev. 03 -- 12 September 2002 2 of 24 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 45 46 AGND1 1 VCCA6 2 41 BLK AGND6 CLPOB CLPDM 40 44 48 43 CLK 47 OE 39 22 21 CDS CLOCK GENERATOR 37 CPCDS1 38 8 AGND2 IN n.c. 36 9 35 7 input buffer 34 3 33 PGA CORRELATED DOUBLE SAMPLING 4 BLACK LEVEL SHIFT SHIFT BLANKING 25, 26 DATA FLIPFLOP 32 OUTPUT BUFFER 31 30 12-bit ADC 29 CLAMP 28 27 VCCA3 AGND3 26 Vref 14 9-BIT REGISTER 5 25 7-BIT REGISTER 24 OFD DAC OFDOUT VCCD1 OGND2 VCCO2 23 11 SERIAL INTERFACE 8-BIT REGISTER 6 13 15 16 VCCA4 VCCA5 19 18 17 20 42 FCE504 TEST Fig 1. Block diagram. AGND4 AGND5 SEN SCLK SDATA VSYNC STDBY D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 OGND1 VCCO1 DCLPC TDA9962 3 of 24 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 12 REGULATOR 10 D11 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Rev. 03 -- 12 September 2002 VCCA2 DGND1 TDA9962 CLAMP CPCDS2 Philips Semiconductors VCCA1 SHD 6. Block diagram 9397 750 10167 Preliminary data SHP TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 7. Pinning information 37 OGND2 38 VCCO2 39 OE 40 AGND6 41 VCCA6 42 STDBY 43 BLK 44 CLPOB 45 SHP 46 SHD 47 CLK 48 CLPDM 7.1 Pinning VCCA1 1 36 D11 AGND1 2 35 D10 AGND2 3 34 D9 IN 4 33 D8 AGND3 5 32 D7 AGND4 6 31 D6 TDA9962HL VCCA2 7 30 D5 OGND1 24 DGND1 22 VCCO1 23 VCCD1 21 VSYNC 20 25 D0 SEN 19 TEST 12 SCLK 18 26 D1 SDATA 17 27 D2 OFDOUT 11 VCCA5 16 28 D3 DCLPC 10 VCCA4 15 CPCDS2 9 VCCA3 14 29 D4 AGND5 13 CPCDS1 8 FCE505 Fig 2. Pin configuration. 7.2 Pin description Table 3: Pin description Symbol Pin Description VCCA1 1 analog supply voltage 1 AGND1 2 analog ground 1 AGND2 3 analog ground 2 IN 4 input signal from CCD AGND3 5 analog ground 3 AGND4 6 analog ground 4 VCCA2 7 analog supply voltage 2 CPCDS1 8 clamp storage capacitor pin 1 CPCDS2 9 clamp storage capacitor pin 2 DCLPC 10 regulator decoupling pin OFDOUT 11 analog output of the additional 8-bit control DAC TEST 12 test mode input pin (should be connected to AGND5) AGND5 13 analog ground 5 VCCA3 14 analog supply voltage 3 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 4 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Table 3: Pin description...continued Symbol Pin Description VCCA4 15 analog supply voltage 4 VCCA5 16 analog supply voltage 5 SDATA 17 serial data input for serial interface control SCLK 18 serial clock input for serial interface SEN 19 strobe pin for serial interface VSYNC 20 vertical sync pulse input VCCD1 21 digital supply voltage 1 DGND1 22 digital ground 1 VCCO1 23 digital outputs supply voltage 1 OGND1 24 digital output ground 1 D0 25 ADC digital output 0 (LSB) D1 26 ADC digital output 1 D2 27 ADC digital output 2 D3 28 ADC digital output 3 D4 29 ADC digital output 4 D5 30 ADC digital output 5 D6 31 ADC digital output 6 D7 32 ADC digital output 7 D8 33 ADC digital output 8 D9 34 ADC digital output 9 D10 35 ADC digital output 10 D11 36 ADC digital output 11 (MSB) OGND2 37 digital output ground 2 VCCO2 38 digital outputs supply voltage 2 OE 39 output enable control input (LOW = outputs active; HIGH = outputs in high-impedance) AGND6 40 analog ground 6 VCCA6 41 analog supply voltage 4 STDBY 42 standby mode control input (LOW = TDA9962 active; HIGH = TDA9962 standby) BLK 43 blanking control input CLPOB 44 clamp pulse input at optical black SHP 45 preset sample-and-hold pulse input SHD 46 data sample-and-hold pulse input CLK 47 data clock input CLPDM 48 clamp pulse input at dummy pixel (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 5 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 8. Limiting values Table 4: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit analog supply voltage [1] -0.3 +4.5 V digital supply voltage [1] -0.3 +4.5 V VCCO digital outputs supply voltage [1] -0.3 +4.5 V VCC supply voltage difference between VCCA and VCCD -0.5 +0.5 V between VCCA and VCCO -0.5 +1.2 V VCCA VCCD Parameter Conditions -0.5 +1.2 V -0.3 +6.5 V data output current - 10 mA Tstg storage temperature -55 +150 C Tamb ambient temperature -20 +75 C Tj junction temperature - +150 C between VCCD and VCCO Vi input voltage Io [1] referenced to AGND All supplies are connected together. 9. Thermal characteristics Table 5: Thermal characteristics Symbol Parameter Conditions Rth(j-a) thermal resistance from junction to ambient in free air Unit 76 K/W (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Value Rev. 03 -- 12 September 2002 6 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 10. Characteristics Table 6: Characteristics VCCA = VCCD = 3.0 V; VCCO = 2.5 V; fpix = 30 MHz; Tamb = -20 to +75 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.7 3.0 3.6 V Supplies VCCA analog supply voltage VCCD digital supply voltage 2.7 3.0 3.6 V VCCO digital outputs supply voltage 2.2 2.5 3.6 V ICCA analog supply current all clamps active - 41 - mA ICCD digital supply current - 2.0 - mA ICCO digital outputs supply current CL = 10 pF on all data outputs; input ramp of 800 s duration - 0.5 - mA Digital inputs Pins SHP, SHD and CLK (referenced to DGND) VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V Ii input current -3 - +3 A Ci input capacitance - - 2 pF 0 Vi 5.5 V Pins CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK and VSYNC VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V Ii input current 0 Vi 5.5 V -2 - +2 A PGA code = 255 for maximum 8 LSB error; CCPCDS = 1 F 15 - - pixels - 15 - mS VCC = 2.85 V 650 - - mV VCC 3.0 V 800 - - mV - - 1.5 V - - 3 A - 2 - pF 11 - - ns Clamps Global characteristics of the clamp loops tW(clamp) clamp active pulse width in number of pixels Input clamp (driven by CLPDM) gm(CDS) CDS input clamp transconductance Correlated Double Sampling (CDS) Vi(CDS)(p-p) maximum peak-to-peak CDS input amplitude (video signal) Vreset(max) maximum CDS input reset pulse amplitude Ii(IN) input current into pin IN Ci input capacitance tCDS(min) CDS control pulses minimum active time at floating gate level Vi(CDS)(p-p) = 800 mV black-to-white transition in 1 pixel with 98.5% Vi recovery (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 7 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Table 6: Characteristics...continued VCCA = VCCD = 3.0 V; VCCO = 2.5 V; fpix = 30 MHz; Tamb = -20 to +75 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit th(IN;SHP) CDS input hold time (pin IN) compared to control pulse SHP see Figure 3 and 4 3 - - ns th(IN;SHD) CDS input hold time (pin IN) compared to control pulse SHD see Figure 3 and 4 3 - - ns DRPGA PGA dynamic range see Figure 7 and Table 7 - 24 - dB GPGA PGA gain step 0.08 0.10 0.12 dB - 0.5 0.9 LSB 30 - - MHz OCCD(max) = 100 mV - - 1 MHz OCCD(max) = 200 mV - - 2 MHz Amplifier Analog-to-Digital Converter (ADC) DNL differential non linearity fpix = 30 MHz; ramp input Total chain characteristics (CDS + PGA + ADC) fpix(max) maximum pixel frequency fpix(min) minimum pixel rate tCLKH CLK pulse width HIGH 15 - - ns tCLKL CLK pulse width LOW 15 - - ns td(SHD;CLK) time delay between SHD and CLK see Figure 3 and 4 - 10 - ns tsu(BLK;SHD) set-up time of BLK compared to SHD see Figure 3 and 4 5 - - ns Vi(IN)(FS) video input dynamic signal for ADC full-scale output PGA code = 00 - 800 - mV PGA code = 255 - 50 - mV total noise from CDS input to ADC output (RMS value) see Figure 8 PGA code = 00 - 1.4 - LSB PGA code = 96 - 2.3 - LSB equivalent input noise voltage (RMS value) PGA code = 255 - 125 - V PGA code = 96 - 150 - V -200 - +200 mV Ri = 1 M VOFDOUT(p-p) additional 8-bit control DAC (OFD) output voltage (peak-to-peak value) - 1.0 - V VOFDOUT(0) DC output voltage for code 0 - AGND - V VOFDOUT(255) DC output voltage for code 255 - AGND + 1.0 - V TCDAC DAC output range temperature coefficient - 250 - ZOFDOUT DAC output impedance - 2000 - IOFDOUT DAC output current drive - - 100 A Ntot(rms) Ein(rms) OCCD(max) maximum offset between CCD floating level and CCD dark pixel level [1] Digital-to-analog converter (OFDOUT DAC) static (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data ppm/C Rev. 03 -- 12 September 2002 8 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Table 6: Characteristics...continued VCCA = VCCD = 3.0 V; VCCO = 2.5 V; fpix = 30 MHz; Tamb = -20 to +75 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCCO V Digital outputs (fpix = 30 MHz; CL = 10 pF); see Figure 3 and 4 VOH HIGH-level output voltage IOH = -1 mA VCCO - 0.5 - VOL LOW-level output voltage IOL = 1 mA 0 - 0.5 V IOZ output current in 3-state mode 0.5 V < Vo < VCCO -20 - +20 A th(o) output hold time 5 - - ns td(o) output delay time CL = 10 pF; VCCO = 3.6 V; VCCD = 3.6 V - 10 13 ns CL = 10 pF; VCCO = 2.5 V; VCCD = 3 V - 12 15 ns CL = 10 pF; VCCO = 2.2 V; VCCD = 2.7 V - 13 16 ns - - 20 pF 10 - - MHz output load capacitance CL Serial interface fSCLK(max) [1] maximum frequency of serial clock interface Noise figure includes the internal input buffer circuit. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 9 of 24 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors 9397 750 10167 Preliminary data IN N+1 N N+2 N+3 N+4 N+5 tCDS(min) 2.0 V SHP 0.8 V th(IN;SHP) tCDS(min) 2.0 V 2.0 V SHD 0.8 V 0.8 V th(IN;SHD) Rev. 03 -- 12 September 2002 2.0 V CLK 0.8 V 0.8 V td(SHD;CLK) DATA N-4 N-3 50% N-2 N-1 N ADC CLAMP CODE th(o) td(o) 2.0 V BLK MCE028 tsu(BLK;SHD) Recommended placement for CLK rising edge is between the falling edge of SHD and the rising edge of SHP. Fig 3. Pixel frequency timing diagram; all polarities active HIGH. TDA9962 10 of 24 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at the falling edge. 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras tCLKH 2.0 V xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Philips Semiconductors 9397 750 10167 Preliminary data IN N+1 N N+2 N+3 N+4 N+5 2.0 V SHP 0.8 V tCDS(min) th(IN;SHP) 2.0 V 2.0 V SHD 0.8 V 0.8 V tCDS(min) th(IN;SHD) 2.0 V 0.8 V 0.8 V tCLKL DATA N-4 td(SHD;CLK) N-3 50% N-2 N-1 N ADC CLAMP CODE th(o) td(o) BLK 0.8 V MCE029 SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at the rising edge. Recommended placement for CLK falling edge is between the rising edge of SHD and the falling edge of SHP. Fig 4. Pixel frequency timing diagram; all polarities active LOW. TDA9962 11 of 24 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. tsu(BLK;SHD) 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Rev. 03 -- 12 September 2002 2.0 V CLK TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras FCE508 1.0 OFDOUT DAC voltage output (V) 0 255 0 OFDOUT control DAC input code Fig 5. DAC voltage output as a function of DAC input code. CLPOB WINDOW PGAOUT VIDEO OPTICAL BLACK CLPDM WINDOW HORIZONTAL FLYBACK DUMMY VIDEO CLPOB (active HIGH) CLPDM (active HIGH) BLK (active HIGH) BLK window MCE025 Fig 6. Line frequency timing diagram. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 12 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras MCE026 42 TOTAL gain (dB) 36 37.9 30 24 18 12 6 1.9 0 0 64 128 192 256 320 384 448 511 PGA input code PGAcode Gain ( dB ) = 1.9 + 36 x ------------------------- [ dB ] 383 Full-scale at the ADC input is reached at Vi(CDS)(p-p) = 800 mV; PGA code 0. To use 36 dB gain range refer to Table 7, address 0100. Fig 7. Total gain from CDS input to ADC input as a function of PGA control code. MCE027 11 10 Ntot(rms) (LSB) 9 8 7 6 5 4 3 2 1 0 0 64 128 192 255 PGA code Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 30 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account. Fig 8. Typical total noise performance as a function of PGA gain. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 13 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras SDATA SHIFT REGISTER SD0 SD1 SD2 SD3 SD5 SD6 SD4 SD7 SD8 SD9 SD10 SD11 A0 SCLK 12 8 9 7 8-bit DAC A3 PGA GAIN LATCHES ADC CLAMP LATCHES 10 CONTROL PULSE POLARITY LATCHES LOAD FLIP-FLOP A2 LATCH SELECTION SEN OFDOUT DAC LATCHES A1 MSB LSB FLIP-FLOP FLIP-FLOP PGA control ADC clamp control control pulses polarity settings CONDITIONING VSYNC VSYNC MCE030 First logic layer (DFF) is clocked by the first falling SCLK edge after the rising SEN edge. Second logic layer is clocked by the LOAD signal; this signal depends on the VSYNC signal. If vertical sync is not available, VSYNC should be connected to SEN. Fig 9. Serial interface block diagram. tsu2 thd4 MSB SDATA A3 A2 A1 A0 SD11 SD10 SD9 SD8 SD7 SD6 LSB SD5 SD4 SD3 SD2 SD1 SD0 SCLK SEN tsu1 tsu3 thd5 thd6 VSYNC MCE031 tsu1 = tsu2 = tsu3 = 10 ns (min.); thd4 = thd5 = thd6 10 ns (min.). Fig 10. Loading sequence of control input data via the serial interface. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 14 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Table 7: Serial interface programming Address bits Data bits SD11 to SD0 A3 A2 A1 A0 0 0 0 0 PGA gain control (SD7 to SD0) 0 0 0 1 DAC OFDOUT output control (SD7 to SD0) 0 0 1 0 ADC clamp reference control (SD6 to SD0); from code 0 to 127 0 0 1 1 control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings; SD2, SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see Table 9 and 10 0 1 0 0 SD7 = 0 by default; SD7 = 1 for 36 dB PGA gain range but noise and clamp behaviour are not guaranteed other addresses Table 8: test modes (do not use in normal application) Polarity settings Symbol Pin SHP and SHD 45 and 46 SD4 1 = HIGH; 0 = LOW CLK 47 SD5 1 = rising; 0 = falling CLPDM 48 SD0 1 = HIGH; 0 = LOW CLPOB 44 SD1 1 = HIGH; 0 = LOW BLK 43 SD3 1 = HIGH; 0 = LOW VSYNC 20 SD8 0 = rising; 1 = falling Table 9: Serial control bit Active edge or level Standby control using pin STDBY Bit SD7 of register 0011 STDBY ADC digital outputs SD11 to SD0 ICCA + ICCD (typ.) 1 1 last logic state 1.5 mA 0 active 43 mA 1 active 43 mA 0 test logic state 1.5 mA 0 Table 10: Output enable selection using output enable pin (OE) Bit SD6 of register 0011 OE ADC digital outputs SD9 to SD0 1 0 active binary 1 high-impedance 0 high-impedance 1 active binary 0 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 15 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 11. Application information VCCD VCCA VCCD VCCO 100 nF 100 nF OGND2 OE VCCO2 VCCA6 AGND6 STDBY BLK SHP (2) CLPOB 1 F SHD CLPDM CCD(2)(3) CLK (2) 48 47 46 45 44 43 42 41 40 39 38 37 1 F CPCDS2 1 F DCLPC 1 F OFDOUT TEST 33 5 32 6 31 TDA9962 7 30 8 29 9 28 10 27 11 26 12 25 VCCA5 VCCA4 VCCA3 AGND5 13 14 15 16 100 nF VCCA 17 18 19 20 21 22 23 serial interface (1) 100 nF VCCD D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 24 OGND1 CPCDS1 100 nF 4 VCCO1 VCCA 34 DGND1 VCCA2 3 VCCD1 AGND4 35 SEN IN AGND3 2 VSYNC AGND2 36 SCLK AGND1 100 nF 1 SDATA VCCA1 VCCA 100 nF VCCO FCE514 (1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available. (2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN;SHP) and th(IN;SHD) (see Section 10 "Characteristics"). (3) As an internal buffer is incorporated, depending on the CCD output impedance, an external input buffer may not be necessary and consequently power savings can be made. Fig 11. Application diagram. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 16 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras (1) CCD 12-bit data bus TDA9962 DIGITAL SIGNAL PROCESSOR MCE032 clamp signals HORIZONTAL AND VERTICAL DRIVER clock signals PULSE PATTERN GENERATOR (1) The external input buffer can be omitted for CCDs with low output impedance, for CCDs with high output impedance, a small current (around 1 mA) is needed. Fig 12. Typical imaging application. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 17 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 11.1 Power and grounding recommendations Care should be taken to minimize the noise when designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as classical operational amplifiers) must be taken into account, particularly with respect to power and ground connections. The connections between the CCD interface and the CDS input should be as short as possible and a ground ring protection around these connections can be beneficial. Separate analog and digital supplies provide the best performance. If it is not possible to do this on the board then the analog supply pins must be decoupled effectively from the digital supply pins. The decoupling capacitors must be placed as close as possible to the IC package. In a two-ground system, in order to minimize the noise through package and die parasitics, the following recommendation must be implemented. * The ground pin associated with the digital outputs must be connected to the digital ground plane and special care should be taken to avoid feedthrough in the analog ground plane. The analog and digital ground planes must be connected together with an inductor as closely as possible to the IC in order for them to have the same DC voltage. * The digital output pins and their associated lines should be shielded by the digital ground plane which can then be used as a return path for digital signals. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 18 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT313-2 136E05 MS-026 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 Fig 13. SOT313-2. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 19 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 13. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 14. Soldering 14.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages. 14.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 20 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 14.5 Package related soldering information Table 11: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA Reflow[2] not suitable suitable suitable[3] HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC[4], SO, SOJ suitable not SSOP, TSSOP, VSO not recommended[6] [2] [3] [4] [5] [6] suitable suitable recommended[4][5] LQFP, QFP, TQFP [1] suitable suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Wave Rev. 03 -- 12 September 2002 21 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 15. Revision history Table 12: Revision history Rev Date CPCN Description 03 20020912 - Preliminary specification; third version 02 20000804 - Objective specification; second version 01 20000501 - Objective specification; initial version (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Preliminary data Rev. 03 -- 12 September 2002 22 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras 16. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] [2] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17. Definitions 18. Disclaimers Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Preliminary data Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 10167 Rev. 03 -- 12 September 2002 23 of 24 TDA9962 Philips Semiconductors 12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . 16 Power and grounding recommendations . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Handling information. . . . . . . . . . . . . . . . . . . . 20 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 21 Package related soldering information . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 (c) Koninklijke Philips Electronics N.V. 2002. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 September 2002 Document order number: 9397 750 10167