RT8298ZQW - Richtek - Product.Network

DS8298-01 November 2011 www.richtek.com

RT8298

Simplified Application Circuit

General Description

The RT8298 is a synchronous step-down DC/DC converter

with an integrated high side internal power MOSFET a nd

a gate driver for a low side external power MOSFET. It

can deliver up to 6A output current from a 4.5V to 24V

input supply. The RT8298's current mode architecture

allows the transient response to be optimized over a wider

input voltage a nd load range. Cycle-by-cycle current limit

provides protection against shorted outputs a nd soft-start

eliminates input current surge during start-up. The RT8298

is synchronizable to an external clock with frequency

ranging from 300kHz to 1.5MHz.

The RT8298 is available in WDFN-14L 4x3 and SOP-8

(Exposed Pad) pa ckages.

6A, 24V, 600kHz Step-Down Converter with Synchronous

Gate Driver

Features

z4.5V to 24V Input Voltage Range

z6A Output Current

z45mΩΩ

ΩΩ

Ω Internal High Side N-MOSFET

zCurrent Mode Control

z600kHz Switching Frequency

zAdjustable Output from 0.8V to 15V

zUp to 95% Efficiency

zInternal Compensation

zStable with Ceramic Capacitors

zSynchronous External Clock : 300kHz to 1.5MHz

zCycle-by-Cycle Current Limit

zInput Under Voltage Lockout

zOutput Under Voltage Protection

zPower Good Indicator

zThermal Shutdown Protection

zRoHS Compliant and Halogen Free

Applications

zPoint of Load Regulator in Distributed Power Syste m

zDigital Set top Boxes

zPersonal Digital Recorders

zBroadband Communications

zFlat Pa nel TVs a nd Monitors

RT8298

VIN

CIN

VIN

VCC

CVCC

PGOODPower Good

EN/SYNC

BOOT CBOOT LVOUT

COUT

Chip Enable GND

2DS8298-01 November 2011www.richtek.com

RT8298

Ordering Information

Note :

Richtek products are :

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

Marking Information

04 YM

DNN

RT8298

ZSPYMDNN

RT8298ZQW

RT8298ZSP

04 : Product Code

YMDNN : Date Code

RT8298ZSP : Product Number

YMDNN : Date Code

Pin Configurations

(TOP VIEW)

WDFN-14L 4x3

PGOOD

VIN

GND

VCC

BOOT

EN/SYNC

VIN SW

NC SW

GND

SOP-8 (Exposed Pad)

BOOT

VCC

VIN

EN/SYNC

GND

RT8298 Package Type

QW : WDFN-14L 4x3 (W-Type)

SP : SOP-8 (Exposed Pad-Option 2)

Lead Plating System

Z : ECO (Ecological Element with

Halogen Free and Pb free)

DS8298-01 November 2011 www.richtek.com

RT8298

Functional Pin Description

Pin No.

WDFN-1 4L 4x3 SOP-8

(Exposed Pad)

Pi n Name P in Function

1 6 FB

Feedback Input. This pin is connected t o the converter out put . It

is used to set the output of the converter to regulate to the

desired value via an external resistive divider. The feedback

r ef er ence voltage is 0. 808V typically.

2 -- PGOOD

Power Good Indicator with Open Drain. (for RT8298ZQW only)

A 100kΩ pull-high resistor is needed. The output of this pin is

pulled to low when the FB is lower than 0.75V; otherwise it is

hi gh impedance.

3 7 EN/SYNC

Enable or External Frequency Synchronization Input. A

logic-high (2V < EN < 5.5V) enables the converter; a logic-low

forces the IC i nto shutdown m ode reducing the supply cur rent t o

l ess t han 3μA. For external frequen cy synch ronization operation,

the avail abl e fr equency range is f rom 300kH z to 1.5M Hz.

4, 5, 6 8 VIN Power Input. The available input voltage range is from 4.5V to

24V. A 22μF or larger input capacitor is needed to reduce

volt age s pi kes at the input.

7 - - N C N o In ternal Connection.

8, 9, 10 1 S W Switching Node. Output of the internal high side MOSFET.

Connect this pin to external low-side N-MOSFET, inductor and

boot strap cap acit or .

11 2 BOOT

Bootstrap for High side Gate Driver. Connect a 1μF ceramic

capaci to r between the B OO T pin a nd SW pin.

12 3 VCC

BG Driver Bias Supply. Decouple with a 1μF X5R /X7 R ceram ic

capaci to r betwe en the V CC pi n and G ND .

13 4 BG

Gate D river Output. Connect this pi n to the gate of the external

low -sid e N-MO SFET.

14,

15 (Exposed P ad) 5,

9 (Exposed Pad) GND Ground. The exposed pad must be sol der ed to a l ar ge PCB and

connect ed t o GND for maximum th er ma l di ssipati on.

4DS8298-01 November 2011www.richtek.com

RT8298

Function Block Diagram

Operation

The RT8298 is a synchronous high voltage Buck Converter

that can support the input voltage range from 4.5V to 24V

and the output current can be up to 6A. The RT8298 uses

a constant frequency , current mode architecture. In normal

operation, the high side N-MOSFET is turned on when

the Switch Controller is set by the oscillator (OSC) and is

turned off when the current comparator resets the Switch

Controller. While the N-MOSFET is turned off, the external

low side N-MOSFET is turned on by BG Driver with 5V

driving voltage from Internal Regulator (VCC) until next

cycle begins.

High side MOSFET pea k current is mea sured by internal

RSENSE. The Current Signal is where Slope Compensator

works together with sensing voltage of RSENSE. The error

amplifier EA adjusts COMP voltage by comparing the

feedback signal (VFB) from the output voltage with the

internal 0.808V reference. When the load current

increa ses, it causes a drop in the feedback voltage relative

to the reference, the COMP voltage then rises to allow

higher inductor current to match the load current.

UV Comparator : If the feedback voltage (VFB) is lower

than threshold voltage 0.4V, the UV Comparator's output

will go high and the Switch Controller will turn off the high

side MOSFET. The output under voltage protection is

designed to operate in Hiccup mode.

Oscillator (OSC) : The internal oscillator runs at nominal

frequency 600kHz and can be synchronized by an external

clock in the range between 300kHz and 1.5MHz from EN/

SYNC pin.

PGOOD Comparator : This function is available for

RT8298ZQW only. When the feedback voltage (VFB) is

higher than threshold voltage 0.75V, the PGOOD open

drain output will be high impeda nce.

Enable Comparator : Internal 5kΩ resistor and Zener diode

are used to cla mp the input signal to 3V . A 1.7V reference

voltage is for EN logic-high threshold voltage. The EN pin

can be connected to VIN through a 100kΩ resistor for

automatic startup.

Foldback Control : When VFB is lower than 0.7V, the

oscillation frequency will be proportional to the feedba ck

voltage.

Soft-Start (SS) : An internal current source (6nA) charges

an internal capacitor (15pF) to build the soft-start ramp

voltage (VSS). The VFB voltage will tra ck the internal ra mp

voltage during soft-start interval. The typical soft-start time

is 2ms.

Internal

Regulator

Enable

Comparator

EN/SYNC 1.7V

5k 3V

VIN

OSC

Foldback

Control

1pF

54pF 300k

-EA

0.808V

UV Comparator

-Current

Comparator

0.4V

BOOT

45m

PGOOD

GND

Current Sense

Amplifier

Slope

Compensator

PGOOD

Comparator

Driver BG

Switch

Controller

0.75V

VCC

RSENSE

VCC

OTP

COMP

6nA

15pF

VCC

VSS

VCC

Current

Signal

DS8298-01 November 2011 www.richtek.com

RT8298

Recommended Operating Conditions (Note 4)

zSupply Input Voltage, VIN ------------------------------------------------------------------------------------------ 4.5V to 24V

zJunction T emperature Range-------------------------------------------------------------------------------------- −40°C to 125°C

zAmbient T emperature Range-------------------------------------------------------------------------------------- −40°C to 85°C

Absolute Maximum Ratings (Note 1)

zSupply Input Voltage, VIN ------------------------------------------------------------------------------------------ –0.3V to 26V

zSwitching Voltage, SW -------------------------------------------------------------------------------------------- –0.3V to (VIN + 0.3V)

zBOOT to SW --------------------------------------------------------------------------------------------------------- –0.3V to 6V

zAll Other Voltage ---------------------------------------------------------------------------------------------------- −0.3V to 6V

z Power Dissipation, PD @ TA = 25°C

WDFN-14L 4x3------------------------------------------------------------------------------------------------------- 1.667W

SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------- 1.333W

zPa ckage Thermal Resista nce (Note 2)

W DF N-14L 4x3, θJA ------------------------------------------------------------------------------------------------- 60°C/W

WDFN-14L 4x3, θJC ------------------------------------------------------------------------------------------------- 7.5°C/W

SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 75°C/W

SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------- 15°C/W

zLead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------- 260°C

zJunction T emperature----------------------------------------------------------------------------------------------- 150°C

zStorage T emperature Range -------------------------------------------------------------------------------------- –65°C to 150°C

zESD Susceptibility (Note 3)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------- 2kV

MM (Ma chine Mode) ------------------------------------------------------------------------------------------------ 200V

Parameter Symbol Test Conditions Min Typ Max Unit

S hutdown Suppl y Cur r ent VEN = 0V -- 1 -- μA

Supply Curr ent VEN = 3V , VFB = 1 V -- 0 . 9 -- mA

Feedba ck R eference Vol tage V REF 4.5V ≤ VIN ≤ 24V 0. 796 0.808 0. 82 V

Feedba ck C urrent I FB V

FB = 0.8V -- 10 -- nA

H ig h-S ide Sw i tch On Resi st ance R DS(ON) -- 45 -- mΩ

High-Side Switch Current Limit BOOT − SW = 4.8 V -- 10 -- A

O scil l ati on Frequency f OSC1 -- 600 -- kHz

S hor t C ircuit Osc i ll at ion Frequency f OSC2 V

FB = 0V -- 190 -- kHz

M a x imum Duty Cycle DMAX V

FB = 0.6V -- 90 -- %

Minimu m On -Time tON V

FB = 1V -- 100 -- ns

I nput Unde r V ol t age Loc kout Thres hold V UVLO 4 4.2 4.4 V

I nput Unde r V ol t age Loc kout Thres hold

Hysteresis ΔVUVLO -- 400 -- mV

Logic-High VIH 2 -- 5.5

EN Threshold

Voltage Logic-Low VIL -- -- 0.4

(VIN = 12V, TA = 25°C, unless otherwise specified)

Electrical Characteristics

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RT8298

Parameter Symbol Test Conditions Min Typ Max Unit

S ync Frequency R ange fSync 0.3 -- 1.5 MHz

EN T urn-Off Delay tOFF -- 10 -- μs

E N Pu ll Low Curr ent VEN = 2V -- 1 -- μA

Th er ma l Sh ut down TSD -- 150 -- °C

Th er ma l Sh ut down H yst eresi s ΔTSD -- 20 -- °C

Power Good Thr eshold Rising -- 0.75 -- V

Power Good Thr eshold Hysteresis -- 40 -- mV

P ower G ood Pi n Level PG O OD Si nk 1 0mA - - - - 0. 125 V

BG Dr iver Bi as Suppl y Vol tage VCC 4.5 5 -- V

Gate Driver Sink Imped ance RSink -- 0.9 -- Ω

G at e Driver So ur ce I m pedance R Source -- 3.3 -- Ω

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect

device reliability.

Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

DS8298-01 November 2011 www.richtek.com

RT8298

Typical Application Circuit

For WDFN-14L 4x3 Package

For SOP-8 (Exposed Pad) Package

Table 1. Recommended Component Selection

VOUT (V) R1 (kΩ) R2 (kΩ) L (μH) COUT (μF)

1.2 62 127 1.5 22μF x 3

1.8 62 50.5 1.5 22μF x 3

2.5 62 30 2.2 22μF x 3

3.3 62 20 2.2 22μF x 3

5 93 18 2.8 22μF x 3

8 120 13.5 3.6

22μF x 3

RT8298

VIN

CIN

22µF

VIN

4.5V to 24V

VCC

100k

CVCC

1µF

4, 5, 6

2PGOODPower Good

EN/SYNC

BOOT

8, 9, 10

CBOOT

1µF 2.2µH

LVOUT

3.3V

COUT

22µF x 3

62k

20k

14, 15 (Exposed Pad)

Chip Enable GND

RT8298

VIN

CIN

22µF

VIN

4.5V to 24V

VCC

CVCC

1µF

EN/SYNC

BOOT

CBOOT

1µF 2.2µH

LVOUT

3.3V

COUT

22µF x 3

62k

20k

5, 9 (Exposed Pad)

Chip Enable GND

8DS8298-01 November 2011www.richtek.com

RT8298

Output Voltage vs. Temperature

3.20

3.22

3.24

3.26

3.28

3.30

3.32

3.34

3.36

3.38

3.40

-50 -25 0 25 50 75 100 125

Temperature (°C)

Output Vol tage (V)

VIN = 12V, VOUT = 3.3V, IOUT = 0A

Output Voltage vs. Output Current

3.20

3.22

3.24

3.26

3.28

3.30

3.32

3.34

3.36

3.38

3.40

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Output Current (A)

Output Voltage (V)

VIN = 6V

VIN = 12V

VIN = 24V

VOUT = 3.3V

Typical Operating Characteristics

Switching Frequenc y vs. Input Voltage

550

560

570

580

590

600

610

620

630

640

650

4 6 8 1012141618202224

In put Volt age ( V)

Swit ching Frequency (kHz) 1

VOUT = 3.3V, IOUT = 0A

Efficiency vs. Output Current

100

0123456

Ou tput Current (A)

Eff iciency (%)

VOUT = 3.3V

VIN = 6V

VIN = 12V

VIN = 24V

Output Voltage vs. Input Voltage

3.27

3.28

3.29

3.30

3.31

3.32

3.33

4 6 8 1012141618202224

In put Voltage (V)

Output Voltage (V)

VIN = 4.5V to 24V, VOUT = 3.3V, IOUT = 0A

Switc hing Frequency vs. Tempe rature

550

560

570

580

590

600

610

620

630

640

650

-50 -25 0 25 50 75 100 125

Temperat ur e (°C)

Swit ching Frequency (kHz) 1

VIN = 12V, VOUT = 3.3V, IOUT = 0A

DS8298-01 November 2011 www.richtek.com

RT8298

Current Limit vs. Tem pe rature

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

-50 -25 0 25 50 75 100 125

Temperature (°C)

Curr ent Limit (A)

VIN = 12V, VOUT = 3.3V

Time (2.5ms/Div)

Power On from VIN

VIN = 12V, VOUT = 3.3V, IOUT = 6A

VOUT

(2V/Div)

VIN

(5V/Div)

(5A/Div)

Time (1μs/Div)

Output Ripple Voltage

VOUT

(10mV/Div)

VSW

(10V/Div)

(5A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 6A

Time (1μs/Div)

Output Ripple Voltage

VOUT

(10mV/Div)

VSW

(10V/Div)

(2A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 3A

Time (250μs/Div)

Load Transient Response

VOUT

(100mV/Div)

IOUT

(5A/Div)

VIN = 12V, VOUT = 3.3V, IOUT = 0A to 6A

Time (250μs/Div)

Load Transient Response

VOUT

(100mV/Div)

IOUT

(5A/Div)

VIN = 12V, VOUT = 3.3V, IOUT = 3A to 6A

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RT8298

Time (5ms/Div)

Power Off from EN

VOUT

(2V/Div)

VEN

(5V/Div)

(5A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 6A

Time (500ns/Div)

External SYNC

VLX

(10V/Div)

Clock

(5V/Div)

(5A/Div)

VIN = 12V, VOUT = 3.3V, IOUT = 6A, Clock = 800kHz

VOUT

(5V/Div)

Time (2.5ms/Div)

Power On from EN

VOUT

(2V/Div)

VEN

(5V/Div)

(5A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 6A

Time (5ms/Div)

Power Off from VIN

VOUT

(2V/Div)

VIN

(5V/Div)

(5A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 6A

DS8298-01 November 2011 www.richtek.com

RT8298

Application Information

Output Voltage Setting

The resistive divider allows the FB pin to sense the output

voltage a s shown in Figure 1.

Figure 1. Output Voltage Setting

The output voltage is set by a n external resistive voltage

divider a ccording to the following equation :

OUT REF R1

V = V 1

⎛⎞

⎜⎟

⎝⎠

Where VREF is the feedback reference voltage (0.808V

typ.).

External Bootstrap Diode

Connect a 1μF low ESR ceramic capacitor between the

BOOT pin and SW pin. This capacitor provides the gate

driver voltage for the high side MOSFET.

It is recommended to add an external bootstrap diode

between an external 5V and BOOT pin for efficiency

improvement when input voltage is lower than 5.5V or duty

ratio is higher than 65% .The bootstrap diode can be a

low cost one such as IN4148 or BA T54. The external 5V

ca n be a 5V fixed input from system or a 5V output of the

RT8298. Note that the external boot voltage must be lower

than 5.5V.

Figure 2. External Bootstra p Diode

RT8298

GND

VOUT

BOOT

RT8298 1µF

Chip Enable Operation

The EN pin is the chip enable input. Pulling the EN pin

low (<0.4V) will shutdown the device. During shutdown

mode, the RT8298 quiescent current drops to lower than

3μA. Driving the EN pin high (2V < EN < 5.5V) will turn on

An external MOSFET can be added to implement digital

control on the EN pin, as shown in Figure 4. In this ca se,

a 100kΩ pull-up resistor , REN, is connected between VIN

pin and the EN pin. MOSFET Q2 will be under logic control

to pull down the EN pin.

Figure 3. Enable Timing Control

Figure 4. Digital Ena ble Control Circuit

RT8298

GND

100k

VIN

REN

the device again. For external timing control, the EN pin

can also be externally pulled high by adding a REN resistor

a nd CEN ca pa citor from the VIN pin (see Figure 3).

The chip starts to operate when VIN rises to 4.2V (UVLO

threshold). During the VIN rising period, if an 8V output

voltage is set, VIN is lower tha n the VOUT target value and

it may cause the chip to shut down. To prevent this

situation, a resistive voltage divider can be placed between

the input voltage and ground and connected to the EN pin

to adjust enable threshold, as shown in Figure 5. For

example, the setting VOUT is 8V and VIN is from 0V to

12V, when VIN is higher tha n 10V, the chip is triggered to

ena ble the converter . Assume REN1 = 50kΩ. Then,

Figure 5. Resistor Divider for Lockout Threshold Setting

RT8298

GND

VIN REN1

REN2

RT8298

GND

VIN REN

CEN

EN1 EN_T

EN2 IN_S EN_T

(R x V )

R =

(V V ) −

where VEN_T is the enable comparator's logic-high reference

threshold voltage (1.7V) and VIN_S is the target turn on

input voltage (10V in this example). According to the

equation, the suggested resistor R EN2 is 10.2kΩ.

12 DS8298-01 November 2011www.richtek.com

RT8298

Figure 6. Startup Sequence Using External Sync Clock

Soft-Start

The RT8298 provides soft-start function. The soft-start

function is used to prevent large inrush current while

converter is being powered-up. An internal current source

(6nA) charges an internal ca pacitor (15pF) to build a soft-

start ra mp voltage. The VFB voltage will tra ck the internal

ramp voltage during soft-start interval. The typical soft-

start time is calculated as follows :

Figure 6 shows the synchronization operation in startup

period. When the EN/SYNC is triggered by an external

clock, the RT8298 enters soft-start pha se a nd the output

voltage starts to rise. When VFB is lower than 0.7V, the

oscillation frequency will be proportional to the feedba ck

voltage. With higher VFB, the switching frequency is

relatively higher . After startup period about 3.5ms, the IC

operates with the same frequency a s the extern al clock.

Figure 7. Hiccup Mode U nder Voltage Protection

SS (0.808V 15pF)

t = = 2ms

6nA

Operating Frequency and Synchronization

The internal oscillator runs at 600kHz (typ.) when the EN/

SYNC pin is at logic-high level (>2V). If the EN pin is

pulled to low-level for 10μs above, the IC will shut down.

The RT8298 ca n be synchronized with a n external clock

ranging from 300kHz to 1.5MHz a pplied to the EN/SYNC

pin. The external clock duty cycle must be from 10% to

90%.

Over Temperature Protection

The RT8298 features an Over Temperature Protection

(OTP) circuitry to prevent from overheating due to

excessive power dissipation. The OTP will shut down

switching operation when junction temperature exceeds

150°C. Once the junction temperature cools down by

a pproximately 20°C, the converter will resume operation.

To maintain continuous operation, the maximum junction

temperature should be lower than 125°C.

Under Voltage Protection

For the RT8298, it provide s Hiccup Mode Under Voltage

Protection (UVP). When the VFB voltage drops below 0.4V,

the UVP function will be triggered to shut down switching

operation. If the UV condition remains for a period, the

RT8298 will retry every 2ms. When the UV condition is

removed, the converter will resume operation. The UVP

is disabled during soft-start period.

EN/SYNC

VFB

CLK

Foldback 600kHz External CLK

3.5ms (Start-up peri od) 10µs

Duty Cycle Limitation

The RT8298 has a maximum duty cycle 90%. The

minimum input voltage is determined by the maximum

duty cycle and its minimum operating voltage 4.5V. The

voltage drops of high side MOSFET and low side MOSFET

also must be considered for the minimum input voltage.

The minimum duty cycle can be calculated by the following

equation :

Duty Cycle(min) = fSW x tON(min)

Time (2.5ms/Div)

Hiccup Mode

VOUT

(1V/Div)

(5A/Div)

VIN = 12V, IOUT = Short

DS8298-01 November 2011 www.richtek.com

RT8298

External N-MOSFET Selection

The RT8298 is designed to operate using an external low

side N-MOSFET. Important parameters for the power

MOSFETs are the breakdown voltage (BVDSS), threshold

voltage (VGS_TH), on-resistance (RDS(ON)), total gate charge

(Qg) and maximum current (ID(MAX)). The gate driver voltage

is from internal regulator (5V, VCC). Theref ore logic level

N-MOSFET must be used in the RT8298 a pplication. The

total gate charge (Qg) must be less tha n 50nC, lower Qg

characteristics results in lower power losses. Drain-source

on-resistance (RDS(ON)) should be as small as possible,

less than 30mΩ is desirable. Lower RDS(ON) results in

higher efficiency .

Table 2. External N-MOSFET Selection

Part No. Manufacture

Si7114 Vishay

A04474 ALPHA & OMEGA

FDS6670AS Fairchild

IRF7821 International Rectifier

Inductor Selection

The inductor value and operating frequency determine the

ripple current according to a specific input and output

voltage. The ripple current ΔIL increases with higher VIN

and decrea ses with higher inductance.

OUT OUT

LIN

I = 1

fL V

⎡⎤⎡ ⎤

Δ×−

⎢⎥⎢ ⎥

⎣⎦⎣ ⎦

Having a lower ripple current reduces not only the ESR

losses in the output ca pacitors but also the output voltage

ripple. High frequency with small ripple current can reduce

voltage. For the highest eff iciency operation, however , it

requires a large inductor to a chieve this goal.

OUT OUT

L(MAX) IN(MAX)

L = 1

fI V

⎡⎤⎡ ⎤

×−

⎢⎥⎢ ⎥

×Δ

⎣⎦⎣ ⎦

The inductor's current rating (cause a 40°C temperature

rising from 25°C ambient) should be greater than the

maximum load current and its saturation current should

be greater than the short circuit peak current limit. Plea se

see Ta ble 3 for the inductor selection reference.

Table 3. Suggested Inductors for Typical

Application Circuit

Component

Supplier Series Dimensions

(mm)

10 x 10 x 4

Zenithtek ZPWM 6 x 6 x 3

WE 74477 10 x 10 x 4

TAIYOYUDEN NR80 40 8 x 10 x 4

OUT IN

RMS OUT(MAX) IN OUT

I = I 1

−

CIN and COUT Selection

The input capacitance, CIN, is needed to filter the

trapezoidal current at the source of the high side MOSFET .

To prevent large ripple current, a low ESR input ca pacitor

sized for the maximum RMS current should be used. The

a pproxi mate RMS current equation is given :

This formula has a maximum at VIN = 2VOUT, where

IRMS = IOUT / 2. This simple worst case condition is

commonly used for design because even significant

deviations do not offer much relief.

Choose a capacitor rated at a higher temperature than

required. Several capacitors may also be paralleled to

meet size or height requirements in the design.

where fsw is the switching frequency, tON (min) is the

minimum switch on time (100ns). This equation shows

that the minimum duty cycle increa ses when the switching

frequency is increased. Therefore, slower switching

frequency is necessary to achieve high VIN/VOUT ratio

application.

For the ripple current selection, the value of ΔIL = 0.24(IMAX)

will be a reasonable starting point. The largest ripple

current occurs at the highest VIN. To guarantee that the

ripple current stays below the specified maximum, the

inductor value should be chosen according to the following

equation :

14 DS8298-01 November 2011www.richtek.com

RT8298

Table 4. Suggested Capacitors for CIN and COUT

Location Component Supplier Part No. Capacitan ce ( μF) Case Size

CIN MURATA GRM31CR61E106K 10 1206

CIN TDK C3225X5R1E106K 10 1206

CIN TAIYO YUDEN TMK316BJ106ML 10 1206

COUT MURATA GRM31CR60J476M 47 1206

COUT TDK C3225X5R0J476M 47 1210

COUT MURATA GRM32ER71C226M 22 1210

COUT TDK C3225X5R1C22M 22 1210

Checking Tran sient Re spon se

The regulator loop response can be checked by looking

at the load tra nsient response. Switching regulators ta ke

several cycles to respond to a step load cha nge. When a

step load occurs, VOUT immediately shifts by an amount

equal to ΔILOAD x ESR also begins to charge or discharge

COUT generating a feedba ck error signal f or the regulator

to return VOUT to its steady-state value. During this

recovery time, VOUT can be monitored for overshoot or

ringing that would indicate a stability problem.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

where TJ(MAX) is the maximum junction temperature, TA is

the a mbient temperature, and θJA is the junction to a mbient

thermal resistance.

For recommended operating condition specifications of

the RT8298, the maximum junction temperature is 125°C.

The junction to a mbient thermal resista nce, θJA, is layout

dependent. For SOP-8 (Exposed Pad) package, the

thermal resistance, θJA, is 75°C/W on a standard JEDEC

51-7 four-layer thermal test board.

The output ripple will be the highest at the maximum input

voltage since ΔIL increases with input voltage. Multiple

capa citors pla ced in parallel may be needed to meet the

ESR and RMS current handling requirement.

Higher values, lower cost ceramic capacitors are now

becoming available in smaller ca se sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. When a ceramic

capacitor is used at the input and the power is supplied

by a wall adapter through long wires, a load step at the

output can induce ringing at the input, VIN. This ringing

can couple to the output and be mistaken. A sudden inrush

of current through the long wires ca n potentially cause a

voltage spike at VIN large enough to da mage the part.

For the input capacitor, two 10μF low ESR ceramic

capacitors are recommended. For the recommended

ca p acitor , ple a se refer to Table 4 for more details.

The selection of COUT is determined by the required ESR

to minimize voltage ripple.

Moreover, the amount of bulk capacitance is also a key

for COUT selection to ensure that the control loop is stable.

Loop stability can be checked by viewing the load transient

response as described in a later section.

The output ripple, ΔVOUT , is determined by :

OUT L OUT

VIESR

8fC

⎡⎤

Δ≤Δ +

⎢⎥

⎣⎦

DS8298-01 November 2011 www.richtek.com

RT8298

Figure 8. Derating Curves for RT8298 Package

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0255075100125

Ambient Temperatur e (°C)

Maximum Pow er Dissipati on (W) 1

WDFN-14L 4x3

SOP-8 (Exposed Pad)

Four-Layer PCB

For WDF N-14L 4x3 package, the thermal resistance, θJA,

is 60°C/W on a sta ndard JEDEC 51-7 four-layer thermal

test board. The maximum power dissipation at TA = 25°C

ca n be calculated by the f ollowing f ormulas :

PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for

SOP-8 (Exposed Pad) pa ckage

PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for

W DFN-14L 4x3 pa ckage

The maximum power dissipation depends on the operating

ambient temperature for fixed TJ(MAX) and thermal

resistance, θJA. For the RT8298 package, the derating

curves in Figure 8 allow the designer to see the effect of

rising ambient temperature on the maximum power

dissipation.

Layout Consideration

Follow the PCB layout guidelines for optimal performa nce

of the RT8298.

`Keep the tra ces of the main current paths a s short a n d

wide as possible.

`Put the input ca pacitor as close a s possible to the device

pins (VIN and GND).

`SW node is with high frequency voltage swing and

should be kept at small area. Keep analog components

away from the SW node to prevent stray ca pacitive noise

pick-up.

`Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback

components near the RT8298.

`Connect all analog grounds to a common node and then

connect the common node to the power ground behind

the output ca p a citors.

`An example of PCB layout guide is shown in Figure 9

and Figure 10 for reference.

16 DS8298-01 November 2011www.richtek.com

RT8298

Figure 9. PCB Layout Guide f or SOP-8 (Exposed Pad)

Figure 10. PCB Layout Guide for W DFN-14L 4x3

VOUT

GND

VOUT

BOOT

VCC

VIN

EN/SYNC

GND

CIN

CBOOT GND

COUT

The feedback components

must be connected as close

to the device as possible.

Input capacitor must be placed

as close to the IC as possible.

SW should be connected to inductor by

wide and short trace. Keep sensitive

components away from this trace.

The EN/SYNC must be kept

away from noise. The trace

should be short and shielded

with a ground trace.

CVCC

GND

CVCC capacitor must

be placed as close t o

the IC as possible.

VIN

VCC

GND

R1 R2

CBOOT

LVOUT

COUT

VOUT

GND

CIN

GND

The feedback components

must be connected as close

to the device as possible.

Input capacitor must be

placed as close to the

IC as possible.

SW should be connected

to inductor by wide and

short trace. Keep sensitive

components away from

this trace.

The EN/SYNC must be kept

away from noise. The tr ace

should be short and shielded

with a ground trace.

PGOOD

VIN

GND

VCC

BOOT

EN/SYNC

VIN SW

NC SW

GND

CVCC capacitor must

be placed as close to

the IC as possible.

CVCC

VIN

DS8298-01 November 2011 www.richtek.com

RT8298

Outline Dimension

Dime nsions In Millim eters Dimension s In Inch e s

Symbol Min Max Min Max

A 0.700 0.800 0.028 0.031

A1 0.000 0.050 0.000 0.002

A3 0.175 0.250 0.007 0.010

b 0.180 0.300 0.007 0.012

D 3.900 4.100 0.154 0.161

D2 3.250 3.350 0.128 0.132

E 2.900 3.100 0.114 0.122

E2 1.650 1.750 0.065 0.069

e 0.500 0.020

L 0.350 0.450

0.014 0.018

W-Type 14L DFN 4x3 Package

18 DS8298-01 November 2011www.richtek.com

RT8298

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

EXPOSED THERMAL PAD

(Bottom of Package)

8-Lead SOP (Exposed Pad) Plastic Package

Dime nsions In Millime ters Dimensions In In c hes

Symbol Min Max Min Max

A 4.801 5.004 0.189 0.197

B 3.810 4.000 0.150 0.157

C 1.346 1.753 0.053 0.069

D 0.330 0.510 0.013 0.020

F 1.194 1.346 0.047 0.053

H 0.170 0.254 0.007 0.010

I 0.000 0.152 0.000 0.006

J 5.791 6.200 0.228 0.244

M 0.406 1.270 0.016 0.050

X 2.000 2.300 0.079 0.091

Option 1 Y 2.000 2.300 0.079 0.091

X 2.100 2.500 0.083 0.098

Option 2 Y 3.000 3.500 0.118 0.138