74AC899QCQB - National Semiconductor

TL/F/10637

74AC899 #54ACT/74ACT899

9-Bit Latchable Transceiver with Parity Generator/Checker

August 1994

74AC899 #54ACT/74ACT899

9-Bit Latchable Transceiver

with Parity Generator/Checker

General Description

The ’AC/’ACT899 is a 9-bit to 9-bit parity transceiver with

transparent latches. The device can operate as a feed-

through transceiver or it can generate/check parity from the

8-bit data busses in either direction. The ’AC/’ACT899 fea-

tures independent latch enables for the A-to-B direction and

the B-to-A direction, a select pin for ODD/EVEN parity, and

separate error signal output pins for checking parity.

Features

YLatchable transceiver with output sink of 24 mA

YOption to select generate parity and check or ‘‘feed-

through’’ data/parity in directions A-to-B or B-to-A

YIndependent latch enable for A-to-B and B-to-A direc-

tions

YSelect pin for ODD/EVEN parity

YERRA and ERRB output pins for parity checking

YAbility to simultaneously generate and check parity

YMay be used in system applications in place of the ’280

YMay be used in system applications in place of the ’657

and ’373 (no need to change T/R to check parity)

Y4 kV minimum ESD immunity

Logic Symbol

TL/F/10637–1

Connection Diagram

Pin Assignment for PCC and LCC

TL/F/10637–2

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

FACTTM is a trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

Pin Names Description

A0–A7A Bus Data Inputs/Data Outputs

B0–B7B Bus Data Inputs/Data Outputs

APAR, BPAR A and B Bus Parity Inputs

ODD/EVEN ODD/EVEN Parity Select, Active

LOW for EVEN Parity

GBA, GAB Output Enables for A or B Bus,

Active LOW

SEL Select Pin for Feed-Through or

Generate Mode, LOW for Generate

Mode

LEA, LEB Latch Enables for A and B Latches,

HIGH for Transparent Mode

ERRA, ERRB Error Signals for Checking

Generated Parity with Parity In,

LOW if Error Occurs

Functional Description

The ’AC/’ACT899 has three principal modes of operation

which are outlined below. These modes apply to both the A-

to-B and B-to-A directions.

Ð Bus A (B) communicates to Bus B (A), parity is generat-

ed and passed on to the B (A) Bus as BPAR (APAR). If

LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,

the parity generated from B[0:7](A[0:7]) can be

checked and monitored by ERRB (ERRA).

Ð Bus A (B) communicates to Bus B (A) in a feed-through

mode if SEL is HIGH. Parity is still generated and

checked as ERRA and ERRB in the feed-through mode

(can be used as an interrupt to signal a data/parity bit

error to the CPU).

Ð Independent Latch Enables (LEA and LEB) allow other

permutations of generating/checking (see Function Ta-

ble below).

Function Table

Inputs Operation

GAB GBA SEL LEA LEB

H H X X X Busses A and B are TRI-STATEÉ.

H L L L H Generates parity from B[0:7]based on O/E (Note 1). Generated parity

APAR. Generated parity checked against BPAR and output as

ERRB.

H L L H H Generates parity from B[0:7]based on O/E. Generated parity

APAR. Generated parity checked against BPAR and output as ERRB.

Generated parity also fed back through the A latch for generate/check

as ERRA.

H L L X L Generates parity from B latch data based on O/E. Generated parity

APAR. Generated parity checked against latched BPAR and

output as ERRB.

H L H X H BPAR/B[0:7]

APAR/A0:7]Feed-through mode. Generated parity

checked against BPAR and output as ERRB.

H L H H H BPAR/B[0:7]

APAR/A[0:7]

Feed-through mode. Generated parity checked against BPAR and

output as ERRB. Generated parity also fed back through the A latch for

generate/check as ERRA.

L H L H L Generates parity for A[0:7]based on O/E. Generated parity

BPAR. Generated parity checked against APAR and output as ERRA.

L H L H H Generates parity from A[0:7]based on O/E. Generated parity

BPAR. Generated parity checked against APAR and output as ERRA.

Generated parity also fed back through the B latch for generate/check

as ERRB.

L H L L X Generates parity from A latch data based on O/E. Generated parity

BPAR. Generated parity checked against latched APAR and

output as ERRA.

L H H H L APAR/A[0:7]

BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and

output as ERRA.

L H H H H APAR/A[0:7]

BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and

output as ERRA. Generated parity also fed back through the B latch for

generate/check as ERRB.

HeHIGH Voltage Level

LeLOW Voltage Level

XeImmaterial

Note 1: O/E eODD/EVEN

Functional Block Diagram

TL/F/10637–3

AC Path

TL/F/10637–4

An, APAR

Bn, BPAR

(Bn, BPAR

An, APAR)

FIGURE 1

AC Path (Continued)

BPAR

(Bn

APAR) TL/F/10637–5

FIGURE 2

ERRA

(Bn

ERRB) TL/F/10637–6

FIGURE 3

O/E

ERRA

O/E

ERRB TL/F/10637–7

FIGURE 4

AC Path (Continued)

O/E

BPAR

(O/E

APAR) TL/F/10637–8

FIGURE 5

APAR

ERRA

(BPAR

ERRB) TL/F/10637–9

FIGURE 6

TL/F/10637–10

ZH, HZ

FIGURE 7

AC Path (Continued)

TL/F/10637–11

ZL, LZ

FIGURE 8

TL/F/10637–12

SEL

BPAR

(SEL

APAR)

FIGURE 9

TL/F/10637–13

LEA

BPAR, B[0:7]

(LEB

APAR, A[0:7])

FIGURE 10

AC Path (Continued)

TS(H), TH(H)

TL/F/10637–14

LEA

APAR, A[0:7]

(LEB

BPAR, B[0:7])

FIGURE 11

TS(L), TH(L)

TL/F/10637–15

LEA

APAR, A[0:7]

(LEB

BPAR, B[0:7])

FIGURE 12

TL/F/10637–16

FIGURE 13

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VCC)b0.5V to a7.0V

DC Input Diode Current (IIK)

VIeb

0.5V b20 mA

VIeVCC a0.5V a20 mA

DC Input Voltage (VI)b0.5V to VCC a0.5V

DC Output Diode Current (IOK)

VOeb

0.5V b20 mA

VOeVCC a0.5V a20 mA

DC Output Voltage (VO)b0.5V to VCC a0.5V

DC Output Source

or Sink Current (IO)g50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)g50 mA

Storage Temperature (TSTG)b65§Ctoa

150§C

DC Latch-Up Source or

Sink Current g300 mA

Junction Temperature (TJ)

CDIP 175§C

PDIP 140§C

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

mend operation of FACTTM circuits outside databook specifications.

Recommended Operating

Conditions

Supply Voltage (VCC)

’AC 2.0V to 6.0V

’ACT 4.5V to 5.5V

Input Voltage (VI) 0VtoV

Output Voltage (VO) 0VtoV

Operating Temperature (TA)

74AC/ACT b40§Ctoa

85§C

54ACT b55§Ctoa

125§C

Minimum Input Edge Rate DV/Dt

’AC Devices

VIN from 30% to 70% of VCC

VCC @3.0V, 4.5V, 5.5V 125 mV/ns

Minimum Input Edge Rate DV/Dt

’ACT Devices

VIN from 0.8V to 2.0V

VCC @4.5V, 5.5V 125 mV/ns

Note: PLCC packaging is not recommended for applications requiring great-

er than 2000 temperature cycles from b40§Ctoa

125§C.

DC Electrical Characteristics for ’AC Family Devices

74AC 74AC

Symbol Parameter VCC TAea

25§CTAeUnits Conditions

(V) b40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 3.0 1.5 2.1 2.1 VOUT e0.1V

Input Voltage 4.5 2.25 3.15 3.15 V or VCC b0.1V

5.5 2.75 3.85 3.85

VIL Maximum Low Level 3.0 1.5 0.9 0.9 VOUT e0.1V

Input Voltage 4.5 2.25 1.35 1.35 V or VCC b0.1V

5.5 2.75 1.65 1.65

VOH Minimum High Level 3.0 2.99 2.9 2.9 IOUT eb

50 mA

Output Voltage 4.5 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4

*VIN eVIL or VIH

3.0 2.56 2.46 Vb12 mA

4.5 3.86 3.76 IOH b24 mA

5.5 4.86 4.76 b24 mA

VOL Maximum Low Level 3.0 0.002 0.1 0.1 IOUT e50 mA

Output Voltage 4.5 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1

*VIN eVIL or VIH

3.0 0.36 0.44 12 mA

4.5 0.36 0.44 V IOL 24 mA

5.5 0.36 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 mAVIeVCC, GND

Leakage Current (Note)

*Maximum of 9 outputs loaded; thresholds on input associated with output under test.

DC Electrical Characteristics for ’AC Family Devices (Continued)

74AC 74AC

Symbol Parameter VCC TAea

25§CTAeUnits Conditions

(V) b40§Ctoa

85§C

Typ Guaranteed Limits

IOLD ²Minimum Dynamic 5.5 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 8.0 80.0 mAVIN eVCC

Supply Current or GND (Note)

IOZ Maximum TRI-STATE VI(OE) eVIL,V

Leakage Current 5.5 g0.5 g5.0 mAV

CC, GND

VOeVCC, GND

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: IIN and ICC @3.0V are guaranteed to be less than or equal to the respective limit @5.5V VCC.I

CC for 54AC @25§C is identical to 74AC @25§C.

DC Electrical Characteristics for ’ACT Family Devices

74ACT 54ACT 74ACT

Symbol Parameter VCC TAea

25§CTAeTAeUnits Conditions

(V) b55§Ctoa

125§Cb40§Ctoa

85§C

Typ Guaranteed Limits

VIH Minimum High Level 4.5 1.5 2.0 2.0 2.0 VVOUT e0.1V

Input Voltage 5.5 1.5 2.0 2.0 2.0 or VCC b0.1V

VIL Maximum Low Level 4.5 1.5 0.8 0.8 0.8 VVOUT e0.1V

Input Voltage 5.5 1.5 0.8 0.8 0.8 or VCC b0.1V

VOH Minimum High Level 4.5 4.49 4.4 4.4 4.4 VIOUT eb

50 mA

Output Voltage 5.5 5.49 5.4 5.4 5.4

*VIN eVIL or VIH

4.5 3.86 3.70 3.76 V IOH b24 mA

5.5 4.86 4.70 4.76 b24 mA

VOL Maximum Low Level 4.5 0.001 0.1 0.1 0.1 VIOUT e50 mA

Output Voltage 5.5 0.001 0.1 0.1 0.1

*VIN eVIL or VIH

4.5 0.36 0.50 0.44 VIOL 24 mA

5.5 0.36 0.50 0.44 24 mA

IIN Maximum Input 5.5 g0.1 g1.0 g1.0 mAVIeVCC, GND

Leakage Current

IOZ Maximum TRI-STATE 5.5 g0.5 g10.0 g5.0 mAVIeVIL,V

Leakage Current VOeVCC, GND

ICCT Maximum ICC/Input 5.5 0.6 1.6 1.5 mA VIeVCC b2.1V

IOLD ²Minimum Dynamic 5.5 50 75 mA VOLD e1.65V Max

IOHD Output Current 5.5 b50 b75 mA VOHD e3.85V Min

ICC Maximum Quiescent 5.5 8.0 160.0 80.0 mAVIN eVCC

Supply Current or GND (Note)

*Maximum of 9 outputs loaded; thresholds on input associated with output under test.

²Maximum test duration 2.0 ms, one output loaded at a time.

Note: ICC for 54ACT @25§C is identical to 74ACT @25§C.

AC Electrical Characteristics

74AC 74AC

VCC*TAea

25§CTAeb

40§CFig.

Symbol Parameter (V) CLe50 pF to a85§C Units No.

CLe50 pF

Min Typ Max Min Max

tPLH Propagation Delay 3.3 2.5 12.0 15.0 2.5 15.5 ns 1

tPHL An,B

nto Bn,A

n5.0 1.5 7.0 10.0 1.5 10.5

tPLH Propagation Delay 3.3 2.5 9.5 12.0 2.5 12.5 ns 1

tPHL APAR, BPAR to BPAR, APAR 5.0 1.5 5.5 8.0 1.5 8.5

tPLH Propagation Delay 3.3 3.0 13.5 16.5 3.0 17.0 ns 2

tPHL An,B

nto BPAR, APAR 5.0 2.0 8.0 11.0 2.0 11.5

tPLH Propagation Delay 3.3 2.5 12.5 15.5 2.5 16.5 ns 3

tPHL An,B

nto ERRA, ERRB 5.0 1.5 7.5 10.5 1.5 11.0

tPLH Propagation Delay 3.3 2.5 12.5 15.5 2.5 16.5 ns 4

tPHL ODD/EVEN to ERRA, ERRB 5.0 1.5 7.5 10.5 1.5 11.0

tPLH Propagation Delay 3.3 3.0 12.5 15.5 3.0 16.5 ns 5

tPHL ODD/EVEN to APAR, BPAR 5.0 2.0 7.5 10.5 2.0 11.0

tPLH Propagation Delay 3.3 2.0 12.5 15.5 2.0 16.5 ns 6

tPHL APAR, BPAR to ERRA, ERRB 5.0 1.5 7.5 10.5 1.5 11.0

tPLH Propagation Delay 3.3 2.0 10.0 12.5 2.0 13.5 ns 9

tPHL SEL to APAR, BPAR 5.0 1.5 6.0 8.5 1.5 9.0

tPLH Propagation Delay 3.3 4.0 12.0 15.5 4.0 16.5 ns 10, 11

tPHL LEB, LEA to An,B

n5.0 2.5 7.0 10.5 2.5 11.0

tPLH Propagation Delay 3.3 3.0 13.5 17.0 3.0 18.0 ns 10, 11

tPHL LEB, LEA to APAR, BPAR 5.0 2.0 8.0 11.5 2.0 12.0

tPLH Propagation Delay 3.3 4.0 13.5 17.0 4.0 18.0 ns 12

tPHL LEB, LEA to ERRA, ERRB 5.0 2.5 8.0 11.5 2.5 12.0

tPZH Output Enable Time 3.3 3.0 12.5 15.5 3.0 16.5 ns 7, 8

tPZL GBA, GAB to An,B

n5.0 2.0 7.5 10.5 2.0 11.0

tPZH Output Enable Time 3.3 2.5 10.5 13.5 2.5 14.0 ns 7, 8

tPZL GBA, GAB to APAR, BPAR 5.0 1.5 6.0 9.0 1.5 9.5

tPHZ Output Disable Time 3.3 1.5 11.0 14.0 1.5 14.0 ns 7, 8

tPLZ GBA, GAB to An,B

n5.0 1.0 6.5 9.5 1.0 9.5

tPHZ Output Disable Time 3.3 1.5 11.0 14.0 1.5 14.0 ns 7, 8

tPHL GBA, GAB to APAR, BPAR 5.0 1.0 6.5 9.5 1.0 9.5

*Voltage Range 5.0 is 5.0V g0.5V.

Voltage Range 3.3 is 3.3V g0.3V.

AC Operating Requirements

74AC 74AC

VCC*TAea

25§CTAeb

40§CFig.

Symbol Parameter (V) CLe50 pF to a85§C Units No.

CLe50 pF

Guaranteed Minimum

tsSetup Time, HIGH or LOW 3.3 3.0 3.0 ns 11, 12

An,B

, PAR to LEA, LEB 5.0 3.0 3.0

thHold Time, HIGH or LOW 3.3 2.0 2.0 ns 11, 12

An,B

, PAR to LEA, LEB 5.0 1.5 1.5

twPulse Width for LEA, LEB 3.3 4.0 4.0 ns 13

5.0 4.0 4.0

*Voltage Range 5.0 is 5.0V g0.5V.

Voltage Range 3.3 is 3.3V g0.3V.

AC Electrical Characteristics

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§CFig.

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units No.

CLe50 pF CLe50 pF

Min Typ Max Min Max Min Max

tPLH Propagation Delay 5.0 2.5 7.5 11.5 1.5 13.5 2.5 12.0 ns 1

tPHL An,B

nto Bn,A

PLH Propagation Delay 5.0 1.5 6.0 8.5 1.5 11.0 1.5 9.0 ns 1

tPHL APAR, BPAR to BPAR , APAR

tPLH Propagation Delay 5.0 2.5 8.5 12.0 1.5 16.0 2.5 12.5 ns 2

tPHL An,B

nto BPAR, APAR

tPLH Propagation Delay 5.0 2.0 8.0 11.5 1.5 16.0 2.0 12.0 ns 3

tPHL An,B

nto ERRA, ERRB

tPLH Propagation Delay 5.0 2.0 8.0 11.5 1.5 16.0 2.0 12.0 ns 4

tPHL ODD/EVEN to ERRA, ERRB

tPLH Propagation Delay 5.0 2.5 8.0 11.5 1.5 14.5 2.5 12.0 ns 5

tPHL ODD/EVEN to APAR, BPAR

tPLH Propagation Delay 5.0 1.5 7.5 10.5 1.5 11.5 1.5 11.5 ns 6

tPHL APAR, BPAR to ERRA, ERRB

tPLH Propagation Delay 5.0 1.5 6.5 9.0 1.5 12.5 1.5 9.5 ns 9

tPHL SEL to APAR, BPAR

tPLH Propagation Delay 5.0 2.5 7.0 10.5 1.5 13.5 2.5 11.0 ns 10, 11

tPHL LEB to An,B

PLH Propagation Delay 5.0 2.0 8.0 11.5 1.5 16.0 2.0 12.0 ns 10, 11

tPHL LEA to APAR, BPAR

tPLH Propagation Delay 5.0 2.5 8.0 11.5 1.5 16.0 2.5 12.0 ns 12

tPHL LEA, LEB to ERRA, ERRB

tPZH Output Enable Time 5.0 2.5 7.0 10.5 1.5 16.0 2.5 11.0 ns 7, 8

tPZL GBA or GAB to An,B

PZH Output Enable Time 5.0 1.5 6.0 9.0 1.5 11.0 1.5 9.5 ns 7, 8

tPZL GBA or GAB to BPAR or APAR

tPHZ Output Disable Time 5.0 1.5 6.5 9.5 1.5 11.0 1.5 9.5 ns 7, 8

tPHL GBA or GAB to An,B

PHZ Output Disable Time 5.0 1.5 6.5 9.5 1.5 11.0 1.5 9.5 ns 7, 8

tPLZ GBA or GAB to BPAR, APAR

*Voltage Range 5.0 is 5.0V g0.5V.

AC Operating Requirements

74ACT 54ACT 74ACT

VCC*TAea

25§CTAeb

55§CT

40§CFig.

Symbol Parameter (V) CLe50 pF to a125§Cto

85§C Units No.

CLe50 pF CLe50 pF

Guaranteed Minimum

tsSetup Time, HIGH or LOW 5.0 3.0 3.0 3.0 ns 11, 12

An,B

, PAR to LEA, LEB

thHold Time, HIGH or LOW 5.0 1.5 3.0 1.5 ns 11, 12

An,B

, PAR to LEA, LEB

twPulse Width for LEB, LEA 5.0 4.0 4.0 4.0 ns 13

*Voltage Range 5.0 e5.0V g0.5V.

Capacitance

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 4.5 pF VCC e5.0V

CPD Power Dissipation 210 pF VCC e5.0V

Capacitance

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are

defined as follows:

74ACT 899 Q C X

Temperature Range Family Special Variations

74AC eCommercial X eDevices shipped in 13×reels

74ACT eCommercial TTL-Compatible QB eMilitary grade with environmental

54ACT eMilitary TTL-Compatible and burn-in processing shipped

in tubes

Device Type

Temperature Range

Package Code CeCommercial (b40§Ctoa

85§C)

QePlastic Leaded Chip Carrier (PCC) MeMilitary (b55§Ctoa

125§C)

74AC899 #54ACT/74ACT899

9-Bit Latchable Transceiver with Parity Generator/Checker

Physical Dimensions inches (millimeters) Lit. Ý115200

28-Lead Plastic Chip Carrier (Q)

NS Package Number V28A

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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

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