
V96SSC
HIGH INTEGRATION
SYSTEM CONTROLLER
For i960® Jx/Sx and PowerPC 401™ Gx Processors
Glueless interface between Intel®
i960® Jx/Sx series and IBM®
PowerPC 401™ Gx processors,
DRAM arrays, and peripheral
devices
Local bus speeds up to 33 MHz
High performance burst DRAM
controller with DRAM page cache
management
Synchronous/asynchronous serial
communications unit
Two-channel y-by DMA controller
Support for boot PROM devices
System heartbeat and watchdog
timers
Interrupt control unit
Up to ve programmable chip
select/peripheral device
strobe generation
Two 32-bit general purpose timers
with pulse width modulation
capability
Supports 32-bit bus masters
Supports extended burst
transactions, up to 1 Kbyte
16 general-purpose I/Os
Supports 3.3 V DRAM modules
Industrial temperature range
(−40°C to +85°C)
Low-cost 100-pin EIAJ PQFP
package
The V96SSC High Integration System Controller simplies the design of systems based
on Intel’s i960® Jx/SX and IBM’s PowerPC 401™ Gx microprocessors. By using the
V96SSC, designers can replace many lower-integration support components with a single,
high-integration device—this saves design time, board area, and manufacturing cost.
The integrated DRAM controller directly connects the supported i960®/PowerPC 401™
processor to DRAM arrays ranging from 128 Kbyte to 128 Mbyte. The fully programmable
DRAM controller allows use of a wide range of DRAM speeds and congurations. It
supports burst accesses up to 1 Kbyte in length, allowing the use of high-performance,
bus-mastering peripherals.
The two-channel y-by DMA controller makes it easy to use less expensive, non-mastering
peripherals. To further aid in connecting the processor, the V96SSC’s I/O Controller
performs address decoding and chip-select/strobe generation. In addition, the I/O lines can
be used as simple I/O ports on a bit-by-bit basis. The serial communications unit connects
to either RS-232 or synchronous serial devices.
The two general-purpose, 32-bit timers can be individually congured as a pulse width
modulator or used in other modes, such as retriggering or one-shot. The bus watch timer
prevents system hangs during accesses to unpopulated memory. Interrupts for a real-time
OS are generated easily by the system heartbeat timer. A watchdog timer is also provided
for graceful recovery from catastrophic program failures.
Interrupt requests for all on-chip peripherals are managed by the Interrupt Control Unit
(ICU). Additionally, off-chip interrupts can be routed via the I/O multiplexer to the ICU.
The V96SSC is packaged in a low-cost 100-pin EIAJ Plastic Quad Flat Pack (PQFP), and is
available in a 33 MHz speed grade.