LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
LM4857 Stereo 1.2W Audio Sub-system with 3D
Enhancement
Check for Samples: LM4857
1FEATURES KEY SPECIFICATIONS
2• Stereo Speaker Amplifier • POUT, Stereo Loudspeakers, 4Ω, 5V, 1%
THD+N (LM4857SP) 1.6W (typ)
• Stereo Headphone Amplifier • POUT, Stereo Loudspeakers, 8Ω, 5V, 1%
• Mono Earpiece Amplifier THD+N 1.2W (typ)
• Mono Line Output for External Handsfree • POUT, Stereo Headphones, 32Ω, 5V, 1%
Carkit THD+N 75mW (typ)
• Independent Left, Right, and Mono Volume • POUT, Mono Earpiece, 32Ω, 5V, 1% THD+N
Controls 100mW (typ)
• TI 3D Enhancement • POUT, Stereo Loudspeakers, 8Ω, 3.3V, 1%
• I2C Compatible Interface THD+N 495mW (typ)
• Ultra low Shutdown Current • POUT, Stereo Headphones, 32Ω, 3.3V, 1%
• Click and Pop Suppression Circuit THD+N 33mW (typ)
• 16 distinct Output Modes • POUT, Mono Earpiece, 32Ω, 3.3V, 1% THD+N
• Thermal Shutdown Protection 43mW (typ)
• Available in DSBGA and UQFN packages • Shutdown Current 0.06μA (typ)
APPLICATIONS DESCRIPTION
The LM4857 is an integrated audio sub-system
• Cell Phones designed for stereo cell phone applications.
• PDAs Operating on a 3.3V supply, it combines a stereo
• Portable Gaming Devices speaker amplifier delivering 495mW per channel into
• Internet Appliances an 8Ωload, a stereo headphone amplifier delivering
33mW per channel into a 32Ωload, a mono earpiece
• Portable DVD/CD/AAC/MP3 players amplifier delivering 43mW into a 32Ωload, and a line
output for an external powered handsfree speaker. It
integrates the audio amplifiers, volume control, mixer,
power management control, and TI 3D enhancement
all into a single package. In addition, the LM4857
routes and mixes the stereo and mono inputs into 16
distinct output modes. The LM4857 is controlled
through an I2C compatible interface. Other features
include an ultra-low current shutdown mode and
thermal shutdown protection.
Boomer audio power amplifiers are designed
specifically to provide high quality output power with a
minimal amount of external components.
The LM4857 is available in a 30-bump DSBGA
package and a 28–lead UQFN package.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Connection Diagram
Figure 2. 30 Bump DSBGA Package – Top View (Bump-side down)
See Package Number YZR0030
PIN CONNECTION (DSBGA)
Pin Name Pin Description
A1 RLS+ Right Loudspeaker Positive Output
A2 VDD Power Supply
A3 SDA Data
A4 RHP3D Right Headphone 3D
A5 RHP Right Headphone Output
B1 GND Ground
B2 I2CVDD I2C Interface Power Supply
B3 ADR I2C Address Select
B4 LHP3D Left Headphone 3D
B5 VDD Power Supply
C1 RLS- Right Loudspeaker Negative Output
C2 NC No Connect
C3 SCL Clock
C4 LINEOUT Mono Line Output
C5 GND Ground
D1 LLS- Left Loudspeaker Negative Output
D2 VDD Power Supply
D3 MIN Mono Input
D4 NC No Connect
D5 EP+ Mono Earpiece Positive Output
E1 GND Ground
E2 BYPASS Half-supply bypass
E3 LLS3D Left Loudspeaker 3D
E4 RIN Right Stereo Input
E5 EP- Mono Earpiece Negative Output
F1 LLS+ Left Loudspeaker Positive Output
F2 VDD Power Supply
F3 RLS3D Right Loudspeaker 3D
F4 LIN Left Stereo Input
F5 LHP Left Headphone Output
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: LM4857
28
LHP3D
27
RHP3D
26
SCL
25
ADR
24
SDA
23
I2CVDD
22
VDD
8
RIN
9
LIN
10
MIN
11
LLS3D
12
RLS3D
13
BYPASS
14
VDD
15 LLS+
16 GND
17 LLS-
18 VDD
19 RLS-
20 GND
21 RLS+
RHP 1
VDD 2
LINEOUT 3
GND 4
EP- 5
EP+ 6
LHP 7
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Connection Diagram
Figure 3. 28 – UQFN Package, Top View
See Package Number NJD0028A
PIN CONNECTION (UQFN)
Pin Name Pin Description
1 RHP Right Headphone Output
2 VDD Power Supply
3 LINEOUT Mono Line Output
4 GND Ground
5 EP- Mono Earpiece Negative Output
6 EP+ Mono Earpiece Positive Output
7 LHP Left Headphone Output
8 RIN Right Stereo Input
9 LIN Left Stereo Input
10 MIN Mono Input
11 LLS3D Left Loudspeaker 3D
12 RLS3D Right Loudspeaker 3D
13 BYPASS Half-supply bypass
14 VDD Power Supply
15 LLS+ Left Loudspeaker Positive Output
16 GND Ground
17 LLS- Leftt Loudspeaker Negative Output
18 VDD Power Supply
19 RLS- Right Loudspeaker Negative Output
20 GND Ground
21 RLS+ Right Loudspeaker Positive Output
22 VDD Power Supply
23 I2CVDD I2C Interface Power Supply
24 SDA Data
25 ADR I2C Address Select
26 SCL Clock
27 RHP3D Right Headphone 3D
28 LHP3D Left Headphone 3D
4Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)(3)
Supply Voltage 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation(4) Internally Limited
ESD Susceptibility(5) 2000V
ESD Susceptibility(6) 200V
Junction Temperature (TJ) 150°C
θJA (YZR0030)(7) 62°C/W
Thermal Resistance θJA (NJD0028A)(8) 42°C/W
θJC (NJD0028A) 3°C/W
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4857 operating in Mode 3, 8, or 13 with VDD = 5V, 8Ωstereo loudspeakers and 32Ωstereo headphones,
the total power dissipation is 1.348W. θJA = 62°C/W.
(5) Human body model, 100pF discharged through a 1.5kΩresistor.
(6) Machine Model, 220pF - 240pF discharged through all pins.
(7) The given θJA is for an LM4857ITL mounted on a PCB with a 2in2area of 1oz printed circuit board copper ground plane.
(8) The given θJA is for an LM4857SP mounted on a PCB with a 2in2area of 1oz printed circuit board ground plane.
Operating Ratings
Temperature Range
TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C
Supply Voltage 2.7V ≤VDD ≤5.5V
2.5V ≤I2CVDD ≤5.5V
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Audio Amplifier Electrical Characteristics VDD = 5.0V(1)(2)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA= 25°C.
Symbol Parameter Conditions LM4857 Units
(Limits)
Typical(3) Limits(4)(5)
VIN = 0V, No load;
LD5 = RD5 = 0(6)
Mode 1, 6, 11 6 9.5 mA (max)
IDD Supply Current Mode 4, 5, 9, 10, 14, 15 5 8 mA (max)
Mode 2, 3, 7, 8, 12, 13 13 21 mA (max)
ISD Shutdown Current Output mode 0(6) 0.2 3 µA (max)
LM4857SP
Speaker; THD+N = 1%; 1.6 W
f = 1kHz; 4ΩBTL
Speaker; THD+N = 1%; 1.2 0.9 W (min)
f = 1kHz; 8ΩBTL
POOutput Power Headphone; THD+N = 1%; 75 60 mW (min)
f = 1kHz; 32ΩSE
Earpiece; THD+N = 1%; 100 80 mW (min)
f = 1kHz; 32ΩBTL, CD4 = 0
Earpiece; THD+N = 1%; 135 mW
f = 1kHz; 32ΩBTL, CD4 = 1
LD5 = RD5 = 0
Speaker; PO= 400mW; 0.05 %
f = 1kHz; 8ΩBTL
Headphone; PO= 15mW;
Total Harmonic Distortion Plus 0.04 %
THD+N f = 1kHz; 32ΩSE
Noise Earpiece; PO= 15mW; 0.05 %
f = 1kHz; 32ΩBTL, CD4 = 0
Line Out, VO= 1VRMS;0.009 %
f = 1kHz; 5kΩSE
Speaker; LD5 = RD5 = 0 5 40 mV (max)
VOS Offset Voltage Earpiece; LD5 = RD5 = 0 5 30 mV (max)
A-weighted, 0dB gain;(7)
LD5 = RD5 = 0; Audio Inputs Terminated
Speaker; Mode 2, 3, 7, 8 27 µV
Speaker; Mode 12, 13 38 µV
Headphone; Mode 3, 4, 8, 9 10 µV
Headphone; Mode 13, 14 14 µV
NOUT Output Noise Earpiece; Mode 1; CD4 = 0 13 µV
Earpiece; Mode 6 18 µV
Earpiece; Mode 11 21 µV
Line Out; Mode 5 11 µV
Line Out; Mode 10 14 µV
Line Out; Mode 15 17 µV
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at +25°C and represent the parametric norm.
(4) Limits are ensured to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
(6) Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD.
(7) “0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
6Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Audio Amplifier Electrical Characteristics VDD = 5.0V(1)(2) (continued)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA= 25°C.
Symbol Parameter Conditions LM4857 Units
(Limits)
Typical(3) Limits(4)(5)
f = 217Hz; Vrip = 200mVpp; CB= 2.2µF;
0dB gain;(7)
LD5 = RD5 = 0; Audio Inputs Terminated
Speaker; Mode 2, 3, 7, 8 70 dB
Speaker; Mode 12, 13, 64 54 dB (min)
Headphone; Mode 3, 4, 8, 9 86 dB
Headphone; Mode 13, 14 73 60 dB (min)
PSRR Power Supply Rejection Ratio Earpiece; Mode1 75 dB
Earpiece; Mode 6 70 dB
Earpiece; Mode 11 66 57 dB (min)
Line Out; Mode 5 86 dB
Line Out; Mode 10 74 dB
Line Out; Mode 15 68 57 dB (min)
LD5 = RD5 = 0
Loudspeaker; PO= 400mW; 85 dB
Xtalk Crosstalk f = 1kHz
Headphone; PO= 15mW; 85 dB
f = 1kHz
CD5 = 0; CB= 2.2µF 120 ms
TWU Wake-up Time CD5 = 1; CB= 2.2µF 230 ms
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Audio Amplifier Electrical Characteristics VDD = 3.0V(1)(2)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA= 25°C.
Symbol Parameter Conditions LM4857 Units
(Limits)
Typical(3) Limits(4)(5)
VIN = 0V, No load;
LD5 = RD5 = 0(6)
Mode 1, 6, 11 5.5 9 mA (max)
IDD Supply Current Mode 4, 5, 9, 10, 14, 15 4.5 7.5 mA (max)
Mode 2, 3, 7, 8, 12, 13 11.2 19 mA (max)
ISD Shutdown Current Mode 0(6) 0.06 2.5 µA (max)
LM4857SP
POOutput Power Speaker; THD+N = 1%; 530 mW
f = 1kHz; 4ΩBTL
Speaker; THD+N = 1%; 400 320 mW (min)
f = 1kHz; 8ΩBTL
Headphone; THD+N = 1%; 25 20 mW (min)
f = 1kHz; 32ΩSE
POOutput Power Earpiece; THD+N = 1%; 30 22 mW (min)
f = 1kHz; 32ΩBTL; CD4 = 0
Earpiece; THD+N = 1%; 30 mW
f = 1kHz; 32ΩBTL; CD4 = 1
LD5 = RD5 = 0
Speaker; PO= 200mW; 0.05 %
f = 1kHz; 8ΩBTL
Headphone; PO= 10mW;
Total Harmonic Distortion Plus 0.04 %
THD+N f = 1kHz; 32ΩSE
Noise Earpiece; PO=10mW; 0.06 %
f = 1kHz; 32ΩBTL; CD4 = 0
Line Out; VO= 1VRMS;0.015 %
f = 1kHz; 5kΩSE
Speaker; LD5 = RD5 = 0 5 40 mV (max)
VOS Offset Voltage Earpiece; LD5 = RD5 = 0 5 30 mV (max)
A-weighted; 0dB gain;(7)
LD5 = RD5 = 0; All Inputs Terminated
Speaker; Mode 2, 3, 7, 8 27 µV
Speaker; Mode 12, 13 38 µV
Headphone; Mode 3, 4, 8, 9 10 µV
Headphone; Mode 13, 14 14 µV
NOUT Output Noise Earpiece; Mode 1 13 µV
Earpiece; Mode 6 18 µV
Earpiece; Mode 11 21 µV
Line Out; Mode 5 11 µV
Line Out; Mode 10 14 µV
Line Out; Mode 15 17 µV
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at +25°C and represent the parametric norm.
(4) Limits are ensured to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
(6) Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD.
(7) “0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
8Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Audio Amplifier Electrical Characteristics VDD = 3.0V(1)(2) (continued)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA= 25°C.
Symbol Parameter Conditions LM4857 Units
(Limits)
Typical(3) Limits(4)(5)
f = 217Hz, Vrip = 200mVpp; CB= 2.2µF;
0dB gain;(8)
LD5 = RD5 = 0; All Audio Inputs Terminated
Speaker; Mode 2, 3, 7, 8 70 dB
Speaker; Mode 12, 13, 65 55 dB (min)
Headphone; Mode 3, 4, 8, 9 87 dB
Headphone; Mode 13, 14 75 62 dB (min)
PSRR Power Supply Rejection Ratio Earpiece; Mode1 76 dB
Earpiece; Mode 6 70 dB
Earpiece; Mode 11 67 57 dB (min)
Line Out; Mode 5 88 dB
Line Out; Mode 10 74 dB
Line Out; Mode 15 71 58 dB (min)
LD5 = RD5 = 0
Loudspeaker; PO= 200mW; 82 dB
Xtalk Crosstalk f = 1kHz
Headphone; PO= 10mW; 82 dB
f = 1kHz
CD5 = 0; CB= 2.2µF 80 ms
TWU Wake-up Time CD5 = 1; CB= 2.2µF 140 ms
(8) “0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Volume Control Electrical Characteristics(1)(2)
The following specifications apply for VDD = 5.0V and VDD = 3.0V, unless otherwise specified. Limits apply for TA= 25°C.
Symbol Parameter Conditions LM4857 Units
(Limits)
Typical(3) Limits(4)(5)
maximum gain setting 6 5.5 dB (min)
6.5 dB (max)
Stereo Volume Control Range minimum gain setting -40.5 -41 dB (min)
-40 dB (max)
maximum gain setting 12 11.5 dB (min)
12.5 dB (max)
Mono Volume Control Range minimum gain setting -34.5 -35 dB (min)
-34 dB (max)
Volume Control Step Size 1.5 dB
Volume Control Step Size Error +/-0.2 +/-0.5 dB (max)
Stereo Channel to Channel Gain 0.3 dB
Mismatch Mode 12, Vin = 1VRMS
Mute Attenuation Headphone 85 dB
Line Out 85 dB
maximum gain setting 33.5 25 kΩ(min)
42 kΩ(max)
LIN and RIN Input Impedance minimum gain setting 100 75 kΩ(min)
125 kΩ(max)
MIN Input Impedance maximum gain setting 20 15 kΩ(min)
25 kΩ(max)
minimum gain setting 98 73 kΩ(min)
123 kΩ(max)
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at +25°C and represent the parametric norm.
(4) Limits are ensured to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
10 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Control Interface Electrical Characteristics(1)(2)
The following specifications apply for VDD = 5V and VDD = 3V and 2.5V ≤I2CVDD ≤5.5V, unless otherwise specified. Limits
apply for TA= 25°C.
Symbol Parameter Conditions LM4857 Units
(Limits)
Typical(3) Limits(4)(5)
t1SCL period 2.5 µs (min)
t2SDA Set-up Time 100 ns (min)
t3SDA Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition time 100 ns (min)
VIH Digital Input High Voltage 0.7 x I2CVDD V (min)
VIL Digital Input Low Voltage 0.3 x I2CVDD V (max)
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at +25°C and represent the parametric norm.
(4) Limits are ensured to AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are ensured by design, test, or statistical analysis.
External Components Description
Components Functional Description
1. CIN This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier's input
terminals. CIN also creates a highpass filter with the internal resistor Ri(Input Impedance) at fc= 1/(2πRiCIN).
2. CSThis is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps reduce the noise at
the VDD pin.
3. CBThis is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4857's PSRR.
4. COUT This is the output coupling capacitor. It blocks the DC voltage and couples the output signal to the speaker load RL.
COUT also creates a high pass filter with RLat fO= 1/(2πRLCOUT).
5. R3D This resistor sets the gain of the TI 3D effect. Please refer to the TI 3D ENHANCEMENT section for information on
selecting the value of R3D.
6. C3D This capacitor sets the frequency at which the TI 3D effect starts to occur. Please refer to the TI 3D
ENHANCEMENT section for information on selecting the value of C3D.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM4857
10m 100m
OUTPUT POWER (W)
120m 200m 250m 500m
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
10m 100m
OUTPUT POWER (W)
120m 200m 250m 500m
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
20 100 1k 20k
FREQUENCY (Hz)
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
10k
20 100 1k 20k
FREQUENCY (Hz)
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
10k
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (1)
LM4857SP THD+N LM4857SP THD+N
vs vs
Frequency Frequency
Figure 4. VDD = 5V; LLS, RLS; PO= 400mW; Figure 5. VDD = 3V; LLS, RLS; PO= 200mW;
RL= 4Ω; Mode 7; 0dB Gain RL= 4Ω; Mode 7; 0dB Gain
LM4857SP THD+N LM4857SP THD+N
vs vs
Output Power Output Power
Figure 6. VDD = 5V; LLS, RLS; f = 1kHz; Figure 7. VDD = 3V; LLS, RLS; f = 1kHz;
RL= 4Ω; Mode 7; 0dB Gain RL= 4Ω; Mode 7; 0dB Gain
THD+N THD+N
vs vs
Frequency Frequency
Figure 8. VDD = 5V; LLS, RLS; PO= 400mW; Figure 9. VDD = 3V; LLS, RLS; PO= 200mW;
RL= 8Ω; Mode 7; 0dB Gain RL= 8Ω; Mode 7; 0dB Gain
(1) “0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
12 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Typical Performance Characteristics (1) (continued)
THD+N THD+N
vs vs
Frequency Frequency
Figure 10. VDD = 5V; LHP, RHP; PO= 15mW; Figure 11. VDD = 3V; LHP, RHP; PO= 10mW;
RL= 32Ω; Mode 9; 0dB Gain RL= 32Ω; Mode 9; 0dB Gain
THD+N THD+N
vs vs
Frequency Frequency
Figure 12. VDD = 5V; EP; PO= 15mW; Figure 13. VDD = 3V; EP; PO= 10mW;
RL= 32Ω; Mode 1; 0dB Gain, CD4 = 0 RL= 32Ω; Mode 1; 0dB Gain, CD4 = 0
THD+N THD+N
vs vs
Frequency Frequency
Figure 14. VDD = 5V; LINEOUT; VO= 1VRMS; Figure 15. VDD = 3V; LINEOUT; VO= 1VRMS;
RL= 5kΩ; Mode 5; 0dB Gain RL= 5kΩ; Mode 5; 0dB Gain
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
THD+N THD+N
vs vs
Frequency Frequency
Figure 16. VDD = 5V; LINEOUT; VO= 1VRMS; Figure 17. VDD = 3V; LINEOUT; VO= 1VRMS;
RL= 5kΩ; Mode 10; 0dB Gain RL= 5kΩ; Mode 10; 0dB Gain
THD+N THD+N
vs vs
Output Power Output Power
Figure 18. VDD = 5V; LLS, RLS; f = 1kHz; Figure 19. VDD = 3V; LLS, RLS; f = 1kHz;
RL= 8Ω; Mode 7; 0dB Gain RL= 8Ω; Mode 7; 0dB Gain
THD+N THD+N
vs vs
Output Power Output Power
Figure 20. VDD = 5V; LHP, RHP; f = 1kHz; Figure 21. VDD = 3V; LHP, RHP; f = 1kHz;
RL= 32Ω; Mode 9; 0dB Gain RL= 32Ω; Mode 9; 0dB Gain
14 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Typical Performance Characteristics (1) (continued)
THD+N THD+N
vs vs
Output Power Output Power
Figure 22. VDD = 5V; EP; f = 1kHz; RL= 32Ω; Figure 23. VDD = 3V; EP; f = 1kHz;
Mode 1; 0dB Gain; Top-CD4 = 1; Bot-CD4 = 0 RL= 32Ω; Mode 1; 0dB Gain
PSRR PSRR
vs vs
Frequency Frequency
Figure 24. VDD = 5V; LLS, RLS; RL= 8Ω; 0db Gain; Figure 25. VDD = 3V; LLS, RLS; RL= 8Ω; 0db Gain;
All audio inputs terminated All audio inputs terminated
Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8 Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8
PSRR PSRR
vs vs
Frequency Frequency
Figure 26. VDD = 5V; LHP, RHP; RL= 32Ω; 0db Gain; Figure 27. VDD = 3V; LHP, RHP; RL= 32Ω; 0db Gain;
All audio inputs terminated All audio inputs terminated
Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9 Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
PSRR PSRR
vs vs
Frequency Frequency
Figure 28. VDD = 5V; EP; RL= 32Ω; 0db Gain; Figure 29. VDD = 3V; EP; RL= 32Ω; 0db Gain;
All audio inputs terminated All audio inputs terminated
Top-Mode 11; Mid-Mode 6; Bot-Mode 1 Top-Mode 11; Mid-Mode 6; Bot-Mode 1
PSRR PSRR
vs vs
Frequency Frequency
Figure 30. VDD = 5V; LINEOUT; RL= 5kΩ; 0db Gain; Figure 31. VDD = 3V; LINEOUT; RL= 5kΩ; 0db Gain;
All audio inputs terminated All audio inputs terminated
Top-Mode 15; Mid-Mode 10; Bot-Mode 5 Top-Mode 15; Mid-Mode 10; Bot-Mode 5
Crosstalk Crosstalk
vs vs
Frequency Frequency
Figure 32. VDD = 5V; LLS, RLS; PO= 400mW; RL= 8Ω; Figure 33. VDD = 3V; LLS, RLS; PO= 200mW; RL= 8Ω;
Mode 7; 0db Gain; 3D off Mode 7; 0db Gain; 3D off
Top-Left to Right; Bot- Right to Left Top-Left to Right; Bot- Right to Left
16 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
20 20k
FREQUENCY (Hz)
50 100 200 500 10k1k 2k 5k
+6
+7
+8
+9
+10
+11
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
GAIN (dB)
20 20k
FREQUENCY (Hz)
50 10
020
050
010k1k 2k 5k
+6
+14
GAIN (dB)
+6.
5
+7
+7.
5
+8
+8.
5
+9
+9.
5
+10
+10.5
+11
+11.5
+12
+12.5
+13
+13.5
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Typical Performance Characteristics (1) (continued)
Crosstalk Crosstalk
vs vs
Frequency Frequency
Figure 34. VDD = 5V; LHP, RHP; PO= 15mW; RL= 32Ω; Figure 35. VDD = 3V; LHP, RHP; PO= 10mW; RL= 32Ω;
Mode 9; 0db Gain; 3D off Mode 9; 0db Gain; 3D off
Top-Left to Right; Bot- Right to Left Top-Left to Right; Bot- Right to Left
Frequency Frequency
vs vs
Response Response
Figure 36. LLS, RLS; RL= 8Ω; Figure 37. LLS, RLS; RL= 8Ω;
Mode 2; Full Gain Mode 7; Full Gain
Frequency Frequency
vs vs
Response Response
Figure 38. LHP, RHP; RL= 32Ω; CO= 100μF Figure 39. LHP, RHP; RL= 32Ω; CO= 100μF
Mode 4; Full Gain Mode 9; Full Gain
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
Frequency Frequency
vs vs
Response Response
Figure 40. EP; RL= 32Ω; Mode 1; Full Gain Figure 41. LINEOUT; RL= 5kΩ; CO= 2.2μF
Top-CD4 = 1; Bot-CD4 = 0 Mode 5; Full Gain
Frequency Power Dissipation
vs vs
Response Output Power
Figure 42. LINEOUT; RL= 5kΩ; CO= 2.2μF Figure 43. LLS, RLS; RL= 8Ω; THD+N ≤1%
Mode 10; Full Gain Top-VDD = 5V; Bot-VDD = 3V
per channel
Power Dissipation Power Dissipation
vs vs
Output Power Output Power
Figure 44. LHP, RHP; RL= 32Ω; THD+N ≤1% Figure 45. EP; RL= 32Ω; THD+N ≤1%
Top-VDD = 5V; Bot-VDD = 3V Top-VDD = 5V; Bot-VDD = 3V
per channel
18 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Typical Performance Characteristics (1) (continued)
Output Power Output Power
vs vs
Load Resistance Load Resistance
Figure 46. LLS, RLS; RL= 8Ω; Figure 47. LHP, RHP; RL= 32Ω;
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
Output Power Output Power
vs vs
Load Resistance Load Resistance
Figure 48. EP; RL= 32Ω; CD4 = 0 Figure 49. EP; RL= 32Ω; CD4 = 1
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N;
Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N
Output Power Output Power
vs vs
Supply Voltage Supply Voltage
Figure 50. LLS, RLS; RL= 8Ω; Figure 51. LHP, RHP; RL= 32Ω;
Top–10% THD+N; Bot–1% THD+N Top–10% THD+N; Bot–1% THD+N
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (1) (continued)
Output Power
vs
Supply Voltage
Figure 52. EP; RL= 32Ω;
Top–10% THD+N; CD4 = 1; Topmid–1% THD+N, CD4 = 1
Botmid–10% THD+N; CD4 = 0; Bot–1% THD+N, CD4 = 0
20 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
APPLICATION INFORMATION
Figure 53. I2C Bus Format
Figure 54. I2C Timing Diagram
Table 1. Chip Address
A7 A6 A5 A4 A3 A2 A1 A0
Chip Address 1 1 1 1 1 0 EC 0
ADR=011111000
ADR=111111010
Table 2. Control Registers
D7 D6 D5 D4 D3 D2 D1 D0
Mono Volume control 0 0 0 MD4 MD3 MD2 MD1 MD0
Left Volume control 0 1 LD5 LD4 LD3 LD2 LD1 LD0
Right Volume control 1 0 RD5 RD4 RD3 RD2 RD1 RD0
Mode control 1 1 CD5 CD4 CD3 CD2 CD1 CD0
Table 3. Mono Volume Control
MD4 MD3 MD2 MD1 MD0 Gain (dB)
0 0 0 0 0 -34.5
0 0 0 0 1 -33.0
0 0 0 1 0 -31.5
0 0 0 1 1 -30.0
0 0 1 0 0 -28.5
0 0 1 0 1 -27.0
0 0 1 1 0 -25.5
0 0 1 1 1 -24.0
0 1 0 0 0 -22.5
0 1 0 0 1 -21.0
0 1 0 1 0 -19.5
0 1 0 1 1 -18.0
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Table 3. Mono Volume Control (continued)
MD4 MD3 MD2 MD1 MD0 Gain (dB)
0 1 1 0 0 -16.5
0 1 1 0 1 -15.0
0 1 1 1 0 -13.5
0 1 1 1 1 -12.0
1 0 0 0 0 -10.5
1 0 0 0 1 -9.0
1 0 0 1 0 -7.5
1 0 0 1 1 -6.0
1 0 1 0 0 -4.5
1 0 1 0 1 -3.0
1 0 1 1 0 -1.5
1 0 1 1 1 0.0
1 1 0 0 0 1.5
1 1 0 0 1 3.0
1 1 0 1 0 4.5
1 1 0 1 1 6.0
1 1 1 0 0 7.5
1 1 1 0 1 9.0
1 1 1 1 0 10.5
1 1 1 1 1 12.0
Table 4. Stereo Volume Control
LD4//RD4 LD3//RD3 LD2//RD2 LD1//RD1 LD0//RD0 Gain (dB)
0 0 0 0 0 -40.5
0 0 0 0 1 -39.0
0 0 0 1 0 -37.5
0 0 0 1 1 -36.0
0 0 1 0 0 -34.5
0 0 1 0 1 -33.0
0 0 1 1 0 -31.5
0 0 1 1 1 -30.0
0 1 0 0 0 -28.5
0 1 0 0 1 -27.0
0 1 0 1 0 -25.5
0 1 0 1 1 -24.0
0 1 1 0 0 -22.5
0 1 1 0 1 -21.0
0 1 1 1 0 -19.5
0 1 1 1 1 -18.0
1 0 0 0 0 -16.5
1 0 0 0 1 -15.0
1 0 0 1 0 -13.5
1 0 0 1 1 -12.0
1 0 1 0 0 -10.5
1 0 1 0 1 -9.0
1 0 1 1 0 -7.5
1 0 1 1 1 -6.0
22 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
Table 4. Stereo Volume Control (continued)
LD4//RD4 LD3//RD3 LD2//RD2 LD1//RD1 LD0//RD0 Gain (dB)
1 1 0 0 0 -4.5
1 1 0 0 1 -3.0
1 1 0 1 0 -1.5
1 1 0 1 1 0.0
1 1 1 0 0 1.5
1 1 1 0 1 3.0
1 1 1 1 0 4.5
1 1 1 1 1 6.0
Table 5. Mixer and Output Mode Control
Mode CD3 CD2 CD1 CD Mono Mono Earpiece Loudspeaker Loudspeaker Headphone Headphone
0 Line Out L R L R
(CD4 = 0) (CD4 =
1)
0 0 0 0 0 SD SD SD SD SD SD SD
1 0 0 0 1 MUTE (GMx M) 2(GMx SD SD MUTE MUTE
M)
2 0 0 1 0 MUTE SD SD 2(GMx M) 2(GMx M) MUTE MUTE
3 0 0 1 1 MUTE SD SD 2(GMx M) 2(GMx M) (GMx M) (GMx M)
4 0 1 0 0 MUTE SD SD SD SD (GMx M) (GMx M)
5 0 1 0 1 (GMx M) SD SD SD SD MUTE MUTE
6 0 1 1 0 MUTE (GLx L) + 2(GLx L) SD SD MUTE MUTE
(GRx R) + 2(GRx
R)
7 0 1 1 1 MUTE SD SD 2(GLx L) 2(GRx R) MUTE MUTE
8 1 0 0 0 MUTE SD SD 2(GLx L) 2(GRx R) (GLx L) (GRx R)
9 1 0 0 1 MUTE SD SD SD SD (GLx L) (GRx R)
10 1 0 1 0 (GLx L) + SD SD SD SD MUTE MUTE
(GRx R)
11 1 0 1 1 MUTE (GMx M) + 2(GMx SD SD MUTE MUTE
(GLx L) + M) +
(GRx R) 2(GLx L)
+2(GRx
R)
12 1 1 0 0 MUTE SD SD 2(GLx L) + 2(GRx R) + MUTE MUTE
2(GMx M) 2(GMx M)
13 1 1 0 1 MUTE SD SD 2(GLx L) + 2(GRx R) + (GLx L) + (GM(GRx R) +
2(GMx M) 2(GMx M) x M) (GMx M)
14 1 1 1 0 MUTE SD SD SD SD (GLx L) + (GM(GRx R) +
x M) (GMx M)
15 1 1 1 1 (GMx M) SD SD SD SD MUTE MUTE
+(GLx L)
+(GRx R)
Table 6. TI 3D Enhancement
0 Loudspeaker TI 3D Off
LD5 1 Loudspeaker TI 3D On
0 Headphone TI 3D Off
RD5 1 Headphone TI 3D On
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Table 7. Wake-up Time Select
0 Fast Wake-up Setting
CD5 1 Slow Wake-up Setting
Table 8. Earpiece Amplifier Gain Select
0 0dB Earpiece Output Stage Gain Setting
CD4 1 6dB Earpiece Output Stage Gain Setting
I2C COMPATIBLE INTERFACE
The LM4857 uses a serial bus, which conforms to the I2C protocol, to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4857.
The I2C address for the LM4857 is determined using the ADR pin. The LM4857's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1= 0, if ADR is logic low; and X1= 1, if ADR is logic high.
If the I2C interface is used to address a number of chips in a system, the LM4857's chip address can be changed
to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 53. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4857 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM4857.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM4857 received the
data.
If the master has more data bytes to send to the LM4857, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4857's I2C interface is powered up through the I2CVDD pin. The LM4857's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
TI 3D ENHANCEMENT
The LM4857 features a 3D audio enhancement effect that widens the perceived soundstage from a stereo audio
signal. The 3D audio enhancement improves the apparent stereo channel separation whenever the left and right
speakers are too close to one another, due to system size constraints or equipment limitations.
An external RC network, shown in Figure 1, is required to enable the 3D effect. There are separate RC networks
for both the stereo loudspeaker outputs as well as the stereo headphone outputs, so the 3D effect can be set
independently for each set of stereo outputs.
24 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
The amount of the 3D effect is set by the R3D resistor. Decreasing the value of R3D will increase the 3D effect.
The C3D capacitor sets the low cutoff frequency of the 3D effect. Increasing the value of C3D will decrease the
low cutoff frequency at which the 3D effect starts to occur, as shown by Equation 1.
f3D(-3dB) = 1 / 2π(R3D)(C3D) (1)
Activating the 3D effect will cause an increase in gain by a multiplication factor of (1 + 9kΩ/R3D). Setting R3D to
9kΩwill result in a gain increase by a multiplication factor of (1+ 9kΩ/9kΩ) = 2 or 6dB whenever the 3D effect is
activated. The volume control can be programmed through the I2C compatible interface to compensate for the
extra 6dB increase in gain. For example, if the stereo volume control is set at 0dB (11011 from Table 4) before
the 3D effect is activated, the volume control should be programmed to –6dB (10111 from Table 4) immediately
after the 3D effect has been activated. Setting R3D = 20kΩand C3D = 0.22μF allows the LM4857 to produce a
pronounced 3D effect with a minimal increase in output noise.
EXPOSED-DAP MOUNTING CONSIDERATIONS
The LM4857's exposed-DAP (die attach paddle) package (UQFN) provides a low thermal resistance between the
die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a
low voltage audio power amplifier that produces 1.6W dissipation in a 4Ωload at ≤1% THD+N and over 1.8W in
a 3Ωload at 10% THD+N. This high power is achieved through careful consideration of necessary thermal
design. Failing to optimize thermal design may compromise the LM4857's high power performance and activate
unwanted, though necessary, thermal shutdown protection.
The UQFN package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is
then, ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat
sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-layer
PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance,
however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with
9 (3 X 3) (UQFN) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient
thermal conductivity by plugging and tenting the vias with plating and solder mask, respectively.
Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and
amplifier share the same PCB layer, a nominal 2in2area is necessary for 5V operation with a 4Ωload. Heatsink
areas not placed on the same PCB layer as the LM4857 should be 4in2for the same supply voltage and load
resistance. The last two area recommendations apply for 25°C ambient temperature. Increase the area to
compensate for ambient temperatures above 25°C. In all circumstances and under all conditions, the junction
temperature must be held below 150°C to prevent activating the LM4857's thermal shutdown protection. An
example PCB layout for the exposed-DAP UQFN package is shown in the Demonstration Board Layout
section. Information on the UQFN style package is provided in the AN-1187 Application Report (literature number
SNOA401).
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3ΩAND 4Ω
LOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1Ω
trace resistance reduces the output power dissipated by a 4Ωload from 1.6W to 1.5W. The problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
BRIDGE CONFIGURATION EXPLANATION
The LM4857 consists of three sets of a bridged-tied amplifier pairs that drive the left loudspeaker (LLS), the right
loudspeaker (RLS), and the mono earpiece (EP). For this discussion, only the LLS bridge-tied amplifier pair will
be referred to. The LM4857 drives a load, such as a speaker, connected between outputs, LLS+ and LLS-. In the
LLS amplifier block, the output of the amplifier that drives LLS- serves as the input to the unity gain inverting
amplifier that drives LLS+.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between LLS- and LLS+ and driven differentially (commonly referred to
as 'bridge mode'). This results in a differential or BTL gain of:
AVD = 2(Rf/ Ri) = 2 (2)
Both the feedback resistor, Rf, and the input resistor, Ri, are internally set.
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the single-
ended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing LLS- and LLS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, single-
ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a
single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation
and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM4857 has 3 sets of bridged-tied amplifier pairs driving LLS, RLS, and EP. The maximum
internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation 3
and Equation 4, assuming a 5V power supply and an 8Ωload, the maximum power dissipation for LLS and RLS
is 634mW per channel. From Equation 5, assuming a 5V power supply and a 32Ωload, the maximum power
dissipation for EP is 158mW.
PDMAX-LLS = 4(VDD)2/(2π2RL): Bridged (3)
PDMAX-RLS = 4(VDD)2/(2π2RL): Bridged (4)
PDMAX-EP = 4(VDD)2/(2π2RL): Bridged (5)
The LM4857 also has 3 sets of single-ended amplifiers driving LHP, RHP, and LINEOUT. The maximum internal
power dissipation for ROUT and LOUT is given by Equation 6 and Equation 7. From Equation 6 and Equation 7,
assuming a 5V power supply and a 32Ωload, the maximum power dissipation for LOUT and ROUT is 40mW per
channel. From Equation 8, assuming a 5V power supply and a 5kΩload, the maximum power dissipation for
LINEOUT is negligible.
PDMAX-LHP = (VDD)2/ (2π2RL): Single-ended (6)
PDMAX-RHP = (VDD)2/ (2π2RL): Single-ended (7)
26 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
www.ti.com
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
PDMAX-LINE = (VDD)2/ (2π2RL): Single-ended (8)
The maximum internal power dissipation of the LM4857 occurs during output modes 3, 8, and 13 when both
loudspeaker and headphone amplifiers are simultaneously on; and is given by Equation 9.
PDMAX-TOTAL = PDMAX-LLS + PDMAX-RLS + PDMAX-LHP + PDMAX-RHP (9)
The maximum power dissipation point given by Equation 9 must not exceed the power dissipation given by
Equation 10:
PDMAX' = (TJMAX - TA) / θJA (10)
The LM4857's TJMAX = 150°C. In the DSBGA package, the LM4857's θJA is 62°C/W. At any given ambient
temperature TA, use Equation 10 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 10 and substituting PDMAX-TOTAL for PDMAX' results in Equation 11. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4857's
maximum junction temperature.
TA= TJMAX - PDMAX-TOTAL θJA (11)
For a typical application with a 5V power supply, stereo 8Ωloudspeaker load, and the stereo 32Ωheadphone
load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the
maximum junction temperature is approximately 66.4°C for the DSBGA package.
TJMAX = PDMAX-TOTAL θJA + TA(12)
Equation 12 gives the maximum junction temperature TJMAX. If the result violates the LM4857's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 9 is greater than that of Equation 10,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC,θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance.) Refer to the
Typical Performance Characteristics (1) curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4857's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4857's power supply pin and ground as short as possible.
(1) “0dB gain” refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB.
Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high value input coupling capacitor (Ciin Figure 1). In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 50Hz. Applications using speakers with this limited frequency response reap little
improvement; by using a large input capacitor.
The internal input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found
using Equation 13.
fc= 1 / (2πRiCi) (13)
As an example when using a speaker with a low frequency limit of 50Hz and Ri= 20kΩ, Ci, using Equation 13 is
0.19µF. The 0.22µF Cishown in Figure 55 allows the LM4857 to drive high efficiency, full range speaker whose
response extends below 40Hz.
Output Capacitor Value Selection
Amplifying the lowest audio frequencies also requires the use of a high value output coupling capacitor (COin
Figure 1). A high value output capacitor can be expensive and may compromise space efficiency in portable
design.
The speaker load (RL) and the output capacitor (CO) form a high pass filter with a low cutoff frequency
determined using Equation 14.
fc= 1 / (2πRLCO) (14)
When using a typical headphone load of RL= 32Ωwith a low frequency limit of 50Hz, COis 99µF.
The 100µF COshown in Figure 55 allows the LM4857 to drive a headphone whose frequency response extends
below 50Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CBdetermines how fast the LM4857 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4857's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CBequal to 2.2µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Cino larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 10 times the value of Ci. This ensures that output transients are eliminated
when the LM4857 transitions in and out of shutdown mode. Connecting a 2.2µF capacitor, CB, between the
BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The
PSRR improvements increase as the bypass pin capacitor value increases. However, increasing the value of CB
will increase wake-up time. The selection of bypass capacitor value, CB, depends on desired PSRR
requirements, click and pop performance, wake-up time, system cost, and size constraints.
28 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Demonstration Board DSBGA PCB Layout
Figure 56. Recommended DSBGA PCB Layout:
Top Silkscreen
Figure 57. Recommended DSBGA PCB Layout:
Top Layer
30 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Figure 60. Recommended DSBGA PCB Layout:
Bottom Layer
Demonstration Board UQFN PCB Layout
Figure 61. Recommended UQFN PCB Layout:
Top Over Layer
32 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
LM4857
SNAS229I –OCTOBER 2003–REVISED APRIL 2013
www.ti.com
Figure 64. Recommended UQFN PCB Layout:
Bottom Layer
Revision History
Rev Date Description
1.1 6/03/05 Changed the numerical value of 20 into 9 in the last
paragraph of "NATIONAL 3D ENHANCEMENT (per
Alvin F.), then re-released D/S to the WEB. (MC)
1.2 6/07/05 Deleted all references on GR pkg (GR pkgs on HOLD)
per Kevin Chen, then re-WEBd the D/S. (MC)
C 4/19/2013 Changed layout of National Data Sheet to TI format
34 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: LM4857
PACKAGE OPTION ADDENDUM
www.ti.com 26-Aug-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM4857SP/NOPB ACTIVE UQFN NJD 28 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L4857SP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4857SP/NOPB UQFN NJD 28 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Aug-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4857SP/NOPB UQFN NJD 28 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Aug-2013
Pack Materials-Page 2
MECHANICAL DATA
NJD0028A
www.ti.com
SPA28A (Rev A)
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
