LM4857 www.ti.com LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Stereo 1.2W Audio Sub-system with 3D Enhancement Check for Samples: LM4857 FEATURES KEY SPECIFICATIONS * * * * * 1 2 * * * * * * * * Stereo Speaker Amplifier Stereo Headphone Amplifier Mono Earpiece Amplifier Mono Line Output for External Handsfree Carkit Independent Left, Right, and Mono Volume Controls TI 3D Enhancement I2C Compatible Interface Ultra low Shutdown Current Click and Pop Suppression Circuit 16 distinct Output Modes Thermal Shutdown Protection Available in DSBGA and UQFN packages * * * * * * * POUT, Stereo Loudspeakers, 4, 5V, 1% THD+N (LM4857SP) 1.6W (typ) POUT, Stereo Loudspeakers, 8, 5V, 1% THD+N 1.2W (typ) POUT, Stereo Headphones, 32, 5V, 1% THD+N 75mW (typ) POUT, Mono Earpiece, 32, 5V, 1% THD+N 100mW (typ) POUT, Stereo Loudspeakers, 8, 3.3V, 1% THD+N 495mW (typ) POUT, Stereo Headphones, 32, 3.3V, 1% THD+N 33mW (typ) POUT, Mono Earpiece, 32, 3.3V, 1% THD+N 43mW (typ) Shutdown Current 0.06A (typ) APPLICATIONS DESCRIPTION * * * * * The LM4857 is an integrated audio sub-system designed for stereo cell phone applications. Operating on a 3.3V supply, it combines a stereo speaker amplifier delivering 495mW per channel into an 8 load, a stereo headphone amplifier delivering 33mW per channel into a 32 load, a mono earpiece amplifier delivering 43mW into a 32 load, and a line output for an external powered handsfree speaker. It integrates the audio amplifiers, volume control, mixer, power management control, and TI 3D enhancement all into a single package. In addition, the LM4857 routes and mixes the stereo and mono inputs into 16 distinct output modes. The LM4857 is controlled through an I2C compatible interface. Other features include an ultra-low current shutdown mode and thermal shutdown protection. Cell Phones PDAs Portable Gaming Devices Internet Appliances Portable DVD/CD/AAC/MP3 players Boomer audio power amplifiers are designed specifically to provide high quality output power with a minimal amount of external components. The LM4857 is available in a 30-bump DSBGA package and a 28-lead UQFN package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2013, Texas Instruments Incorporated LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Typical Application Figure 1. Typical Audio Amplifier Application Circuit 2 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Connection Diagram Figure 2. 30 Bump DSBGA Package - Top View (Bump-side down) See Package Number YZR0030 PIN CONNECTION (DSBGA) Pin Name Pin Description A1 RLS+ A2 VDD Power Supply A3 SDA Data A4 RHP3D Right Loudspeaker Positive Output Right Headphone 3D A5 RHP Right Headphone Output B1 GND Ground B2 I2CVDD B3 ADR I2C Address Select B4 LHP3D Left Headphone 3D B5 VDD Power Supply C1 RLS- Right Loudspeaker Negative Output C2 NC No Connect C3 SCL Clock C4 LINEOUT C5 GND Ground D1 LLS- Left Loudspeaker Negative Output D2 VDD Power Supply D3 MIN Mono Input D4 NC No Connect D5 EP+ Mono Earpiece Positive Output E1 GND Ground E2 BYPASS E3 LLS3D E4 RIN Right Stereo Input E5 EP- Mono Earpiece Negative Output F1 LLS+ Left Loudspeaker Positive Output F2 VDD F3 RLS3D F4 LIN F5 LHP I2C Interface Power Supply Mono Line Output Half-supply bypass Left Loudspeaker 3D Power Supply Right Loudspeaker 3D Left Stereo Input Left Headphone Output Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 3 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com ADR SDA 26 25 24 3 19 RLS- GND 4 18 VDD EP- 5 17 LLS- EP+ 6 16 GND LHP 7 15 14 LLS+ 9 10 11 12 13 VDD GND LINEOUT BYPASS 20 RLS3D 2 MIN RLS+ VDD LLS3D 22 21 LIN 1 RIN RHP 8 23 VDD SCL 27 2 RHP3D 28 I CVDD LHP3D Connection Diagram Figure 3. 28 - UQFN Package, Top View See Package Number NJD0028A PIN CONNECTION (UQFN) 4 Pin Name Pin Description 1 RHP Right Headphone Output 2 VDD Power Supply 3 LINEOUT 4 GND Ground 5 EP- Mono Earpiece Negative Output 6 EP+ Mono Earpiece Positive Output 7 LHP Left Headphone Output 8 RIN Right Stereo Input 9 LIN Left Stereo Input 10 MIN Mono Input Mono Line Output 11 LLS3D Left Loudspeaker 3D 12 RLS3D Right Loudspeaker 3D 13 BYPASS Half-supply bypass 14 VDD 15 LLS+ Power Supply Left Loudspeaker Positive Output 16 GND Ground 17 LLS- Leftt Loudspeaker Negative Output 18 VDD Power Supply 19 RLS- Right Loudspeaker Negative Output 20 GND Ground 21 RLS+ Right Loudspeaker Positive Output 22 VDD 23 I2CVDD Power Supply I2C Interface Power Supply 24 SDA Data 25 ADR I2C Address Select 26 SCL Clock 27 RHP3D Right Headphone 3D 28 LHP3D Left Headphone 3D Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage 6.0V -65C to +150C Storage Temperature -0.3V to VDD +0.3V Input Voltage (4) Internally Limited ESD Susceptibility (5) 2000V ESD Susceptibility (6) 200V Power Dissipation Junction Temperature (TJ) Thermal Resistance 150C JA (YZR0030) (7) 62C/W JA (NJD0028A) (8) 42C/W JC (NJD0028A) (1) (2) (3) (4) (5) (6) (7) (8) 3C/W All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication of device performance. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, JA, and the ambient temperature, TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / JA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM4857 operating in Mode 3, 8, or 13 with VDD = 5V, 8 stereo loudspeakers and 32 stereo headphones, the total power dissipation is 1.348W. JA = 62C/W. Human body model, 100pF discharged through a 1.5k resistor. Machine Model, 220pF - 240pF discharged through all pins. The given JA is for an LM4857ITL mounted on a PCB with a 2in2 area of 1oz printed circuit board copper ground plane. The given JA is for an LM4857SP mounted on a PCB with a 2in2 area of 1oz printed circuit board ground plane. Operating Ratings Temperature Range TMIN TA TMAX -40C TA +85C 2.7V VDD 5.5V Supply Voltage 2.5V I2CVDD 5.5V Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 5 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Audio Amplifier Electrical Characteristics VDD = 5.0V (1) (2) The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4857 Typical (3) Limits (4) (5) Units (Limits) VIN = 0V, No load; LD5 = RD5 = 0 (6) IDD Supply Current ISD Shutdown Current PO Output Power Mode 1, 6, 11 6 9.5 mA (max) Mode 4, 5, 9, 10, 14, 15 5 8 mA (max) Mode 2, 3, 7, 8, 12, 13 13 21 mA (max) Output mode 0 (6) 0.2 3 A (max) LM4857SP Speaker; THD+N = 1%; f = 1kHz; 4 BTL 1.6 Speaker; THD+N = 1%; f = 1kHz; 8 BTL 1.2 0.9 W (min) Headphone; THD+N = 1%; f = 1kHz; 32 SE 75 60 mW (min) Earpiece; THD+N = 1%; f = 1kHz; 32 BTL, CD4 = 0 100 80 mW (min) Earpiece; THD+N = 1%; f = 1kHz; 32 BTL, CD4 = 1 135 mW Speaker; PO= 400mW; f = 1kHz; 8 BTL 0.05 % Headphone; PO= 15mW; f = 1kHz; 32 SE 0.04 % Earpiece; PO= 15mW; f = 1kHz; 32 BTL, CD4 = 0 0.05 % Line Out, VO= 1VRMS; f = 1kHz; 5k SE 0.009 % W LD5 = RD5 = 0 THD+N VOS Total Harmonic Distortion Plus Noise Offset Voltage Speaker; LD5 = RD5 = 0 5 40 mV (max) Earpiece; LD5 = RD5 = 0 5 30 mV (max) (7) A-weighted, 0dB gain; LD5 = RD5 = 0; Audio Inputs Terminated NOUT (1) (2) (3) (4) (5) (6) (7) 6 Output Noise Speaker; Mode 2, 3, 7, 8 27 V Speaker; Mode 12, 13 38 V Headphone; Mode 3, 4, 8, 9 10 V Headphone; Mode 13, 14 14 V Earpiece; Mode 1; CD4 = 0 13 V Earpiece; Mode 6 18 V Earpiece; Mode 11 21 V Line Out; Mode 5 11 V Line Out; Mode 10 14 V Line Out; Mode 15 17 V All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at +25C and represent the parametric norm. Limits are ensured to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD. "0dB gain" refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Audio Amplifier Electrical Characteristics VDD = 5.0V(1)(2) (continued) The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4857 Typical (3) Limits (4) (5) Units (Limits) f = 217Hz; Vrip = 200mVpp; CB = 2.2F; 0dB gain; (7) LD5 = RD5 = 0; Audio Inputs Terminated PSRR Power Supply Rejection Ratio Speaker; Mode 2, 3, 7, 8 70 Speaker; Mode 12, 13, 64 Headphone; Mode 3, 4, 8, 9 86 Headphone; Mode 13, 14 73 Earpiece; Mode1 75 Earpiece; Mode 6 70 Earpiece; Mode 11 66 Line Out; Mode 5 86 Line Out; Mode 10 74 Line Out; Mode 15 68 dB 54 dB (min) dB 60 dB (min) dB dB 57 dB (min) dB dB 57 dB (min) LD5 = RD5 = 0 Xtalk TWU Crosstalk Wake-up Time Loudspeaker; PO= 400mW; f = 1kHz 85 dB Headphone; PO= 15mW; f = 1kHz 85 dB CD5 = 0; CB = 2.2F 120 ms CD5 = 1; CB = 2.2F 230 ms Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 7 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Audio Amplifier Electrical Characteristics VDD = 3.0V (1) (2) The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4857 Typical (3) Limits (4) (5) Units (Limits) VIN = 0V, No load; LD5 = RD5 = 0 (6) IDD Supply Current Mode 1, 6, 11 5.5 9 mA (max) Mode 4, 5, 9, 10, 14, 15 4.5 7.5 mA (max) Mode 2, 3, 7, 8, 12, 13 11.2 19 mA (max) 2.5 A (max) ISD Shutdown Current Mode 0 (6) 0.06 PO Output Power LM4857SP Speaker; THD+N = 1%; f = 1kHz; 4 BTL 530 Speaker; THD+N = 1%; f = 1kHz; 8 BTL 400 320 mW (min) Headphone; THD+N = 1%; f = 1kHz; 32 SE 25 20 mW (min) Earpiece; THD+N = 1%; f = 1kHz; 32 BTL; CD4 = 0 30 22 mW (min) Earpiece; THD+N = 1%; f = 1kHz; 32 BTL; CD4 = 1 30 mW Speaker; PO= 200mW; f = 1kHz; 8 BTL 0.05 % Headphone; PO= 10mW; f = 1kHz; 32 SE 0.04 % Earpiece; PO=10mW; f = 1kHz; 32 BTL; CD4 = 0 0.06 % Line Out; VO= 1VRMS; f = 1kHz; 5k SE 0.015 % PO Output Power mW LD5 = RD5 = 0 THD+N VOS Total Harmonic Distortion Plus Noise Offset Voltage Speaker; LD5 = RD5 = 0 5 40 mV (max) Earpiece; LD5 = RD5 = 0 5 30 mV (max) (7) A-weighted; 0dB gain; LD5 = RD5 = 0; All Inputs Terminated NOUT (1) (2) (3) (4) (5) (6) (7) 8 Output Noise Speaker; Mode 2, 3, 7, 8 27 V Speaker; Mode 12, 13 38 V Headphone; Mode 3, 4, 8, 9 10 V Headphone; Mode 13, 14 14 V Earpiece; Mode 1 13 V Earpiece; Mode 6 18 V Earpiece; Mode 11 21 V Line Out; Mode 5 11 V Line Out; Mode 10 14 V Line Out; Mode 15 17 V All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at +25C and represent the parametric norm. Limits are ensured to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Shutdown current and supply current are measured in a normal room environment. All digital input pins are connected to I2CVDD. "0dB gain" refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Audio Amplifier Electrical Characteristics VDD = 3.0V(1)(2) (continued) The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4857 Typical (3) Limits (4) (5) Units (Limits) f = 217Hz, Vrip = 200mVpp; CB = 2.2F; 0dB gain; (8) LD5 = RD5 = 0; All Audio Inputs Terminated PSRR Power Supply Rejection Ratio Speaker; Mode 2, 3, 7, 8 70 Speaker; Mode 12, 13, 65 Headphone; Mode 3, 4, 8, 9 87 Headphone; Mode 13, 14 75 Earpiece; Mode1 76 Earpiece; Mode 6 70 Earpiece; Mode 11 67 Line Out; Mode 5 88 Line Out; Mode 10 74 Line Out; Mode 15 71 dB 55 dB (min) dB 62 dB (min) dB dB 57 dB (min) dB dB 58 dB (min) LD5 = RD5 = 0 Xtalk TWU (8) Crosstalk Wake-up Time Loudspeaker; PO= 200mW; f = 1kHz 82 dB Headphone; PO= 10mW; f = 1kHz 82 dB CD5 = 0; CB = 2.2F 80 ms CD5 = 1; CB = 2.2F 140 ms "0dB gain" refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 9 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Volume Control Electrical Characteristics (1) (2) The following specifications apply for VDD = 5.0V and VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4857 Typical Stereo Volume Control Range Mono Volume Control Range (3) Limits (4) (5) Units (Limits) maximum gain setting 6 5.5 6.5 dB (min) dB (max) minimum gain setting -40.5 -41 -40 dB (min) dB (max) maximum gain setting 12 11.5 12.5 dB (min) dB (max) minimum gain setting -34.5 -35 -34 dB (min) dB (max) +/-0.5 dB (max) Volume Control Step Size 1.5 dB Volume Control Step Size Error +/-0.2 Stereo Channel to Channel Gain Mismatch 0.3 dB 85 dB Mode 12, Vin = 1VRMS Mute Attenuation Headphone Line Out LIN and RIN Input Impedance MIN Input Impedance (1) (2) (3) (4) (5) 10 85 dB maximum gain setting 33.5 25 42 k (min) k (max) minimum gain setting 100 75 125 k (min) k (max) maximum gain setting 20 15 25 k (min) k (max) minimum gain setting 98 73 123 k (min) k (max) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at +25C and represent the parametric norm. Limits are ensured to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Control Interface Electrical Characteristics (1) (2) The following specifications apply for VDD = 5V and VDD = 3V and 2.5V I2CVDD 5.5V, unless otherwise specified. Limits apply for TA = 25C. Symbol Parameter Conditions LM4857 Typical (3) Limits (4) (5) Units (Limits) t1 SCL period 2.5 s (min) t2 SDA Set-up Time 100 ns (min) t3 SDA Stable Time 0 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition time 100 ns (min) VIH Digital Input High Voltage 0.7 x I2CVDD V (min) VIL Digital Input Low Voltage 0.3 x I2CVDD V (max) (1) (2) (3) (4) (5) All voltages are measured with respect to the GND pin unless otherwise specified. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not specify specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not specified for parameters where no limit is given, however, the typical value is a good indication of device performance. Typicals are measured at +25C and represent the parametric norm. Limits are ensured to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are ensured by design, test, or statistical analysis. External Components Description Components Functional Description 1. CIN This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier's input terminals. CIN also creates a highpass filter with the internal resistor Ri (Input Impedance) at fc = 1/(2RiCIN). 2. CS This is the supply bypass capacitor. It filters the supply voltage applied to the VDD pin and helps reduce the noise at the VDD pin. 3. CB This is the BYPASS pin capacitor. It filters the VDD / 2 voltage and helps maintain the LM4857's PSRR. 4. COUT This is the output coupling capacitor. It blocks the DC voltage and couples the output signal to the speaker load RL. COUT also creates a high pass filter with RL at fO = 1/(2RLCOUT). 5. R3D This resistor sets the gain of the TI 3D effect. Please refer to the TI 3D ENHANCEMENT section for information on selecting the value of R3D. 6. C3D This capacitor sets the frequency at which the TI 3D effect starts to occur. Please refer to the TI 3D ENHANCEMENT section for information on selecting the value of C3D. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 11 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (1) LM4857SP THD+N vs Frequency LM4857SP THD+N vs Frequency 10 10 5 5 2 2 1 THD+N (%) THD+N (%) 1 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 20 100 1k 0.01 20 10k 20k 10k 20k Figure 4. VDD = 5V; LLS, RLS; PO = 400mW; RL = 4; Mode 7; 0dB Gain Figure 5. VDD = 3V; LLS, RLS; PO = 200mW; RL = 4; Mode 7; 0dB Gain LM4857SP THD+N vs Output Power LM4857SP THD+N vs Output Power 10 10 5 5 2 2 THD+N (%) THD+N (%) 1 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 10m 20m 50m 100m 200m 500m 1 0.01 10m 20m 2 OUTPUT POWER (W) 12 1k FREQUENCY (Hz) 1 (1) 100 FREQUENCY (Hz) 50m 100m 200m 500m 1 2 OUTPUT POWER (W) Figure 6. VDD = 5V; LLS, RLS; f = 1kHz; RL = 4; Mode 7; 0dB Gain Figure 7. VDD = 3V; LLS, RLS; f = 1kHz; RL = 4; Mode 7; 0dB Gain THD+N vs Frequency THD+N vs Frequency Figure 8. VDD = 5V; LLS, RLS; PO = 400mW; RL = 8; Mode 7; 0dB Gain Figure 9. VDD = 3V; LLS, RLS; PO = 200mW; RL = 8; Mode 7; 0dB Gain "0dB gain" refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Typical Performance Characteristics (1) (continued) THD+N vs Frequency THD+N vs Frequency Figure 10. VDD = 5V; LHP, RHP; PO = 15mW; RL = 32; Mode 9; 0dB Gain Figure 11. VDD = 3V; LHP, RHP; PO = 10mW; RL = 32; Mode 9; 0dB Gain THD+N vs Frequency THD+N vs Frequency Figure 12. VDD = 5V; EP; PO = 15mW; RL = 32; Mode 1; 0dB Gain, CD4 = 0 Figure 13. VDD = 3V; EP; PO = 10mW; RL = 32; Mode 1; 0dB Gain, CD4 = 0 THD+N vs Frequency THD+N vs Frequency Figure 14. VDD = 5V; LINEOUT; VO = 1VRMS; RL = 5k; Mode 5; 0dB Gain Figure 15. VDD = 3V; LINEOUT; VO = 1VRMS; RL = 5k; Mode 5; 0dB Gain Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 13 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (1) (continued) 14 THD+N vs Frequency THD+N vs Frequency Figure 16. VDD = 5V; LINEOUT; VO = 1VRMS; RL = 5k; Mode 10; 0dB Gain Figure 17. VDD = 3V; LINEOUT; VO = 1VRMS; RL = 5k; Mode 10; 0dB Gain THD+N vs Output Power THD+N vs Output Power Figure 18. VDD = 5V; LLS, RLS; f = 1kHz; RL = 8; Mode 7; 0dB Gain Figure 19. VDD = 3V; LLS, RLS; f = 1kHz; RL = 8; Mode 7; 0dB Gain THD+N vs Output Power THD+N vs Output Power Figure 20. VDD = 5V; LHP, RHP; f = 1kHz; RL = 32; Mode 9; 0dB Gain Figure 21. VDD = 3V; LHP, RHP; f = 1kHz; RL = 32; Mode 9; 0dB Gain Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Typical Performance Characteristics (1) (continued) THD+N vs Output Power THD+N vs Output Power Figure 22. VDD = 5V; EP; f = 1kHz; RL = 32; Mode 1; 0dB Gain; Top-CD4 = 1; Bot-CD4 = 0 Figure 23. VDD = 3V; EP; f = 1kHz; RL = 32; Mode 1; 0dB Gain PSRR vs Frequency PSRR vs Frequency Figure 24. VDD = 5V; LLS, RLS; RL = 8; 0db Gain; All audio inputs terminated Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8 Figure 25. VDD = 3V; LLS, RLS; RL = 8; 0db Gain; All audio inputs terminated Top-Mode 12, 13; Mid-Mode 2, 3; Bot-Mode 7, 8 PSRR vs Frequency PSRR vs Frequency Figure 26. VDD = 5V; LHP, RHP; RL = 32; 0db Gain; All audio inputs terminated Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9 Figure 27. VDD = 3V; LHP, RHP; RL = 32; 0db Gain; All audio inputs terminated Top-Mode 13, 14; Mid-Mode 3, 4; Bot-Mode 8, 9 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 15 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (1) (continued) 16 PSRR vs Frequency PSRR vs Frequency Figure 28. VDD = 5V; EP; RL = 32; 0db Gain; All audio inputs terminated Top-Mode 11; Mid-Mode 6; Bot-Mode 1 Figure 29. VDD = 3V; EP; RL = 32; 0db Gain; All audio inputs terminated Top-Mode 11; Mid-Mode 6; Bot-Mode 1 PSRR vs Frequency PSRR vs Frequency Figure 30. VDD = 5V; LINEOUT; RL = 5k; 0db Gain; All audio inputs terminated Top-Mode 15; Mid-Mode 10; Bot-Mode 5 Figure 31. VDD = 3V; LINEOUT; RL = 5k; 0db Gain; All audio inputs terminated Top-Mode 15; Mid-Mode 10; Bot-Mode 5 Crosstalk vs Frequency Crosstalk vs Frequency Figure 32. VDD = 5V; LLS, RLS; PO = 400mW; RL = 8; Mode 7; 0db Gain; 3D off Top-Left to Right; Bot- Right to Left Figure 33. VDD = 3V; LLS, RLS; PO = 200mW; RL = 8; Mode 7; 0db Gain; 3D off Top-Left to Right; Bot- Right to Left Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Typical Performance Characteristics (1) (continued) Figure 34. VDD = 5V; LHP, RHP; PO = 15mW; RL = 32; Mode 9; 0db Gain; 3D off Top-Left to Right; Bot- Right to Left Figure 35. VDD = 3V; LHP, RHP; PO = 10mW; RL = 32; Mode 9; 0db Gain; 3D off Top-Left to Right; Bot- Right to Left Frequency vs Response Frequency vs Response +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 20 GAIN (dB) Crosstalk vs Frequency GAIN (dB) Crosstalk vs Frequency +14 +13.5 +13 +12.5 +12 +11.5 +11 +10.5 +10 +9. 5 +9 +8. 5 +8 +7. 5 +7 +6. 5 +6 20 50 100 200 500 1k 2k 5k 10k 20k 50 10 20 0 0 50 1k 2k 0 5k 10k 20k FREQUENCY (Hz) FREQUENCY (Hz) Figure 36. LLS, RLS; RL = 8; Mode 2; Full Gain Figure 37. LLS, RLS; RL = 8; Mode 7; Full Gain Frequency vs Response Frequency vs Response Figure 38. LHP, RHP; RL = 32; CO = 100F Mode 4; Full Gain Figure 39. LHP, RHP; RL = 32; CO = 100F Mode 9; Full Gain Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 17 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (1) (continued) 18 Frequency vs Response Frequency vs Response Figure 40. EP; RL = 32; Mode 1; Full Gain Top-CD4 = 1; Bot-CD4 = 0 Figure 41. LINEOUT; RL = 5k; CO = 2.2F Mode 5; Full Gain Frequency vs Response Power Dissipation vs Output Power Figure 42. LINEOUT; RL = 5k; CO = 2.2F Mode 10; Full Gain Figure 43. LLS, RLS; RL = 8; THD+N 1% Top-VDD = 5V; Bot-VDD = 3V per channel Power Dissipation vs Output Power Power Dissipation vs Output Power Figure 44. LHP, RHP; RL = 32; THD+N 1% Top-VDD = 5V; Bot-VDD = 3V per channel Figure 45. EP; RL = 32; THD+N 1% Top-VDD = 5V; Bot-VDD = 3V Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Typical Performance Characteristics (1) (continued) Output Power vs Load Resistance Output Power vs Load Resistance Figure 46. LLS, RLS; RL = 8; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N Figure 47. LHP, RHP; RL = 32; Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N Output Power vs Load Resistance Output Power vs Load Resistance Figure 48. EP; RL = 32; CD4 = 0 Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N Figure 49. EP; RL = 32; CD4 = 1 Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1% THD+N; Botmid-VDD = 3V, 10% THD+N; Bot-VDD = 3V, 1% THD+N Output Power vs Supply Voltage Output Power vs Supply Voltage Figure 50. LLS, RLS; RL = 8; Top-10% THD+N; Bot-1% THD+N Figure 51. LHP, RHP; RL = 32; Top-10% THD+N; Bot-1% THD+N Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 19 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (1) (continued) Output Power vs Supply Voltage Figure 52. EP; RL = 32; Top-10% THD+N; CD4 = 1; Topmid-1% THD+N, CD4 = 1 Botmid-10% THD+N; CD4 = 0; Bot-1% THD+N, CD4 = 0 20 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 APPLICATION INFORMATION Figure 53. I2C Bus Format Figure 54. I2C Timing Diagram Table 1. Chip Address A7 A6 A5 A4 A3 A2 A1 A0 Chip Address 1 1 1 1 1 0 EC 0 ADR = 0 1 1 1 1 1 0 0 0 ADR = 1 1 1 1 1 1 0 1 0 Table 2. Control Registers D7 D6 D5 D4 D3 D2 D1 D0 Mono Volume control 0 0 0 MD4 MD3 MD2 MD1 MD0 Left Volume control 0 1 LD5 LD4 LD3 LD2 LD1 LD0 Right Volume control 1 0 RD5 RD4 RD3 RD2 RD1 RD0 Mode control 1 1 CD5 CD4 CD3 CD2 CD1 CD0 Table 3. Mono Volume Control MD4 MD3 MD2 MD1 MD0 Gain (dB) 0 0 0 0 0 -34.5 0 0 0 0 1 -33.0 0 0 0 1 0 -31.5 0 0 0 1 1 -30.0 0 0 1 0 0 -28.5 0 0 1 0 1 -27.0 0 0 1 1 0 -25.5 0 0 1 1 1 -24.0 0 1 0 0 0 -22.5 0 1 0 0 1 -21.0 0 1 0 1 0 -19.5 0 1 0 1 1 -18.0 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 21 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Table 3. Mono Volume Control (continued) MD4 MD3 MD2 MD1 MD0 Gain (dB) 0 1 1 0 0 -16.5 0 1 1 0 1 -15.0 0 1 1 1 0 -13.5 0 1 1 1 1 -12.0 1 0 0 0 0 -10.5 1 0 0 0 1 -9.0 1 0 0 1 0 -7.5 1 0 0 1 1 -6.0 1 0 1 0 0 -4.5 1 0 1 0 1 -3.0 1 0 1 1 0 -1.5 1 0 1 1 1 0.0 1 1 0 0 0 1.5 1 1 0 0 1 3.0 1 1 0 1 0 4.5 1 1 0 1 1 6.0 1 1 1 0 0 7.5 1 1 1 0 1 9.0 1 1 1 1 0 10.5 1 1 1 1 1 12.0 LD4//RD4 LD3//RD3 LD2//RD2 LD1//RD1 LD0//RD0 Gain (dB) 0 0 0 0 0 -40.5 0 0 0 0 1 -39.0 0 0 0 1 0 -37.5 0 0 0 1 1 -36.0 0 0 1 0 0 -34.5 0 0 1 0 1 -33.0 0 0 1 1 0 -31.5 0 0 1 1 1 -30.0 0 1 0 0 0 -28.5 0 1 0 0 1 -27.0 0 1 0 1 0 -25.5 0 1 0 1 1 -24.0 0 1 1 0 0 -22.5 0 1 1 0 1 -21.0 0 1 1 1 0 -19.5 0 1 1 1 1 -18.0 1 0 0 0 0 -16.5 1 0 0 0 1 -15.0 1 0 0 1 0 -13.5 1 0 0 1 1 -12.0 1 0 1 0 0 -10.5 1 0 1 0 1 -9.0 1 0 1 1 0 -7.5 1 0 1 1 1 -6.0 Table 4. Stereo Volume Control 22 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Table 4. Stereo Volume Control (continued) LD4//RD4 LD3//RD3 LD2//RD2 LD1//RD1 LD0//RD0 Gain (dB) 1 1 0 0 0 -4.5 1 1 0 0 1 -3.0 1 1 0 1 0 -1.5 1 1 0 1 1 0.0 1 1 1 0 0 1.5 1 1 1 0 1 3.0 1 1 1 1 0 4.5 1 1 1 1 1 6.0 Table 5. Mixer and Output Mode Control Mode CD3 CD2 CD1 CD 0 Mono Line Out Mono Earpiece (CD4 = 0) (CD4 = 1) Loudspeaker L Loudspeaker R Headphone L Headphone R 0 0 0 0 0 SD SD SD SD SD SD SD 1 0 0 0 1 MUTE (GM x M) 2(GM x M) SD SD MUTE MUTE 2 0 0 1 0 MUTE SD SD 2(GM x M) 2(GM x M) MUTE MUTE 3 0 0 1 1 MUTE SD SD 2(GM x M) 2(GM x M) (GM x M) (GM x M) 4 0 1 0 0 MUTE SD SD SD SD (GM x M) (GM x M) 5 0 1 0 1 (GM x M) SD SD SD SD MUTE MUTE 6 0 1 1 0 MUTE (GL x L) + (GR x R) 2(GL x L) + 2(GR x R) SD SD MUTE MUTE 7 0 1 1 1 MUTE SD SD 2(GL x L) 2(GR x R) MUTE MUTE 8 1 0 0 0 MUTE SD SD 2(GL x L) 2(GR x R) (GL x L) (GR x R) 9 1 0 0 1 MUTE SD SD SD SD (GL x L) (GR x R) 10 1 0 1 0 (GL x L) + (GR x R) SD SD SD SD MUTE MUTE 11 1 0 1 1 MUTE (GM x M) + (GL x L) + (GR x R) 2(GM x M) + 2(GL x L) +2(GR x R) SD SD MUTE MUTE 12 1 1 0 0 MUTE SD SD 2(GL x L) + 2(GM x M) 2(GR x R) + 2(GM x M) MUTE MUTE 13 1 1 0 1 MUTE SD SD 2(GL x L) + 2(GM x M) 2(GR x R) + 2(GM x M) (GL x L) + (GM x M) (GR x R) + (GM x M) 14 1 1 1 0 MUTE SD SD SD SD (GL x L) + (GM x M) (GR x R) + (GM x M) 15 1 1 1 1 (GM x M) +(GL x L) +(GR x R) SD SD SD SD MUTE MUTE Table 6. TI 3D Enhancement LD5 RD5 0 Loudspeaker TI 3D Off 1 Loudspeaker TI 3D On 0 Headphone TI 3D Off 1 Headphone TI 3D On Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 23 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Table 7. Wake-up Time Select CD5 0 Fast Wake-up Setting 1 Slow Wake-up Setting Table 8. Earpiece Amplifier Gain Select CD4 0 0dB Earpiece Output Stage Gain Setting 1 6dB Earpiece Output Stage Gain Setting I2C COMPATIBLE INTERFACE The LM4857 uses a serial bus, which conforms to the I2C protocol, to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4857. The I2C address for the LM4857 is determined using the ADR pin. The LM4857's two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ADR is logic low; and X1 = 1, if ADR is logic high. If the I2C interface is used to address a number of chips in a system, the LM4857's chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 53. The bus format diagram is broken up into six major sections: The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is high. After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM4857 has received the address correctly, then it holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4857. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable high. After the data byte is sent, the master must check for another acknowledge to see if the LM4857 received the data. If the master has more data bytes to send to the LM4857, then the master can repeat the previous two steps until all data bytes have been sent. The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The data line should be held high when not in use. I2C INTERFACE POWER SUPPLY PIN (I2CVDD) The LM4857's I2C interface is powered up through the I2CVDD pin. The LM4857's I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. TI 3D ENHANCEMENT The LM4857 features a 3D audio enhancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement improves the apparent stereo channel separation whenever the left and right speakers are too close to one another, due to system size constraints or equipment limitations. An external RC network, shown in Figure 1, is required to enable the 3D effect. There are separate RC networks for both the stereo loudspeaker outputs as well as the stereo headphone outputs, so the 3D effect can be set independently for each set of stereo outputs. 24 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 The amount of the 3D effect is set by the R3D resistor. Decreasing the value of R3D will increase the 3D effect. The C3D capacitor sets the low cutoff frequency of the 3D effect. Increasing the value of C3D will decrease the low cutoff frequency at which the 3D effect starts to occur, as shown by Equation 1. f3D(-3dB) = 1 / 2(R3D)(C3D) (1) Activating the 3D effect will cause an increase in gain by a multiplication factor of (1 + 9k/R3D). Setting R3D to 9k will result in a gain increase by a multiplication factor of (1+ 9k/9k) = 2 or 6dB whenever the 3D effect is activated. The volume control can be programmed through the I2C compatible interface to compensate for the extra 6dB increase in gain. For example, if the stereo volume control is set at 0dB (11011 from Table 4) before the 3D effect is activated, the volume control should be programmed to -6dB (10111 from Table 4) immediately after the 3D effect has been activated. Setting R3D = 20k and C3D = 0.22F allows the LM4857 to produce a pronounced 3D effect with a minimal increase in output noise. EXPOSED-DAP MOUNTING CONSIDERATIONS The LM4857's exposed-DAP (die attach paddle) package (UQFN) provides a low thermal resistance between the die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the surrounding PCB copper area heatsink, copper traces, ground plane, and finally, surrounding air. The result is a low voltage audio power amplifier that produces 1.6W dissipation in a 4 load at 1% THD+N and over 1.8W in a 3 load at 10% THD+N. This high power is achieved through careful consideration of necessary thermal design. Failing to optimize thermal design may compromise the LM4857's high power performance and activate unwanted, though necessary, thermal shutdown protection. The UQFN package must have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad is then, ideally, connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and radiation area. Place the heat sink area on either outside plane in the case of a two-sided or multi-layer PCB. (The heat sink area can also be placed on an inner layer of a multi-layer board. The thermal resistance, however, will be higher.) Connect the DAP copper pad to the inner layer or backside copper heat sink area with 9 (3 X 3) (UQFN) vias. The via diameter should be 0.012in - 0.013in with a 1.27mm pitch. Ensure efficient thermal conductivity by plugging and tenting the vias with plating and solder mask, respectively. Best thermal performance is achieved with the largest practical copper heat sink area. If the heatsink and amplifier share the same PCB layer, a nominal 2in2 area is necessary for 5V operation with a 4 load. Heatsink areas not placed on the same PCB layer as the LM4857 should be 4in2 for the same supply voltage and load resistance. The last two area recommendations apply for 25C ambient temperature. Increase the area to compensate for ambient temperatures above 25C. In all circumstances and under all conditions, the junction temperature must be held below 150C to prevent activating the LM4857's thermal shutdown protection. An example PCB layout for the exposed-DAP UQFN package is shown in the Demonstration Board Layout section. Information on the UQFN style package is provided in the AN-1187 Application Report (literature number SNOA401). PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 3 AND 4 LOADS Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1 trace resistance reduces the output power dissipated by a 4 load from 1.6W to 1.5W. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 25 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com BRIDGE CONFIGURATION EXPLANATION The LM4857 consists of three sets of a bridged-tied amplifier pairs that drive the left loudspeaker (LLS), the right loudspeaker (RLS), and the mono earpiece (EP). For this discussion, only the LLS bridge-tied amplifier pair will be referred to. The LM4857 drives a load, such as a speaker, connected between outputs, LLS+ and LLS-. In the LLS amplifier block, the output of the amplifier that drives LLS- serves as the input to the unity gain inverting amplifier that drives LLS+. This results in both amplifiers producing signals identical in magnitude, but 180 out of phase. Taking advantage of this phase difference, a load is placed between LLS- and LLS+ and driven differentially (commonly referred to as 'bridge mode'). This results in a differential or BTL gain of: AVD = 2(Rf / Ri) = 2 (2) Both the feedback resistor, Rf, and the input resistor, Ri, are internally set. Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped. Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing LLS- and LLS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers. POWER DISSIPATION Power dissipation is a major concern when designing a successful single-ended or bridged amplifier. A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM4857 has 3 sets of bridged-tied amplifier pairs driving LLS, RLS, and EP. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation 3 and Equation 4, assuming a 5V power supply and an 8 load, the maximum power dissipation for LLS and RLS is 634mW per channel. From Equation 5, assuming a 5V power supply and a 32 load, the maximum power dissipation for EP is 158mW. PDMAX-LLS = 4(VDD)2/ (22 RL): Bridged (3) PDMAX-RLS = 4(VDD)2/ (22 RL): Bridged (4) PDMAX-EP = 4(VDD)2/ (22 RL): Bridged (5) The LM4857 also has 3 sets of single-ended amplifiers driving LHP, RHP, and LINEOUT. The maximum internal power dissipation for ROUT and LOUT is given by Equation 6 and Equation 7. From Equation 6 and Equation 7, assuming a 5V power supply and a 32 load, the maximum power dissipation for LOUT and ROUT is 40mW per channel. From Equation 8, assuming a 5V power supply and a 5k load, the maximum power dissipation for LINEOUT is negligible. 26 PDMAX-LHP = (VDD)2 / (22 RL): Single-ended (6) PDMAX-RHP = (VDD)2 / (22 RL): Single-ended (7) Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 PDMAX-LINE = (VDD)2 / (22 RL): Single-ended (8) The maximum internal power dissipation of the LM4857 occurs during output modes 3, 8, and 13 when both loudspeaker and headphone amplifiers are simultaneously on; and is given by Equation 9. PDMAX-TOTAL = PDMAX-LLS + PDMAX-RLS + PDMAX-LHP + PDMAX-RHP (9) The maximum power dissipation point given by Equation 9 must not exceed the power dissipation given by Equation 10: PDMAX' = (TJMAX - TA) / JA (10) The LM4857's TJMAX = 150C. In the DSBGA package, the LM4857's JA is 62C/W. At any given ambient temperature TA, use Equation 10 to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation 10 and substituting PDMAX-TOTAL for PDMAX' results in Equation 11. This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4857's maximum junction temperature. TA = TJMAX - PDMAX-TOTAL JA (11) For a typical application with a 5V power supply, stereo 8 loudspeaker load, and the stereo 32 headphone load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 66.4C for the DSBGA package. TJMAX = PDMAX-TOTAL JA + TA (12) Equation 12 gives the maximum junction temperature TJMAX. If the result violates the LM4857's 150C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation 9 is greater than that of Equation 10, then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce JA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the JA is the sum of JC, CS, and SA. (JC is the junction-to-case thermal impedance, CS is the case-to-sink thermal impedance, and SA is the sink-to-ambient thermal impedance.) Refer to the Typical Performance Characteristics (1) curves for power dissipation information at lower output power levels. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 10F in parallel with a 0.1F filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response. However, their presence does not eliminate the need for a local 1.0F tantalum bypass capacitance connected between the LM4857's supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM4857's power supply pin and ground as short as possible. (1) "0dB gain" refers to the volume control gain setting of MIN, LIN, and RIN set at 0dB. Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 27 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com SELECTING EXTERNAL COMPONENTS Input Capacitor Value Selection Amplifying the lowest audio frequencies requires a high value input coupling capacitor (Ci in Figure 1). In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 50Hz. Applications using speakers with this limited frequency response reap little improvement; by using a large input capacitor. The internal input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found using Equation 13. fc = 1 / (2RiCi) (13) As an example when using a speaker with a low frequency limit of 50Hz and Ri = 20k, Ci, using Equation 13 is 0.19F. The 0.22F Ci shown in Figure 55 allows the LM4857 to drive high efficiency, full range speaker whose response extends below 40Hz. Output Capacitor Value Selection Amplifying the lowest audio frequencies also requires the use of a high value output coupling capacitor (CO in Figure 1). A high value output capacitor can be expensive and may compromise space efficiency in portable design. The speaker load (RL) and the output capacitor (CO) form a high pass filter with a low cutoff frequency determined using Equation 14. fc = 1 / (2RLCO) (14) When using a typical headphone load of RL = 32 with a low frequency limit of 50Hz, CO is 99F. The 100F CO shown in Figure 55 allows the LM4857 to drive a headphone whose frequency response extends below 50Hz. Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS pin. Since CB determines how fast the LM4857 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4857's outputs ramp to their quiescent DC voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 2.2F along with a small value of Ci (in the range of 0.1F to 0.39F), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in the range of 5 times to 10 times the value of Ci. This ensures that output transients are eliminated when the LM4857 transitions in and out of shutdown mode. Connecting a 2.2F capacitor, CB, between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. However, increasing the value of CB will increase wake-up time. The selection of bypass capacitor value, CB, depends on desired PSRR requirements, click and pop performance, wake-up time, system cost, and size constraints. 28 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 TI 3D Figure 55. Reference Design Board Schematic Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 29 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Demonstration Board DSBGA PCB Layout Figure 56. Recommended DSBGA PCB Layout: Top Silkscreen Figure 57. Recommended DSBGA PCB Layout: Top Layer 30 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Figure 58. Recommended DSBGA PCB Layout: Inner Layer 1 Figure 59. Recommended DSBGA PCB Layout: Inner Layer 2 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 31 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Figure 60. Recommended DSBGA PCB Layout: Bottom Layer Demonstration Board UQFN PCB Layout Figure 61. Recommended UQFN PCB Layout: Top Over Layer 32 Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 LM4857 www.ti.com SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 Figure 62. Recommended UQFN PCB Layout: Top Layer Figure 63. Recommended UQFN PCB Layout: Mid Layer Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 33 LM4857 SNAS229I - OCTOBER 2003 - REVISED APRIL 2013 www.ti.com Figure 64. Recommended UQFN PCB Layout: Bottom Layer Revision History 34 Rev Date Description 1.1 6/03/05 Changed the numerical value of 20 into 9 in the last paragraph of "NATIONAL 3D ENHANCEMENT (per Alvin F.), then re-released D/S to the WEB. (MC) 1.2 6/07/05 Deleted all references on GR pkg (GR pkgs on HOLD) per Kevin Chen, then re-WEBd the D/S. (MC) C 4/19/2013 Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright (c) 2003-2013, Texas Instruments Incorporated Product Folder Links: LM4857 PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) LM4857SP/NOPB ACTIVE Package Type Package Pins Package Drawing Qty UQFN NJD 28 1000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (C) Device Marking (3) CU SN Level-1-260C-UNLIM (4/5) -40 to 85 L4857SP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM4857SP/NOPB Package Package Pins Type Drawing UQFN NJD 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 178.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 1.3 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM4857SP/NOPB UQFN NJD 28 1000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NJD0028A SPA28A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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