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Rev. G
7/30/2014
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
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IS42S16400J
IS45S16400J
FEATURES
• Clock frequency: 200, 166, 143, 133 MHz
• Fullysynchronous;allsignalsreferencedtoa
positive clock edge
• Internalbankforhidingrowaccess/precharge
• Single3.3Vpowersupply
• LVTTLinterface
• Programmableburstlength
– (1, 2, 4, 8, full page)
• Programmableburstsequence:
Sequential/Interleave
• Selfrefreshmodes
• Autorefresh(CBR)
• 4096refreshcyclesevery64ms(Com,Ind,A1
grade) or 16ms (A2 grade)
• Randomcolumnaddresseveryclockcycle
• ProgrammableCAS latency (2, 3 clocks)
• Burstread/writeandburstread/singlewrite
operations capability
• Burstterminationbyburststopandprecharge
command
OPTIONS
• Package:
54-pinTSOPII
54-ballTF-BGA(8mmx8mm)
60-ballTF-BGA(10.1mmx6.4mm)
• OperatingTemperatureRange
Commercial (0oC to +70oC)
Industrial (-40oC to +85oC)
AutomotiveGradeA1(-40oC to +85oC)
AutomotiveGradeA2(-40oC to +105oC)
OVERVIEW
ISSI's64MbSynchronousDRAMisorganizedas1,048,576
bits x 16-bit x 4-bank for improved performance. The
synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM JULY 2014
KEY TIMING PARAMETERS
Parameter -5 -6 -7 Unit
ClkCycleTime 
CASLatency=3 5 6 7 ns
CASLatency=2 7.5 7.5 7.5 ns
ClkFrequency 
CASLatency=3 200 166 143 Mhz
CASLatency=2 133 133 133 Mhz
AccessTimefromClock
CASLatency=3 4.8 5.4 5.4 ns
CASLatency=2 5.4 5.4 5.4 ns
Parameter 4M x 16
 1M x 16 x 4


Com./Ind.
A1
A2



 A0-A11
 A0-A7
 BA0, BA1
 
ADDRESS TABLE
2 Integrated Silicon Solution, Inc. — www.issi.com
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IS42S16400J
IS45S16400J
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
congured as a quad-bank DRAM with a synchronous
interface.Each16,777,216-bitbankisorganizedas4,096
rows by 256 columns by 16 bits.
The64MbSDRAMincludesanAUTOREFRESHMODE,
and a power-saving, power-down mode. All signals are
registeredonthepositiveedgeoftheclocksignal,CLK.
AllinputsandoutputsareLVTTLcompatible.
The64MbSDRAMhastheabilitytosynchronouslyburst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequenceisavailablewiththeAUTOPRECHARGEfunction
enabled.
Precharge
one bank while accessing one of the
other three banks will hide the
precharge
cycles and provide
seamless, high-speed, random-access operation.
SDRAM
read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followedbyaREADorWRITEcommand.TheACTIVE
command in conjunction with address bits registered are
usedtoselectthe bankand rowtobe accessed(BA0,
BA1selectthebank;A0-A11selecttherow).TheREAD
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
ProgrammableREADorWRITEburstlengthsconsistof
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
CLK
CKE
CS
RAS
CAS
WE
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A11
COMMAND
DECODER
&
CLOCK
GENERATORMODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQM
DQ 0-15
VDD/VDDQ
GND/GNDQ
12
12
8
12
12
8
16
16 16
16
256K
(x 16)
4096
4096
4096
ROW DECODER
4096 MEMORY CELL
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
ROW
ADDRESS
BUFFER
FUNCTIONAL BLOCK DIAGRAM
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IS42S16400J
IS45S16400J
PIN CONFIGURATION


1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
GNDQ
VDDQ
GNDQ
VDDQ
GND
CKE
A9
A6
A4
VDDQ
GNDQ
VDDQ
GNDQ
VDD
CAS
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
DQML
RAS
BA1
A1
A2
GND
DQ14
DQ12
DQ10
DQ8
DQMH
NC
A8
GND
VDD
DQ1
DQ3
DQ5
DQ7
WE
CS
A10
VDD
PIN DESCRIPTIONS
 
 
 
 
 
 
CS 
RAS 
CAS 
WE 
 
Vdd 
 
Vddq 
 
 
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
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IS42S16400J
IS45S16400J
PIN CONFIGURATION
PACKAGECODE:
B260BALLTF-BGA(TopView)(10.1mmx6.4mmBody,0.65mmBallPitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
GND
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
A11
A8
A6
GND
DQ15
GNDQ
VDDQ
DQ11
GNDQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
DQ0
VDDQ
GNDQ
DQ4
VDDQ
GNDQ
NC
VDD
LDQM
RAS
NC
BA1
A0
A2
A3
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE
CAS
CS
BA0
A10
A1
VDD
PIN DESCRIPTIONS
A0-A11 RowAddressInput
A0-A7 Column Address Input
BA0,BA1 BankSelectAddresses
DQ0toDQ15 DataI/O
CLK SystemClockInput
CKE ClockEnable
CS Chip Select
RAS RowAddressStrobeCommand
CAS Column Address Strobe Command
WE WriteEnable
LDQM,UDQM x16Input/OutputMask
Vdd Power
GND Ground
Vddq PowerSupplyforI/OPin
GNDq GroundforI/OPin
NC NoConnection
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IS45S16400J
PIN CONFIGURATIONS
54 pin TSOP - Type II
PIN DESCRIPTIONS
A0-A11 RowAddressInput
A0-A7 Column Address Input
BA0,BA1 BankSelectAddress
DQ0toDQ15 DataI/O
CLK SystemClockInput
CKE ClockEnable
CS Chip Select
RAS RowAddressStrobeCommand
CAS Column Address Strobe Command
V
DD
DQ0
V
DD
Q
DQ1
DQ2
GNDQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
GNDQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ15
GNDQ
DQ14
DQ13
V
DD
Q
DQ12
DQ11
GNDQ
DQ10
DQ9
V
DD
Q
DQ8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
WE WriteEnable
LDQM x16LowerByte,Input/OutputMask
UDQM x16UpperByte,Input/OutputMask
Vdd Power
GND Ground
Vddq PowerSupplyforI/OPin
GNDq GroundforI/OPin
NC NoConnection
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
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IS42S16400J
IS45S16400J
PIN FUNCTIONS
Symbol TSOP Pin No. Type Function
A0-A11
23 to 26 Input Pin
AddressInputs:A0-A11aresampledduringtheACTIVE
29to34
command(row-addressA0-A11)andREAD/WRITEcommand(A0-A7
22, 35
with A10 defining auto precharge) to select one location out of the memory array
intherespectivebank.A10issampledduringaPRECHARGEcommandtodeter-
mineifallbanksaretobeprecharged(A10HIGH)orbankselectedby
BA0,BA1(LOW).Theaddressinputsalsoprovidetheop-codeduringaLOAD
MODEREGISTERcommand.
BA0,BA1
20, 21 Input Pin
BankSelectAddress:BA0andBA1deneswhichbanktheACTIVE,READ,WRITE
orPRECHARGEcommandisbeingapplied.
CAS
17 Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
"CommandTruthTable"fordetailsondevicecommands.
CKE
37 Input Pin
TheCKEinputdetermineswhethertheCLKinputisenabled.Thenextrisingedge
oftheCLKsignalwillbevalidwhenisCKEHIGHandinvalidwhenLOW.WhenCKE
isLOW,thedevicewillbeineitherpower-downmode,clocksuspendmode,orself
refresh mode.
CKEisan
asynchronous i
nput.
CLK
38 Input Pin
CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdevice
are acquired in synchronization with the rising edge of this pin.
CS
19 InputPin
TheCS input determines whether command input is enabled within the device.
Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.The
device remains in the previous state when CSisHIGH.
DQ0 to
2, 4, 5, 7, 8, 10, DQ Pin
DQ0toDQ15areI/Opins.I/Othroughthesepinscanbecontrolledinbyteunits
DQ15
11,13, 42, 44, 45,
usingtheLDQMandUDQMpins.
47, 48, 50, 51, 53
LDQM,
15,39 InputPin
LDQMandUDQMcontrolthelowerandupperbytesoftheI/Obuffers.Inread
UDQM mode,LDQMandUDQMcontroltheoutputbuffer.WhenLDQMorUDQMisLOW,
thecorrespondingbufferbyteisenabled,andwhenHIGH,disabled.Theoutputs
gototheHIGHimpedancestatewhenLDQM/UDQMisHIGH.Thisfunctioncor-
responds to OEinconventionalDRAMs.Inwritemode,LDQMandUDQMcontrol
theinputbuffer.WhenLDQMorUDQMisLOW,thecorrespondingbufferbyteisen-
abled,anddatacanbewrittentothedevice.WhenLDQMorUDQMisHIGH,input
data is masked and cannot be written to the device.
RAS
18 Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Com-
mandTruthTable"itemfordetailsondevicecommands.
WE
16 Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Com-
mandTruthTable"itemfordetailsondevicecommands.
Vddq
3,9,43,49 PowerSupplyPin
Vddq is the output buffer power supply.
Vdd
1, 14, 27 Power Supply Pin
Vdd is the device internal power supply.
GNdq
6, 12, 46, 52 Power Supply Pin
GNdq is the output buffer ground.
GNd
28, 41, 54 Power Supply Pin
GNd is the device internal ground.
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IS42S16400J
IS45S16400J
READ
TheREADcommandselectsthebankfromBA0,BA1inputs
and starts a burst read access to an active row. Inputs
A0-A7providesthestartingcolumnlocation.WhenA10is
HIGH,thiscommandfunctionsasanAUTOPRECHARGE
command.Whentheautoprechargeisselected,therow
beingaccessedwillbeprechargedattheendoftheREAD
burst.Therowwillremainopenforsubsequentaccesses
when AUTO PRECHARGE is not selected. DQ’s read
data is subject to the logic level on the DQM inputs two
clocksearlier.WhenagivenDQMsignalwasregistered
HIGH,thecorrespondingDQ’swillbeHigh-Ztwoclocks
later.DQ’swillprovidevaliddatawhentheDQMsignal
wasregisteredLOW.
WRITE
A burst write access to an active row is initiated with the
WRITE command. BA0, BA1 inputs selects the bank,
and the starting column location is provided by inputs
A0-A7. Whether or not AUTO-PRECHARGE is used is
determined by A10.
Therowbeingaccessedwillbeprechargedattheendof
theWRITE burst,if AUTOPRECHARGE is selected. If
AUTOPRECHARGEisnotselected,therowwillremain
open for subsequent accesses.
A memory array is written with corresponding input data
onDQ’sandDQMinputlogiclevelappearingatthesame
time. Data will be written to memory when DQM signal is
LOW.WhenDQMisHIGH,thecorrespondingdatainputs
willbeignored,andaWRITEwillnotbeexecutedtothat
byte/column location.
PRECHARGE
ThePRECHARGEcommandisusedtodeactivatetheopen
rowinaparticularbankortheopenrowinallbanks.BA0,
BA1canbeusedtoselectwhichbankisprechargedorthey
aretreatedas“Don’tCare”.A10determineswhetherone
or all banks are precharged. After executing this command,
the next command for the selected bank(s) is executed after
passage of the period tRP
, which is the period required for
bankprecharging.Onceabankhasbeenprecharged,it
isintheidlestateandmustbeactivatedpriortoanyREAD
orWRITEcommandsbeingissuedtothatbank.
AUTO PRECHARGE
The AUTO PRECHARGE function ensures that the
precharge is initiated at the earliest valid stage within a
burst.Thisfunctionallowsforindividual-bankprecharge
without requiring an explicit command. A10 can be used
toenabletheAUTOPRECHARGEfunctioninconjunc-
tionwithaspecicREADorWRITEcommand.Foreach
individualREADorWRITEcommand,autoprechargeis
eitherenabledordisabled.AUTOPRECHARGEdoesnot
applyexceptinfull-pageburstmode.Uponcompletionof
theREADorWRITEburst,aprechargeofthebank/row
that is addressed is automatically performed.
AUTO REFRESH COMMAND
ThiscommandexecutestheAUTOREFRESHoperation.
Therowaddressandbanktoberefreshedareautomatically
generatedduringthisoperation. Thestipulatedperiod(trc) is
required for a single refresh operation, and no other com-
mandscanbeexecutedduringthisperiod. Thiscommand
isexecutedatleast4096timeseveryTref.DuringanAUTO
REFRESHcommand,addressbitsare“Don’tCare”.This
commandcorrespondstoCBRAuto-refresh.
SELF REFRESH
DuringtheSELFREFRESHoperation,therowaddressto
be refreshed, the bank, and the refresh interval are gen-
eratedautomaticallyinternally.SELFREFRESHcanbe
usedtoretaindataintheSDRAMwithoutexternalclocking,
eveniftherestofthesystemispowereddown.TheSELF
REFRESHoperationisstartedbydroppingtheCKEpin
fromHIGHtoLOW.DuringtheSELFREFRESHoperation
allotherinputstotheSDRAMbecome“Don’tCare”.The
device must remain in self refresh mode for a minimum
period equal to tras or may remain in self refresh mode
foranindeniteperiodbeyondthat.TheSELF-REFRESH
operationcontinuesaslongastheCKEpinremainsLOW
and there is no need for external control of any other pins.
Thenextcommandcannotbeexecuteduntilthedevice
internal recovery period (trc) has elapsed. Once CKE
goesHIGH,theNOPcommandmustbeissued
(minimum
of two clocks)
to provide time for the completion of any
internal refresh in progress. After the self-refresh, since it
is impossible to determine the address of the last row to
berefreshed,anAUTO-REFRESHshouldimmediatelybe
performed for all addresses.
BURST TERMINATE
The BURSTTERMINATE command forcibly terminates
the burst read and write operations by truncating either
fixed-length or full-page bursts and the most recently
registeredREADorWRITEcommandpriortotheBURST
TERMINATE.
COMMAND INHIBIT
COMMANDINHIBITpreventsnewcommandsfrombeing
executed.Operationsinprogressarenotaffected,apart
fromwhethertheCLKsignalisenabled
NO OPERATION
WhenCSislow,theNOPcommandpreventsunwanted
commands from being registered during idle or wait
states.
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LOAD MODE REGISTER
DuringtheLOADMODEREGISTERcommandthemode
registerisloadedfromA0-A11.Thiscommandcanonly
be issued when all banks are idle.
ACTIVE COMMAND
When the ACTIVE COMMAND is activated, BA0, BA1
inputs selects a bank to be accessed, and the address
inputsonA0-A11selectstherow.UntilaPRECHARGE
command is issued to the bank, the row remains open
for accesses.
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TRUTH TABLE – COMMANDS AND DQM OPERATION(1)
FUNCTION CS RAS CAS WE DQM ADDR DQs
COMMANDINHIBIT(NOP) H X X X X X X
NOOPERATION(NOP) L H H H X X X
ACTIVE(Selectbankandactivaterow)(3) L L H H X Bank/Row X
READ(Selectbank/column,startREADburst)
(4) L H L H L/H(8) Bank/Col X
WRITE(Selectbank/column,startWRITEburst)
(4) L H L L L/H(8) Bank/Col Valid
BURSTTERMINATE L H H L X X Active
PRECHARGE(Deactivaterowinbankorbanks)
(5) L L H L X Code X
AUTOREFRESHorSELFREFRESH(6,7) L L L H X X X
(Enter self refresh mode)
LOADMODEREGISTER(2) L L L L X Op-Code X
WriteEnable/OutputEnable(8) — — — — L — Active
WriteInhibit/OutputHigh-Z(8) — — — — H — High-Z
NOTES:
1. CKEisHIGHforallcommandsexceptSELFREFRESH.
2. A0-A11 define the op-code written to the mode register.
3. A0-A11providerowaddress,andBA0,BA1determinewhichbankismadeactive.
4. A0-A7(x16)providecolumnaddress;A10HIGHenablestheautoprechargefeature(nonpersistent),whileA10LOWdisables
autoprecharge;BA0,BA1determinewhichbankisbeingreadfromorwrittento.
5. A10LOW:BA0,BA1determinethebankbeingprecharged.A10HIGH:AllbanksprechargedandBA0,BA1are“Don’tCare.”
6. AUTOREFRESHifCKEisHIGH,SELFREFRESHifCKEisLOW.
7. Internalrefreshcountercontrolsrowaddressing;allinputsandI/Osare“Don’tCare”exceptforCKE.
8. ActivatesordeactivatestheDQsduringWRITEs(zero-clockdelay)andREADs(two-clockdelay).
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TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6)
CURRENTSTATE
COMMAND(ACTION) CS RAS CAS WE
Any COMMANDINHIBIT
(NOP/Continuepreviousoperation)
H X X X
NOOPERATION
(NOP/Continuepreviousoperation)
L H H H
Idle ACTIVE(Selectandactivaterow) L L H H
AUTOREFRESH(7) L L L H
LOADMODEREGISTER(7) L L L L
PRECHARGE(11) L L H L
RowActive READ(SelectcolumnandstartREADburst)(10) L H L H
WRITE(SelectcolumnandstartWRITEburst)(10) L H L L
PRECHARGE(Deactivaterowinbankorbanks)(8) L L H L
Read READ(SelectcolumnandstartnewREADburst)(10) L H L H
(Auto WRITE(SelectcolumnandstartWRITEburst)(10) L H L L
Precharge PRECHARGE(TruncateREADburst,startPRECHARGE)(8) L L H L
Disabled) BURSTTERMINATE(9) L H H L
Write READ(SelectcolumnandstartREADburst)(10) L H L H
(Auto WRITE(SelectcolumnandstartnewWRITEburst)(10) L H L L
Precharge PRECHARGE(TruncateWRITEburst,startPRECHARGE)(8) L L H L
Disabled) BURSTTERMINATE(9) L H H L
NOTE:
1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(seeTruthTable-CKE)andaftertxsr has been met (if the
previous state was SELFREFRESH).
2.Thistableisbank-specic,exceptwherenoted;i.e.,thecurrentstateisforaspecicbankandthecommandsshownarethose
allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
TRUTH TABLE – CKE (1-4)
CURRENT STATE COMMANDn ACTIONn CKEn-1 CKEn
Power-Down X MaintainPower-Down L L
SelfRefresh X MaintainSelfRefresh L L
ClockSuspend X MaintainClockSuspend L L
Power-Down(5) COMMANDINHIBITorNOP ExitPower-Down L H
SelfRefresh(6) COMMANDINHIBITorNOP ExitSelfRefresh L H
Clock Suspend(7) X ExitClockSuspend L H
AllBanksIdle COMMANDINHIBITorNOP Power-DownEntry H L
AllBanksIdle AUTOREFRESH SelfRefreshEntry H L
ReadingorWriting VALID ClockSuspendEntry H L
See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n
H H
NOTES:
1. CKEnisthelogicstateofCKEatclockedgen;CKEn-1 wasthestateofCKEatthepreviousclockedge.
2. CurrentstateisthestateoftheSDRAMimmediatelypriortoclockedgen.
3. COMMANDnisthecommandregisteredatclockedgen,andACTONnisaresultofCOMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1
(provided that tcks is
met)
.
6. Exiting self refresh at clock edge n will put the device in all banks idle state once txsrismet.COMMANDINHIBITorNOP
commands should be issued on clock edges occurring during the txsrperiod.AminimumoftwoNOPcommandsmustbesent
during txsr period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge
n+1.
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3. Current state definitions:
Idle:Thebankhasbeenprecharged,andtrp has been met.
RowActive:Arowinthebankhasbeenactivated,andtrcdhasbeenmet.Nodatabursts/accessesandnoregister
accesses are in progress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
nated.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
nated.
4.Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.COMMANDINHIBITorNOPcommands,
or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mandstotheotherbankaredeterminedbyitscurrentstateandCURRENTSTATEBANKntruthtables.
Precharging:StartswithregistrationofaPRECHARGEcommandandendswhentrpismet.Oncetrp is met, the bank
will be in the idle state.
RowActivating:StartswithregistrationofanACTIVEcommandandendswhentrcdismet.Oncetrcd is met, the bank will
be in the row active state.
Readw/Auto
Precharge Enabled:
StartswithregistrationofaREADcommandwithautoprechargeenabledandendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state.
Writew/Auto
Precharge Enabled:
StartswithregistrationofaWRITEcommandwithautoprechargeenabledandendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state.
5.Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;COMMANDINHIBITorNOPcommandsmustbe
applied on each positive clock edge during these states.
Refreshing:StartswithregistrationofanAUTOREFRESHcommandandendswhentrcismet.Oncetrc is met, the
SDRAMwillbeintheallbanksidlestate.
Accessing Mode
Register:StartswithregistrationofaLOADMODEREGISTERcommandandendswhentmrdhasbeenmet.Once
tmrdismet,theSDRAMwillbeintheallbanksidlestate.
Precharging All:
StartswithregistrationofaPRECHARGEALLcommandandendswhentrpismet.Oncetrp is met, all
banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7.Notbank-specic;requiresthatallbanksareidle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9.Notbank-specic;BURSTTERMINATEaffectsthemostrecentREADorWRITEburst,regardlessofbank.
10.READsorWRITEslistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabledand
READsorWRITEswithautoprechargedisabled.
11.DoesnotaffectthestateofthebankandactsasaNOPtothatbank.
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TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m (1-6)
CURRENTSTATE
COMMAND(ACTION) CS RAS CAS WE
Any COMMANDINHIBIT(NOP/Continuepreviousoperation) H X X X
NOOPERATION(NOP/Continuepreviousoperation) L H H H
Idle AnyCommandOtherwiseAllowedtoBankm X X X X
Row ACTIVE(Selectandactivaterow) L L H H
Activating, READ(SelectcolumnandstartREADburst)(7) L H L H
Active,or WRITE(SelectcolumnandstartWRITEburst)(7) L H L L
Precharging PRECHARGE L L H L
Read ACTIVE(Selectandactivaterow) L L H H
(Auto READ(SelectcolumnandstartnewREADburst)(7,10) L H L H
Precharge WRITE(SelectcolumnandstartWRITEburst)(7,11) L H L L
Disabled) PRECHARGE(9) L L H L
Write ACTIVE(Selectandactivaterow) L L H H
(Auto READ(SelectcolumnandstartREADburst)(7,12) L H L H
Precharge WRITE(SelectcolumnandstartnewWRITEburst)(7,13) L H L L
Disabled) PRECHARGE(9) L L H L
Read ACTIVE(Selectandactivaterow) L L H H
(WithAuto READ(SelectcolumnandstartnewREADburst)(7,8,14) L H L H
Precharge) WRITE(SelectcolumnandstartWRITEburst)(7,8,15) L H L L
PRECHARGE(9) L L H L
Write ACTIVE(Selectandactivaterow) L L H H
(WithAuto READ(SelectcolumnandstartREADburst)(7,8,16) L H L H
Precharge) WRITE(SelectcolumnandstartnewWRITEburst)(7,8,17) L H L L
PRECHARGE(9) L L H L
NOTE:
1.ThistableapplieswhenCKEn-1wasHIGHandCKEnisHIGH(TruthTable-CKE)andaftertxsr has been met (if the previ-
ous state was self refresh).
2.Thistabledescribesalternatebankoperation,exceptwherenoted;i.e.,thecurrentstateisforbankn and the commands
shown are those allowed to be issued to bank m
(assuming that bank m is in such a state that the given command is allowable)
. Excep-
tions are covered in the notes below.
3. Current state definitions:
Idle:Thebankhasbeenprecharged,andtrp has been met.
RowActive:Arowinthebankhasbeenactivated,andtrcdhasbeenmet.Nodatabursts/accessesandnoregister
accesses are in progress.
Read:AREADbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
nated.
Write:AWRITEbursthasbeeninitiated,withautoprechargedisabled,andhasnotyetterminatedorbeentermi-
nated.
Readw/Auto
Precharge Enabled:
StartswithregistrationofaREADcommandwithautoprechargeenabled,andendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state.
Writew/Auto
Precharge Enabled:
StartswithregistrationofaWRITEcommandwithautoprechargeenabled,andendswhentrp has been
met.Oncetrp is met, the bank will be in the idle state.
4.AUTOREFRESH,SELFREFRESHandLOADMODEREGISTERcommandsmayonlybeissuedwhenallbanksareidle.
5.ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;itappliestothebankrepresentedbythecurrentstate
only.
6. All states and sequences not shown are illegal or reserved.
7.READsorWRITEstobankmlistedintheCommand(Action)columnincludeREADsorWRITEswithautoprechargeenabled
andREADsorWRITEswithautoprechargedisabled.
Integrated Silicon Solution, Inc. — www.issi.com 13
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8.CONCURRENTAUTOPRECHARGE:BanknwillinitiatetheAUTOPRECHARGEcommandwhenitsbursthasbeeninter-
ruptedbybankm’sburst.
9.Burstinbankncontinuesasinitiated.
10.ForaREADwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt
theREADonbankn,CASlatencylater(ConsecutiveREADBursts).
11.ForaREADwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinter-
rupttheREADonbanknwhenregistered(READtoWRITE).DQMshouldbeusedoneclockpriortotheWRITEcommandto
prevent bus contention.
12.ForaWRITEwithoutautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt
theWRITEonbanknwhenregistered(WRITEtoREAD),withthedata-outappearingCASlatencylater.ThelastvalidWRITE
tobanknwillbedata-inregisteredoneclockpriortotheREADtobankm.
13.ForaWRITEwithoutautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinter-
rupttheWRITEonbanknwhenregistered(WRITEtoWRITE).ThelastvalidWRITEtobanknwillbedata-inregisteredone
clockpriortotheREADtobankm.
14.ForaREADwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterruptthe
READonbankn,CASlatencylater.ThePRECHARGEtobanknwillbeginwhentheREADtobankmisregistered(FigCAP
1).
15.ForaREADwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt
theREADonbanknwhenregistered.DQMshouldbeusedtwoclockspriortotheWRITEcommandtopreventbuscontention.
ThePRECHARGEtobanknwillbeginwhentheWRITEtobankmisregistered(FigCAP2).
16.ForaWRITEwithautoprechargeinterruptedbyaREAD(withorwithoutautoprecharge),theREADtobankmwillinterrupt
theWRITEonbanknwhenregistered,withthedata-outappearingCASlatencylater.ThePRECHARGEtobanknwillbegin
after tWR is met, where twrbeginswhentheREADtobankmisregistered.ThelastvalidWRITEtobanknwillbedata-inregis-
teredoneclockpriortotheREADtobankm(FigCAP3).
17.ForaWRITEwithautoprechargeinterruptedbyaWRITE(withorwithoutautoprecharge),theWRITEtobankmwillinterrupt
theWRITEonbanknwhenregistered.ThePRECHARGEtobanknwillbeginaftertwrismet,wheretWRbeginswhenthe
WRITEtobankmisregistered.ThelastvalidWRITEtobanknwillbedataregisteredoneclockpriortotheWRITEtobankm
(FigCAP4).
14 Integrated Silicon Solution, Inc. — www.issi.com
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IS42S16400J
IS45S16400J
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vdd max MaximumSupplyVoltage –1.0to+4.6 V
Vddq max MaximumSupplyVoltageforOutputBuffer –1.0to+4.6 V
ViN InputVoltage –1.0toVddq +0.5 V
Vout OutputVoltage –1.0toVddq +0.5 V
Pd max AllowablePowerDissipation 1 W
Ics output Shorted Current 50 mA
Topr operatingTemperature Com. 0 to +70 °C
Ind. -40 to +85 °C
A1 -40 to +85 °C
A2 -40 to +105 °C
Tstg StorageTemperature –65to+150 °C
DC RECOMMENDED OPERATING CONDITIONS(2)
(AtTa=0to+70°Cforcommercialgrade.Ta=-40to+85°CforindustrialandA1grade.Ta=-40to+105°CforA2grade)
Symbol Parameter Min. Typ. Max. Unit
Vdd, Vddq SupplyVoltage 3.0 3.3 3.6 V
Vih InputHighVoltage(3) 2.0 — Vdd +0.3 V
Vil InputLowVoltage(4) -0.3 — +0.8 V
CAPACITANCE CHARACTERISTICS(1,2) (AtTa=0to+25°C,Vdd=Vddq=3.3±0.3V,f=1MHz)
Symbol Parameter Typ. Max. Unit
CiN InputCapacitance:AddressandControl — 3.8 pF
Cclk InputCapacitance:(CLK) — 3.5 pF
CI/O DataInput/OutputCapacitance:I/O0-I/O15 — 6.5 pF
Notes:
1. StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.Thisisa
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. AllvoltagesarereferencedtoGND.
3.Vih(max)=Vddq+1.2Vwithapulsewidth<3ns.
4.Vil(min)=GND-1.2Vwithapulsewidth<3ns.
Package Substrate Theta-ja
(Airow = 0m/s)
Theta-ja
(Airow = 1m/s)
Theta-ja
(Airow = 2m/s)
Theta-jc Units
    77.4 16.1 C/W
  51.7 49.0 47.7 11.9 C/W
  50.5 44.6 41.7 11.3 C/W
   42.3 41 7.5 C/W
THERMAL RESISTANCE
Integrated Silicon Solution, Inc. — www.issi.com 15
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IS45S16400J
DC ELECTRICAL CHARACTERISTICS 1 (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol Parameter Test Condition -5 -6 -7 Unit
idd1
(1)
OperatingCurrent Onebankactive,CL=3,BL=1, 90 80 70 mA
tclk=tclk (min), trc=trc (min)
idd2p PrechargeStandbyCurrent CKE≤ Vil (max), tck=15ns 2 2 2 mA
(In Power-Down Mode) CS ≥ Vdd-0.2V
idd2ps PrechargeStandbyCurrent CKE≤ Vil (max),CLK≤ Vil (max) 2 2 2 mA
with clock stop CS ≥ Vdd-0.2V
(In Power-Down Mode)
idd2N
(2)
Precharge Standby Current CS ≥ Vdd-0.2V,CKE≥ Vih (miN) 20 20 20 mA
(InNonPower-DownMode) tck=15ns
Idd2Ns Precharge Standby Current CS ≥ Vdd-0.2V,CKE≥ Vih (miN) 10 10 10 mA
with clock stop
(InNonPower-DownMode) All inputs stable
idd3p
(2)
ActiveStandbyCurrent CKE≤ Vil (max), CS ≥ Vdd-0.2V 6 6 6 mA
(In Power-Down Mode) tck=15ns
idd3ps ActiveStandbyCurrent CKE≤ Vil (max),CLK≤ Vil (max), 6 6 6 mA
with clock stop CS ≥ Vdd-0.2V
(In Power-Down Mode)
idd3N
(2)
Active Standby Current CS ≥ Vdd-0.2V,CKE≥ Vih (miN) 25 25 25 mA
(InNonPower-DownMode) tck=15ns
Idd3Ns Active Standby Current CS ≥ Vdd-0.2V,CKE≥ Vih (miN) 20 20 20 mA
with clock stop All inputs stable
(InNonPower-DownMode)
idd4 OperatingCurrent Allbanksactive,BL=4,CL=3, 110 100 90 mA
tck=tck (min)
idd5 Auto-RefreshCurrent trc=trc (min), tclk=tclk(min) 110 100 90 mA
idd6 Self-RefreshCurrent CKE≤ 0.2V 2 2 2 mA
Notes:
1. Idd (max) is specified at the output open condition.
2. Input signals are changed one time during 30ns.
DC ELECTRICAL CHARACTERISTICS 2 (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol Parameter Test Condition Min Max Unit
iil InputLeakageCurrent 0V≤Vin≤Vdd, with pins other than -5 5
µA
thetestedpinat0V
iol OutputLeakageCurrent Outputisdisabled,0V≤Vout≤Vdd, -5 5
µA
Voh OutputHighVoltageLevel Ioh=-2mA 2.4
—
V
Vol OutputLowVoltageLevel Iol=2mA
—
0.4
V
16 Integrated Silicon Solution, Inc. — www.issi.com
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IS42S16400J
IS45S16400J
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-5 -6 -7
Symbol Parameter Min. Max. Min. Max. Min. Max. Units
tck3 ClockCycleTime CASLatency=3 5 — 6 — 7 — ns
tck2 CASLatency=2 7.5 — 7.5 — 7.5 — ns
tac3 AccessTimeFromCLK(4,6) CASLatency=3 — 4.8 — 5.4 — 5.4 ns
tac2 CASLatency=2 — 5.4 — 5.4 — 5.4 ns
tch CLKHIGHLevelWidth 2 — 2 — 2.5 — ns
tcl CLKLOWLevelWidth 2 — 2 — 2.5 — ns
toh3 OutputDataHoldTime(6) CASLatency=3 2.5 — 2.5 — 2.7 — ns
toh2 CAS Latency=2 2.5 — 2.5 — 2.7 — ns
tlz OutputLOWImpedanceTime 0 — 0 — 0 — ns
thz3 OutputHIGHImpedanceTime(5) CASLatency=3 — 4.8 — 5.4 — 5.4 ns
thz2 CASLatency=2 — 5.4 — 5.4 — 5.4 ns
tds InputDataSetupTime 1.5 — 1.5 — 1.5 — ns
tdh InputDataHoldTime 0.8 — 0.8 — 0.8 — ns
tas AddressSetupTime 1.5 — 1.5 — 1.5 — ns
tah AddressHoldTime 0.8 — 0.8 — 0.8 — ns
tcks CKESetupTime 1.5 — 1.5 — 1.5 — ns
tckh CKEHoldTime 0.8 — 0.8 — 0.8 — ns
tcka CKEtoCLKRecoveryDelayTime
1CLK+3
—
1CLK+3
—
1CLK+3
— ns
tcms CommandSetupTime(CS, RAS, CAS, WE, DQM) 1.5 — 1.5 — 1.5 — ns
tcmh CommandHoldTime(CS, RAS, CAS, WE, DQM) 0.8 — 0.8 — 0.8 — ns
trc CommandPeriod(REFtoREF/ACTtoACT) 55 — 60 — 63 — ns
tras CommandPeriod(ACTtoPRE) 40
100,000
42
100,000
42
100,000
ns
trp CommandPeriod(PREtoACT) 15 — 15 — 15 — ns
trcd ActiveCommandToRead/WriteCommandDelayTime 15 — 15 — 15 — ns
trrd CommandPeriod(ACT[0]toACT[1]) 10 — 12 — 14 — ns
tdpl or InputDataToPrecharge CASLatency=3 2CLK — 2CLK — 2CLK — ns
twr Command Delay time
CAS Latency=2 2CLK — 2CLK — 2CLK — ns
tdal InputDataToActive/Refresh CASLatency=3
2CLK+trp
—
2CLK+trp
—
2CLK+trp
— ns
Command Delay time
(During Auto-Precharge) CAS Latency=2
2CLK+trp
—
2CLK+trp
—
2CLK+trp
— ns
tt TransitionTime 0.3 1.2 0.3 1.2 0.3 1.2 ns
txsr ExitSelf-RefreshtoActiveTime 60 — 66 — 70 — ns
tref RefreshCycleTime(4096)
 Ta ≤ 70oC Com., Ind., A1, A2 — 64 — 64 — 64 ms
 Ta ≤ 85oC Ind., A1, A2 — — — 64 — 64 ms
 Ta > 85oC A2 — — — 16 — 16 ms
Notes:
1. Whenpowerisrstapplied,memoryoperationshouldbestarted200µsafterVddandVddq reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.
2. measured with tt =1ns.
3. Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming.RiseandfalltimesaremeasuredbetweenVih (min.)andVil
(max.).
4. Accesstimeismeasuredat1.4Vwiththeloadshowninthegurebelow.
5. Thetimethz (max.)isdenedasthetimerequiredfortheoutputvoltagetotransitionby±200mVfromVoh (min.)orVol (max.)
when the output is in the high impedance state.
6. If clock rising time is longer than 1ns, tt/2 - 0.5ns should be added to the parameter.
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AC TEST CONDITIONS (Input/OutputReferenceLevel:1.4V)
I/O
50 Ω
+1.4V
50 pF
Input Load Output Load
3.0V
1.4V
0V
CLK
INPUT
OUTPUT
t
CH
t
CMH
t
AC
t
OH
t
CMS
t
CK
t
CL
3.0V
1.4V
1.4V 1.4V
0V
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER -5 -6 -7 UNITS
tck ClockCycleTime CL=3 5 6 7 ns
CL=2 7.5 7.5 7.5 ns
Freq. OperatingFrequency CL=3 200 166 143 MHz
CL=2 133 133 133 MHz
tccd READ/WRITEcommandtoREAD/WRITEcommand 1 1 1 cycle
tcked CKEtoclockdisableorpower-downentrymode 1 1 1 cycle
tped CKEtoclockenableorpower-downexitsetupmode 1 1 1 cycle
tdqd DQM to input data delay 0 0 0 cycle
tdqm DQMtodatamaskduringWRITEs 0 0 0 cycle
tdqz DQMtodatahigh-impedanceduringREADs 2 2 2 cycle
tdwd WRITEcommandtoinputdatadelay 0 0 0 cycle
tdal Data-intoACTIVEcommand CL=3 5 5 5 cycle
CL=2 4 4 4 cycle
tdpl Data-intoPRECHARGEcommand 2 2 2 cycle
tbdl Lastdata-intoburstSTOPcommand 1 1 1 cycle
tcdl Lastdata-intonewREAD/WRITEcommand 1 1 1 cycle
trdl Lastdata-intoPRECHARGEcommand 2 2 2 cycle
tmrd LOADMODEREGISTERcommand 2 2 2 cycle
toACTIVEorREFRESHcommand
troh Data-outtohigh-impedancefrom CL=3 3 3 3 cycle
PRECHARGEcommand CL=2 2 2 2 cycle
18 Integrated Silicon Solution, Inc. — www.issi.com
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FUNCTIONAL DESCRIPTION
The64MbSDRAMs(1Megx16x4banks)arequad-bank
DRAMswhichoperateat3.3Vandincludeasynchronous
interface (all signals are registered on the positive edge of
theclocksignal,CLK).Eachofthe16,777,216-bitbanksis
organizedas4,096rowsby256columnsby16bits.
ReadandwriteaccessestotheSDRAMareburstoriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVEcommandwhichisthenfollowedbyaREADorWRITE
command.Theaddressbitsregisteredcoincidentwiththe
ACTIVEcommandareusedtoselectthebankandrowto
be accessed
(BA0andBA1selectthebank,A0-A11selectthe
row)
.Theaddressbits
(A0-A7)
registered coincident with the
READorWRITEcommandareusedtoselectthestarting
column location for the burst access.
Prior to normal operation, the SDRAM must be initial-
ized.Thefollowingsectionsprovidedetailedinformation
covering device initialization, register definition, command
descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The64MbSDRAMisinitializedafterthepowerisapplied
toVddandVddq (simultaneously), and the clock is stable
withDQMHighandCKEHigh.
A100µsdelayisrequiredpriortoissuinganycommand
other than a
COMMANDINHIBIT
or a
NOP
.TheCOMMAND
INHIBITorNOPmaybeappliedduringthe100µsperiodand
continue should at least through the end of the period.
WithatleastoneCOMMANDINHIBITorNOPcommand
havingbeenapplied,aPRECHARGEcommandshould
beappliedoncethe100µsdelayhasbeensatised.All
banksmustbeprecharged.Thiswillleaveallbanksin
an idle state,
afterwhichatleasttwoAUTOREFRESH
cycles
must be performed. After the
AUTOREFRESH
cycles are
complete, the SDRAM is then ready for mode register
programming.
The mode register should be loaded prior to applying
any operational command because it will power up in an
unknownstate.AftertheLoadModeRegistercommand,
at least one NOP command must be asserted prior to
any command.
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REGISTER DEFINITION
Mode Register
The mode register is used to dene the specic mode
ofoperationoftheSDRAM.Thisdenitionincludesthe
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODEREGISTERDEFINITION.
ThemoderegisterisprogrammedviatheLOADMODE
REGISTERcommandandwillretainthestoredinformation
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst
(sequential or interleaved)
, M4- M6
specify the CAS latency, M7 and M8 specify the operating
mode,M9speciestheWRITEburstmode,andM10and
M11 are reserved for future use.
Themoderegistermustbe loaded when all banks are
idle, and the controller must wait the specified time before
initiatingthesubsequentoperation.Violatingeitherofthese
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Latency Mode
M6 M5 M4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
Write Burst Mode
M9 Mode
0 Programmed Burst Length
1 Single Location Access
Operating Mode
M8 M7 M6-M0 Mode
0 0 Defined Standard Operation
— — — All Other States Reserved
Burst Type
M3 Type
0 Sequential
1 Interleaved
Burst Length
M2 M1 M0 M3=0 M3=1
0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Reserved
Address Bus
Mode Register (Mx)
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
(1)
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BURST DEFINITION
Burst Starting Column Order of Accesses Within a Burst
Length Address Type = Sequential Type = Interleaved
A0
2 0 0-1 0-1
1 1-0 1-0
A1 A0
0 0 0-1-2-3 0-1-2-3
4 0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full n=A0-A7 Cn,Cn+1,Cn+2 NotSupported
Page Cn + 3, Cn + 4...
(y) (location 0-y) …Cn - 1,
Cn…
Burst Length
ReadandwriteaccessestotheSDRAMareburstoriented,
with the burst length being programmable, as shown in
MODEREGISTERDEFINITION.Theburstlengthdeter-
mines the maximum number of column locations that can
beaccessedforagivenREADorWRITEcommand.Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page
burst is available for the sequential type.The full-page
burstisusedinconjunctionwiththeBURSTTERMINATE
command to generate arbitrary burst lengths.
Reservedstatesshouldnotbeused,asunknownoperation
or incompatibility with future versions may result.
WhenaREADorWRITEcommandisissued,ablockof
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary
isreached.TheblockisuniquelyselectedbyA1-A7(x16)
when the burst length is set to two; by A2-A7 (x16) when
the burst length is set to four; and by A3-A7 (x16) when the
burstlengthissettoeight.Theremaining(leastsignicant)
address bit(s) is (are) used to select the starting location
withintheblock.Full-pageburstswrapwithinthepageif
the boundary is reached.
Burst Type
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
Theorderingofaccesseswithinaburstisdeterminedby
the burst length, the burst type and the starting column
address,asshowninBURSTDEFINITIONtable.
Integrated Silicon Solution, Inc. — www.issi.com 21
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DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ NOP NOP NOP
CAS Latency - 3
t
AC
t
OH
D
OUT
T0 T1 T2 T3 T4
tLZ
CLK
COMMAND
DQ
READ NOP NOP
CAS Latency - 2
t
AC
t
OH
D
OUT
T0 T1 T2 T3
tLZ
CAS Latency
CAS Latency
TheCAS latencyisthe delay, inclockcycles,between
the
registrationofaREADcommandandtheavailabilityof
therstpieceofoutputdata.Thelatencycanbesettotwoor
three clocks.
IfaREADcommandisregisteredatclockedgen,and
the latency is m clocks, the data will be available by clock
edge n + m.TheDQswillstartdrivingasaresultofthe
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m.Forexample,assumingthattheclock
cycle time is such that all relevant access times are met,
ifaREADcommandisregisteredatT0andthelatency
is programmed to two clocks, the DQs will start driving
afterT1andthedatawillbevalidbyT2,asshowninCAS
Latencydiagrams.TheAllowable Operating Frequency
table indicates the operating frequencies at which each
CAS latency setting can be used.
Reservedstatesshouldnotbeusedasunknownoperation
or incompatibility with future versions may result.
CAS Latency
Allowable Operating Frequency (MHz)
Speed CAS Latency = 2 CAS Latency = 3
-5 133 200
-6 133 166
-7 133 143
Operating Mode
ThenormaloperatingmodeisselectedbysettingM7andM8
to zero; the other combinations of values for M7 and M8 are
reservedforfutureuseand/ortestmodes.Theprogrammed
burstlengthappliestobothREADandWRITEbursts.
Testmodesandreservedstatesshouldnotbeusedbe-
cause unknown operation or incompatibility with future
versions may result.
Write Burst Mode
WhenM9=0,theburstlengthprogrammedviaM0-M2
appliestobothREADandWRITEbursts;whenM9=1,
theprogrammedburstlengthappliestoREADbursts,but
write accesses are single-location (nonburst) accesses.
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Activating Specific Row Within Specific Bank
DON'T CARE
CLK
COMMAND ACTIVE NOP NOP
tRCD
T0 T1 T2 T3 T4
READ or
WRITE
OPERATION
BANK/ROW ACTIVATION
BeforeanyREAD orWRITEcommandscanbeissued
toabankwithintheSDRAM,arowinthatbankmustbe
“opened.”
ThisisaccomplishedviatheACTIVEcommand,
which selects both the bank and the row to be activated
(see
ActivatingSpecicRowWithinSpecicBank
).
After opening a row
(issuinganACTIVEcommand)
,aREAD
orWRITEcommandmaybeissuedtothatrow,subjectto
the trcd specification. Minimum trcd should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
commandonwhichaREADorWRITEcommandcanbe
entered.Forexample,atrcd specification of 20ns with a
125 MHz clock (8ns period) results in 2.5 clocks, rounded
to3.Thisisreectedinthefollowingexample,whichcov-
ersanycasewhere2<[trcd(MIN)/tck] ≤3.(Thesame
procedure is used to convert other specification limits from
time units to clock cycles).
AsubsequentACTIVEcommandtoadifferentrowinthe
same bank can only be issued after the previous active
rowhasbeen“closed”(precharged).Theminimumtime
intervalbetweensuccessiveACTIVEcommandstothe
same bank is defined by trc.
AsubsequentACTIVEcommandtoanotherbankcanbe
issued while the first bank is being accessed, which results
inareductionoftotalrow-accessoverhead.Theminimum
timeintervalbetweensuccessiveACTIVEcommandsto
different banks is defined by trrd.
Example: Meeting tRCD (MIN) when 2 < [tRCD (min)/tCK] ≤ 3
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CLK
CKE HIGH
COLUMN ADDRESS
AUTO PRECHARGE
NO PRECHARGE
CS
RAS
CAS
WE
A0-A7
A10
BA0, BA1 BANK ADDRESS
A8, A9, A11
READ COMMANDREADS
READ bursts are initiated with a READ command, as
shownintheREADCOMMANDdiagram.
Thestartingcolumnandbankaddressesareprovidedwith
theREADcommand,andautoprechargeiseitherenabledor
disabled for that burst access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theburst.ForthegenericREADcommandsusedinthefol-
lowing illustrations, auto precharge is disabled.
DuringREADbursts,thevaliddata-outelementfromthe
starting column address will be available following the
CASlatencyaftertheREADcommand.Eachsubsequent
data-out element will be valid by the next positive clock
edge.The CAS Latency diagram shows general timing
for each possible CAS latency setting.
Uponcompletionofaburst,assumingnoothercommands
havebeeninitiated,theDQswillgoHigh-Z.Afull-pageburst
will continue until terminated. (At the end of the page, it will
wrap to column 0 and continue.)
DatafromanyREADburstmaybetruncatedwithasub-
sequentREADcommand,anddatafromaxed-length
READburstmaybeimmediatelyfollowedbydatafroma
READcommand.Ineithercase,acontinuousowofdata
canbemaintained.Therstdataelementfromthenew
burst follows either the last element of a completed burst
or the last desired data element of a longer burst which
is being truncated.
ThenewREADcommandshouldbeissuedx cycles before
the clock edge at which the last desired data element is
valid, where x equalstheCASlatencyminusone.Thisis
showninConsecutiveREADBurstsforCASlatenciesof
two and three; data element n + 3 is either the last of a
burstoffourorthelastdesiredofalongerburst.The64Mb
SDRAMusesapipelinedarchitectureandthereforedoes
not require the 2n rule associated with a prefetch architec-
ture.AREADcommandcanbeinitiatedonanyclockcycle
followingapreviousREADcommand.Full-speedrandom
read accesses can be performed to the same bank, as
showninRandomREADAccesses,oreachsubsequent
READmaybeperformedtoadifferentbank.
DatafromanyREADburstmaybetruncatedwithasub-
sequent WRITE command, and data from a xed-length
READburstmaybeimmediatelyfollowedbydatafroma
WRITEcommand(subjecttobusturnaroundlimitations).
TheWRITEburstmaybeinitiatedontheclockedgeim-
mediately following the last (or last desired) data element
fromtheREADburst,providedthatI/Ocontentioncanbe
avoided. In a given system design, there may be a pos-
sibilitythatthedevicedrivingtheinputdatawillgoLow-Z
beforetheSDRAMDQsgoHigh-Z.Inthiscase,atleast
a single-cycle delay should occur between the last read
dataandtheWRITEcommand.
TheDQMinputisusedtoavoidI/Ocontention,asshown
inFiguresRW1andRW2.TheDQMsignalmustbeas-
serted (HIGH)atleastthree clocksprior totheWRITE
command (DQM latency is two clocks for output buffers)
tosuppress data-outfromthe READ.OncetheWRITE
commandisregistered,theDQswillgoHigh-Z(orremain
High-Z),regardlessofthestateoftheDQMsignal,provided
theDQMwasactiveontheclockjustpriortotheWRITE
commandthattruncatedtheREADcommand.Ifnot,the
secondWRITEwillbeaninvalidWRITE.Forexample,if
DQMwasLOWduringT4inFigureRW2,thentheWRITEs
atT5andT7wouldbevalid,whiletheWRITEatT6would
be invalid.
TheDQMsignalmustbede-assertedpriortotheWRITE
command (DQM latency is zero clocks for input buffers)
to ensure that the written data is not masked.
Axed-lengthREADburstmaybefollowedby,ortruncated
with, a
PRECHARGE
command to the same bank
(provided
that auto precharge was not activated)
, and a full-page burst
maybetruncatedwithaPRECHARGEcommandtothe
samebank.ThePRECHARGEcommandshouldbeissued
x cycles before the clock edge at which the last desired
data element is valid, where x equals the CAS latency
minusone.ThisisshownintheREADtoPRECHARGE
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DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ NOP NOP NOP
CAS Latency - 3
t
AC
t
OH
D
OUT
T0 T1 T2 T3 T4
tLZ
CLK
COMMAND
DQ
READ NOP NOP
CAS Latency - 2
t
AC
t
OH
D
OUT
T0 T1 T2 T3
tLZ
CAS Latency
diagram for each possible CAS latency; data element n +
3 is either the last of a burst of four or the last desired of
alongerburst.FollowingthePRECHARGEcommand,a
subsequent command to the same bank cannot be issued
until trpismet.Notethatpartoftherowprechargetimeis
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burstwithautoprecharge.ThedisadvantageofthePRE-
CHARGEcommandisthatitrequiresthatthecommand
and address buses be available at the appropriate time to
issuethecommand;theadvantageofthePRECHARGE
command is that it can be used to truncate fixed-length
or full-page bursts.
Full-pageREADburstscanbetruncatedwiththeBURST
TERMINATE command, and xed-length READ bursts
maybetruncatedwithaBURSTTERMINATEcommand,
providedthatautoprechargewasnotactivated.TheBURST
TERMINATEcommandshouldbeissuedx cycles before
the clock edge at which the last desired data element is
valid, where x equalstheCASlatencyminusone.Thisis
shownintheREADBurstTerminationdiagramforeach
possible CAS latency; data element n + 3 is the last desired
data element of a longer burst.
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
NOP NOP NOP READ NOP NOP
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
D
OUT
b
BANK,
COL nBANK,
COL b
CAS Latency - 2
x = 1 cycle
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP READ NOP NOP NOP
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
D
OUT
b
BANK,
COL nBANK,
COL b
CAS Latency - 3
x = 2 cycles
Consecutive READ Bursts
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
READ
READ
READ
READ
NOP NOP
D
OUT
n
D
OUT
b
D
OUT
m
D
OUT
x
BANK,
COL nBANK,
COL b
CAS Latency - 2
BANK,
COL mBANK,
COL x
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
READ
READ
READ
NOP NOP NOP
D
OUT
n
D
OUT
b
D
OUT
m
D
OUT
x
BANK,
COL nBANK,
COL b
CAS Latency - 3
BANK,
COL mBANK,
COL x
Random READ Accesses
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CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
READ
NOP NOP NOP NOP WRITE
BANK,
COL nBANK,
COL b
D
OUT
n
D
IN
b
t
DS
t
HZ
CAS Latency - 3
RW1 - READ to WRITE
RW2 - READ to WRITE
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
NOP NOP NOP NOP NOP WRITE
BANK,
COL n
DIN b
tDS
tHZ
BANK,
COL b
CAS Latency - 2
DOUT n
D
OUT
n+1 D
OUT
n+2
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP NOP NOP ACTIVE
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
BANK a,
COL nBANK a,
ROW
BANK
(a or all)
CAS Latency - 2
x = 1 cycle
t
RP
PRECHARGE
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP NOP NOP ACTIVE
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
BANK,
COL nBANK,
COL b
CAS Latency - 3
x = 2 cycles
t
RP
BANK a,
ROW
PRECHARGE
READ to PRECHARGE
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
NOP NOP NOP NOP NOP
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
BANK a,
COL n
CAS Latency - 2
x = 1 cycle
BURST
TERMINATE
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP NOP NOP NOP
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
BANK,
COL n
CAS Latency - 3
x = 2 cycles
BURST
TERMINATE
READ Burst Termination
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CLK
CKE
HIGH
COLUMN ADDRESS
AUTO PRECHARGE
BANK ADDRESS
CS
RAS
CAS
WE
A0-A7
A10
BA0, BA1
NO PRECHARGE
A8, A9, A11
WRITE Command
Thestartingcolumnandbankaddressesareprovidedwith
theWRITEcommand,andautoprechargeiseitherenabled
or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of
theburst.ForthegenericWRITEcommandsusedinthe
following illustrations, auto precharge is disabled.
DuringWRITEbursts,therstvalid
data-in
element will be
registered coincident
with the
WRITE
command.
Subsequent
data elements will be registered on each successive posi-
tiveclockedge.Uponcompletionofaxed-lengthburst,
assuming no other commands have been initiated, the
DQswillremainHigh-Zandanyadditionalinputdatawill
beignored(seeWRITEBurst).Afull-pageburstwillcon-
tinue until terminated. (At the end of the page, it will wrap
to column 0 and continue.)
DataforanyWRITEburstmaybetruncatedwithasubse-
quentWRITEcommand,anddataforaxed-lengthWRITE
burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on
anyclockfollowingthepreviousWRITEcommand,andthe
data provided coincident with the new command applies to
the new command.
AnexampleisshowninWRITEtoWRITEdiagram.Data
n + 1 is either the last of a burst of two or the last desired
of a longer burst.The 64Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule as-
sociatedwithaprefetcharchitecture.AWRITEcommand
can be initiated on any clock cycle following a previous
WRITEcommand.Full-speedrandomwriteaccesseswithin
a page can be performed to the same bank, as shown in
RandomWRITECycles,oreachsubsequentWRITEmay
be performed to a different bank.
DataforanyWRITEburstmaybetruncatedwithasubse-
quentREADcommand,anddataforaxed-lengthWRITE
burstmaybeimmediatelyfollowedbyasubsequentREAD
command.OncetheREADcommandisregistered,the
datainputswillbeignored,andWRITEswillnotbeex-
ecuted.AnexampleisshowninWRITEtoREAD.Datan
+ 1 is either the last of a burst of two or the last desired
of a longer burst.
Data for a xed-length WRITE burst may be followed
by, ortruncatedwith,a PRECHARGEcommand tothe
same bank (provided that auto precharge was not acti-
vated), and afull-page WRITE burst may be truncated
withaPRECHARGE command tothesame bank.The
PRECHARGEcommandshouldbeissuedtwr after the
clock edge at which the last desired input data element
isregistered.Theautoprechargemoderequiresatwr of
at least one clock plus time, regardless of frequency. In
addition,whentruncatingaWRITEburst,theDQMsignal
must be used to mask input data for the clock edge prior
to,andtheclockedgecoincidentwith,thePRECHARGE
command.AnexampleisshownintheWRITEtoPRE-
CHARGEdiagram.Datan+1 is either the last of a burst
oftwoorthelastdesiredofalongerburst.Followingthe
PRECHARGEcommand,asubsequentcommandtothe
same bank cannot be issued until trp is met.
In the case of a fixed-length burst being executed to comple-
tion, a PRECHARGE command issued at the optimum
time
(as described above)
provides the same operation that
would result from the same fixed-length burst with auto
precharge.Thedisadvantageofthe
PRECHARGE
command
is that it requires that the command and address buses be
available at the appropriate time to issue the command; the
advantageofthePRECHARGEcommandisthatitcanbe
used to truncate fixed-length or full-page bursts.
Fixed-lengthorfull-pageWRITEburstscanbetruncated
withtheBURSTTERMINATEcommand.Whentruncat-
ingaWRITEburst,theinputdataappliedcoincidentwith
theBURSTTERMINATEcommandwillbeignored.The
lastdatawritten(providedthatDQMisLOWatthattime)
will be the input data applied one clock previous to the
BURSTTERMINATEcommand.ThisisshowninWRITE
BurstTermination,wheredatan is the last desired data
element of a longer burst.
WRITEs
WRITEburstsareinitiatedwithaWRITEcommand,as
showninWRITECommanddiagram.
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3
WRITE
NOP
NOP
NOP
D
IN
n
D
IN
n+1
BANK,
COL n
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2
WRITE
NOP
WRITE
D
IN
n
D
IN
n+1
D
IN
b
BANK,
COL nBANK,
COL b
DON'T CARE
WRITE Burst
WRITE to WRITE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3
WRITE
WRITE
WRITE
WRITE
DIN n
DIN b
DIN m
DIN x
BANK,
COL nBANK,
COL bBANK,
COL mBANK,
COL x
Random WRITE Cycles
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
WRITE
NOP
READ
NOP
NOP NOP
D
IN
n
D
IN
n+1
D
OUT
b
D
OUT
b+1
BANK,
COL nBANK,
COL b
CAS Latency - 2
WRITE to READ
WP1 - WRITE to PRECHARGE
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
WRITE
NOP NOP ACTIVE NOP NOP
BANK a,
COL nBANK a,
ROW
BANK
(a or all)
t
WR
t
RP
PRECHARGE
D
IN
n
D
IN
n+1
CAS Latency - 2
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CLK
COMMAND
ADDRESS
DQ
T0 T1 T2
WRITE
DIN n
(DATA )
BANK,
COL n
DON'T CARE
(ADDRESS)
BURST
TERMINATE
NEXT
COMMAND
WRITE Burst Termination
DON'T CARE
CLK
DQM
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
WRITE
NOP NOP NOP ACTIVE NOP
BANK a,
COL nBANK a,
ROW
BANK
(a or all)
t
WR
t
RP
PRECHARGE
D
IN
n
D
IN
n+1
CAS Latency - 3
WP2 - WRITE to PRECHARGE
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CLK
CKE
HIGH
ALL BANKS
BANK SELECT
BANK ADDRESS
CS
RAS
CAS
WE
A0-A9, A11
A10
BA0, BA1
DON'T CARE
CLK
CKE
COMMAND NOP NOP
ACTIVE
≥ t
CKS
t
CKS
All banks idle
Enter
power-down mode
Exit power-down mode
t
RCD
t
RAS
t
RC
Input buffers gated
off
PRECHARGE Command
POWER-DOWN
POWER-DOWN
Power-downoccursifCKEisregisteredLOWcoincident
withaNOPorCOMMANDINHIBITwhennoaccesses
are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in either
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers,excludingCKE,formaximumpowersavingswhile
instandby.Thedevicemaynotremaininthepower-down
state longer than the refresh period (64ms) since no refresh
operations are performed in this mode.
Thepower-downstateisexitedbyregisteringaNOPor
COMMANDINHIBITandCKEHIGHatthedesiredclock
edge (meeting tcks). See figure below.
PRECHARGE
ThePRECHARGEcommand(seegure)isusedtodeac-
tivate the open row in a particular bank or the open row in
allbanks.Thebank(s)willbeavailableforasubsequentrow
access some specified time (trp)afterthePRECHARGE
command is issued. Input A10 determines whether one or
all banks are to be precharged, and in the case where only
onebankistobeprecharged,inputsBA0,BA1selectthe
bank.Whenallbanksaretobeprecharged,inputsBA0,
BA1aretreatedas“Don’tCare.”Onceabankhasbeen
precharged, it is in the idle state and must be activated
priortoanyREADorWRITEcommandsbeingissuedto
that bank.
Integrated Silicon Solution, Inc. — www.issi.com 35
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DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
NOP
WRITE
NOP NOP
BANK a,
COL n
D
IN
n
DIN n+1 DIN n+2
INTERNAL
CLOCK
DON'T CARE
CLK
CKE
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
NOP NOP NOP NOP NOP
BANK a,
COL n
DOUT n
DOUT n+1
D
OUT
n+2
D
OUT
n+3
INTERNAL
CLOCK
CLOCK SUSPEND
Clock suspend mode occurs when a column access/burst
isinprogressandCKEisregisteredLOW.Intheclock
suspendmode,theinternalclockisdeactivated,“freezing”
the synchronous logic.
ForeachpositiveclockedgeonwhichCKEissampled
LOW,thenextinternalpositiveclockedgeissuspended.
Any command or data present on the input pins at the time
of a suspended internal clock edge is ignored; any data
present on the DQ pins remains driven; and burst counters
are not incremented, as long as the clock is suspended.
(See following examples.)
ClocksuspendmodeisexitedbyregisteringCKEHIGH;
the internal clock and related operation will resume on the
subsequent positive clock edge.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
36 Integrated Silicon Solution, Inc. — www.issi.com
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DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
D
OUT
a
D
OUT
a+1
D
OUT
b
D
OUT
b+1
BANK n,
COL aBANK m,
COL b
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
READ - AP
BANK n
READ - AP
BANK m
Page Active READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active READ with Burst of 4 Precharge
Internal States
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
DOUT a
DIN b
DIN b+1
DIN b+2
DIN b+3
BANK n,
COL aBANK m,
COL b
CAS Latency - 3 (BANK n)
t
RP - BANK n tRP - BANK m
WRITE - AP
BANK n
WRITE - AP
BANK m
READ with Burst of 4 Interrupt Burst, Precharge Idle
Page Active WRITE with Burst of 4 Write-Back
Internal States
Page Active
BURST READ/SINGLE WRITE
Theburstread/singlewritemodeisenteredbyprogramming
the write burst mode bit
(M9)
in the mode register to a logic
1. In this mode, all
WRITE
commands result in the access
of a single column location (burst of one), regardless of
theprogrammedburstlength.READcommandsaccess
columns according to the programmed burst length and
sequence,justasinthenormalmodeofoperation(M9
=0).
CONCURRENT AUTO PRECHARGE
Anaccesscommand(READorWRITE)toanotherbank
while an access command with auto precharge enabled is
executingisnotallowedbySDRAMs,unlesstheSDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMssupportCONCURRENTAUTOPRECHARGE.
FourcaseswhereCONCURRENTAUTOPRECHARGE
occurs are defined below.
READ with Auto Precharge
1.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankmwillinterruptaREADonbankn,
CAS latency later.The PRECHARGE to bank n will
beginwhentheREADtobankmisregistered.
2.InterruptedbyaWRITE(withorwithoutautoprecharge):
AWRITEtobankmwillinterruptaREADonbankn
when registered. DQM should be used two clocks prior
totheWRITEcommandtopreventbuscontention.The
PRECHARGEtobanknwillbeginwhentheWRITEto
bank m is registered.
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
Integrated Silicon Solution, Inc. — www.issi.com 37
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DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
D
IN
a
D
IN
a+1
D
OUT
b
D
OUT
b+1
BANK n,
COL aBANK m,
COL b
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
WRITE - AP
BANK n
READ - AP
BANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active READ with Burst of 4 Precharge
Internal States
t
WR
- BANK n
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
BANK n,
COL aBANK m,
COL b
t
RP - BANK n
t
RP - BANK m
WRITE - AP
BANK n
WRITE - AP
BANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active WRITE with Burst of 4 Write-Back
Internal States
t
WR
- BANK n
D
IN
a
D
IN
a+1 D
IN
a+2
D
IN
b
D
IN
b+1 D
IN
b+2 D
IN
b+3
WRITE with Auto Precharge
3.InterruptedbyaREAD(withorwithoutautoprecharge):
AREADtobankm willinterrupta WRITEonbank n
when registered, with the data-out appearing
CAS latency
later.ThePRECHARGEtobanknwillbeginaftertwr
is met, where twrbeginswhentheREADtobankmis
registered.Thelastvalid
WRITE
to bank n will be data-in
registeredoneclockpriortotheREADtobankm.
4.InterruptedbyaWRITE(withorwithoutautoprecharge):
A
WRITE
to bank m will interrupt a
WRITE
on bank n when
registered.ThePRECHARGEtobanknwillbeginafter
twr is met, where twrbeginswhentheWRITEtobank
misregistered.ThelastvaliddataWRITEtobankn
willbedataregisteredoneclockpriortoaWRITEto
bank m.
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
38 Integrated Silicon Solution, Inc. — www.issi.com
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INITIALIZE AND LOAD MODE REGISTER(1)
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CMS
t
CMH
t
CMS
t
CMH
t
CKS
t
CKH
T0 T1 Tn+1 To+1 Tp+1 Tp+2 Tp+3
t
MRD
t
RC
t
RC
t
RP
ROW
ROW
BANK
t
AS
t
AH
t
AS
t
AH
CODE
CODE
ALL BANKS
SINGLE BANK
ALL BANKS
AUTO
REFRESH AUTO
REFRESH Load MODE
REGISTER
T = 100µs Min.
Power-up: V
CC
and CLK stable
Precharge
all banks
AUTO REFRESH Program MODE REGISTER
NOP
PRECHARGE
NOP NOP NOP ACTIVE
T
(2, 3, 4)
AUTO REFRESH
At least 2 Auto-Refresh Commands
Notes:
1. If CSisHighatclockHightime,allcommandsappliedareNOP.
2.TheModeregistermaybeloadedpriortotheAuto-Refreshcyclesifdesired.
3. JEDEC and PC100 specify three clocks.
4.OutputsareguaranteedHigh-Zafterthecommandisissued.
Integrated Silicon Solution, Inc. — www.issi.com 39
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POWER-DOWN MODE CYCLE
CASlatency=2,3
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
AS
t
AH
BANK
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
PRECHARGE
NOP NOP NOP
ACTIVE
ALL BANKS
SINGLE BANK
ROW
ROW
BANK
t
CKS
t
CKS
Precharge all
active banks
All banks idle
Two clock cycles
Input buffers gated
off while in
power-down mode
All banks idle, enter
power-down mode
Exit
p
ower-down mode
T0 T1 T2 Tn+1 Tn+2
High-Z
40 Integrated Silicon Solution, Inc. — www.issi.com
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CLOCK SUSPEND MODE
Notes:
1. CASlatency=3,burstlength=2
2. A8, A9, and A11="Don'tCare"
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tCH
tCLtCK
tCMS tCMH
tCKS tCKH
COLUMN m
(2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
READ NOP NOP NOP NOP NOP WRITE NOP
tCKS tCKH
BANK BANK
COLUMN n
(2)
tAC tAC
tOH
tHZ
D
OUT
m D
OUT
m+1
t
LZ
UNDEFINED
D
OUT
e+1
tDS tDH
D
OUT
e
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AUTO-REFRESH CYCLE
CASlatency=2,3
tRP tRC tRC
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tAS tAH
tCH
tCL
tCK
tCMS tCMH
tCKS tCKH
T0 T1 T2 Tn+1 To +1
ALL BANKS
SINGLE BANK
BANK
(s)
ROW
ROW
BANK
High-Z
PRECHARGE
NOP NOP NOP ACTIVE
Auto
Refresh
Auto
Refresh
42 Integrated Silicon Solution, Inc. — www.issi.com
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SELF-REFRESH CYCLE
Note:
1.Self-RefreshModeisnotsupportedforA2gradewithTa > 85oC.
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tAS tAH
BANK
tCL
tCHtCK
tCMS tCMH
tCKS tCKH
ALL BANKS
SINGLE BANK
tCKS
Precharge all
active banks
CLK stable prior to exiting
self refresh mode
Enter self
refresh
mode
Exit
self refresh
mode
(Restart refresh time base)
T0 T1 T2 Tn+1 To +1 To +2
High-Z
Auto
Refresh Auto
Refresh
PRECHARGE
NOP NOP NOP
tCKS
≥ tRAS
tRP tXSR
DON'T CARE
Integrated Silicon Solution, Inc. — www.issi.com 43
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READ WITH AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ROW
ROW
BANK
COLUMN m
(2)
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
BANK
t
RCD
t
RAS
t
RC
CAS Latency
t
AC
t
AC
t
AC
t
AC
t
OH
t
HZ
t
OH
D
OUT
m
t
OH
D
OUT
m+1
t
OH
D
OUT
m+2 D
OUT
m+3
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
RP
ENABLE AUTO PRECHARGE
ROW
ROW
BANK
tLZ
Notes:
1. CASlatency=2,burstlength=4
2. A8, A9, and A11="Don'tCare"
44 Integrated Silicon Solution, Inc. — www.issi.com
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READ WITHOUT AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP READ NOP NOP NOP
PRECHARGE
NOP ACTIVE
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ROW
ROW
BANK
COLUMN m(2)
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
BANK
t
RCD
CAS Latency
t
AC
t
AC
t
AC
t
AC
tOH
t
HZ
tOH
DOUT m
tOH
DOUT m+1
tOH
DOUT m+2 DOUT m+3
T0 T1 T2 T3 T4 T5 T6 T7 T8
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
t
LZ
t
RAS
t
RC
t
RP
ALL BANKS
SINGLE BANK
BANK
Notes:
1. CASlatency=2,burstlength=4
2. A8, A9, and A11="Don'tCare"
Integrated Silicon Solution, Inc. — www.issi.com 45
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SINGLE READ WITH AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ROW
ROW
BANK
COLUMN m(2)
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
BANK
t
RCD
t
RAS
t
RC
CAS Latency
t
AC
t
HZ
t
OH
DOUT m
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
RP
ENABLE AUTO PRECHARGE
ROW
ROW
BANK
Notes:
1. CASlatency=2,burstlength=1
2. A8, A9, and A11="Don'tCare"
46 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
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SINGLE READ WITHOUT AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP READ NOP NOP
PRECHARGE
NOP ACTIVE NOP
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ROW
ROW
BANK
COLUMN m(2)
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
BANK
t
RCD
t
RAS
t
RC
CAS Latency
t
AC
t
HZ
t
OH
DOUT m
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
RP
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
tLZ
ALL BANKS
SINGLE BANK
BANK
Notes:
1. CASlatency=2,burstlength=1
2. A8, A9, and A11="Don'tCare"
Integrated Silicon Solution, Inc. — www.issi.com 47
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WRITE - WITH AUTO PRECHARGE
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
RCD
t
RAS
t
RC
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
ACTIVE
NOP WRITE NOP NOP NOP NOP NOP NOP
ACTIVE
t
WR
t
RP
COLUMN m
(2)
ROW
BANK BANK
ENABLE AUTO PRECHARGE
ROW
ROW
ROW
BANK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
D
IN
m D
IN
m+
1
D
IN
m+
2
D
IN
m+
3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Notes:
1. burstlength=4
2. A8, A9, and A11="Don'tCare"
48 Integrated Silicon Solution, Inc. — www.issi.com
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WRITE - WITHOUT AUTO PRECHARGE
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tRCD
tRAS
tRC
tCH
tCLtCK
tCMS tCMH
tCKS tCKH
ACTIVE
NOP WRITE NOP NOP NOP
PRECHARGE
NOP
ACTIVE
tWR
(3)
tRP
COLUMN m
(2)
ROW
DISABLE AUTO PRECHARGE
ROW
ROW
ROW
BANK
tDS tDH tDS tDH tDS tDHtDS tDH
DIN m DIN m+
1
DIN m+
2
DIN m+
3
BANK BANK BANK
ALL BANKS
SINGLE BANK
T0 T1 T2 T3 T4 T5 T6 T7 T8
Notes:
1. burstlength=4
2. A8, A9, and A11="Don'tCare"
3. tras must not be violated
Integrated Silicon Solution, Inc. — www.issi.com 49
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
SINGLE WRITE - WITH AUTO PRECHARGE
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
DS
t
DH
t
RCD
t
RAS
t
RC
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
ACTIVE NOP
(3)
NOP
(3)
NOP
(3)
WRITE NOP NOP NOP ACTIVE NOP
t
WR
t
RP
COLUMN m
(2)
ROW
BANK BANK
ENABLE AUTO PRECHARGE
ROW
ROW
ROW
BANK
D
IN
m
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Notes:
1. burstlength=1
2. A8, A9, and A11="Don'tCare"
50 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
SINGLE WRITE - WITHOUT AUTO PRECHARGE
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
DS
t
DH
t
RCD
t
RAS
t
RC
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
ACTIVE NOP WRITE NOP
(4)
NOP
(4)
PRECHARGE
NOP
ACTIVE
NOP
t
WR
(3)
t
RP
DISABLE AUTO PRECHARGE
ROW
ROWROW
ROW
BANK
D
IN
m
COLUMN m
(2)
BANK BANK BANK
ALL BANKS
SINGLE BANK
T0 T1 T2 T3 T4 T5 T6 T7 T8
Notes:
1. burstlength=1
2. A8, A9, and A11="Don'tCare"
3. tras must not be violated
Integrated Silicon Solution, Inc. — www.issi.com 51
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
ALTERNATING BANK READ ACCESSES
BANK 0 BANK 3 BANK 3 BANK 0
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tRCD - BANK 0
CAS Latency - BANK 0
tRCD
- BANK 0
tRAS - BANK 0
tRC - BANK 0
tCH
tCLtCK
tCMS tCMH
tCKS tCKH
ACTIVE
NOP READ NOP
ACTIVE
NOP READ NOP
ACTIVE
ROW
ROW
BANK 0
ROW ROW
tRRD tRCD - BANK 3
tRP - BANK 0
COLUMN m(2)
ROW
COLUMN b(2)
ROW
ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8
tAC
tOH tOH tOH tOH tOH
DOUT m DOUT m+1 DOUT m+2 DOUT m+3 DOUT b
tAC tAC tAC tAC tAC
tLZ
CAS Latency - BANK 3
Notes:
1. CASlatency=2,burstlength=4
2. A8, A9, and A11="Don'tCare"
52 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
READ - FULL-PAGE BURST
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP READ NOP NOP NOP NOP NOP
BURST TERM NOP NOP
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ROW
ROW
BANK
COLUMN m
(2)
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
BANK
t
RCD
CAS Latency
t
AC
t
AC
t
AC
t
AC
t
AC
t
HZ
t
LZ
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
t
OH
D
OUT
m D
OUT
m+1 D
OUT
m+2 D
OUT
m-1 D
OUT
m D
OUT
m+1
each row (x4) has
1,024 locations Full page
completion
Full-page burst not self-terminating.
Use BURST TERMINATE command.
T0 T1 T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4
Notes:
1. CASlatency=2,burstlength=fullpage
2. A8, A9, and A11="Don'tCare"
Integrated Silicon Solution, Inc. — www.issi.com 53
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
READ - DQM OPERATION
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP READ NOP NOP NOP NOP NOP NOP
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
t
RCD
CAS Latency
D
OUT
m
D
OUT
m+2
D
OUT
m+3
COLUMN m
(2)
BANK
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
t
OH
t
OH
t
OH
t
AC
t
AC
t
AC
t
HZ
t
HZ
t
LZ
t
LZ
T0 T1 T2 T3 T4 T5 T6 T7 T8
Notes:
1. CASlatency=2,burstlength=4
2. A8, A9, and A11="Don'tCare"
54 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
ALTERNATING BANK WRITE ACCESS
BANK 0 BANK 1 BANK 1 BANK 0
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tCMS tCMH
tAS tAH
tAS tAH
tAS tAH
tDS tDH tDS tDH tDS tDH
tRCD - BANK 0
tRCD
- BANK 0
tWR
- BANK 1
tRAS - BANK 0
tRC - BANK 0
tCH
tCLtCK
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
tCMS tCMH
tCKS tCKH
ACTIVE NOP WRITE NOP ACTIVE NOP WRITE NOP NOP ACTIVE
DIN m DIN m+
1
DIN m+
2
DIN m+
3
DIN b DIN b+
1
DIN b+
2
DIN b+
3
ROW
ROW
BANK 0
ROW ROW
tRRD tRCD - BANK 1
tWR - BANK 0 tRP - BANK 0
COLUMN m(2)
ROW
COLUMN b(2)
ROW
ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
Notes:
1. burstlength=4
2. A8, A9, and A11="Don'tCare"
Integrated Silicon Solution, Inc. — www.issi.com 55
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP WRITE NOP NOP NOP NOP
BURST TERM NOP
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
ROW
ROW
BANK
t
RCD
D
IN
m D
IN
m+
1
D
IN
m+
2
D
IN
m+
3
D
IN
m-
1
COLUMN m(2)
t
CH
t
CL
t
CK
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
CMS
t
CMH
t
CKS
t
CKH
BANK
Full page completed
T0 T1 T2 T3 T4 T5 Tn+1 Tn+2
WRITE - FULL PAGE BURST
Notes:
1. burstlength=fullpage
2. A8, A9, and A11="Don'tCare"
56 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
DON'T CARE
CLK
CKE
COMMAND
DQM/
DQML, DQMH
A0-A9, A11
A10
BA0, BA1
DQ
tCMS tCMH
ACTIVE NOP WRITE NOP NOP NOP NOP NOP
tAS tAH
tAS tAH
tAS tAH
tDS tDH tDS tDH tDS tDH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
ROW
ROW
BANK
tRCD
DIN m DIN m+
2
DIN m+
3
COLUMN m
(2)
BANK
tCH
tCLtCK
tCMS tCMH
tCKS tCKH
T0 T1 T2 T3 T4 T5 T6 T7
WRITE - DQM OPERATION
Notes:
1. burstlength=4
2. A8, A9, and A11="Don'tCare"
Integrated Silicon Solution, Inc. — www.issi.com 57
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS42S16400J-5TL 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS42S16400J-5BL 54-ballBGA,SnAgCuballs
166MHz 6 IS42S16400J-6TL 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS42S16400J-6BL 54-ballBGA,SnAgCuballs
143MHz 7 IS42S16400J-7TL 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS42S16400J-7BL 54-ballBGA,SnAgCuballs
Industrial Range: -40°C to 85°C
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS42S16400J-5BLI 54-ballBGA,SnAgCuballs
166MHz 6 IS42S16400J-6TLI 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS42S16400J-6BLI 54-ballBGA,SnAgCuballs
143MHz 7 IS42S16400J-7TLI 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS42S16400J-7BLI 54-ballBGA,SnAgCuballs
IS42S16400J-7B2LI 60-ballBGA,SnAgCuballs
Automotive Range (A1): -40°C to 85°C
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS45S16400J-5TLA1 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS45S16400J-5CTLA1 54-PinTSOPII,Cu leadframe plated with matte Sn
IS45S16400J-5BLA1 54-ballBGA,SnAgCuballs
166MHz 6 IS45S16400J-6TLA1 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS45S16400J-6CTLA1 54-PinTSOPII,Cu leadframe plated with matte Sn
IS45S16400J-6BLA1 54-ballBGA,SnAgCuballs
143MHz 7 IS45S16400J-7TLA1 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS45S16400J-7CTLA1 54-PinTSOPII,Cu leadframe plated with matte Sn
IS45S16400J-7BLA1 54-ballBGA,SnAgCuballs
Notes:
1. Contact ISSI for leaded and copper leadframe parts support.
2.Partnumberswith"L"or"N"areleadfree,andRoHScompliant.
Frequency Speed (ns) OrderPartNo. Package
166 MHz 6 IS45S16400J-6CTLA2 54-PinTSOPII,CuleadframeplatedwithmatteSn
IS45S16400J-6BLA2 54-ballBGA,SnAgCuballs
143 MHz 7 IS45S16400J-7TLA2 54-PinTSOPII,Alloy42leadframeplatedwithmatteSn
IS45S16400J-7CTLA2 54-PinTSOPII,CuleadframeplatedwithmatteSn
IS45S16400J-7BLA2 54-ballBGA,SnAgCuballs
Automotive Range (A2): -40°C to 105°C
58 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
Integrated Silicon Solution, Inc. — www.issi.com 59
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
Package Outline 10/17/2007
60 Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
IS42S16400J
IS45S16400J