1.2 A, 20 V, 700 kHz/1.4 MHz,
Nonsynchronous Step-Down Regulator
Data Sheet
ADP2300/ADP2301
Rev. B
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FEATURES
1.2 A maximum load current
±2% output accuracy over temperature range
Wide input voltage range: 3.0 V to 20 V
700 kHz (ADP2300) or 1.4 MHz (ADP2301)
switching frequency options
High efficiency up to 91%
Current-mode control architecture
Output voltage from 0.8 V to 0.85 × VIN
Automatic PFM/PWM mode switching
Precision enable pin with hysteresis
Integrated high-side MOSFET
Integrated bootstrap diode
Internal compensation and soft start
Minimum external components
Undervoltage lockout (UVLO)
Overcurrent protection (OCP) and thermal shutdown (TSD)
Available in ultrasmall, 6-lead TSOT package
Supported by ADIsimPower™ design tool
APPLICATIONS
LDO replacement for digital load applications
Intermediate power rail conversion
Communications and networking
Industrial and instrumentation
Healthcare and medical
Consumer
TYPICAL APPLICATIONS CIRCUIT
3.0V TO 20V VIN BST
SW
FB
VOUT
EN
ON
OFF GND
ADP2300/
ADP2301
08342-001
Figure 1.
60
65
70
75
80
85
90
95
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
IOUT (A)
VIN = 12V
VOUT = 5. 0V
fSW = 1.4MHz
fSW = 700kHz
08342-069
Figure 2. Efficiency vs. Output Current
GENERAL DESCRIPTION
The ADP2300/ADP2301 are compact, constant-frequency,
current-mode, step-down dc-to-dc regulators with integrated
power MOSFET. The ADP2300/ADP2301 devices run from
input voltages of 3.0 V to 20 V, making them suitable for a wide
range of applications. A precise, low voltage internal reference
makes these devices ideal for generating a regulated output
voltage as low as 0.8 V, with ±2% accuracy, for up to 1.2 A load
current.
There are two frequency options: the ADP2300 runs at 700 kHz,
and the ADP2301 runs at 1.4 MHz. These options allow users to
make decisions based on the trade-off between efficiency and
total solution size. Current-mode control provides fast and stable
line and load transient performance. The ADP2300/ADP2301
devices include internal soft start to prevent inrush current at
power-up. Other key safety features include short-circuit protec-
tion, thermal shutdown (TSD), and input undervoltage lockout
(UVLO). The precision enable pin threshold voltage allows the
ADP2300/ADP2301 to be easily sequenced from other input/
output supplies. It can also be used as a programmable UVLO
input by using a resistive divider.
The ADP2300/ADP2301 are available in a 6-lead TSOT package
and are rated for the −40°C to +125°C junction temperature range.
ADP2300/ADP2301 Data Sheet
Rev. B | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Applications Circuit ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Functional Block Diagram ............................................................ 13
Theory of Operation ...................................................................... 14
Basic Operation .......................................................................... 14
PWM Mode ................................................................................. 14
Power Saving Mode .................................................................... 14
Bootstrap Circuitry .................................................................... 14
Precision Enable ......................................................................... 14
Integrated Soft Start ................................................................... 14
Current Limit .............................................................................. 14
Short-Circuit Protection ............................................................ 15
Undervoltage Lockout (UVLO) ............................................... 15
Thermal Shutdown ..................................................................... 15
Control Loop ............................................................................... 15
Applications Information .............................................................. 16
ADIsimPower Design Tool ....................................................... 16
Programming the Output Voltage ........................................... 16
Voltage Conversion Limitations ............................................... 16
Low Input Voltage Considerations .......................................... 17
Programming the Precision Enable ......................................... 17
Inductor ....................................................................................... 18
Catch Diode ................................................................................ 19
Input Capacitor ........................................................................... 19
Output Capacitor ........................................................................ 19
Thermal Considerations ............................................................ 20
Design Example .............................................................................. 21
Switching Frequency Selection ................................................. 21
Catch Diode Selection ............................................................... 21
Inductor Selection ...................................................................... 21
Output Capacitor Selection....................................................... 21
Resistive Voltage Divider Selection .......................................... 22
Circuit Board Layout Recommendations ................................... 23
Typical Application Circuits ......................................................... 24
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/12—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Added ADIsimPower Design Tool Section ................................. 16
6/10—Rev. 0 to Rev. A
Changes to Figure 54 ...................................................................... 25
Changes to Ordering Guide .......................................................... 26
2/10—Revision 0: Initial Version
Data Sheet ADP2300/ADP2301
Rev. B | Page 3 of 28
SPECIFICATIONS
VIN = 3.3 V, T J = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions Min Typ Max Unit
VIN
Voltage Range
3
20
V
Supply Current I
No switching, V
IN
= 12 V 640 800 µA
Shutdown Current I
V
EN
= 0 V, V
IN
= 12 V 18 35 µA
Undervoltage Lockout Threshold UVLO V
IN
rising 2.80 2.95 V
V
IN
falling 2.15 2.40 V
FB
Regulation Voltage V
T
J
= 0°C to +125°C 0.788 0.800 0.812 V
T
J
= −40°C to +125°C 0.784 0.800 0.816 V
Bias Current I
0.01 0.1 µA
SW
On Resistance1 V
BST
− V
SW
= 5 V, I
SW
= 150 mA 440 700 mΩ
Peak Current Limit2 V
BST
− V
SW
= 5 V, V
IN
= 12 V 1.5 1.9 2.5 A
Minimum On Time 100 135 ns
Minimum Off Time ADP2300 145 190 ns
ADP2301 70 120 ns
OSCILLATOR FREQUENCY ADP2300 0.5 0.7 0.9 MHz
ADP2301 1.0 1.4 1.75 MHz
SOFT START TIME ADP2300 1460 µs
ADP2301 730 µs
EN
Input Threshold
1.13
1.2
1.27
V
Input Hysteresis 100 mV
Pull-Down Current 1.2 µA
BOOTSTRAP VOLTAGE V
No switching, V
IN
= 12 V 5.0 V
THERMAL SHUTDOWN
Threshold 140 °C
Hysteresis 15 °C
1 Pin-to-pin measurements.
2 Guaranteed by design.
ADP2300/ADP2301 Data Sheet
Rev. B | Page 4 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VIN, EN −0.3 V to +28 V
SW
−1.0 V to +28 V
BST to SW
−0.6 V to +6 V
BST −0.3 V to +28 V
FB −0.3 V to +3.3 V
Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all voltages are
referenced to GND.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance1
Package Type θ
JA
θ
JC
Unit
6-Lead TSOT 186.02 66.34 °C/W
1 θJA and θJC are measured using natural convection on a JEDEC 4-layer board.
ESD CAUTION
Data Sheet ADP2300/ADP2301
Rev. B | Page 5 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP2300/
ADP2301
TOP VIEW
(Not t o Scale)
1
2
3
6
5
4
08342-002
SW
VIN
EN
BST
GND
FB
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 BST Boost Supply for the High-Side MOSFET Driver. A 0.1 µF capacitor is connected between the SW and BST pins
to form a floating supply to drive the gate of the MOSFET switch above the V
IN
supply voltage.
2
GND
Ground. Connect this pin to the ground plane.
3 FB Feedback Voltage Sense Input. Connect this pin to a resistive divider from VOUT. Set the voltage to 0.8 V for a
desired V
OUT
.
4 EN Output Enable. Pull this pin high to enable the output. Pull this pin low to disable the output. This pin can
also be used as a programmable UVLO input. This pin has a 1.2 µA pull-down current to GND.
5 VIN Power Input. Connect to the input power source with a ceramic bypass capacitor to GND directly from this pin.
6 SW Switch Node Output. Connect an inductor to V
OUT
and a catch diode to GND from this pin.
ADP2300/ADP2301 Data Sheet
Rev. B | Page 6 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.3 V, T A = 25°C, VEN = VIN, unless otherwise noted.
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
I
OUT
(A)
INDUCTOR: LPS 6225- 472M LC
DIODE: B230A
V
OUT
= 12V
V
OUT
= 9V
V
OUT
= 5.0V
V
OUT
= 3.3V
08342-070
Figure 4. Efficiency Curve, VIN = 18 V, fSW = 1.4 MHz
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
I
OUT
(A)
V
OUT
= 12V
V
OUT
= 9V
V
OUT
= 5.0V
V
OUT
= 3.3V
INDUCTOR: LPS 6225- 103M LC
DIODE: B230A
08342-071
Figure 5. Efficiency Curve, VIN = 18 V, fSW = 700 kHz
I
OUT
(A)
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
V
OUT
= 5.0V
V
OUT
= 3.3V
V
OUT
= 2.5V
INDUCTOR: LPS 6225- 472M LC
DIODE: B230A
08342-072
Figure 6. Efficiency Curve, VIN = 12 V, fSW = 1.4 MHz
IOUT (A)
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
VOUT = 5. 0V
VOUT = 3. 3V
VOUT = 2. 5V
VOUT = 1. 8V
VOUT = 1. 2V
INDUCTOR: LPS 6225- 103M LC
DIODE: B230A
08342-073
Figure 7. Efficiency Curve, VIN = 12 V, fSW = 700 kHz
I
OUT
(A)
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
= 1.2V
INDUCTOR: LPS 6225- 472M LC
DIODE: B230A
08342-074
Figure 8. Efficiency Curve, VIN = 5.0 V, fSW = 1.4 MHz
IOUT (A)
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
VOUT = 2. 5V
VOUT = 1. 8V
VOUT = 1. 2V
INDUCTOR: LPS 6225- 103M LC
DIODE: B230A
08342-075
Figure 9. Efficiency Curve, VIN = 5.0 V, fSW = 700 kHz
Data Sheet ADP2300/ADP2301
Rev. B | Page 7 of 28
08342-089
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
I
OUT
(A)
V
OUT
= 1.8V
V
OUT
= 1.2V
V
OUT
= 0.8V
INDUCTOR: LPS 6225- 472M LC
DIODE: B230A
Figure 10. Efficiency Curve, VIN = 3.3 V with External 5.0 V Bootstrap Bias
Voltage, fSW = 1.4 MHz
40
50
60
70
80
90
100
00.2 0.4 0.6 0.8 1.0 1.2
EFFICIENCY (%)
VOUT = 1. 8V
VOUT = 1. 2V
VOUT = 0. 8V
INDUCTOR: LPS 6225- 103M LC
DIODE: B230A
IOUT (A)
08342-066
Figure 11. Efficiency Curve, VIN = 3.3 V with External 5.0 V Bootstrap Bias
Voltage, fSW = 700 kHz
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.200.4 0.6 0.8 1.0 1.2
LOAD REG UL ATION (%)
F
SW
= 1.4M Hz
F
SW
= 700kHz
I
OUT
(A)
08342-067
Figure 12. Load Regulation, VOUT = 3.3 V, VIN = 12 V
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
5 8 11 14 17 20
LINE REGULATION (%)
fSW
= 1.4M Hz
fSW
= 700kHz
V
IN
(V)
08342-068
Figure 13. Line Regulation, VOUT = 3.3 V, IOUT = 500 mA
400
600
800
1000
1200
1400
1600
–50 –20 10 40 70 100 130
FREQUENCY (kHz)
TEMPERAT URE ( °C)
fSW
= 1.4M Hz
fSW
= 700kHz
08342-076
Figure 14. Frequency vs. Temperature
400
600
800
1000
1200
1400
1600
FREQUENCY (kHz)
f
SW
= 1.4M Hz
f
SW
= 700kHz
2 5 8 11 14 17 20
V
IN
(V)
08342-077
Figure 15. Frequency vs. VIN
ADP2300/ADP2301 Data Sheet
Rev. B | Page 8 of 28
0
5
10
15
20
25
30
35
40
2 5 8 11 14 17 20
SHUT DOWN CURRE NT (µA)
VIN (V)
TJ = −40°C
TJ = +25°C
TJ = +125°C
08342-078
Figure 16. Shutdown Current vs. VIN
0.792
0.794
0.796
0.798
0.800
0.802
0.804
–50 –20 10 40 70 100 130
0.8V FEEDBACK V OLTAGE (V)
TEMPERAT URE ( °C)
08342-079
Figure 17. 0.8 V Feedback Voltage vs. Temperature
80
85
90
95
100
105
110
MINIMUM ON TIME (n s)
–50 –20 10 40 70 100 130
TEMPERAT URE ( °C)
08342-080
Figure 18. Minimum On Time vs. Temperature
0
20
40
60
80
100
120
140
160
–50 –20 10 40 70 100 130
MINIMUM OFF TIME (ns)
fSW
= 1.4M Hz
fSW
= 700kHz
TEMPERAT URE ( °C)
08342-081
Figure 19. Minimum Off Time vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
2 5 8 11 14 17 20
CURRENT LIM IT ( A)
V
IN
(V)
08342-082
Figure 20. Current-Limit Threshold vs. VIN, VBST − VSW = 5.0 V
–50 –20 10 40 70 100 130
0
0.5
1.0
1.5
2.0
2.5
CURRENT LIM IT ( A)
TEMPERAT URE ( °C)
08342-083
Figure 21. Current-Limit Threshold vs. Temperature
Data Sheet ADP2300/ADP2301
Rev. B | Page 9 of 28
500
540
580
620
660
700
QUIESCE NT CURRENT (µA)
2 5 8 11 14 17 20
V
IN (V)
TJ
= −40°C
T
J
= +25°C
T
J
= +125°C
08342-084
Figure 22. Quiescent Current vs. VIN
0
100
200
300
400
500
600
700
800
900
–50 –20 10 40 70 100 130
MOSFET R
DS (ON)
(mΩ)
V
GS
= 5V
V
GS = 4V
VGS = 3V
TEMPERAT URE ( °C)
08342-085
Figure 23. MOSFET RDS(ON) vs. Temperature (Pin-to-Pin Measurements)
1.00
1.05
1.10
1.15
1.20
1.25
1.30
–50 –20 10 40 70 100 130
ENABL E THRESHOL D ( V )
RISING
FALLING
TEMPERAT URE ( °C)
08342-086
Figure 24. Enable Threshold vs. Temperature
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
–50 –20 10 40 70 100 130
UVL O THRE S HOL D ( V )
RISING
FALLING
TEMPERAT URE ( °C)
08342-087
Figure 25. UVLO Threshold vs. Temperature
CH1 5mV CH4 500mAΩ
CH2 5V M400ns A CH2 7.4V
2
4
1
BWBWBW
V
OUT
IL
SW
08342-024
Figure 26. Steady State at Heavy Load, fSW = 1.4 MHz, IOUT = 1 A
CH1 20mV CH4 200mAΩ
CH2 5V M10µs A CH2 8V
2
4
1
BWBWBW
V
OUT
IL
SW
08342-025
Figure 27. Steady State at Light Load, fSW = 1.4 MHz, IOUT = 40 mA
ADP2300/ADP2301 Data Sheet
Rev. B | Page 10 of 28
CH1 1V CH4 500m AΩ
CH2 10V M100µs A CH3 8V
2
4
3
1
BW
CH3 10V
BW
BW
BW
V
OUT
IL
EN
SW
08342-026
Figure 28. Soft Start with 1 A Resistance Load, fSW = 1.4 MHz
CH1 1V CH4 500m AΩ
CH2 10V M100µs A CH3 8V
2
4
3
1
BW
CH3 10V
BW
BW
BW
V
OUT
IL
EN
SW
08342-027
Figure 29. Soft Start with No Load, fSW = 1.4 MHz
08342-057
2
1
4
V
OUT
I
OUT
SW
CH1 100mV CH4 500mA Ω
CH2 10V M100µs A CH4 580mA
BWBW
BW
Figure 30. ADP2301 Load Transient, 0.2 A to 1.0 A, VOUT = 5.0 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 µH, COUT = 10 µF)
08342-058
2
1
4
V
OUT
I
OUT
SW
CH1 50mV CH4 500mA Ω
CH2 10V M100µs A CH4 630mA
BWBW
BW
Figure 31. ADP2301 Load Transient, 0.2 A to 1.0 A, VOUT = 3.3 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 µH, COUT = 22 µF)
08342-059
2
1
4
V
OUT
I
OUT
SW
CH1 200mV CH4 500mA Ω
CH2 10V M100µs A CH4 630mA
BWBW
BW
Figure 32. ADP2300 Load Transient, 0.2 A to 1.0 A, VOUT = 5.0 V, VIN = 12 V
(fSW = 700 kHz, L = 10 µH, COUT = 22 µF)
08342-060
2
1
4
V
OUT
I
OUT
SW
CH1 100mV CH4 500mA Ω
CH2 10V M100µs A CH4 630mA
BWBW
BW
Figure 33. ADP2300 Load Transient, 0.2 A to 1.0 A, VOUT = 3.3 V, VIN = 12 V
(fSW = 700 kHz, L = 10 µH, COUT = 22 µF)
Data Sheet ADP2300/ADP2301
Rev. B | Page 11 of 28
08342-061
1
3
V
OUT
V
IN
SW
CH1 5mV
CH3 5V CH2 10V M1ms A CH3 11.4V
BWBW
2
Figure 34. ADP2301 Line Transient,
7 V to 15 V, VOUT = 3.3 V, IOUT = 1.2 A, fSW = 1.4 MHz
CH1 1V CH4 1A Ω
CH2 10V M10µs A CH1 2.56V
2
4
1
BWBW
BW
V
OUT
SW
08342-033
IL
Figure 35. ADP2301 Short-Circuit Entry, VOUT = 3.3 V
(fSW = 1.4 MHz)
CH1 1V CH4 1AΩ
CH2 10V M100µs A CH1 1.2V
2
4
1
BWBW
BW
V
OUT
SW
08342-034
IL
Figure 36. ADP2301 Short-Circuit Recovery, VOUT = 3.3 V
(fSW = 1.4 MHz)
–100
–80
–60
–40
–20
0
20
40
60
80
100
–200
–160
–120
–80
–40
0
40
80
120
160
200
1k 10k 100k
1 2 1M
08342-062
MAG NITUDE [ B/A] ( dB)
PHASE [ B/A] (Degrees)
CROS S FREQ UE NCY: 127kHz
PHASE M ARGIN: 53°
FRE QUENCY ( Hz )
Figure 37. ADP2301 Bode Plot, VOUT = 5.0 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 µH, COUT = 10 µF)
08342-063
–100
–80
–60
–40
–20
0
20
40
60
80
100
–200
–160
–120
–80
–40
0
40
80
120
160
200
1k 10k 100k 21M
MAG NITUDE [ B/A] ( dB)
PHASE [ B/A] (Degrees)
CROS S FREQ UE NCY: 80kHz
PHASE M ARGIN: 68°
1
FRE QUENCY ( Hz )
Figure 38. ADP2301 Bode Plot, VOUT = 3.3 V, VIN = 12 V
(fSW = 1.4 MHz, L = 4.7 µH, COUT = 22 µF)
08342-064
–100
–80
–60
–40
–20
0
20
40
60
80
100
–200
–160
–120
–80
–40
0
40
80
120
160
200
1k 10k 100k
1 2 1M
MAG NITUDE [ B/A] ( dB)
PHASE [ B/A] (Degrees)
CROS S FREQ UE NCY: 27kHz
PHASE M ARGIN: 76°
FRE QUENCY ( Hz )
Figure 39. ADP2300 Bode Plot, VOUT = 5.0 V, VIN = 12 V
(fSW = 700 kHz, L = 10 µH, COUT = 22 µF)
ADP2300/ADP2301 Data Sheet
Rev. B | Page 12 of 28
08342-065
–100
–80
–60
–40
–20
0
20
40
60
80
100
–200
–160
–120
–80
–40
0
40
80
120
160
200
1k 10k 100k
FRE QUENCY ( Hz )
1 2
1M
MAG NITUDE [ B/A] ( dB)
PHASE [ B/A] (Degrees)
CROS S FREQ UE NCY: 47kHz
PHASE M ARGIN: 77°
Figure 40. ADP2300 Bode Plot, VOUT = 3.3 V, VIN = 12 V
(fSW = 700 kHz, L = 10 µH, COUT = 22 µF)
Data Sheet ADP2300/ADP2301
Rev. B | Page 13 of 28
FUNCTIONAL BLOCK DIAGRAM
1
6
2
5
4
3
VIN
VIN
OCP250mV/A
0.5V
OVP
THERMAL
SHUTDOWN SHUTDOWN
LOGIC UVLO
BOOT
REGULATOR
CLK
GENERATOR
FREQUENCY FOLDBACK
(fSW, ½ fSW, ¼ fSW)
R
S
Q
RAMP
GENERATOR
SHUT DOWN IC
0.90V
1.20V
1.2µA
0.8V
90pF
0.7pF
220kΩ
ON
EN
OFF
VBIAS = 1.1V
V
FB
BST
GND
SW
V
OUT
08342-038
ADP2300/ADP2301
FB
Figure 41. ADP2300/ADP2301 Functional Block Diagram
ADP2300/ADP2301 Data Sheet
Rev. B | Page 14 of 28
THEORY OF OPERATION
The ADP2300/ADP2301 are nonsynchronous, step-down
dc-to-dc regulators, each with an integrated high-side power
MOSFET. A high switching frequency and ultrasmall, 6-lead
TSOT package allow small step-down dc-to-dc regulator
solutions.
The ADP2300/ADP2301 can operate with an input voltage from
3.0 V to 20 V while regulating an output voltage down to 0.8 V.
The ADP2300/ADP2301 are available in two fixed-frequency
options: 700 kHz (ADP2300) and 1.4 MHz (ADP2301).
BASIC OPERATION
The ADP2300/ADP2301 use the fixed-frequency, peak current-
mode PWM control architecture at medium to high loads, but
shift to a pulse-skip mode control scheme at light loads to reduce
the switching power losses and improve efficiency. When the
devices operate in fixed-frequency PWM mode, output regulation
is achieved by controlling the duty cycle of the integrated MOSFET.
When the devices operate in pulse-skip mode at light loads, the
output voltage is controlled in a hysteretic manner with higher
output ripple. In this mode of operation, the regulator periodically
stops switching for a few cycles, thus keeping the conversion
losses minimal to improve efficiency.
PWM MODE
In PWM mode, the ADP2300/ADP2301 operate at a fixed
frequency, set by an internal oscillator. At the start of each
oscillator cycle, the MOSFET switch is turned on, sending a
positive voltage across the inductor. The inductor current
increases until the current-sense signal crosses the peak
inductor current threshold that turns off the MOSFET switch;
this threshold is set by the error amplifier output. During the
MOSFET off time, the inductor current declines through the
external diode until the next oscillator clock pulse starts a new
cycle. The ADP2300/ADP2301 regulate the output voltage by
adjusting the peak inductor current threshold.
POWER SAVING MODE
To achieve higher efficiency, the ADP2300/ADP2301 smoothly
transition to the pulse-skip mode when the output load decreases
below the pulse-skip current threshold. When the output voltage
dips below regulation, the ADP2300/ADP2301 enter PWM mode
for a few oscillator cycles until the voltage increases to within
regulation. During the idle time between bursts, the MOSFET
switch is turned off, and the output capacitor supplies all the
output current.
Since the pulse-skip mode comparator monitors the internal
compensation node, which represents the peak inductor current
information, the average pulse-skip load current threshold depends
on the input voltage (VIN), the output voltage (VOUT), the inductor,
and the output capacitor.
Because the output voltage occasionally dips below regulation
and then recovers, the output voltage ripple in the power saving
mode is larger than the ripple in the PWM mode of operation.
BOOTSTRAP CIRCUITRY
The ADP2300/ADP2301 each have an integrated boot regulator,
which requires that a 0.1 µF ceramic capacitor (X5R or X7R) be
placed between the BST and SW pins to provide the gate drive
voltage for the high-side MOSFET. There must be at least a 1.2 V
difference between the BST and SW pins to turn on the high-side
MOSFET. This voltage should not exceed 5.5 V in case the BST
pin is supplied with an external voltage source through a diode.
The ADP2300/ADP2301 generate a typical 5.0 V bootstrap voltage
for a gate drive circuit by differentially sensing and regulating the
voltage between the BST and SW pins. A diode integrated on the
chip blocks the reverse voltage between the VIN and BST pins
when the MOSFET switch is turned on.
PRECISION ENABLE
The ADP2300/ADP2301 feature a precision enable circuit that
has a 1.2 V reference voltage with 100 mV hysteresis. When the
voltage at the EN pin is greater than 1.2 V, the part is enabled. If the
EN voltage falls below 1.1 V, the chip is disabled. The precision
enable threshold voltage allows the ADP2300/ADP2301 to be
easily sequenced from other input/output supplies. It can also be
used as programmable UVLO input by using a resistive divider.
An internal 1.2 µA pull-down current prevents errors if the EN pin
is floating.
INTEGRATED SOFT START
The ADP2300/ADP2301 include internal soft start circuitry
that ramps the output voltage in a controlled manner during
startup, thereby limiting the inrush current. The soft start time is
typically fixed at 1460 µs for the ADP2300 and at 730 µs for the
ADP2301.
CURRENT LIMIT
The ADP2300/ADP2301 include current-limit protection circuitry
to limit the amount of positive current flowing through the high-
side MOSFET switch. The positive current limit on the power
switch limits the amount of current that can flow from the input
to the output.
Data Sheet ADP2300/ADP2301
Rev. B | Page 15 of 28
SHORT-CIRCUIT PROTECTION
The ADP2300/ADP2301 include frequency foldback to prevent
output current runaway when there is a hard short on the output.
The switching frequency is reduced when the voltage at the FB pin
drops below a certain value, which allows more time for the
inductor current to decline, but increases the ripple current while
regulating the peak current. This results in a reduction in average
output current and prevents output current runaway. The corre-
lation between the switching frequency and the FB pin voltage
is shown in Table 5.
Table 5. Correlation Between the Switching Frequency
and the FB Pin Voltage
FB Pin Voltage Switching Frequency
V
FB
≥ 0.6 V f
SW
0.6 V > VFB > 0.2 V ½ fSW
V
FB
≤ 0.2 V ¼ f
SW
When a hard short (VFB ≤ 0.2 V) is removed, a soft start cycle
is initiated to regulate the output back to its level during normal
operation, which helps to limit the inrush current and prevent
possible overshoot on the output voltage.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP2300/ADP2301 have fixed, internally set undervoltage
lockout circuitry. If the input voltage drops below 2.4 V, the
ADP2300/ADP2301 shut down and the MOSFET switch turns
off. After the voltage rises again above 2.8 V, the soft start
period is initiated, and the part is enabled.
THERMAL SHUTDOWN
If the ADP2300/ADP2301 junction temperature rises above 140°C,
the thermal shutdown circuit disables the chip. Extreme junction
temperature can be the result of high current operation, poor
circuit board design, or high ambient temperature. A 15°C
hysteresis is included so that when thermal shutdown occurs,
the ADP2300/ADP2301 do not return to operation until the on-
chip temperature drops below 125°C. After the devices recover
from thermal shutdown, a soft start is initiated.
CONTROL LOOP
The ADP2300/ADP2301 are internally compensated to minimize
external component count and cost. In addition, the built-in
slope compensation helps to prevent subharmonic oscillations
when the ADP2300/ADP2301 operate at a duty cycle greater
than or close to 50%.
ADP2300/ADP2301 Data Sheet
Rev. B | Page 16 of 28
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
The ADP2300/ADP2301 are supported by the ADIsimPower
design tool set. ADIsimPower is a collection of tools that produce
complete power designs optimized for a specific design goal.
The tools enable the user to generate a full schematic and bill of
materials, and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and parts count
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For
more information about ADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board
through the tool.
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage of the ADP2300/ADP2301 is externally set by
a resistive voltage divider from the output voltage to the FB pin,
as shown in Figure 42. Suggested resistor values for the typical
output voltage setting are listed in Table 6. The equation for the
output voltage setting is
+×=
2
1
1V800.0
FB
FB
OUT R
R
V
where:
VOUT is the output voltage.
RFB1 is the feedback resistor from VOUT to FB.
RFB2 is the feedback resistor from FB to GND.
ADP2300/
ADP2301
V
OUT
R
FB1
R
FB2
FB
08342-039
Figure 42. Programming the Output Voltage Using a Resistive Voltage Divider
Table 6. Suggested Values for Resistive Voltage Divider
V
OUT
(V) R
FB1
(kΩ), ±1% R
FB2
(kΩ), ±1%
1.2 4.99 10
1.8 12.7 10.2
2.5 21.5 10.2
3.3 31.6 10.2
5.0 52.3 10
VOLTAGE CONVERSION LIMITATIONS
There are both lower and upper output voltage limitations for a
given input voltage due to the minimum on time, the minimum
off time, and the bootstrap dropout voltage.
The lower limit of the output voltage is constrained by the finite,
controllable minimum on time, which can be as high as 135 ns for
the worst case. By considering the variation of both the switching
frequency and the input voltage, the equation for the lower limit
of the output voltage is
DD
INSW
ONMIN
OUT VVVftV
−+××=
)( (max)(max)
-
(min)
where:
VIN(max) is the maximum input voltage.
fSW(max) is the maximum switching frequency for the worst case.
tMIN-ON is the minimum controllable on time.
VD is the diode forward drop.
The upper limit of the output voltage is constrained by the mini-
mum controllable off time, which can be as high as 120 ns in
the ADP2301 for the worst case. By considering the variation of
both the switching frequency and the input voltage, the equation
for the upper limit of the output voltage is
DD
INSW
OFFMIN
OUT
VVVftV −+××−= )()1(
(min)(max)
-
(max)
where:
VIN(min) is the minimum input voltage.
fSW(max) is the maximum switching frequency for the worst case.
VD is the diode forward drop.
tMIN-OFF is the minimum controllable off time.
In addition, the bootstrap circuit limits the minimum input
voltage for the desired output due to internal dropout voltage.
To attain stable operation at light loads and ensure proper startup
for the prebias condition, the ADP2300/ADP2301 require the
voltage difference between the input voltage and the regulated
output voltage (or between the input voltage and the prebias
voltage) to be greater than 2.1 V for the worst case. If the voltage
difference is smaller, the bootstrap circuit relies on some minimum
load current to charge the boost capacitor for startup. Figure 43
shows the typical required minimum input voltage vs. load current
for the 3.3 V output voltage.
Data Sheet ADP2300/ADP2301
Rev. B | Page 17 of 28
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.3
5.5
110 100 1k
LOAD CURRENT ( mA)
MINIMUM VIN (V)
FOR ST ARTUP
FOR RUNNING
VOUT = 3. 3V
f
SW = 1.4MHz
Figure 43. Minimum Input Voltage vs. Load Current
Based on three conversion limitations (the minimum on time,
the minimum off time, and the bootstrap dropout voltage),
Figure 44 shows the voltage conversion limitations.
08342-055
22
17
V
IN
(V)
V
OUT
(V)
12
7
2
246810 12 14 160
MAXIM UM INPUT FOR ADP2300
MAXIM UM INPUT FOR ADP2301
MINI MUM I NPUT FOR ADP2300/ADP2301
Figure 44. Voltage Conversion Limitations
LOW INPUT VOLTAGE CONSIDERATIONS
For low input voltage between 3 V and 5 V, the internal boot
regulator cannot provide enough 5.0 V bootstrap voltage due to
the internal dropout voltage. As a result, the increased MOSFET
RDS(ON) reduces the available load current. To prevent this, add
an external small-signal Schottky diode from a 5.0 V external
bootstrap bias voltage. Because the absolute maximum rating
between the BST and SW pins is 6.0 V, the bias voltage should
be less than 5.5 V. Figure 45 shows the application diagram for
the external bootstrap circuit.
3V ~ 5V VIN BST
SW
FB
EN
ON
OFF GND
ADP2300/
ADP2301
08342-042
SCHOTTKY DI ODE
5V BI AS
VOLTAGE
Figure 45. External Bootstrap Circuit for Low Input Voltage Application
PROGRAMMING THE PRECISION ENABLE
Generally, the EN pin can be easily tied to the VIN pin so that the
device automatically starts up when the input power is applied.
However, the precision enable feature allows the ADP2300/
ADP2301 to be used as a programmable UVLO by connecting
a resistive voltage divider to VIN, as shown in Figure 46. This
configuration prevents the start-up problems that can occur
when VIN ramps up slowly in soft start with a relatively high
load current.
ADP2300/
ADP2301
VIN
V
IN
EN
R
EN1
R
EN2
08342-043
Figure 46. Precision Enable Used as a Programmable UVLO
The precision enable feature also allows the ADP2300/ADP2301 to
be sequenced precisely by using a resistive voltage divider with
another dc-to-dc output supply, as shown in Figure 47.
ADP2300/
ADP2301
EN
REN1
REN2
08342-044
OT HE R DC-TO-DC
OUTPUT
Figure 47. Precision Enable Used as a Sequencing Control
from Another DC-to-DC Output
With a 1.2 µA pull-down current on the EN pin, the equation for
the start-up voltage in Figure 46 and Figure 47 is
V2.1μA2.1
V2.1
1
2
+×
+=
EN
EN
STARTUP
R
R
V
where:
VSTARTUP is the start-up voltage to enable the chip.
REN1 is the resistor from the dc source to EN.
REN2 is the resistor from EN to GND.
ADP2300/ADP2301 Data Sheet
Rev. B | Page 18 of 28
INDUCTOR
The high switching frequency of the ADP2300/ADP2301 allows
the use of small inductors. For best performance, use inductor
values between 2 μH and 10 μH for ADP2301, and use inductor
values between 2 μH and 22 μH for ADP2300.
The peak-to-peak inductor current ripple is calculated using the
following equation:
+
+
×
×
−
=∆
DIN
D
OUT
sw
OUT
IN
RIPPLE
VV
VV
fL
VV
I)(
where:
fSW is the switching frequency.
L is the inductor value.
VD is the diode forward drop.
VIN is the input voltage.
VOUT is the output voltage.
Inductors of smaller values are usually smaller in size and less
expensive, but increase the ripple current and the output voltage
ripple. As a guideline, the inductor peak-to-peak current ripple
should typically be set to 30% of the maximum load current for
optimal transient response and efficiency. Therefore, the inductor
value is calculated using the following equation:
( )
+
+
×
××
−
=
DIN
D
OUT
sw
LOAD
OUT
IN
VV
VV
fI
VV
L
(max)
3.0
where ILOAD(max) is the maximum load current.
The inductor peak current is calculated using the following
equation:
2
(max)
RIPPLE
LOAD
PEAK
I
II ∆
+=
The minimum current rating of the inductor must be greater
than the inductor peak current. For ferrite core inductors with a
quick saturation characteristic, the inductor saturation current
rating should be higher than the switch current-limit threshold
to prevent the inductor from reaching its saturation point. Be
sure to validate the worst-case condition, in which there is a
shorted output, over the intended temperature range.
Inductor conduction losses are caused by the flow of current
through the inductor, which is associated with the internal dc
resistance (DCR). Larger sized inductors have smaller DCR and,
therefore, may reduce inductor conduction losses. However,
inductor core losses are also related to the core material and the
ac flux swing, which are affected by the peak-to-peak induc-
tor ripple current. Because the ADP2300/ADP2301 are high
switching frequency regulators, shielded ferrite core materials
are recommended for their low core losses and low EMI. Some
recommended inductors are shown in Table 7.
Table 7. Recommended Inductors
Vendor Value (µH) Part No. DCR (mΩ) I
SAT
(A)
Dimensions
L × W × H (mm)
Coilcraft 4.7 LPS6225-472MLC 65 3.1 6.0 × 6.0 × 2.4
6.8 LPS6225-682MLC 95 2.7 6.0 × 6.0 × 2.4
10 LPS6225-103MLC 105 2.1 6.0 × 6.0 × 2.4
Sumida 4.7 CDRH5D28RHPNP-4R7N 43 3.7 6.2 × 6.2 × 3.0
4.7
CDRH5D16NP-4R7N
64
2.15
5.8 × 5.8 × 1.8
6.8 CDRH5D28RHPNP-6R8N 61 3.1 6.2 × 6.2 × 3.0
6.8 CDRH5D16NP-6R8N 84 1.8 5.8 × 5.8 × 1.8
10 CDRH5D28RHPNP-100M 93 2.45 6.2 × 6.2 × 3.0
Cooper Bussmann 4.7 SD53-4R7-R 39 2.1 5.2 × 5.2 × 3.0
6.8 SD53-6R8-R 59 1.85 5.2 × 5.2 × 3.0
10 DR73-100-R 65 2.47 7.6 × 7.6 × 3.5
Toko 4.7 B1077AS-4R7N 34 2.6 7.6 × 7.6 × 4.0
6.8 B1077AS-6R8N 40 2.3 7.6 × 7.6 × 4.0
10 B1077AS-100M 58 1.8 7.6 × 7.6 × 4.0
TDK 4.7 VLC5045T-4R7M 34 3.3 5.0 × 5.0 × 4.5
6.8 VLC5045T-6R8M 46 2.7 5.0 × 5.0 × 4.5
10 VLC5045T-100M 66 2.1 5.0 × 5.0 × 4.5
Data Sheet ADP2300/ADP2301
Rev. B | Page 19 of 28
CATCH DIODE
The catch diode conducts the inductor current during the off
time of the internal MOSFET. The average current of the diode
in normal operation is, therefore, dependent on the duty cycle
of the regulator as well as the output load current.
(max))(
1
LOAD
DIN
D
OUT
AVGDIODE
I
VV
VV
I×
+
+
−=
where VD is the diode forward drop.
The only reason to select a diode with a higher current rating than
necessary in normal operation is for the worst-case condition, in
which there is a shorted output. In this case, the diode current
increases up to the typical peak current-limit threshold. Be sure to
consult the diode data sheet to ensure that the diode can operate
well within the thermal and electrical limits.
The reverse breakdown voltage rating of the diode must be higher
than the highest input voltage and allow an appropriate margin
for the ringing that may be present on the SW node. A Schottky
diode is recommended for best efficiency because it has a low
forward voltage drop and fast switching speed. Table 8 provides
a list of recommended Schottky diodes.
Table 8. Recommended Schottky Diodes
Vendor Part No.
VRRM
(V)
IAVG
(A)
ON Semiconductor MBRS230LT3 30 2
MBRS240LT3 40 2
Diodes Inc. B230A 30 2
B240A 40 2
Vishay SL23 30 2
SS24 40 2
INPUT CAPACITOR
The input capacitor must be able to support the maximum input
operating voltage and the maximum rms input current. The
maximum rms input current flowing through the input
capacitor is ILOAD(max)/2. Select an input capacitor capable of
withstanding the rms input current for an application’s maxi-
mum load current using the following equation:
)1(
(max))(
DDII
LOADRMSIN
−××=
where D is the duty cycle and is equal to
DIN
D
OUT
VV
VV
D+
+
=
The recommended input capacitor is ceramic with X5R or X7R
dielectrics due to its low ESR and small temperature coefficients.
A capacitance of 10 µF should be adequate for most applications.
To minimize supply noise, place the input capacitor as close to
the VIN pin of the ADP2300/ADP2301 as possible.
OUTPUT CAPACITOR
The output capacitor selection affects both the output voltage ripple
and the loop dynamics of the regulator. The ADP2300/ADP2301
are designed to operate with small ceramic capacitors that have low
equivalent series resistance (ESR) and equivalent series inductance
(ESL) and are, therefore, easily able to meet stringent output voltage
ripple specifications.
When the regulator operates in forced continuous conduction
mode, the overall output voltage ripple is the sum of the voltage
spike caused by the output capacitor ESR plus the voltage ripple
caused by charging and discharging the output capacitor.
+
××
×∆=∆
OUT
C
OUT
sw
RIPPLERIPPLE ESR
Cf
IV 8
1
Capacitors with lower ESR are preferable to guarantee low
output voltage ripple, as shown in the following equation:
RIPPLE
RIPPLE
CI
V
ESR
OUT
∆
∆
≤
Ceramic capacitors are manufactured with a variety of dielectrics,
each with different behavior over temperature and applied voltage.
X5R or X7R dielectrics are recommended for best performance,
due to their low ESR and small temperature coefficients. Y5V
and Z5U dielectrics are not recommended because of their poor
temperature and dc bias characteristics.
In general, most applications using the ADP2301 (1.4 MHz
switching frequency) require a minimum output capacitor value
of 10 µF, whereas most applications using the ADP2300 (700 kHz
switching frequency) require a minimum output capacitor value
of 20 µF. Some recommended output capacitors for VOUT ≤ 5.0 V
are listed in Table 9.
Table 9. Recommended Capacitors for VOUT ≤ 5.0 V
Vendor Value Part No.
Dimensions
L × W × H (mm)
Murata 10 µF, 6.3 V GRM31MR60J106KE19 3.2 × 1.6 × 1.15
22 µF, 6.3 V GRM31CR60J226KE19 3.2 × 1.6 × 1.6
TDK 10 µF, 6.3 V C3216X5R0J106K 3.2 × 1.6 × 1.6
22 µF, 6.3 V C3216X5R0J226M 3.2 × 1.6 × 0.85
ADP2300/ADP2301 Data Sheet
Rev. B | Page 20 of 28
THERMAL CONSIDERATIONS
The ADP2300/ADP2301 store the value of the inductor current
only during the on time of the internal MOSFET. Therefore, a small
amount of power is dissipated inside the ADP2300/ADP2301
package, which reduces thermal constraints.
However, when the application is operating under maximum
load with high ambient temperature and high duty cycle, the
heat dissipated within the package may cause the junction
temperature of the die to exceed the maximum junction
temperature of 125°C. If the junction temperature exceeds
140°C, the regulator goes into thermal shutdown and recovers
when the junction temperature drops below 125°C.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to power dissipation, as indicated in the following
equation:
TJ = TA + TR
where:
TJ is the junction temperature.
TA is the ambient temperature.
TR is the rise in temperature of the package due to power
dissipation.
The rise in temperature of the package is directly proportional
to the power dissipation in the package. The proportionality
constant for this relationship is the thermal resistance from the
junction of the die to the ambient temperature, as shown in the
following equation:
TR = θJA × PD
where:
TR is the rise in temperature of the package.
θJA is the thermal resistance from the junction of the die to the
ambient temperature of the package.
PD is the power dissipation in the package.
Data Sheet ADP2300/ADP2301
Rev. B | Page 21 of 28
DESIGN EXAMPLE
This section provides the procedures to select the external com-
ponents, based on the example specifications listed in Table 10.
The schematic for this design example is shown in Figure 48.
Table 10. Step-Down DC-to-DC Regulator Requirements
Parameter Specification
Additional
Requirements
Input Voltage, V
IN
12.0 V ± 10% None
Output Voltage, VOUT 3.3 V, 1.2 A, 1% VOUT
ripple at CCM mode
None
Programmable
UVLO Voltage
VIN start-up voltage
approximately 7.8 V
None
SWITCHING FREQUENCY SELECTION
Select the switching frequency—700 kHz (ADP2300) or 1.4 MHz
(ADP2301)—using the conversion limitation curve shown in
Figure 44 to assess the conversion limitations (the minimum on
time, the minimum off time, and the bootstrap dropout voltage).
For example, in Figure 44 VIN = 12 V ± 10% is within the conver-
sion limitation for both the 700 kHz and 1.4 MHz switching
frequencies for an output voltage of 3.3 V, but choosing the 1.4 MHz
switching frequency provides the smallest sized solution. If higher
efficiency is required, choose the 700 kHz option; however, the
PCB footprint area of the regulator will be larger because of the
bigger inductor and output capacitors.
CATCH DIODE SELECTION
Select the catch diode. A Schottky diode is recommended for best
efficiency because it has a low forward voltage drop and faster
switching speed. The average current of the catch diode in
normal operation, with a typical Schottky diode forward
voltage, can be calculated using the following equation:
(max))(
1
LOAD
DIN
D
OUT
AVGDIODE
I
VV
VV
I×
+
+
−=
where:
VOUT = 3.3 V.
VIN = 12 V.
ILOAD(max) = 1.2 A.
VD = 0.4 V.
Therefore, IDIODE(AVG) = 0.85 A.
However, for the worst-case condition, in which there is a shorted
output, the diode current would be increased to 2 A typical, deter-
mined by the peak switch current limit (see Table 1). In this case,
selecting a B230A, 2.0 A/30 V surface-mount Schottky diode
would result in more reliable operation.
INDUCTOR SELECTION
Select the inductor by using the following equation:
( )
+
+
×
××
−
=
DIN
D
OUT
sw
LOAD
OUT
IN
VV
VV
fI
VV
L
(max)
3.0
where:
VOUT = 3.3 V.
VIN = 12 V.
ILOAD(max) = 1.2 A.
VD = 0.4 V.
fSW = 1.4 MHz.
This results in L = 5.15 µH. The closest standard value is 4.7 µH;
therefore, ΔIRIPPLE = 0.394 A.
The inductor peak current is calculated using the following
equation:
2
(max)
RIPPLE
LOAD
PEAK
I
II ∆
+=
where:
ILOAD(max) = 1.2 A.
ΔIRIPPLE = 0.394 A.
Therefore, the calculated peak current for the inductor is 1.397 A.
However, to protect the inductor from reaching its saturation
point in the current-limit condition, the inductor should be rated
for at least a 2.0 A saturation current for reliable operation.
OUTPUT CAPACITOR SELECTION
Select the output capacitor based on the output voltage ripple
requirement, according to the following equation:
+
××
×∆=∆
OUT
C
OUT
sw
RIPPLERIPPLE
ESR
Cf
IV 8
1
where:
ΔIRIPPLE = 0.394 A.
fSW = 1.4 MHz.
ΔVRIPPLE = 33 mV.
If the ESR of the ceramic capacitor is 3 mΩ, then COUT = 1.2 µF.
Because the output capacitor is one of the two external components
that control the loop stability, most applications using the ADP2301
(1.4 MHz switching frequency) require a minimum 10 µF capaci-
tance to ensure stability. According to the recommended external
components in Table 11, choose 22 µF with a 6.3 V voltage rating
for this example.
ADP2300/ADP2301 Data Sheet
Rev. B | Page 22 of 28
RESISTIVE VOLTAGE DIVIDER SELECTION
To select the appropriate resistive voltage divider, first calculate the
output feedback resistive voltage divider, and then calculate the
resistive voltage divider for the programmable VIN start-up voltage.
The output feedback resistive voltage divider is
+×=
2
1
1V800.0
FB
FB
OUT R
R
V
For the 3.3 V output voltage, choose RFB1 = 31.6 kΩ and RFB2
= 10.2 kΩ as the feedback resistive voltage divider, according to
the recommended values in Table 11.
The resistive voltage divider for the programmable VIN start-up
voltage is
V2.1μA2.1
V2.1
1
2
+×
+=
EN
EN
STARTUP
R
R
V
If VSTARTUP = 7.8 V, choose REN2 = 10.2 kΩ, and then calculate
REN1, which in this case is 56 kΩ.
V
IN
= 12V VIN BST
SW
FB
EN GND
ADP2301
(1.4MHz)
08342-045
R3
56kΩ
1%
R2
10.2kΩ
1%
R1
31.6kΩ
1%
C2
22µF
6.3V
D1
B230A
C3
0.1µF
6.3V L1
4.7µH
2.0A V
OUT
= 3.3V
1.2A
R4
10.2kΩ
1%
C1
10µF
25V
Figure 48. Schematic for the Design Example
Table 11. Recommended External Components for Typical Applications at 1.2 A Output Load
Part Number
VIN (V)
VOUT (V)
IOUT (A)
L (µH)
COUT (µF)
RFB1 (kΩ), ±1%
RFB2 (kΩ), ±1%
ADP2300 (700 kHz) 18 3.3 1.2 10 22 31.6 10.2
18
5.0
1.2
15
22
52.3
10
12 1.2 1.2 6.8 2 × 22 4.99 10
12 1.8 1.2 6.8 2 × 22 12.7 10.2
12 2.5 1.2 10 22 21.5 10.2
12 3.3 1.2 10 22 31.6 10.2
12 5.0 1.2 10 22 52.3 10
9 3.3 1.2 10 22 31.6 10.2
9 5.0 1.2 10 22 52.3 10
5 1.8 1.2 4.7 2 × 22 12.7 10.2
5 2.5 1.2 4.7 22 21.5 10.2
ADP2301 (1.4 MHz) 18 3.3 1.2 4.7 22 31.6 10.2
18 5.0 1.2 6.8 10 52.3 10
12 2.5 1.2 4.7 22 21.5 10.2
12 3.3 1.2 4.7 22 31.6 10.2
12
5.0
1.2
4.7
10
52.3
10
9 3.3 1.2 4.7 22 31.6 10.2
9 5.0 1.2 4.7 10 52.3 10
5 1.8 1.2 2.2 2 × 22 12.7 10.2
5 2.5 1.2 2.2 22 21.5 10.2
Data Sheet ADP2300/ADP2301
Rev. B | Page 23 of 28
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good circuit board layout is essential to obtain the best
performance from the ADP2300/ADP2301. Poor layout can
affect the regulation and stability, as well as the electromagnetic
interface (EMI) and electromagnetic compatibility (EMC)
performance. A PCB layout example is shown in Figure 50.
Refer to the following guidelines for a good PCB layout:
• Place the input capacitor, inductor, catch diode, output
capacitor, and bootstrap capacitor close to the IC using
short traces.
• Ensure that the high current loop traces are as short and wide
as possible. The high current path is shown in Figure 49.
• Maximize the size of ground metal on the component side
to improve thermal dissipation.
• Use a ground plane with several vias connecting to the
component side ground to further reduce noise inter-
ference on sensitive circuit nodes.
• Minimize the length of the FB trace connecting the top of the
feedback resistive voltage divider to the output. In addition,
keep these traces away from the high current traces and the
switch node to avoid noise pickup.
VIN BST
SW
FB
EN GND
ADP2300/
ADP2301
08342-046
Figure 49. Typical Application Circuit with High Current Traces Shown in Blue
08342-056
INDUCTOR
L1
C1
C2
C3
OUTPUT CAP
INPUT CAP
BST CAPD1
CATCH DIODE
R
FB1
R
FB2
ADP2300/ADP2301
Figure 50. Recommended PCB Layout for the ADP2300/ADP2301
ADP2300/ADP2301 Data Sheet
Rev. B | Page 24 of 28
TYPICAL APPLICATION CIRCUITS
V
IN
= 12V VIN BST
SW
FB
EN GND
ADP2300
(700kHz)
08342-052
R3
100kΩ
5%
R2
10kΩ
1%
R1
4.99kΩ
1%
C3
22µF
6.3V
C2
22µF
6.3V
C1
10µF
25V
D1
B230A
C4
0.1µF
6.3V L1
6.8µH
2.0A V
OUT
= 1.2V
1.2A
ON
OFF
Figure 51. ADP2300—700 kHz Typical Application, VIN = 12 V, VOUT = 1.2 V/1.2 A with External Enabling
V
IN
= 12V VIN BST
SW
FB
EN GND
ADP2300
(700kHz)
08342-051
R3
100kΩ
5%
R2
10.2kΩ
1%
R1
12.7kΩ
1%
C3
22µF
6.3V
C2
22µF
6.3V
C1
10µF
25V
D1
B230A
C4
0.1µF
6.3V L1
6.8µH
2.0A V
OUT
= 1.8V
1.2A
ON
OFF
Figure 52. ADP2300—700 kHz Typical Application, VIN = 12 V, VOUT = 1.8 V/1.2 A with External Enabling
V
IN
= 12V VIN BST
SW
FB
EN GND
ADP2300
(700kHz)
08342-050
R3
100kΩ
5%
R2
10.2kΩ
1%
R1
21.5kΩ
1%
C2
22µF
6.3V
D1
B230A
C3
0.1µF
6.3V
C1
10µF
25V
L1
10µH
2.0A V
OUT
= 2.5V
1.2A
ON
OFF
Figure 53. ADP2300—700 kHz Typical Application, VIN = 12 V, VOUT = 2.5 V/1.2 A with External Enabling
Data Sheet ADP2300/ADP2301
Rev. B | Page 25 of 28
VIN = 12V VIN BST
SW
FB
EN GND
ADP2301
(1.4MHz)
08342-049
R3
56kΩ
1%
C1
10µF
25V
R2
10.2kΩ
1%
R1
31.6kΩ
1%
C2
22µF
6.3V
D1
B230A
C3
0.1µF
6.3V L1
4.7µH
2.0A VOUT = 3.3V
1.2A
R4
10.2kΩ
1%
Figure 54. ADP2301—1.4 MHz Typical Application, VIN = 12 V, VOUT = 3.3 V/1.2 A
(with Programmable 7.8 V Start-Up Input Voltage)
VIN = 12V VIN BST
SW
FB
EN GND
ADP2301
(1.4MHz)
08342-048
R3
100kΩ
5%
R2
10kΩ
1%
R1
52.3kΩ
1%
C2
10µF
6.3V
C1
10µF
25V
D1
B230A
C3
0.1µF
6.3V L1
4.7µH
2.0A VOUT = 5V
1.2A
ON
OFF
Figure 55. ADP2301—1.4 MHz Typical Application, VIN = 12 V, VOUT = 5.0 V/1.2 A with External Enabling
08342-090
V
IN
= 18V VIN BST
SW
FB
EN GND
ADP2301
(1.4MHz)
R3
100kΩ
5%
R2
10.2kΩ
1%
R1
52.3kΩ
1%
C2
10µF
6.3V
D1
B230A
C3
0.1µF
6.3V
C1
10µF
25V
L1
6.8µH
2.0A V
OUT
= 5.0V
1.2A
ON
OFF
Figure 56. ADP2301—1.4 MHz Typical Application, VIN = 18 V, VOUT = 5.0 V/1.2 A with External Enabling
08342-091
VIN = 9V VIN BST
SW
FB
EN GND
ADP2301
(1.4MHz)
R3
100kΩ
5%
R2
10.2kΩ
1%
R1
31.6kΩ
1%
C2
22µF
6.3V
D1
B230A
C3
0.1µF
6.3V
C1
10µF
25V
L1
4.7µH
2.0A V
OUT
= 3.3V
1.2A
ON
OFF
Figure 57. ADP2301—1.4 MHz Typical Application, VIN = 9 V, VOUT = 3.3 V/1.2 A with External Enabling
08342-092
V
IN
= 5V VIN BST
SW
FB
EN GND
ADP2301
(1.4MHz)
R3
100kΩ
5%
R2
10.2kΩ
1%
R1
12.7kΩ
1%
C2
22µF
6.3V
C3
22µF
6.3V
D1
B230A
C4
0.1µF
6.3V
C1
10µF
25V
L1
2.2µH
2.0A V
OUT
= 1.8V
1.2A
ON
OFF
Figure 58. ADP2301—1.4 MHz Typical Application, VIN = 5 V, VOUT = 1.8 V/1.2 A with External Enabling
ADP2300/ADP2301 Data Sheet
Rev. B | Page 26 of 28
OUTLINE DIMENSIONS
102808-A
*COM P LIANT T O JEDE C S TANDARDS MO-193- AA WITH
THE E X CE P TION O F PACKAGE HEIG HT AND T HICKNES S .
1 3
45
2
6
2.90 BS C
1.60 BSC 2.80 BS C
1.90
BSC
0.95 BSC
0.10 MAX
*1.00 MAX
PI N 1
INDICATOR
*0.90
0.87
0.84
0.60
0.45
0.30
0.50
0.30
0.20
0.08
SEATING
PLANE 8°
4°
0°
Figure 59. 6-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Switching
Frequency Temperature Range Package Description
Package
Option Branding
ADP2300AUJZ-R7 700 kHz −40°C to +125°C 6-Lead Thin Small Outline Transistor Package [TSOT] UJ-6 L87
ADP2300-EVALZ Evaluation Board
ADP2301AUJZ-R7 1.4 MHz −40°C to +125°C 6-Lead Thin Small Outline Transistor Package [TSOT] UJ-6 L86
ADP2301-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet ADP2300/ADP2301
Rev. B | Page 27 of 28
NOTES
ADP2300/ADP2301 Data Sheet
Rev. B | Page 28 of 28
NOTES
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08342-0-6/12(B)