CD74AC139M96S2463 - TEXAS INSTRUMENTS

March, 2006 − Rev. 7

1Publication Order Number:

MC74AC161/D

MC74AC161, MC74ACT161,

MC74AC163, MC74ACT163

Synchronous Presettable

Binary Counter

The MC74AC161/74ACT161 and MC74AC163/74ACT163 are

high−speed synchronous modulo−16 binary counters. They are

synchronously presettable for application in programmable dividers

and have two types of Count Enable inputs plus a Terminal Count

output for versatility in forming synchronous multistage counters.

The MC74AC161/74ACT161 has an asynchronous Master Reset

input that overrides all other inputs and forces the outputs LOW. The

MC74AC163/74ACT163 has a Synchronous Reset input that

overrides counting and parallel loading and allows the outputs to be

simultaneously reset on the rising edge of the clock.

•Synchronous Counting and Loading

•High−Speed Synchronous Expansion

•Typical Count Rate of 125 MHz

•Outputs Source/Sink 24 mA

•′ACT161 and ′ACT163 Have TTL Compatible Inputs

wThese devices are available in Pb−free package(s). Specifications herein

apply to both standard and Pb−free devices. Please see our website at

www.onsemi.com for specific Pb−free orderable part numbers, or

contact your local ON Semiconductor sales office or representative.

1516 14 13 12 11 10

21 34567

VCC

TC Q0Q1Q2Q3CET PE

*R CP P0P1P2P3CEP GND

Figure 1. Pinout: 16−Lead Packages Conductors

(Top View)

PIN ASSIGNMENT

PIN FUNCTION

CEP Count Enable Parallel Input

CET Count Enable Trickle Input

CP Clock Pulse Input

MR (′161) Asynchronous Master Reset Input

SR (′163) Synchronous Reset Input

P0−P3Parallel Data Inputs

PE Parallel Enable Input

Q0−Q3Flip−Flop Outputs

TC Terminal Count Output

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DIP−16

N SUFFIX

CASE 648

SO−16

D SUFFIX

CASE 751B

See general marking information in the device marking

section on page 11 of this data sheet.

DEVICE MARKING INFORMATION

EIAJ−16

M SUFFIX

CASE 966

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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Figure 2. Logic Symbol

*MR for ′161

*SR for ′163

PE P0P1P2

CEP

CET

*R Q0Q1Q2Q3

FUNCTIONAL DESCRIPTION

The MC74AC161/ACT161 and MC74AC163/ACT163

count modulo−16 binary sequence. From state 15 (HHHH)

they increment to state 0 (LLLL). The clock inputs of all

flip−flops are driven in parallel through a clock buffer. Thus

all changes of the Q outputs (except due to Master Reset of

the ′161) occur as a result of, and synchronous with, the

LOW−to−HIGH transition of the CP input signal. The

circuits have four fundamental modes of operation, in order

of precedence: asynchronous reset (′161), synchronous reset

(′163), parallel load, count−up and hold. Five control inputs

− Master Reset (MR, ′161), Synchronous Reset (SR, ′163),

Parallel Enable (PE), Count Enable Parallel (CEP) and

Count Enable Trickle (CET) −determine the mode of

operation, as shown in the Mode Select Table. A LOW

signal on MR overrides all other inputs and asynchronously

forces all outputs LOW. A LOW signal on SR overrides

counting and parallel loading and allows all outputs to go

LOW on the next rising edge of CP. A LOW signal on PE

overrides counting and allows information on the Parallel

Data (Pn) inputs to be loaded into the flip−flops on the next

rising edge of CP. With PE and MR (′161) or SR (′163)

HIGH, CEP and CET permit counting when both are HIGH.

Conversely, a LOW signal on either CEP or CET inhibits

counting.

The MC74AC161/ACT161 and MC74AC163/ACT163 use

D−type edge−triggered flip−flops and changing the SR, PE,

CEP and CET inputs when the CP is in either state does not

cause errors, provided that the recommended setup and hold

times, with respect to the rising edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is

HIGH and counter is in state 15. To implement synchronous

multistage counters, the TC outputs can be used with the

CEP and CET inputs in two different ways. Please refer to

the MC74AC568 data sheet. The TC output is subject to

decoding spikes due to internal race conditions and is

therefore not recommended for use as a clock or

asynchronous reset for flip−flops, counters or registers.

Logic Equations:

Count Enable = CEP•CET•PE

TC = Q0•Q1•Q2•Q3•CET

MODE SELECT TABLE

*SR PE CET CEP

Action on the Rising

Clock Edge ( )

L X X X Reset (Clear)

HL X X Load (Pn → Qn)

HH H H Count (Increment)

HH L X No Change (Hold)

H H X L No Change (Hold)

*For ′163 only

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Figure 3. State Diagram

1 2 3

11 10 9

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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P0P1P2

CEP

CET

Q0Q1Q2Q3

MR ′161

SR ′163

′163

ONLY

′163

Q0Q0

DETAIL A

DETAIL A DETAIL A DETAIL A

DCP D

Figure 4. Logic Diagram

NOTE: This diagram is provided only for the understanding of logic

operations and should not be used to estimate propagation

delays.

′161

ONLY

′161

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V

VIN DC Input Voltage (Referenced to GND) −0.5 to VCC +0.5 V

VOUT DC Output Voltage (Referenced to GND) −0.5 to VCC +0.5 V

IIN DC Input Current, per Pin ±20 mA

IOUT DC Output Sink/Source Current, per Pin ±50 mA

ICC DC VCC or GND Current per Output Pin ±50 mA

Tstg Storage Temperature −65 to +150 °C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-

mended Operating Conditions.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Typ Max Unit

VCC Supply Voltage

′AC 2.0 5.0 6.0

′ACT 4.5 5.0 5.5

VIN, VOUT DC Input Voltage, Output Voltage (Ref. to GND) 0−VCC V

tr, tfInput Rise and Fall Time (Note 1)

′AC Devices except Schmitt Inputs

VCC @ 3.0 V −150 −

VCC @ 4.5 V −40 −ns/V

VCC @ 5.5 V −25 −

tr, tfInput Rise and Fall Time (Note 2)

′ACT Devices except Schmitt Inputs

VCC @ 4.5 V −10 −

ns/V

VCC @ 5.5 V −8.0 −

TJJunction Temperature (PDIP) − − 140 °C

TAOperating Ambient Temperature Range −40 25 85 °C

IOH Output Current − High − − −24 mA

IOL Output Current − Low − − 24 mA

1. VIN from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.

2. VIN from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

DC CHARACTERISTICS

Symbol Parameter VCC

(V)

74AC 74AC

Unit Conditions

TA = +25°C

TA =

−40°C to

+85°C

Typ Guaranteed Limits

VIH Minimum High Level

Input Voltage

3.0 1.5 2.1 2.1 VOUT = 0.1 V

4.5 2.25 3.15 3.15 V or VCC − 0.1 V

5.5 2.75 3.85 3.85

VIL Maximum Low Level

Input Voltage

3.0 1.5 0.9 0.9 VOUT = 0.1 V

4.5 2.25 1.35 1.35 V or VCC − 0.1 V

5.5 2.75 1.65 1.65

VOH Minimum High Level

Output Voltage

3.0 2.99 2.9 2.9 IOUT = −50 mA

4.5 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4

*VIN = VIL or VIH

3.0 −2.56 2.46 −12 mA

4.5 −3.86 3.76 IOH −24 mA

5.5 −4.86 4.76 −24 mA

VOL Maximum Low Level

Output Voltage

3.0 0.002 0.1 0.1 IOUT = 50 mA

4.5 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1

*VIN = VIL or VIH

3.0 −0.36 0.44 12 mA

4.5 −0.36 0.44 IOL 24 mA

5.5 −0.36 0.44 24 mA

IIN Maximum Input

Leakage Current 5.5 −±0.1 ±1.0 mAVI = VCC, GND

IOLD †Minimum Dynamic

Output Current

5.5 − − 75 mA VOLD = 1.65 V Max

IOHD 5.5 − − −75 mA VOHD = 3.85 V Min

ICC Maximum Quiescent

Supply Current 5.5 −8.0 80 mAVIN = VCC or GND

*All outputs loaded; thresholds on input associated with output under test.

†Maximum test duration 2.0 ms, one output loaded at a time.

NOTE: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

Symbol Parameter VCC*

(V)

74AC161 74AC161

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Min Typ Max Min Max

fmax

Maximum Count 3.3 70 111 −60 −MHz 3−3

Frequency 5.0 110 167 −95 −

tPLH

Propagation Delay 3.3 2.0 7.0 12.0 1.5 13.5 ns 3−6

CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.0 9.0 1.0 9.5

tPHL

Propagation Delay 3.3 1.5 7.0 12.0 1.5 13.0 ns 3−6

CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.0 9.5 1.5 10.0

tPLH

Propagation Delay 3.3 3.0 9.0 15.0 2.5 16.5 ns 3−6

CP to TC 5.0 2.0 6.0 10.5 1.5 11.5

tPHL

Propagation Delay 3.3 3.5 8.5 14.0 2.5 15.5 ns 3−6

CP to TC 5.0 2.0 6.5 11.0 2.0 11.5

tPLH

Propagation Delay 3.3 2.0 5.5 9.5 1.5 11.0 ns 3−6

CET to TC 5.0 1.5 3.5 6.5 1.0 7.5

tPHL

Propagation Delay 3.3 2.5 6.5 11.0 2.0 12.5 ns 3−6

CET to TC 5.0 2.0 5.0 8.5 1.5 9.5

tPHL

Propagation Delay 3.3 2.0 6.0 12.0 1.5 13.5 ns 3−6

MR to Qn5.0 1.5 5.5 9.5 1.5 10.0

tPHL

Propagation Delay 3.3 3.5 10.0 15.0 3.0 17.5 ns 3−6

MR to TC 5.0 2.5 8.5 13.0 2.5 13.5

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

Symbol Parameter VCC*

(V)

74AC163 74AC163

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Min Typ Max Min Max

fmax

Maximum Count 3.3 70 95 −60 −MHz 3−3

Frequency 5.0 110 140 −95 −

tPLH

Propagation Delay 3.3 2.0 7.5 12.5 1.5 13.5 ns 3−6

CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.5 9.0 1.0 9.5

tPHL

Propagation Delay 3.3 1.5 8.5 12.0 1.5 13.0 ns 3−6

CP to Qn (PE Input HIGH or LOW) 5.0 1.5 6.0 9.5 1.5 10.0

tPLH

Propagation Delay 3.3 3.0 9.5 15.0 2.5 16.5 ns 3−6

CP to TC 5.0 2.0 7.0 10.5 1.5 11.5

tPHL

Propagation Delay 3.3 3.5 11.0 14.0 2.5 15.5 ns 3−6

CP to TC 5.0 2.0 8.0 11.0 2.0 11.5

tPLH

Propagation Delay 3.3 2.0 7.5 9.5 1.5 11.0 ns 3−6

CET to TC 5.0 1.5 5.5 6.5 1.0 7.5

tPHL

Propagation Delay 3.3 2.5 8.5 11.0 2.0 12.5 ns 3−6

CET to TC 5.0 2.0 6.0 8.5 1.5 9.5

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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AC OPERATING REQUIREMENTS

Symbol Parameter VCC*

(V)

74AC161 74AC161

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Typ Guaranteed Minimum

Setup Time, HIGH or LOW 3.3 6.0 13.5 16.0 ns 3−9

Pn to CP 5.0 3.5 8.5 10.5

Hold Time, HIGH or LOW 3.3 −7.0 −1.0 −0.5 ns 3−9

Pn to CP 5.0 −4.0 0 0

Setup Time, HIGH or LOW 3.3 6.5 11.5 14.0 ns 3−9

PE to CP 5.0 4.0 7.5 8.5

Hold Time, HIGH or LOW 3.3 −6.0 0 0 ns 3−9

PE to CP 5.0 −3.5 0.5 1.0

Setup Time, HIGH or LOW 3.3 3.0 6.0 7.0 ns 3−9

CEP or CET to CP 5.0 2.0 4.5 5.0

Hold Time, HIGH or LOW 3.3 −3.5 0 0 ns 3−9

CEP or CET to CP 5.0 −2.0 0 0.5

Clock Pulse Width (Load) 3.3 2.0 3.5 4.0 ns 3−6

HIGH or LOW 5.0 2.0 2.5 3.0

Clock Pulse Width (Count) 3.3 2.0 4.0 4.5 ns 3−6

HIGH or LOW 5.0 2.0 3.0 3.5

twMR Pulse Width, LOW 3.3 3.0 5.5 7.5 ns 3−6

5.0 2.5 4.5 6.0

trec

Recovery TIme 3.3 −2.0 −0.5 0 ns 3−9

MR to CP 5.0 −1.0 0 0.5

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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AC OPERATING REQUIREMENTS

Symbol Parameter VCC*

(V)

74AC163 74AC163

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Typ Guaranteed Minimum

Setup Time, HIGH or LOW 3.3 5.5 13.5 16.0 ns 3−9

Pn to CP 5.0 4.0 8.5 10.5

Hold Time, HIGH or LOW 3.3 −7.0 −1.0 −0.5 ns 3−9

Pn to CP 5.0 −5.0 0 0

Setup Time, HIGH or LOW 3.3 5.5 14 16.5 ns 3−9

SR to CP 5.0 4.0 9.5 11.0

Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 ns 3−9

SR to CP 5.0 −5.5 −0.5 0

Setup Time, HIGH or LOW 3.3 5.5 11.5 14.0 ns 3−9

PE to CP 5.0 4.0 7.5 8.5

Hold Time, HIGH or LOW 3.3 −7.5 −1.0 −0.5 ns 3−9

PE to CP 5.0 −5.0 −0.5 0

Setup Time, HIGH or LOW 3.3 3.5 6.0 7.0 ns 3−9

CEP or CET to CP 5.0 2.5 4.5 5.0

Hold Time, HIGH or LOW 3.3 −4.5 0 0 ns 3−9

CEP or CET to CP 5.0 −3.0 0 0.5

Clock Pulse Width (Load) 3.3 3.0 3.5 4.0 ns 3−6

HIGH or LOW 5.0 2.0 2.5 3.0

Clock Pulse Width (Count) 3.3 3.0 4.0 4.5 ns 3−6

HIGH or LOW 5.0 2.0 3.0 3.5

*Voltage Range 3.3 V is 3.3 V ±0.3 V.

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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DC CHARACTERISTICS

Symbol Parameter VCC

(V)

74ACT 74ACT

Unit Conditions

TA = +25°C

TA =

−40°C to

+85°C

Typ Guaranteed Limits

VIH Minimum High Level

Input Voltage

4.5 1.5 2.0 2.0 VVOUT = 0.1 V

5.5 1.5 2.0 2.0 or VCC − 0.1 V

VIL Maximum Low Level

Input Voltage

4.5 1.5 0.8 0.8 VVOUT = 0.1 V

5.5 1.5 0.8 0.8 or VCC − 0.1 V

VOH Minimum High Level

Output Voltage

4.5 4.49 4.4 4.4 VIOUT = −50 mA

5.5 5.49 5.4 5.4

*VIN = VIL or VIH

4.5 −3.86 3.76 V IOH

−24 mA

5.5 −4.86 4.76 −24 mA

VOL Maximum Low Level

Output Voltage

4.5 0.001 0.1 0.1 VIOUT = 50 mA

5.5 0.001 0.1 0.1

*VIN = VIL or VIH

4.5 −0.36 0.44 V IOL

24 mA

5.5 −0.36 0.44 24 mA

IIN Maximum Input

Leakage Current 5.5 −±0.1 ±1.0 mAVI = VCC, GND

DICCT Additional Max. ICC/Input 5.5 0.6 −1.5 mA VI = VCC −2.1 V

IOLD †Minimum Dynamic

Output Current

5.5 − − 75 mA VOLD = 1.65 V Max

IOHD 5.5 − − −75 mA VOHD = 3.85 V Min

ICC Maximum Quiescent

Supply Current 5.5 −8.0 80 mAVIN = VCC or GND

*All outputs loaded; thresholds on input associated with output under test.

†Maximum test duration 2.0 ms, one output loaded at a time.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

Symbol Parameter VCC*

(V)

74ACT161 74ACT161

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Min Typ Max Min Max

fmax Maximum Count

Frequency 5.0 115 125 −100 −MHz 3−3

tPLH Propagation Delay

CP to Qn (PE Input HIGH or LOW) 5.0 1.5 8.0 9.5 1.5 10.5 ns 3−6

tPHL Propagation Delay

CP or Qn (PE Input HIGH or LOW) 5.0 1.5 8.0 10.5 1.5 11.5 ns 3−6

tPLH Propagation Delay

CP to TC 5.0 2.0 11.0 11.0 1.5 12.5 ns 3−6

tPHL Propagation Delay

CP to TC 5.0 1.5 11.0 12.5 1.5 13.5 ns 3−6

tPLH Propagation Delay

CET to TC 5.0 1.5 7.5 8.5 1.5 10.0 ns 3−6

tPHL Propagation Delay

CET to TC 5.0 1.5 8.0 9.5 1.5 10.5 ns 3−6

tPHL Propagation Delay

MR to Qn

5.0 1.5 8.0 10.0 1.5 11.0 ns 3−6

tPHL Propagation Delay

MR to TC 5.0 2.5 10.0 13.5 2.0 14.5 ns 3−6

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)

Symbol Parameter VCC*

(V)

74ACT163 74ACT163

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Min Typ Max Min Max

fmax Maximum Count

Frequency 5.0 120 140 −105 −MHz 3−3

tPLH Propagation Delay

CP to Qn (PE Input HIGH or LOW) 5.0 1.5 5.5 10.0 1.5 11.0 ns 3−6

tPHL Propagation Delay

CP to Qn (PE Input HIGH or LOW) 5.0 1.5 6.0 11.0 1.5 12.0 ns 3−6

tPLH Propagation Delay

CP to TC 5.0 2.5 7.0 11.5 2.0 13.5 ns 3−6

tPHL Propagation Delay

CP to TC 5.0 3.0 8.0 13.5 2.0 15.0 ns 3−6

tPLH Propagation Delay

CET to TC 5.0 2.0 5.5 9.0 1.5 10.5 ns 3−6

tPHL Propagation Delay

CET to TC 5.0 2.0 6.0 10.0 2.0 11.0 ns 3−6

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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AC OPERATING REQUIREMENTS

Symbol Parameter VCC*

(V)

74ACT161 74ACT161

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Typ Guaranteed Minimum

tsSetup Time, HIGH or LOW

Pn to CP 5.0 7.0 9.5 11.5 ns 3−9

thHold Time, HIGH or LOW

Pn to CP 5.0 −3.0 0 0 ns 3−9

tsSetup Time, HIGH or LOW

PE to CP 5.0 6.0 8.5 9.5 ns 3−9

thHold Time, HIGH or LOW

PE to CP 5.0 −3.5 −0.5 −0.5 ns 3−9

tsSetup Time, HIGH or LOW

CEP or CET to CP 5.0 4.0 5.5 6.5 ns 3−9

thHold Time, HIGH or LOW

CEP or CET to CP 5.0 −2.0 0 0 ns 3−9

twClock Pulse Width (Load)

HIGH or LOW 5.0 2.0 3.0 3.5 ns 3−6

twClock Pulse Width (Count)

HIGH or LOW 5.0 2.0 3.0 3.5 ns 3−6

twMR Pulse Width, LOW 5.0 3.0 3.0 7.5 ns 3−6

trec Recovery Time

MR to CP 5.0 0 0 0.5 ns 3−9

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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AC OPERATING REQUIREMENTS

Symbol Parameter VCC*

(V)

74ACT163 74ACT163

Unit Fig.

No.

TA = +25°C

CL = 50 pF

TA = −40°C

to +85°C

CL = 50 pF

Typ Guaranteed Minimum

tsSetup Time, HIGH or LOW

Pn to CP 5.0 4.0 10.0 12.0 ns 3−9

thHold Time, HIGH or LOW

Pn to CP 5.0 −5.0 0.5 0.5 ns 3−9

tsSetup Time, HIGH or LOW

SR to CP 5.0 4.0 10.0 11.5 ns 3−9

thHold Time, HIGH or LOW

SR to CP 5.0 −5.5 −0.5 −0.5 ns 3−9

tsSetup Time, HIGH or LOW

PE to CP 5.0 4.0 8.5 10.5 ns 3−9

thHold Time, HIGH or LOW

PE to CP 5.0 −5.5 −0.5 0 ns 3−9

tsSetup Time, HIGH or LOW

CEP or CET to CP 5.0 2.5 5.5 6.5 ns 3−9

thHold Time, HIGH or LOW

CEP or CET to CP 5.0 −3.0 0 0.5 ns 3−9

twClock Pulse Width

HIGH or LOW 5.0 2.0 3.5 3.5 ns 3−6

twClock Pulse Width (Count)

HIGH or LOW 5.0 2.0 3.5 3.5 ns 3−6

*Voltage Range 5.0 V is 5.0 V ±0.5 V.

CAPACITANCE

Symbol Parameter Value

Typ Unit Test Conditions

CIN Input Capacitance 4.5 pF VCC = 5.0 V

CPD Power Dissipation Capacitance 45 pF VCC = 5.0 V

MARKING DIAGRAMS

x = 1 or 3

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

AC16x

AWLYWW

MC74AC16xN

AWLYYWW

ACT16x

AWLYWW

MC74ACT16xN

AWLYYWW

DIP−16 SO−16 EIAJ−16

74AC16x

ALYW

74ACT16x

ALYW

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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ORDERING INFORMATION

Device Package Shipping

MC74AC161N PDIP−16 25 Units/Rail

MC74ACT161N PDIP−16 25 Units/Rail

MC74AC161D SOIC−16 48 Units/Rail

MC74AC161DR2 SOIC−16 2500 Tape & Reel

MC74ACT161D SOIC−16 48 Units/Rail

MC74ACT161DR2 SOIC−16 2500 Tape & Reel

MC74AC161M EIAJ−16 50 Units/Rail

MC74ACT161MEL EIAJ−16 2000 Tape & Reel

MC74AC163N PDIP−16 25 Units/Rail

MC74ACT163N PDIP−16 25 Units/Rail

MC74AC163D SOIC−16 48 Units/Rail

MC74AC163DR2 SOIC−16 2500 Tape & Reel

MC74ACT163D SOIC−16 48 Units/Rail

MC74ACT163DR2 SOIC−16 2500 Tape & Reel

MC74AC163MEL EIAJ−16 2000 Tape & Reel

MC74ACT163MEL EIAJ−16 2000 Tape & Reel

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

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PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

16 PL

SEATING

916

PLANE

−T−

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

PDIP−16

N SUFFIX

16 PIN PLASTIC DIP PACKAGE

CASE 648−08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

SO−16

D SUFFIX

16 PIN PLASTIC SOIC PACKAGE

CASE 751B−05

ISSUE J

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

http://onsemi.com

PACKAGE DIMENSIONS

EIAJ−16

M SUFFIX

16 PIN PLASTIC EIAJ PACKAGE

CASE966−01

ISSUE O

DIM MIN MAX MIN MAX

INCHES

−−− 2.05 −−− 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

−−− 0.78 −−− 0.031

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

FLASH OR PROTRUSIONS AND ARE MEASURED

AT THE PARTING LINE. MOLD FLASH OR

PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)

PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

DETAIL P

VIEW P

0.13 (0.005) 0.10 (0.004)

16 9

MC74AC161, MC74ACT161, MC74AC163, MC74ACT163

http://onsemi.com

Notes

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