FEDL7022-01-06
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Semiconductor This ver sion: May 2000
Previous vers ion: Sep. 1999
ML7022-01
Single Rail Dual Channel PCM CODEC
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GENERAL DESCRIPTION
The ML7022 is a two-channel single-rail CODEC CMOS IC for voice signals ranging from 300 to 3400Hz. This
device contains two-channel analog-to-digital (A/D) and digital -to-analog (D/ A) converters on a single chip. The
ML7022 is designed especially for a single power supply and low power applications and achieves a reduced
footprint.
The ML7022 is best suited for line card applications with easy interface to subscriber line interface circuits
(SLICs). The SLIC interface latches are embedded onto this CODEC, thus eliminating the need for external
components and optimizing board space.
FEATURES
•Single 5 V Power Supply Operation
•Using ∆-Σ ADC and DAC Technique
•Low Power Consumption
2-Channel Operating Mode: typical: 70 mW max.: 90 mW
1-Channel Operating Mode: typical: 40 mW max.: 55 mW
Power Saving Mode: (CPD1 = CPD2 = “0”) typical: 9 mW max.: 12.5 mW
Power Down Mode: (PDN = “0”) typical: 0.05 mW max.: 0.25 mW
•ITU-T Companding Law - µ-law
•Built-in Dual 3-bit Latches with CMOS Dri ve Capa bility
•Serial PCM Interface
•Master Clock: 4.096 MHz
•Transmission Clocks:
256 to 4096 kbps
•Adjustable Transmit Gai n
•Built-in Reference Voltage Supply
•Analog Output can Directly Drive a 600Ω Line Transformer
•Latched Content Echo-bac k Function
•Package Type:
30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: ML7022-01MB)
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BLOCK DIAGRAM
RC
LPF
RC
LPF
RC
LPF
RC
LPF
∆-Σ AD
CONV BPF
BPF
LPF
LPF
∆-Σ AD
CONV
∆-Σ DA
CONV
∆-Σ DA
CONV
AIN1
GSX1
Compressor
Compressor
Expander
Expander
DOUT
TCONT
AOUT1
AOUT2
RCONT
BCLK
XSYNC
RSYNC
DIN
AIN2
GSX2
LATCH
C1A
C2A
C3A
C1B
C2B
C3B
Power Cont.
&
Clock Gen.
PDN
MCK
SG
Gen.
SGC
VDD
AG
DG
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PIN CONFIGURATION (TOP VIEW)
30-Pin Plastic SSOP
1
VDD
TEST1
TEST2
AIN1
GSX1
AOUT1
TEST3
AG
SGC
AOUT2
GSX2
AIN2
TEST4
TEST5
VDD
PDN
C1A
C2A
C3A
RSYNC
XSYNC
DG
DOUT
DIN
BCLK
MCK
C3B
C2B
C1B
TEST6
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
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PIN DESCRIPTIONS
Pin Symbol Type Description
1V
DD — Power Supply *
2 TEST1 I Device Test Pin 1
3 TEST2 I Device Test Pin 2
4 AIN1 I Channel-1 Transmit Op-amp Input
5 GSX1 O Channel-1 Transmit Op-amp Output
6 AOUT1 O Channel-1 Receive Output
7 TEST3 I Device Test Pin 3
8 AG — Analog Ground
9 SGC O Signal Ground
10 AOUT2 O Channel-2 Receive Output
11 GSX2 O Channel-2 Transmit Op-amp Output
12 AIN2 I Channel-2 Transmit Op-amp Input
13 TEST4 I Devic e Test Pin 4
14 TEST5 I Devic e Test Pin 5
15 VDD — Power Supply *
16 TEST6 I Devic e Test Pin 6
17 C1B O C1B Bit Latched Output
18 C2B O C2B Bit Latched Output
19 C3B O C3B Bit Latched Output
20 MCK I Master Clock (4.096 MHz)
21 BCLK I Shift Clock for the DIN and DOUT
22 DIN I Data Input
23 DOUT O Data Output
24 DG — Digital Ground
25 XSYNC I Transmit Synchronizing Signal
26 RSYNC I Receive Synchronizing Signal
27 C3A O C3A Bit Latched Output
28 C2A O C2A Bit Latched Output
29 C1A O C1A Bit Latched Output
30 PDN I Power Down Control
* VDD of pin 1 and VDD of pin 15 are connected internally, but these pins must be connected on the printed
circuit board.
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ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
Power Supply Voltage VDD — –0.3 to +7.0 V
Analog Input Voltage VAIN — –0.3 to VDD+0.3 V
Digital Input Voltage VDIN — –0.3 to VDD+0.3 V
Storage Temperature TSTG — –55 to +150 °C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition Min. Typ. Max. Unit
Power Supply Voltage VDD Voltage must be fixed 4.75 5.0 5.25 V
Operating Temperature TOP — –40 — +85 °C
Analog Input Voltage VAIN Gain = 1 — — 3.4 VPP
High Level Input Voltage VIH 2.2 — VDD V
Low Level Input Voltage VIL All Digital Input Pins 0—0.8V
MCK Frequency FMCK MCK –0.01% 4096 +0.01% kHz
BCLK Frequency FBCLK BCLK 256 — 4096 kHz
Sync Pulse Frequency FSYNC XSYNC, RSYNC — 8 — kHz
Clock Duty Ratio DCLK MCK, BCLK 40 50 60 %
Digital Input Rise Time TIR ——50ns
Digital Input Fall Time TIF All Digital Input Pins ——50ns
MCK to BCLK Phase
Difference TMB MCK, BCLK — — 50 ns
TXS BCLK to XSYNC 50 — — ns
Transmit Sync Pulse Setting
Time TSX XSYNC to BCLK 50 — — ns
TRS BCLK to RSYNC 50 — — ns
Receive Sync Pulse Setting
Time TSR RSYNC to BCLK 50 — — ns
Sync Pulse Width TWS XSYNC, RSYNC 1 BCLK — 100 µs
DIN Set-up Time TDS DIN 50 — — ns
DIN Hold Time TDH DIN 50 — — ns
RDL Pull-up Resi stor, DOUT 0.5 — — kΩ
DOUT — — 50 pF
Digital Output Load CDL C1A, C2A, C3A,C1B, C2B, C3B — — 50 pF
Bypass Capacitor for SGC CSG SG to AG 0.1 — — µF
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ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter Symbol Condition Min. Typ. Max. Unit
IDD1 2CH Operating Mode, No Signal
PDN = “1”, CPD1 = CPD2 = “1” — 14.0 18.0 mA
IDD2
1CH Operating Mode, No Signal
PDN = “1”, CPD1 = “1”, CPD2 =
“0” or PDN = “1”, CPD1 = “0”,
CPD2 = “1”
— 8.0 11.0 mA
IDD3 Power Saving Mode,
PDN = “1”, CPD1 = CPD2 = “0” —1.82.5mA
Power Supply Current
IDD4 Power Down Mode,
PDN = “0” — 0.01 0.05 mA
High Level Input Leakage
Current IIH All Digital Input Pins
VI = VDD ——2.0µA
Low Level Input Leakage
Current IIL All Digital Input Pins
VI = 0 V ——0.5µA
DOUT, Pull-up = 0.5 kΩ00.20.4V
Digital Output Low Voltage VOL C1A, C2A, C3A, C1B, C2B, C3B
IOL = 0.4 mA 00.20.4V
C1A, C2A, C3A, C1B, C2B, C3B
IOH = 0.4 mA 2.5 — — V
Digital Output High Voltage VOH C1A, C2A, C3A, C1B, C2B, C3B
IOH = 50 µAVDD
–0.5 ——V
Digital Output Leakage
Current IODOUT High Impedance State — — 10 µA
Input Capacitance CIN ——5—pF
Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter Symbol Condition Min. Typ. Max. Unit
SGC Rise Time TSGC SG to AG 0.1 µF
Rise time to 90% of max. level ——10ms
Transmit Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter Symbol Condition Min. Typ. Max. Unit
Input Resistance RINX AIN1, AIN2 10 — — MΩ
Output Load Resistance RLGX 20 — — kΩ
Output Load Capacitance CLGX ——30pF
Output Amplitude VOGX
GSX1, GSX2
with respect to SG
*1 –1.13 — 1.13 V
Offset Voltage VOSGX Gain = 1 –20 — 20 mV
*1 0.27 dBm (600Ω) = 3.17 dBm0 (µ-l a w) = 2.26 VPP
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Receive Analog Interface Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Parameter Symbol Condition Min. Typ. Max. Unit
Output Load Resistance RLAO AOUT1, AOUT2 (each)
with respect to SG 0.6 — — kΩ
Output Load Capacitance CLAO AOUT1, AOUT2 — — 50 pF
Output Amplitude VOAO AOUT1, AOUT2, RLAO = 0.6 kΩ
with respect to SG –1.7 — 1.7 V
Offset Voltage VOSAO AOUT1, AOUT2
with respect to SG –100 — 100 mV
AC Characteristics (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Condition
Parameter Symbol Freq.
(Hz) Level
(dBm0) Min. Typ. Max. Unit
Loss T1 60 25 45 —
Loss T2 300 –0.15 0.15 0.20
Loss T3 1020 Reference
Loss T4 3000 –0.15 0.02 0.20
Loss T5 3300 –0.15 0.1 0.80
Transmit
Frequency Response
Loss T6 3400
0GSXn to DOUT
(Attenuation)
0 0.6 0.80
dB
Loss R1 100 –0.15 0.04 0.2
Loss R2 1020 Reference
Loss R3 3000 –0.15 0.07 0.2
Loss R4 3300 –0.15 0.2 0.8
Receive
Frequency Response
Loss R5 3400
0DIN to AOUTn
(Attenuation)
00.60.8
dB
SDT1 3 36 43 —
SDT2 0 36 40 —
SDT3 –30 36 38 —
SDT4 –40 30 32 —
Transmit
Signal to Distortion
Ratio SDT5
1020
–45
GSXn to DOUT
*2
25 29 —
dB
SDR1 3 36 42 —
SDR2 0 36 39 —
SDR3 –30 36 39 —
SDR4 –40 30 33 —
Receive
Signal to Distortion
Ratio SDR5
1020
–45
DIN to AOUTn
*2
25 30 —
dB
GTT1 3 –0.2 0.02 0.2
GTT2 –10 Reference
GTT3 –40 –0.2 0.06 0.2
GTT4 –50 –0.6 0.4 0.6
Transmit
Gain Tracking
GTT5
1020
–55
GSXn to DOUT
–1.2 0.4 1.2
dB
GTR1 3 –0.2 0 0.2
GTR2 –10 Reference
GTR3 –40 –0.2 –0.02 0.2
GTR4 –50 –0.6 –0.1 0.6
Receive
Gain Tracking
GTR5
1020
–55
DIN to AOUTn
–1.2 –0.2 1.2
dB
NIDLE
T
——
AINn = SG *2
AINn to DOUT —1416
Idle Channel Noise NIDLE
R
——
DIN = 0 code *2
DIN to AOUTn —610
dBrnc0
*2 C-message Filter is used
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AC Characteristics (Continued) (VDD = 4.75 to 5.25 V, Ta = –40 to +85°C)
Condition
Parameter Symbol Freq.
(Hz) Level
(dBm0) Min. Typ. Max. Unit
AVT
GSXn to DOUT
VDD = 5 V,
Ta = 25°C0.535 0.555 0.574
Absolute Level
(Initial Difference) AVR
DIN to AOUTn
VDD = 5 V,
Ta = 25°C0.806 0.835 0.864
Vrms
AVTT –0.3 — 0.3Absolute level
(Deviation of
Temperature and
power) AVRT
1020 0
V
DD
= 4.75 to 5.25 V
Ta = –40 to 85°C–0.3 — 0.3 dB
Absolute Delay TD1020 0 A to A Mode
BCLK = 2048 kHz — 0.58 0.6 ms
TGD T1 500 — 0.26 0.75
TGD T2 600 — 0.16 0.35
TGD T3 1000 — 0.02 0.125
TGD T4 2600 — 0.05 0.125
Transmit Group Delay
TGD T5 2800
0*3
— 0.07 0.75
ms
TGD R1 500 — 0.00 0.75
TGD R2 600 — 0.00 0.35
TGD R3 1000 — 0.00 0.125
TGD R4 2600 — 0.09 0.125
Receive Group Delay
TGD R5 2800
0*3
— 0.12 0.75
ms
CRTTrans to Receive 75 83 —
CRRReceive to Trans 75 80 —
Cross Talk
Attenuation CRCH
1020 0 Channel to Channel 75 78 — dB
Discrimination DIS 4.6 to 72k 0 0 to 4 kHz 30 32 — dB
Out of Band Spurious OBS 300 to
3.4k 0 4.6 kHz to 1000 kHz — –37.5 –35 dB
SFDT— –50 –40
Signal Frequency
Distortion SFDR1020 0 0 to 4 kHz — –48 –40 dBm0
IMDT— –50 –40
Intermoduration
Distortion IMDR
fa = 470
fb = 320 –4 2 fa - fb — –54 –40 dBm0
PSRT1 0 to 4k 40 44 —
PSRT2 4 to 50k 50 55 —
PSRR1 0 to 4k 40 45 —
Power Supply Noise
Rejection Ratio PSRR2 4 to 50k
100
mVrms *4
50 56 —
dB
TSD 20 — 100
TXD1 20 — 100
TXD2
DOUT
Pull-up resister = 0.5 kΩ
CL = 50 pF and 1 LSTTL 20 — 100 ns
Digital Output
Delay Ti me TPDC C1A, C2A, C3A, C1B, C2B, C3B
CL = 50 pF and 1 LSTTL 20 — 1000 ns
DOUT Operation
Delay Ti me TDDO Time of operation start after power on — 4 — ms
AOUT Signal Output
Delay Ti me TDAO Time of base band signal output start
after power on —4—ms
*3 Minimum value of the group delay distortion
*4 The measurement under idle channel noise
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TIMING DIAGRAM
Figure 1 Transmit Side Timing Diagram
Figure 2 Receive Side Timing Diagram
Figure 3 Transmit Side Bit Configuration
Figure 4 Receive Side Bit Configuration
MCK
T
XS
D2
12345678
T
SX
T
XD1
T
SD
D3 D4 D5 D6 D7 D8MSD
T
WS
T
XD2
T
MB
BCLK
XSYNC
DOUT
T
RS
D2
12345678
T
SR
T
DS
T
WS
T
DH
D3 D4 D5MSD D6 D7 D8
T
MB
MCK
BCLK
RSYNC
DIN
MSD
EC3A
D2
D3
D4
D5
D6
D7
D8
EPD1
EC2A
EC1A
MSD
EC3B
D2
D3
D4
D5
D6
D7
D8
EPD2
EC2B
EC1B
MSD
D2
D3
1 9 17 25 1
CH1 PCM DATA ECHO bits CH2 PCM DATA ECHO bits
BCLK
XSYNC
DOUT
MSD
C3A
D2
D3
D4
D5
D6
D7
D8
CPD1
C2A
C1A
MSD
C3B
D2
D3
D4
D5
D6
D7
D8
CPD2
C2B
C1B
MSD
D2
D3
1 9 17 25 1
CH1 PCM DATA
CH1 power down control bit
CH2 PCM DATA Latch Da ta
CH2 power down control bi
t
Latch Data
BCLK
RSYNC
DIN
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MSD
D2
D3
D4
D5
D6
D7
D8
CPD1
C3A
C2A
C1A
MSD
D2
D3
D4
D5
D6
D7
D8
CPD2
C3B
C2B
C1B
MSD
D2
D3
D4
D5
D6
D7
D8
CPD1
C3A
C2A
C1A
MSD
D2
D3
D4
D5
D6
D7
D8
CPD2
C3B
C2B
C1B
CH1 PCM
INPUT DATA Control
DATA CH2 PCM
INPUT DATA Control
DATA CH1 PCM
INPUT DATA Control
DATA CH2 PCM
INPUT DATA Control
DATA
1 9 17 25 1 9 17 25
MSD
D2
D3
D4
D5
D6
D7
D8
EPD1
EC3A
EC2A
EC1A
MSD
D2
D3
D4
D5
D6
D7
D8
EPD2
EC3B
EC2B
EC1B
MSD
D2
D3
D4
D5
D6
D7
D8
EPD1
EC3A
EC2A
EC1A
MSD
D2
D3
D4
D5
D6
D7
D8
EPD2
EC3B
EC2B
EC1B
CH1 PCM
OUTPUT DATA ECHO
BIT CH2 PCM
OUTPUT DATA ECHO
BIT CH2 PCM
OUTPUT DATA ECHO
BIT CH1 PCM
OUTPUT DATA ECHO
BIT
TPDC TPDC
BCLK
XSYNC
RSYNC
DIN
DOUT
C3A, C2A,
C1A, C3B,
C2B, C1B
Figure 5 Control Bit Timing and Echo Back Timing
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Figure 6 SGC, DOUT and AOUT Output Timing
PDN
CPD1
(CPD2)
DOUT
SGC
TSGC
TDDO
TDAO
OUTn
SG Level
High Impedance
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FUNCTIONAL DESCRIPTION
Pin Functional Description
AIN1, AIN2, GSX1, GSX2
AIN1 and AIN2 are the transmit analog inputs for Channels 1 and 2.
GSX1 and GSX2 are the transmit level adjustments for Channels 1 and 2.
AIN1 and AIN2 are inverting inputs for the op-amp; GSX1 and GSX2 are connected to the output of the op-amp
and are used to adjust the level, as shown below.
If AIN1 and AIN2 are not used, connect AIN1 to GSX1 and AIN2 to GSX2. During power saving and power down
mode, the GSX1 and GSX2 outputs are at AG voltage.
In the case of the analog input 2.26 Vpp at GSX pin with digital output +3.17 dBm0 (µ-law).
AOUT1, AOUT2
AOUT1 is the receive analog output for Channel 1 and AOUT2 is used for Channel 2.
The output signal has an amplitude of 3.4Vpp above and below the signal ground voltage (SG).When the digital
signal of +3.17 dBm0 is input to DIN, it can drive a load of 600Ω or more.
During power saving or power down mode, these outputs are at a high impedance.
VDD
Power supply for +5 V.
Connect a bypass capacitor of 0.1 µF with excellent high frequenc y characteristics between this pin and the AG
pin.
Alt ho ug h V DD pin 1 and VDD pin 15 are connected internally, these pins must be connected on the printed circuit
board.
CH1 Gain
Gain = R2/R1 ≤ 10
R1: Variable
R2 > 20 kΩ
C1 > 1/ (2 × 3.14 × 30 × R1)
CH2 Gain
Gain = R4/R3 ≤ 10
R3: Variable
R4 > 20 kΩ
C2 > 1/ (2 × 3.14 × 30 × R3)
CH1
Analog
Input
GSX1
AIN1
SG
R2
R1C1
CH2
Analog
Input
GSX2
AIN2
SG
R4
R3C2
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AG
Ground for the analog signal circuits.
DG
Ground for the digital signal circuits.
This groun d is separate from the analog signal ground. The DG pi n must be conn ected to the A G pin on the pri nted
circuit board to ma ke a common a nalo g gro und.
SGC
Used to generate t he signal ground voltage level, by connecting a b ypass capacitor. Connect a 0.1 µF capacitor
with excellent high frequency characteristics between the AG pin and the SGC pin.
During power down mode, this outputs are at the voltage level of AG with about 50 kΩ impedance.
MCK
Master clock input.
The frequency must be 4.096 MHz.
BCLK
Shift clock signal inpu t for the DIN and DOUT signals.
The frequency, equal to the data rate, is 256 k to 4096 kHz. This signal must be synchronized in phase with the
MCK (generated from the same clock source as MCK). Figure 1 shows the phase difference of MCK and BCLK.
RSYNC
Receive synchronizing signal input.
Signals in the receive section are synchronized b y this synchronizing signal. This signal must be synchronized in
phase with the MCK (generated from the same clock source as MCK).
XSYNC
Transmit synchronizing signal input.
The PCM output signal fro m the DOUT pin is output in synchronization with this transmit synchronizin g signal.
This syn ch ronizing si gnal sy nchroni zes all tim ing signal s of all sect ion. This signal mus t be sy nchron ized in phas e
with the MCK (generated from the same clock source as MCK).
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DIN
DIN is a data input pin.
The voice band signal is converted to an an alog signal in synchronization with the RSYNC signal and BCLK. The
analog signal of channel 1 is output from AOUT1 pin and the analog signal of channel 2 is output from AOUT2
pin.
The 28 bit signal structure is shown in Figure 4. It consists of voice band PCM signals (8 bits each), the general-
purpose latch signal (6 bits total), the power do wn control signal (1 bit per channel) and empt y bits (4 bits). T he
signal is shifted at a falling edge of the BCLK signal and latched into the internal register when shifted by 28 bits.
The start of the PCM data (Channel 1’s M SD) is id entified at the rising edge of RSYNC.
The general purpose lat ch sig nal (C3A, C2A, C1A, C3B, C2B, C1B) are o ut put from six lat ch output pins.
When the CPD1 (bit of DIN) = “0”, Channe l 1 block is in a power down state. When the CPD2 (bit of DIN) = “ 0”,
Channel 2 block is in a power down state.
DOUT
DOUT is a data o utput pin.
The signal consist of a total of 28 bits containing the voice band PCM sign als (each channel 8 bits), the echo bit (6
bits f or l at ch sign al and 2 bits f or power down s tat e indi cati on ), an d empty bits (4 bits). The ou tpu t cording form at
follows ITU-T recommendation on coding law.
The output s ign a l is out put f rom Channel 1’ s MS D bit in a sequ ent ia l order, sy nchronizing with the rising edg e of
the BCLK s ignal. The f irst bit of DOUT may be ou tput at the rising edg e of the XSYNC signal, bas ed on the timi ng
between BCLK and XSYNC.
This pin is in a high impedance state during power down state.
A pull-up resistor must be connected to this pin because it is an open drain output.
Table 1 The Output Cording Format
PCMIN/PCMOUT
µ-law
INPUT/OUTPUT
Level MSDD2D3D4D5D6D7D8
+ Full scale 10000000
+0 11111111
–0 01111111
– Full scale 00000000
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C1A, C2A, C3A, C1B, C2B, C3B
General-purpose latched output signal.
C1A, C2A, C3A, C1B, C2B, C3B bits o f DIN are latched using internal timing.
These outputs can drive a LST TL/CMOS device without external resistor.
PDN
Power down control signal.
When PDN is at logic “0” level, both Channel 1 and Channel 2 circuits are in the power down state. Also, all
internal latches are in initial state (logic “0” leve l).
TEST1, TEST2, TEST3, TEST4 , TEST5, TEST6
These pins are used for device test.
These device test pin must be connected to the AG pin.
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Table 2 Condition of DOUT by the Power Control
PDN CPD1 CPD2 CH1 PCM Data CH2 PCM Data CH1 Ech o Bit CH2 Echo Bit
00/10/1HHHH
1 0 0 11111111 11111111
1 1 0 Operate 11111111
1 0 1 11111111 Operate
1 1 1 Operate Operate
Latched Data Latched Data
Table 3 Condition of the Latched Output by the Power Control
PDN CPD1 CPD2 LIN C1A, C2A, C3A C1B, C2B, C3B
00/10/1 L L
10/10/10Latched Data Latched Data
0/1 0/1 0/1 1 L L
Table 4 Condition of the Analog Output by the Power Control
PDN CPD1 CPD2 GSX1 GSX2 AOUT1 AOUT2 SGC
00/10/1 High
Impedance High
Impedance High
Impedance High
Impedance *5
100 High
Impedance High
Impedance High
Impedance High
Impedance Operate
1 1 0 Operate High
Impedance Operate High
Impedance Operate
101 High
Impedance Operate High
Impedance Operate Operate
1 1 1 Operate Operate Operate Operate Operate
*5 The voltage level of AG with about 50 kΩ
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APPLICATION CIRCUITS
ML7022
A
IN1
GSX1
A
OUT1
A
IN2
GSX2
A
OUT2
SGC
A
G
DG
V
DD
DOUT
DIN
MCK
BCLK
XSYNC
RSYNC
PDN
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
C1A
C2A
C3A
C1B
C2B
C3B
2CH Multiplex PCM signal output
2CH Multiplex PCM signal input
Master clock & Bit clock input
Master clock & Bit clock input
Power down control
0: power down/1: operation
Latch output
Channel 1
analog input
Channel 1
analog output
Channel 2
analog input
Channel 2
analog output
0 V
+5 V
1 kΩ+5 V
0.1 µF
0.1 µF1 µF
+
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RECOMMENDATIONS FOR ACTUAL DESIGN
•To assure specified electrical ch aracteristics, us e bypass capacitors with excellent high frequ ency characteristics
for the power supply and keep them as close as possible to the device pins.
•Connect the AG pin and DG pin each other as closely as possible. Connect to the system ground with low
impedance.
•Unless unavoidable, use short lead type socket.
•When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as
power supply transformers surround the device.
•Keep the voltage on the VDD pin not low er than –0.3 V even inst antaneously to avoid latch- up phenomen on when
turning the power on.
•Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous
operation and the degradation of the characteristics of these device.
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PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Theref ore, bef ore you perfor m reflow m ounting, c ontact O k i’s res ponsibl e sal es pers on for the produc t
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
SSOP30-P-56-0.65-K
Mirror finish
Package material Epoxy resin
Lead frame materi al 42 alloy
Pin treatment Solder plating (≥5µm)
Package weight (g) 0.19 TYP.
5
Rev. No./Last Revised 5/Dec. 5, 1996
(Unit: mm)
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NOTICE
1. The information cont ained herein can change without notice owing to product and/or techn ical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performa nce of the product . When planning t o use the product , please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, a nd operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
grante d by us in conn ection with the use of the product and/or the information and drawings con tained herein.
No responsibility is assumed by us f or any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized f or us e in any system or application that requ ires s pecial
or enhanced quality and reliability characteristics nor in any syste m or ap plication where the failure of suc h
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not lim ited to, traf fic and automotive equ ipment, safety devi ces, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take approp riate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2000 Oki Electric Industry Co., Ltd.