Single-Channel, 1024-Position, Digital Rheostat
with I2C Interface and 50-TP Memory
AD5175
Rev. A
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FEATURES
Single-channel, 1024-position resolution
10 kΩ nominal resistance
50-times programmable (50-TP) wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C
2.7 V to 5.5 V single-supply operation
±2.5 V to ±2.75 V dual-supply operation for ac or bipolar
operations
I2C-compatible interface
Wiper setting and memory readback
Power on refreshed from memory
Resistor tolerance stored in memory
Thin LFCSP, 10-lead, 3 mm × 3 mm × 0.8 mm package
Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package
APPLICATIONS
Mechanical rheostat replacements
Op-amp: variable gain control
Instrumentation: gain, offset adjustment
Programmable voltage to current conversions
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration
FUNCTIONAL BLOCK DIAGRAM
10
V
DD
A
W
AD5175
SCL
ADDR
SDA I
2
C
SERIAL
INTERFACE
POWER-ON
RESET
RDAC
REGISTER
50-TP
MEMORY
BLOCK
RESET
V
SS
EXT_CAP GND
08719-001
Figure 1.
GENERAL DESCRIPTION
The AD5175 is a single-channel, 1024-position digital rheostat
that combines industry leading variable resistor performance
with nonvolatile memory (NVM) in a compact package.
This device supports both dual-supply operation at ±2.5 V to
±2.75 V and single-supply operation at 2.7 V to 5.5 V, and offers
50-times programmable (50-TP) memory.
The AD5175 device wiper settings are controllable through the
I2C–compatible digital interface. Unlimited adjustments are
allowed before programming the resistance value into the
50-TP memory. The AD5175 does not require any external
voltage supply to facilitate fuse blow and there are 50 oppor-
tunities for permanent programming. During 50-TP activation,
a permanent blow fuse command freezes the resistance position
(analogous to placing epoxy on a mechanical rheostat).
The AD5175 is available in a 3 mm × 3mm 10-lead LFCSP
package and in a 10-lead MSOP package. The part is guaranteed
to operate over the extended industrial temperature range of
−40°C to +125°C.
AD5175
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applicat ions ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Interface Timing Specifications .................................................. 4
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 11
Theory of Operation ...................................................................... 12
Serial Data Interface ................................................................... 12
Shift Register ............................................................................... 12
Write Operation.......................................................................... 13
Read Operation........................................................................... 15
RDAC Register ............................................................................ 16
50-TP Memory Block ................................................................ 16
Write Protection ......................................................................... 16
50-TP Memory Write-Acknowledge Polling .......................... 18
Reset ............................................................................................. 18
Shutdown Mode ......................................................................... 18
RDAC Architecture .................................................................... 18
Programming the Variable Resistor ......................................... 18
EXT_CAP Capacitor .................................................................. 19
Terminal Voltage Operating Range ......................................... 19
Power-Up Sequence ................................................................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/10—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 20
3/10—Revision 0: Initial Version
AD5175
Rev. A | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resolution 10 Bits
Resistor Integral Nonlinearity2, 3 R-INL |VDD − VSS| = 3.6 V to 5.5 V −1 +1 LSB
|VDD − VSS| = 3.3 V to 3.6 V −1 +1.5 LSB
|VDD − VSS| = 2.7 V to 3.3 V −2.5 +2.5 LSB
Resistor Differential Nonlinearity2 R-DNL
−1 +1 LSB
Nominal Resistor Tolerance ±15 %
Resistance Temperature Coefficient4, 5 Code = full scale 35 ppm/°C
Wiper Resistance Code = zero scale 35 70 Ω
RESISTOR TERMINALS
Terminal Voltage Range4, 6 V
TERM V
SS V
DD V
Capacitance A4 f = 1 MHz, measured to GND, code = half scale 90 pF
Capacitance W4 f = 1 MHz, measured to GND, code = half scale 40 pF
Common-Mode Leakage Current4 V
A = VW 50 nA
DIGITAL INPUTS
Input Logic4
High VINH 2.0 V
Low VINL 0.8 V
Input Current IIN ±1 µA
Input Capacitance4 C
IN 5 pF
DIGITAL OUTPUT
Output Voltage4
High VOH R
PULL_UP = 2.2 kΩ to VDD V
DD − 0.1 V
Low VOL R
PULL_UP = 2.2 kΩ to VDD
V
DD = 2.7 V to 5.5 V, VSS = 0 V 0.4 V
V
DD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V
Tristate Leakage Current −1 +1 µA
Output Capacitance4 5 pF
POWER SUPPLIES
Single-Supply Power Range VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range ±2.5 ±2.75 V
Supply Current
Positive IDD 1 µA
Negative ISS −1 µA
50-TP Store Current4, 7
Positive IDD_OTP_STORE 4 mA
Negative ISS_OTP_STORE −4 mA
50-TP Read Current4, 8
Positive IDD_OTP_READ 500 µA
Negative ISS_OTP_READ −500 µA
Power Dissipation9 P
DISS V
IH = VDD or VIL = GND 5.5 µW
Power Supply Rejection Ratio4 PSRR ∆VDD/∆VSS = ±5 V ± 10% −50 −55 dB
AD5175
Rev. A | Page 4 of 20
Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS4, 10
Bandwidth −3 dB, RAW = 5 kΩ, Terminal W, see Figure 23 700 kHz
Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ −90 dB
Resistor Noise Density RWB = 5 kΩ, TA = 25°C, f = 10 kHz 13 nV/√Hz
1 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from the ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions.
3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW.
4 Guaranteed by design and not subject to production test.
5 See Figure 8 for more details.
6 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar
signal adjustment.
7 Different from operating current; the supply current for the fuse program lasts approximately 55 ms.
8 Different from operating current; the supply current for the fuse read lasts approximately 500 ns.
9 PDISS is calculated from (IDD × VDD) + (ISS × VSS).
10 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.
INTERFACE TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Limit at TMIN, TMAX
Parameter Conditions1 Min Max Unit Description
fSCL2 Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz Serial clock frequency
t1 Standard mode 4 µs tHIGH, SCL high time
Fast mode 0.6 µs tHIGH, SCL high time
t2 Standard mode 4.7 µs tLOW, SCL low time
Fast mode 1.3 µs tLOW, SCL low time
t3 Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns tSU;DAT, data setup time
t4 Standard mode 0 3.45 µs tHD;DAT, data hold time
Fast mode 0 0.9 µs tHD;DAT, data hold time
t5 Standard mode 4.7 µs tSU;STA, set-up time for a repeated start condition
Fast mode 0.6 µs tSU;STA, set-up time for a repeated start condition
t6 Standard mode 4 µs tHD;STA, hold time (repeated) start condition
Fast mode 0.6 µs tHD;STA, hold time (repeated) start condition
High speed mode 160 ns tHD;STA, hold time (repeated) start condition
t7 Standard mode 4.7 µs tBUF, bus free time between a stop and a start condition
Fast mode 1.3 µs tBUF, bus free time between a stop and a start condition
t8 Standard mode 4 µs tSU;STO, setup time for a stop condition
Fast mode 0.6 µs tSU;STO, setup time for a stop condition
t9 Standard mode 1000 ns tRDA, rise time of the SDA signal
Fast mode 300 ns tRDA, rise time of the SDA signal
t10 Standard mode 300 ns tFDA, fall time of the SDA signal
Fast mode 300 ns tFDA, fall time of the SDA signal
t11 Standard mode 1000 ns tRCL, rise time of the SCL signal
Fast mode 300 ns tRCL, rise time of the SCL signal
t11A Standard mode 1000 ns
tRCL1, rise time of the SCL signal after a repeated start condition
and after an acknowledge bit
Fast mode 300 ns
tRCL1, rise time of the SCL signal after a repeated start condition
and after an acknowledge bit
t12 Standard mode 300 ns tFCL, fall time of the SCL signal
Fast mode 300 ns tFCL, fall time of the SCL signal
t13 RESET pulse time 20 ns
Minimum RESET low time
tSP3 Fast mode 0 50 ns Pulse width of the spike is suppressed
tEXEC4, 5 500 ns Command execute time
AD5175
Rev. A | Page 5 of 20
Limit at TMIN, TMAX
Parameter Conditions1 Min Max Unit Description
tRDAC_R-PERF 2 µs RDAC register write command execute time (R-Perf mode)
tRDAC_NORMAL 600 ns RDAC register write command execute time (normal mode)
tMEMORY_READ 6 µs Memory readback execute time
tMEMORY_PROGRAM 350 ms Memory program time
tRESET 600 µs Reset 50-TP restore time
tPOWER-UP6 2 ms Power-on 50-TP restore time
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations.
5 Refer to tMEMORY_READ and tMEMORY_PROGRAM for memory commands operations.
6 Maximum time after VDD − VSS is equal to 2.5 V.
Shift Register and Timing Diagrams
DATA BI TS
DB9 (MSB) DB0 (L S B)
D7 D6 D5 D4 D3 D2 D1 D0
CONT RO L BI T S
C0 C1
C2 D9 D8
C3
0 0
0
8719-003
Figure 2. Shift Register Content
RESET
t
7
t
6
t
2
t
4
t
11
t
12
t
6
t
5
t
10
t
1
SCL
SDA
PS S P
t
3
t
8
t
9
t
13
0
8719-002
Figure 3. 2-Wire I2C Timing Diagram
AD5175
Rev. A | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7.0 V
VSS to GND +0.3 V to −7.0 V
VDD to VSS 7 V
VA, VW to GND VSS − 0.3 V, VDD + 0.3 V
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
EXT_CAP to VSS 7 V
IA, IW
Pulsed1
Frequency > 10 kHz ±6 mA/d2
Frequency ≤ 10 kHz ±6 mA/√d2
Continuous ±6 mA
Operating Temperature Range3 −40°C to +125°C
Maximum Junction Temperature
(TJ Maximum)
150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A and W terminals at a given
resistance.
2 Pulse duty factor.
3 Includes programming of 50-TP memory.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
10-Lead LFCSP 50 3 °C/W
10-Lead MSOP 1351 N/A °C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
AD5175
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD
1
1
VSS
2
2
A
3
3
W
4
4RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6GND
AD5175
TOP VIEW
(Not t o S ca l e)
ADDR
08719-004
*L EAV E FLOAT ING OR CONNECTED TO V
SS
.
ADDR
V
DD
1
V
SS
2
A
3
W
4RESET
10
9
8
SCL
7
5
EXT_CAP
SDA
6GND
AD5175
(EXPOSED
PAD)*
08719-103
Figure 4. MSOP Pin Configuration Figure 5. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
2 A Terminal A of RDAC. VSS ≤ VA ≤ VDD.
3 W Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
4 VSS Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 F ceramic capacitors
and 10 F capacitors.
5 EXT_CAP
External Capacitor. Connect a 1 µF capacitor between EXT_CAP and VSS. This capacitor must have a voltage
rating of ≥7 V.
6 GND Ground Pin, Logic Ground Reference.
7 RESET Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory
default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET
to VDD if not used.
8 SDA Serial Data Line. This pin is used in conjunction with the SCL line to clock data into or out of the 16-bit input
registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external
pull-up resistor.
9 SCL Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 16-bit
input registers.
10 ADDR Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6).
EPAD Exposed Pad Leave floating or connected to VSS
AD5175
Rev. A | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0 128 256 384 512 640 768 896 1023
INL (LSB)
CODE (De ci mal)
+25°C
–40°C
+125°C
08719-014
Figure 6. R-INL in Normal Mode vs. Code vs. Temperature
0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0 128 256 384 512 640 768 896 1023
DNL ( L S B)
CODE (Deci mal )
+25°C
–40°C
+125°C
08719-015
Figure 7. R-DNL in Normal Mode vs. Code vs. Temperature
700
600
500
400
300
200
100
00 128 256 384 512 640 768 896 1023
RHEO S T AT M O DE T E M P CO (pp m/ ° C)
CODE ( Decimal )
V
DD
/V
SS
= 5V/0V
08719-019
Figure 8. Tempco ΔRWA/ΔT vs. Code
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
CURRENT ( mA)
VOLTAGE (V)
0
8719-038
V
DD
/V
SS
= 5V/0V
Figure 9. Supply Current (IDD) vs. Digital Input Voltage
–500
–400
–300
–200
–100
0
100
200
300
400
500
CURRENT ( n A)
TEMPERATURE (°C)
–40 –30 –20 –10 0 20 30 40 50 60 70 80 90 100 11010
I
DD
= 5V
I
SS
= 5V
I
DD
= 3V
I
SS
= 3V
0
8719-018
Figure 10. Supply Current (IDD, ISS) vs. Temperature
7
0
1
2
3
4
5
6
0 1023850765 935680510 595340 425170 25585
THEO RE T I CAL l
WA_MAX
(mA)
CODE (Decimal)
08719-028
V
DD
/V
SS
= 5V/0V
Figure 11. Theoretical Maximum Current vs. Code
AD5175
Rev. A | Page 9 of 20
08719-031
V
DD
/V
SS
= 5V/0V
–50
–45
–35
–40
–30
–25
–20
–15
–10
–5
0
1 10M1M100k10k1k10010
GAIN (dB)
FREQ UE NCY (Hz )
0x040
0x020
0x010
0x008
0x004
0x002
0x001
0x200
0x100
0x080
Figure 12. Bandwidth vs. Frequency vs. Code
THD + N (dB)
08719-039
0
–120
–100
–80
–60
–40
–20
10 100 1k 10k 100k
FREQUENCY (Hz) 1M
V
DD
/V
SS
= ±2.5V
CODE = HALF SCALE
f
IN
= 1V rms
NOI SE BW = 22kHz
Figure 13. THD + N vs. Frequency
08719-026
0
–100
–80
–60
–40
–20
0.001 0.01 0.1 1
THD + N ( dB)
AMPL I TUDE (V rms)
10kΩ
V
DD
/V
SS
= ±2.5V
CO DE = HA LF SCALE
f
IN
= 1kHz
NOISE BW = 22kHz
Figure 14. THD + N vs. Amplitude
–
20
–25
–30
–35
–40
–45
–50
–55
–6010 100 1M100k10k1k
PSRR (dB)
FREQ UE NCY (Hz )
VDD/VSS = 5V/0V
CODE = HAL F SCAL E
08719-024
Figure 15. PSRR vs. Frequency
4
5
6
7
8
VOLTAGE (V)
TIME (Seconds)
0.07 0.09 0.11 0.13 0.15 0.17
08719-029
Figure 16. VEXT_CAP Waveform While Writing Fuse
20
–70
–60
–50
–40
–30
–20
–10
0
10
–2 420
GLITCH AMPLITUDE (mV)
TIME (µs)
08719-102
V
DD
/V
SS
= ±2.5V
I
AW
= 200µ A
Figure 17. Maximum Glitch Energy
AD5175
Rev. A | Page 10 of 20
1.0
–1.5
–1.0
–0.5
0
0.5
–10 6050403020100
VOLTAGE (mV)
TIME (µs)
08719-100
V
DD
/V
SS
= ±2.5V
I
AW
= 200µ A
0.006
–0.002
–0.001
0
0.001
0.002
0.003
0.004
0.005
0 1000900800700600500400300200100
Δ
R
AW RESIS TANCE (%)
OP E RATION AT 150°C (Hours)
08719-101
V
DD
/V
SS
= 5V/0V
I
AW
= 10µA
CODE = HALF S CALE
Figure 18. Digital Feedthrough Figure 19. Long-Term Drift Accelerated Average by Burn-In
AD5175
Rev. A | Page 11 of 20
TEST CIRCUITS
Figure 20 to Figure 24 define the test conditions used in the Specifications section.
VMS
IW
A
W
DUT
08719-033
Figure 20. Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
R
WA
=
V
MS
I
W
R
W
=R
WA
2
A
W
I
W
DUT
V
MS
CODE = 0x00
08719-034
Figure 21. Wiper Resistance
V
DD
I
W
V
MS
A
W
V+
ΔV
MS
%
ΔV
DD
%
V
MS
V
DD
V
+ = V
DD
±10
%
PSRR (dB) = 20 log
PSS (%/%) =
08719-035
Figure 22. Power Supply Sensitivity (PSS, PSRR)
V
MS
A
W
DUT
V
1GΩ
08719-036
Figure 23. Gain vs. Frequency
I
CM
DUT
W
A
NC = NO CONNECT
GND
+2.75V
NC
+2.75V –2.75V
–2.75V
GND
GND
08719-037
Figure 24. Common Leakage Current
AD5175
Rev. A | Page 12 of 20
THEORY OF OPERATION
The AD5175 is designed to operate as a true variable resistor for
analog signals within the terminal voltage range of VSS < VTERM
< VDD. The RDAC register contents determine the resistor wiper
position. The RDAC register acts as a scratchpad register, which
allows unlimited changes of resistance settings. The RDAC
register can be programmed with any position setting using
the I2C interface. When a desirable wiper position is found, this
value can be stored in a 50-TP memory register. Thereafter, the
wiper position is always restored to that position for subsequent
power-up. The storing of 50-TP data takes approximately 350 ms;
during this time, the AD5175 is locked and does not acknowl-
edge any new command thereby preventing any changes from
taking place. The acknowledge bit can be polled to verify that
the fuse program command is complete.
SERIAL DATA INTERFACE
The AD5175 has a 2-wire I2C-compatible serial interface.
It can be connected to an I2C bus as a slave device under the
control of a master device; see Figure 3 for a timing diagram
of a typical write sequence.
The AD5175 supports standard (100 kHz) and fast (400 kHz)
data transfer modes. Support is not provided for 10-bit
addressing and general call addressing.
The AD5175 has a 7-bit slave address. The five MSBs are 01011
and the two LSBs are determined by the state of the ADDR pin.
The facility to make hardwired changes to ADDR allows the
user to incorporate up to three of these devices on one bus, as
outlined in Tabl e 6.
The 2-wire serial bus protocol operates as follows: The master
initiates a data transfer by establishing a start condition, which
is when a high-to-low transition on the SDA line occurs while
SCL is high. The next byte is the address byte, which consists
of the 7-bit slave address and a R/W bit. The slave device
corresponding to the transmitted address responds by pulling
SDA low during the ninth clock pulse (this is termed the acknowl-
edge bit). At this stage, all other devices on the bus remain idle
while the selected device waits for data to be written to, or read
from, its shift register.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
When all data bits have been read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10th clock pulse to establish a stop condition. In read
mode, the master issues a no acknowledge for the ninth clock
pulse, that is, the SDA line remains high. The master then
brings the SDA line low before the 10th clock pulse, and then
high during the 10th clock pulse to establish a stop condition.
SHIFT REGISTER
For the AD5175, the shift register is 16 bits wide, as shown in
Figure 2. The 16-bit word consists of two unused bits, which
should be set to 0, followed by four control bits and 10 RDAC data
bits, and data is loaded MSB first (Bit D9). The four control bits
determine the function of the software command (Tabl e 7).
Figure 25 shows a timing diagram of a typical AD5175 write
sequence.
The command bits (Cx) control the operation of the digital
potentiometer and the internal 50-TP memory. The data bits
(Dx) are the values that are loaded into the decoded register.
Table 6. Device Address Selection
ADDR Pin A1 A0 7-Bit I2C Device Address
GND 1 1 0101111
VDD 0 0 0101100
NC (No Connection)1 1 0 0101110
1 Not available in bipolar mode. VSS < 0 V.
AD5175
Rev. A | Page 13 of 20
WRITE OPERATION
It is possible to write data for the RDAC register or the control
register. When writing to the AD5175, the user must begin with
a start command followed by an address byte (R/W = 0), after
which the AD5175 acknowledges that it is prepared to receive
data by pulling SDA low.
Two bytes of data are then written to the RDAC, the most
significant byte followed by the least significant byte; both
of these data bytes are acknowledged by the AD5175. A stop
condition follows. The write operations for the AD5175 are
shown in Figure 25.
A repeated write function gives the user flexibility to update the
device a number of times after addressing the part only once, as
shown in Figure 26.
SCL
SDA
START BY
MASTER ACK. BY
AD5175
FRAME 1
SERI AL BUS ADDRESS BY TE FRAME 2
MO S T SI GNIFICANT DATA BYT E
FRAME 3
LEAST SIGNIFICANT DAT A BY TE
SCL (CONTINUED)
SDA (CO NTINUED)
ACK. BY
AD5175
ACK. BY
AD5175 STOP BY
MASTER
0
19
1
99
91
1011A1A0 00C3C2
C1 C0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
R/W
0
8719-005
Figure 25. Write Command
AD5175
Rev. A | Page 14 of 20
SCL
S
D
A
0
19
1
99
91
10 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
SCL (CONTINUED)
SDA (CONTI NUED)
SCL (CONTINUED)
SDA (CONTI NUED)
SCL (CONTINUED)
SDA (CONTI NUED)
199
D7 D6 D5 D4 D3 D2 D1 D0
199
0 0 C3 C2 C1 C0 D9 D8
FRAME 4
MOS T SIGNI FICANT DATA BYTE
FRAME 5
LEAST SIGNIFI CANT DATA BY TE
START BY
MASTER ACK. BY
AD5175 ACK. BY
AD5175
ACK. BY
AD5175
ACK. BY
AD5175
ACK. BY
AD5175 STO P BY
MASTER
FRAME 1
SERIAL BUS ADDRES S BY TE FRAME 2
MOS T SI GNIFICANT DATA BYTE
FRAME 3
LEAS T SI GNIFICANT DATA BY T E
08719-006
Figure 26. Multiple Write
AD5175
Rev. A | Page 15 of 20
READ OPERATION
When reading data back from the AD5175, the user must first
issue a readback command to the device, this begins with a start
command followed by an address byte (R/W = 0), after which
the AD5175 acknowledges that it is prepared to receive data by
pulling SDA low.
Two bytes of data are then written to the AD5175, the most
significant byte followed by the least significant byte; both
of these data bytes are acknowledged by the AD5175. A stop
condition follows. These bytes contain the read instruction,
which enables readback of the RDAC register, 50-TP memory,
or the control register. The user can then read back the data
beginning with a start command followed by an address byte
(R/W = 1), after which the device acknowledges that it is
prepared to transmit data by pulling SDA low. Two bytes of
data are then read from the device, as shown in . A
stop condition follows. If the master does not acknowledge the
first byte, the second byte is not transmitted by the AD5175.
Figure 27
0
19
1
99
91
10 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
0
19
1
99
91
10 1 1 A1 A0 R/W 0 0 X X X X D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
AD5175 ACK. BY
AD5175
ACK. BY
AD5175
ACK. BY
AD5175 ACK. BY
MASTER
NO ACK. BY
MASTER
SCL
SD
A
SCL ( CONTINUED)
SDA (CO NTINUED)
SCL ( CONTINUED)
SDA (CO NTINUED)
START BY
MASTER
SCL
SD
A
START BY
MASTER
STOP BY
MASTER
STO P BY
MASTER
FRAME 1
SERI AL BUS ADDRESS BY T E
FRAME 1
SERI AL BUS ADDRESS BY TE
FRAME 2
MO ST SIGNI FI CANT DATA BYT E
FRAME 2
MOS T SIGNI FICANT DATA BYTE
FRAME 3
LEAS T SI GNIFICANT DATA BY T E
FRAME 3
LEAST SIGNIFICANT DAT A BY TE
08719-007
Figure 27. Read Command
AD5175
Rev. A | Page 16 of 20
RDAC REGISTER
The RDAC register directly controls the position of the digital
rheostat wiper. For example, when the RDAC register is loaded
with all 0s, the wiper is connected to Terminal A of the variable
resistor. It is possible to both write to and read from the RDAC
register using the I2C interface. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
50-TP MEMORY BLOCK
The AD5175 contains an array of 50-TP programmable
memory registers, which allow the wiper position to be pro-
grammed up to 50 times. Table 11 shows the memory map.
Command 3 in Table 7 programs the contents of the RDAC
register to memory. The first address to be programmed is
Location 0x01, see Table 11, and the AD5175 increments the
50-TP memory address for each subsequent program until
the memory is full. Programming data to 50-TP consumes
approximately 4 mA for 55 ms, and takes approximately
350 ms to complete, during which time the shift register is
locked preventing any changes from taking place. Bit C2 of
the control register in Table 10 can be polled to verify that the
fuse program command was successful. No change in supply
voltage is required to program the 50-TP memory; however, a
1 μF capacitor on the EXT_CAP pin is required as shown in
Figure 29.
Prior to 50-TP activation, the AD5175 presets to midscale on
power-up. It is possible to read back the contents of any of the
50-TP memory registers through the I2C interface by using
Command 5 in Table 7. The lower six LSB bits, D0 to D5 of
the data byte, select which memory location is to be read back.
A binary encoded version address of the most recently pro-
grammed wiper memory location can be read back using
Command 6 in Table 7. This can be used to monitor the
spare memory status of the 50-TP memory block.
WRITE PROTECTION
On power-up, serial data input register write commands for
both the RDAC register and the 50-TP memory registers are
disabled. The RDAC write protect bit (Bit C1) of the control
register (see Table 9 and Table 10), is set to 0 by default. This
disables any change of the RDAC register content regardless
of the software commands, except that the RDAC register can
be refreshed from the 50-TP memory using the software reset,
Command 4, or through the hardware by the RESET pin. To
enable programming of the variable resistor wiper position
(programming the RDAC register), the write protect bit
(Bit C1) of the control register must first be programmed.
This is accomplished by loading the serial data input register
with Command 7 (see ). To enable programming of the
50-TP memory block, Bit C0 of the control register, which is set
to 0 by default, must first be set to 1.
Table 7
Table 7. Command Operation Truth Table
Command
Number
Command[DB13:DB10] Data[DB9:DB0]1
C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X NOP: do nothing.
1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Write contents of serial register data
to RDAC.
2 0 0 1 0 X X X X X X X X X X Read contents of RDAC wiper register.
3 0 0 1 1 X X X X X X X X X X Store wiper setting: store RDAC setting
to 50-TP.
4 0 1 0 0 X X X X X X X X X X Software reset: refresh RDAC with the
last 50-TP memory stored value.
52 0 1 0 1 X X X X D5 D4 D3 D2 D1 D0
Read contents of 50-TP from the SDO
output in the next frame.
6 0 1 1 0 X X X X X X X X X X Read address of the last 50-TP
programmed memory location.
73 0 1 1 1 X X X X X X X X D1 D0
Write contents of the serial register data
to the control register.
8 1 0 0 0 X X X X X X X X X X Read contents of the control register.
9 1 0 0 1 X X X X X X X X X D0 Software shutdown.
D0 = 0; normal mode.
D0 = 1; shutdown mode.
1 X is don’t care.
2 See Table 11 for the 50-TP memory map.
3 See Table 10 for bit details.
AD5175
Rev. A | Page 17 of 20
Table 8. Write and Read to RDAC and 50-TP Memory
DIN SDO1 Action
0x1C03 0xXXXX Enable update of wiper position and 50-TP memory contents through digital interface.
0x0500 0x1C03 Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position.
0x0800 0x0500 Prepare data read from RDAC register.
0x0C00 0x100 Stores RDAC register content into 50-TP memory. 16-bit word appears out of SDO, where the last 10-bits contain the
contents of the RDAC Register 0x100.
0x1800 0x0C00 Prepare data read of the last programmed 50-TP memory monitor location.
0x0000 0xXX19 NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs (that is, the last 6 bits) contain the binary address
of the last programmed 50-TP memory location, for example, 0x19 (see Table 11).
0x1419 0x0000 Prepares data read from Memory Location 0x19.
0x2000 0x0100 Prepare data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents
of Memory Location 0x19.
0x0000 0xXXXX NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register.
If Bit C2 = 1, fuse program command successful.
1 X is don’t care.
Table 9. Control Register Bit Map
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 C2 0 C1 C0
Table 10. Control Register Description
Bit Name Description
C0 50-TP program enable
0 = 50-TP program disabled (default)
1 = enable device for 50-TP program
C1 RDAC register write protect
0 = wiper position frozen to value in OTP memory (default)1
1 = allow update of wiper position through a digital interface
C2 50-TP memory program success bit
0 = fuse program command unsuccessful (default)
1 = fuse program command successful
1 Wiper position is frozen to the last value programmed in the 50-TP memory. Wiper freezes to midscale if 50-TP memory has not been previously programmed.
Table 11. Memory Map
Command Number
Data Byte[DB9:DB0]1
Register Contents
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
5 X X X 0 0 0 0 0 0 0 Reserved
X X X 0 0 0 0 0 0 1 1st programmed wiper location (0x01)
X X X 0 0 0 0 0 1 0 2nd programmed wiper location (0x02)
X X X 0 0 0 0 0 1 1 3rd programmed wiper location (0x03)
X X X 0 0 0 0 1 0 0 4th programmed wiper location (0x04)
… … … … … … … … … … …
X X X 0 0 0 1 0 1 0 10th programmed wiper location (0xA)
… … … … … … … … … … …
X X X 0 0 1 0 1 0 0 20th programmed wiper location (0x14)
… … … … … … … … … … …
X X X 0 0 1 1 1 1 0 30th programmed wiper location (0x1E)
… … … … … … … … … … …
X X X 0 1 0 1 0 0 0 40th programmed wiper location (0x28)
… … … … … … … … … … …
X X X 0 1 1 0 0 1 0 50th programmed wiper location (0x32)
… … … … … … … … … … …
X X X 0 1 1 1 0 0 1 MSB resistance tolerance (0x39)
X X X 0 1 1 1 0 1 0 LSB resistance tolerance (0x3A)
1 X is don’t care.
AD5175
Rev. A | Page 18 of 20
50-TP MEMORY WRITE-ACKNOWLEDGE POLLING
After each write operation to the 50-TP registers, an internal
write cycle begins. The I2C interface of the device is disabled.
To determine if the internal write cycle is complete and the
I2C interface is enabled, interface polling can be executed. I2C
interface polling can be conducted by sending a start condition
followed by the slave address and the write bit. If the I2C inter-
face responds with an acknowledge (ACK), the write cycle is
complete and the interface is ready to proceed with further
operations. Otherwise, I2C interface polling can be repeated
until it completes.
RESET
The AD5175 can be reset through software by executing
Command 4 (see Table 7) or through hardware on the low
pulse of the RESET pin. The reset command loads the RDAC
register with the contents of the most recently programmed
50-TP memory location. The RDAC register loads with
midscale if no 50-TP memory location has been previously
programmed. Tie RESET to VDD if the RESET pin is not used.
SHUTDOWN MODE
The AD5175 can be shut down by executing the software
shutdown command, Command 9 (see Table 7), and setting
the LSB to 1. This feature places the RDAC in a zero-power-
consumption state where Terminal A is disconnected from the
wiper terminal. It is possible to execute any command from
Table 7 while the AD5175 is in shutdown mode. The part can
be taken out of shutdown mode by executing Command 9 and
setting the LSB to 0, or by issuing a software or hardware reset.
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5175 employs a
three-stage segmentation approach, as shown in Figure 28.
The AD5175 wiper switch is designed with the transmission
gate CMOS topology.
A
W
10-BIT
ADDRESS
DECODER
R
L
R
L
R
M
R
M
R
W
S
W
R
W
08719-008
Figure 28. Simplified RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance between Terminal W and Terminal A,
RWA , is available in 10 kΩ and has 1024-tap points accessed by
the wiper terminal. The 10-bit data in the RDAC latch is decoded
to select one of the 1024 possible wiper settings. As a result, the
general equation for determining the digitally programmed
output resistance between the W terminal and A terminal is
WAWA R
D
DR ×=
1024
)( (1)
where:
D is the decimal equivalent of the binary code loaded in the
10-bit RDAC register.
RWA is the end-to-end resistance.
In the zero-scale condition, a finite total wiper resistance of
120 Ω is present. Regardless of which setting the part is oper-
ating in, take care to limit the current between the A terminal
to W terminal, and W terminal to B terminal, to the maximum
continuous current of ±6 mA, or the pulse current specified in
Table 3. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
AD5175
Rev. A | Page 19 of 20
Calculate the Actual End-to-End Resistance TERMINAL VOLTAGE OPERATING RANGE
The resistance tolerance is stored in the internal memory
during factory testing. The actual end-to-end resistance
can, therefore, be calculated (which is valuable for calibration,
tolerance matching, and precision applications).
The positive VDD and negative VSS power supplies of the AD5175
define the boundary conditions for proper 2-terminal digital
resistor operation. Supply signals present on Terminal A and
Terminal W that exceed VDD or VSS are clamped by the internal
forward-biased diodes (see Figure 30).
The resistance tolerance in percentage is stored in fixed-point
format, using a 16-bit sign magnitude binary. The sign bit(0 =
negative and 1 = positive) and the integer part is located in
Address 0x39, as shown in Tabl e 11. Address 0x3A contains
the fractional part, as shown in Table 12 .
V
SS
V
DD
A
W
0
8719-109
That is, if the data readback from Address 0x39 is 0000001010
and data from Address 0x3A is 0010110000, then the end-to-end
resistance can be calculated as follows.
For Memory Location 0x39,
DB[9:8]: XX = don’t care
DB[7]: 0 = negative Figure 30. Maximum Terminal Voltages Set by VDD and VSS
DB[6:0]: 0001010 = 10 The ground pin of the AD5175 is primarily used as a digital
ground reference. To minimize the digital ground bounce, join
the AD5175 ground terminal remotely to the common ground.
The digital input control signals to the AD5175 must be refe-
renced to the device ground pin (GND) and satisfy the logic
level defined in the Specifications section. An internal level
shift circuit ensures that the common-mode voltage range of
the three terminals extends from VSS to VDD, regardless of the
digital input level.
For Memory Location 0x3A,
DB[9:8]: XX = don’t care
DB[7:0]: 10110000 = 176 × 2−8 = 0.6875
Therefore, tolerance = −10.6875% and RWA (1023)= 8.931 kΩ.
EXT_CAP CAPACITOR
A 1 μF capacitor to VSS must be connected to the EXT_CAP pin
(see Figure 29) on power-up and throughout the operation of
the AD5175. POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Ter minal A and Termin a l W (se e Figure 30), it is important to
power VDD/VSS first before applying any voltage to Terminal A
and Terminal W; otherwise, the diode is forward-biased such
that VDD/VSS are powered unintentionally. The ideal power-up
sequence is VSS, GND, VDD, digital inputs, VA, and VW. The
order of powering VA, VW, and digital inputs is not important
as long as they are powered after VDD/VSS.
AD5175
50-TP
MEMORY
BLOCK
EXT_CAP
C1
1µF
V
SS
V
SS
0
8719-009
As soon as VDD is powered, the power-on preset activates,
which first sets the RDAC to midscale and then restores the
last programmed 50-TP value to the RDAC register.
Figure 29. EXT_CAP Hardware Setup
Table 12. End-to-End Resistance Tolerance Bytes
Data Byte1
Memory Map Address DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0x39 X X Sign 26 2
5 2
4 2
3 2
2 2
1 2
0
0x3A X X 2−1 2
−2 2
−3 2
−4 2
−5 2
−6 2
−7 2
−8
1 X is don’t care.
AD5175
Rev. A | Page 20 of 20
OUTLINE DIMENSIONS
2.48
2.38
2.23
0.50
0.40
0.30
121009-A
TOP VIEW
10
1
6
5
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
PIN1
INDICATOR
(R0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 31. 10-Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 32. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 R
AB (kΩ) Resolution Temperature Range Package Description Package Option Branding
AD5175BRMZ-10 10 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DDR
AD5175BRMZ-10-RL7 10 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DDR
AD5175BCPZ-10-RL7 10 1,024 −40°C to +125°C 10-Lead LFCSP_WD CP-10-9 DEG
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08719-0-7/10(A)
