1 of 27GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
GS2975A HD-LINX® III Multi-Rate SDI Automatic Reclocker with Dual
Differential Outputs
www.gennum.com
Features
• SMPTE 424M, 292M, and 259M-C compliant
• Supports data rates of 270, 1483.5, 1485, 2967,
2970Mb/s
• Supports DVB-ASI at 270Mb/s
• Pb-free and RoHS Compliant
• Auto and Manual Modes for rate selection
• Standards indication in Auto Mode
• 4:1 input multiplexer patented technology
• Choice of dual reclocked data outputs or one data
output and one recovered clock output
• Footprint and drop-in compatible with existing
GS2975 designs
• Loss of Signal (LOS) Output
•Lock Detect Output
• On-chip Input and Output Termination
• Differential 50Ω inputs and outputs
• Mute, Bypass and Autobypass functions
• SD/HD indication output to control GS2978 Dual
Slew-Rate Cable Driver
• Single 3.3V power supply
• Operating temperature range: 0°C to 70°C
Applications
• SMPTE 424M, SMPTE 292M and SMPTE 259M-C Serial
Digital Interfaces
Description
The GS2975A is a Multi-Rate Serial Digital Reclocker
designed to automatically recover the embedded clock
from a digital video signal and re-time the incoming video
data.
The GS2975A Serial Digital Reclocker will recover the
embedded clock signal and re-time the data from a SMPTE
424M, SMPTE 292M, or SMPTE 259M-C compliant digital
video signal.
The GS2975A removes the high frequency jitter
components from the bit-serial stream. Input termination is
on-chip for seamless matching to 50Ω transmission lines.
The GS2975A can operate in either auto or manual rate
selection mode. In Auto mode the device will automatically
detect and lock onto incoming SMPTE SDI data signals at
any supported rate. For single rate data systems, the
GS2975A can be configured to operate in Manual mode. In
both modes, the device requires only one external crystal to
set the VCO frequency when not locked and provides
adjustment free operation.
In systems which require passing of non-SMPTE data rates,
the GS2975A can be configured to either automatically or
manually enter a bypass mode in order to pass the signal
without reclocking.
The GS2975A offers a choice of dual reclocked data outputs
or one data output and one recovered clock output. The
device is footprint and drop-in compatible with existing
GS2975 designs, with no additional application changes
required.
The GS2975A is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant.
This component and all homogeneous sub-components are
RoHS compliant.
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
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Functional Block Diagram
GS2975A Functional Block Diagram
Revision History
XTAL+ XTAL-
XTAL
OUT-
XTAL
OUT+
DDI_SEL[1:0]
DDI 1
DDI 2
DDI 3
DDI 0
LF+ LF- KBB
DDO_MUTE
DDO 0
AUTOBYPASS BYPASS
LOCKED
AUTO/MAN
SS[2:0]
XTAL
OSC BUFFER
DATA BUFFER
VCO
BYPASS
LOGIC
DIVIDER
PHASE
FREQUENCY
DETECTOR
DIVIDER
CONTROL LOGIC
CHARGE
PUMP
M
U
X
D
A
T
A
M
U
X
M
U
X
RE-TIMER
PHASE
DETECTOR
SD/HD
RCO_MUTE
RCO/DDO1
CLOCK BUFFER
LOS
M
U
X
DATA/CLOCK
Version ECR PCN Date Changes and/or Modifications
4 151358 – April 2009 Added 2.5k reel option to section 6.6
Ordering Information. Changed the
maximum input swing value from 800mV
to 1100mV in Table 2-2: AC Electrical
Characteristics.
3 150068 – June 2008 Removed references to GND_DRV in
Section 1.1 GS2975A Pin Assignment and
Table 1-1: Pin Descriptions.
2 147068 – August 2007 Typo: Functional Block Diagram on
page 2.
1 146316 −July 2007 Typo: Pin 64 in Table 1-1& TAC Figure 5-1
on page 22, Pins 38/40 & 44/46 in
Table 1-1.
0 143947 43428 February 2007 Converting to Data Sheet. Removed
‘Proprietary and Confidential’ footer.
Updated AC Electrical Characteristics
table. Added junction - board thermal
resistance parameter to 6.3 Packaging
Data. Added section 6.4 Marking
Diagram.
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
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Contents
Features.................................................................................................................................................................1
Applications.........................................................................................................................................................1
Description...........................................................................................................................................................1
Functional Block Diagram ..............................................................................................................................2
Revision History .................................................................................................................................................2
1. Pin Out...............................................................................................................................................................4
1.1 GS2975A Pin Assignment ..............................................................................................................4
1.2 GS2975A Pin Descriptions .............................................................................................................5
2. Electrical Characteristics ............................................................................................................................8
2.1 Absolute Maximum Ratings ..........................................................................................................8
2.2 DC Electrical Characteristics ........................................................................................................8
2.3 AC Electrical Characteristics ..................................................................................................... 10
3. Input/Output Circuits ............................................................................................................................... 13
4. Detailed Description.................................................................................................................................. 16
4.1 Slew Rate Phase Lock Loop (S-PLL) ......................................................................................... 16
4.2 VCO .................................................................................................................................................... 17
4.3 Charge Pump ................................................................................................................................... 17
4.4 Frequency Acquisition Loop — The Phase-Frequency Detector .................................. 18
4.5 Phase Acquisition Loop — The Phase Detector ................................................................... 18
4.6 4:1 Input Mux .................................................................................................................................. 19
4.7 Automatic and Manual Data Rate Selection ......................................................................... 19
4.8 Bypass Mode ................................................................................................................................... 20
4.9 DVB-ASI Operation ....................................................................................................................... 20
4.10 Lock and LOS ................................................................................................................................ 20
4.11 Output Drivers and Output Mute .......................................................................................... 21
5. Typical Application Circuit ..................................................................................................................... 22
6. Package & Ordering Information .......................................................................................................... 23
6.1 Package Dimensions ..................................................................................................................... 23
6.2 Recommended PCB Footprint ................................................................................................... 24
6.3 Packaging Data ............................................................................................................................... 25
6.4 Marking Diagram ........................................................................................................................... 25
6.5 Solder Reflow Profiles .................................................................................................................. 26
6.6 Ordering Information ................................................................................................................... 26
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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1. Pin Out
1.1 GS2975A Pin Assignment
Figure 1-1: 64-Pin QFN
DDI0
NC
64-pin QFN
(Top View)
1
DDI0_VTT
DDI0
GND
DDI1
DDI1_VTT
DDI1
GND
DDI2
DDI2_VTT
DDI2
GND
DDI3
DDI3_VTT
DDI3
GND
LF+
NC
NC
NC
NC
NC
XTAL-
XTAL+
XTAL_OUT-
XTAL_OUT+
GND
VEE_DDO
VCC_DDO
RSV
GND
VEE_RCO
VCC_RCO
RCO/DDO1
RSV
RCO/DDO1
KBB
DDI_SEL0
DDI_SEL1
BYPASS
AUTOBYPASS
VCC_VCO
VEE_VCO
LOCKED
SS0
SS1
SS2
LOS
VCC_DIG
VEE_DIG
GND
VCC_CP
VEE_CP
NC
DDO0
DDO0
16
17 32
33
48
4964
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18 19 20 21 23 24 25 2627 28 29 30 3122
34
35
36
37
38
39
40
41
42
43
44
45
46
47
5051525354555657585960
61
6263
LF-
Ground Pad
(bottom of package)
NC
AUTO/MAN
–
–
–
–
DDO_MUTE
SD/HD
GS2975A
RCO_MUTE
DATA/CLOCK
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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1.2 GS2975A Pin Descriptions
Table 1-1: Pin Descriptions
Pin Number Name Ty pe Description
1, 3 DDI0, DDI0 Input Serial digital differential input 0.
2 DDI0_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI0 and
DDI0.
4, 8, 12,16, 32,
43, 49
GND Passive Recommended connect to GND.
5, 7 DDI1,DDI1 Input Serial digital differential input 1.
6 DDI1_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI1 and
DDI1.
9, 11 DDI2, DDI2 Input Serial digital differential input 2.
10 DDI2_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI2 and
DDI2.
13, 15 DDI3, DDI3 Input Serial digital differential input 3.
14 DDI3_VTT Passive Center tap of two 50Ω on-chip termination resistors between DDI3 and
DDI3.
17, 18 DDI_SEL[1:0] Logic Input Serial digital input select.
19 BYPASS Logic Input Bypass the reclocker stage.
When BYPASS is HIGH, it overwrites the AUTOBYPASS setting.
20 AUTOBYPASS Logic Input Automatically bypasses the reclocker stage when the PLL is not locked
This pin is ignored when BYPASS is HIGH.
21 AUTO/MAN Logic Input Auto/Manual select.
When set HIGH, the standard is automatically detected from the input data
rate. When set LOW, the user must program the input standard using the
SS[2:0] pins.
22 VCC_VCO Power Most positive power supply connection for the internal VCO section.
Connect to 3.3V.
23 VEE_VCO Power Most negative power supply connection for the internal VCO section.
Connect to GND.
DDI_SEL1 DDI_SEL0 INPUT SELECTED
0 0 DDI0
0 1 DDI1
1 0 DDI2
1 1 DDI3
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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24, 25, 26 SS[0:2] Bi-directional When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to
which the PLL has locked.
When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to
a selected data rate
.
27 NCNo Connect Not connected internally.
28 LOCKED Output Lock Detect.
This pin is set HIGH by the device when the PLL is locked.
29 LOSOutput Loss of Signal.
Set HIGH when there are no transitions on the active DDI[3:0] input.
30 VCC_DIGPower Most positive power supply connection for the internal glue logic.
Connect to 3.3V.
31 VEE_DIGPower Most negative power supply connection for the internal glue logic.
Connect to GND.
33 SD/HD Output This signal will be set LOW by the device when the reclocker has locked to
2.97Gb/s (2.967Gb/s) or 1.485Gb/s (1.4835Gb/s), or when a non-SMPTE
standard is applied (i.e. the device is not locked).
It will be set HIGH when the reclocker has locked to 270Mbps.
34 KBB Analog Input Controls the loop bandwidth of the PLL.
35 RCO_MUTE Power Serial clock or secondary data output mute.
Assert LOW for reduced power consumption, see 2.2 DC Electrical
Characteristics.
When RCO_MUTE = LOW, the RCO/DDO1 output is powered down.
When RCO_MUTE = HIGH, the RCO/DDO1 output is active.
NOTE: This is not a logic input pin.
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Ty pe Description
SS2SS1SS0 DATA RATE
SELECTED/FORCED (Mb/s)
010 270
1 0 1 1483.5/1485
1 1 0 2967/2970
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
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36 DDO_MUTE Logic Input Mutes the DDO0 and/or RCO/DDO1 outputs.
37 DATA/CLOCKLogic Input Data/Clock select.
When set HIGH, the RCO/DDO1 pin will output a copy of the serial digital
output (DDO0).
When set LOW, the RCO/DDO1 pin will output a re-timed clock (RCO).
38, 40 RCO/DDO1,
RCO/DDO1
Output Serial clock or secondary data output.
When RCO_MUTE is connected to VCC, the serial digital differential clock or
secondary data output will be presented.
39, 45 RSV Reserved Do not connect.
41 VCC_RCO Power Most positive power supply connection for the RCO/DDO1 and RCO/DDO1
output driver.
Connect to 3.3V.
42 VEE_RCO Power Most negative power supply connection for the RCO/DDO1 and RCO/DDO1
output driver.
Connect to GND.
44, 46 DDO0, DDO0 Output Differential Serial Digital Outputs.
47 VCC_DDO Power Most positive power supply connection for the DDO0/DDO0 output driver.
Connect to 3.3V.
48 VEE_DDO Power Most negative power supply connection for the DDO0/DDO0 output driver.
Connect to GND.
50, 51 XTAL_OUT+,
XTAL_OUT-
Output Differential outputs of the reference oscillator used for monitoring or test
purposes.
52, 53 XTAL+, XTAL- Input Reference crystal input. Connect to the GO1535 as shown in the Typical
Application Circuit on page 22.
54 - 59 NCNo Connect Not connected internally.
60 VEE_CP Power Most negative power supply connection for the internal charge pump.
Connect to GND.
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Ty pe Description
DDO_MUTE RCO_MUTE DATA/CLOCKDDO0 RCO/DDO1
11 0DATACLOCK
1 1 1 DATA DATA
01 0MUTECLOCK
0 1 1 MUTE MUTE
10 XDATAPower down
00 XMUTEPower down
NOTE:
MUTE = Outputs latched at previous data bit.
Power down = Outputs pulled to Vcc through 50Ω resistor.
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
2.2 DC Electrical Characteristics
61 VCC_CP Power Most positive power supply connection for the internal charge pump.
Connect to 3.3V.
62, 63 LF+, LF- Passive Loop filter capacitor connection. Connect as shown in the Typical
Application Circuit on page 22.
64 NCNo Connect Not connected internally. Recommended connect to GND.
–Center Pad – Ground pad on bottom of package.
Solder to main ground plane following recommendations under
Recommended PCB Footprint on page 24
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Ty pe Description
Parameter Value
Supply Voltage Range -0.5V to +3.6 VDC
Input Voltage Range Vee - 0.5V to Vcc + 0.5V
Operating Temperature Range -20°C to 85°C
Storage Temperature Range -50°C < Ts < 125°C
Input ESD Voltage 4kV HBM, 100V MM
Solder Reflow Temperature 260°C
NOTE: Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions or at any other condition beyond those
indicated in the AC/DC Electrical Characteristic sections is not implied.
Table 2-1: DC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C
Parameter Symbol Conditions Min Typ Max Units
Supply Voltage VCC Operating Range 3.135 3.3 3.465 V
Supply Current ICC RCO/DD01 enabled – 142 170 mA
ICC RCO/DDO1 disabled – 123 152 mA
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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Power Consumption – RCO/DD01 enabled – 468 590 mW
–RCO/DD01 disabled – 404 528 mW
Logic Inputs
DDI_SEL[1:0], BYPASS, AUTOBYPASS,
AUTO/MAN, ASI/177, DDO_MUTE
VIH High 2.0 – – V
VIL Low – – 0.8 V
Logic Outputs
SD/HD, LOCKED, LOS
VOH IOH = -2mA 2.4 – – V
VOL IOL = 2mA – – 0.4 V
Bi-Directional Pins (Manual Mode)
SS[2:0], AUTO/MAN = 0
VIH High 2.0 – – V
VIL Low – – 0.8 V
Bi-Directional Pins (Auto Mode)
SS[2:0], AUTO/MAN = 1
VOH IOH = -2mA 2.4 – – V
VOL IOL = 2mA – – 0.4 V
XTAL_OUT+, XTAL_OUT- VOH High – VCC - 0.075 – V
VOL Low – VCC - 0.300 – V
RCO_MUTE – I = -1.5mA VCC - 0.165 VCC VCC + 0.165 V
Serial Input Voltage – Common Mode 1.65 +
(VSID/2)
–V
CC -
(VSID/2)
V
Serial Output Voltage
DDO0/DDO0,
RCO/DDO1 / RCO/DDO1
–Common Mode – VCC - (VOD/2) – V
Table 2-1: DC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C
Parameter Symbol Conditions Min Typ Max Units
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
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2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C
Parameter Symbol Conditions Min Ty p Max Units Notes
Serial Input Data Rate – – 270 – 2970 Mb/s –
Serial Input Jitter Tolerance – Worst case modulation
(e.g. square wave
modulation)
270, 1485, 2970 Mb/s
0.8 – – UI –
PLL Lock Time - Asynchronous tALOCK––1.510ms–
PLL Lock Time - Synchronous tSLOCKKBB = Float, CLF=47nF
SD/HD = 0
–0.5 4 μs–
KBB = Float, CLF=47nF
SD/HD = 1
–520μs–
Serial Output Rise/Fall Time
SDO0 and RCO/DDO1 (20% -
80%)
trSDO,trRCO50Ω load (on chip) – 110 – ps –
tfSDO,tfRCO50Ω load (on chip) – 110 – ps –
Serial Digital Input Signal Swing VSID Differential with internal
100Ω input termination
See Figure 2-1
100 – 1100 mVp-p –
Serial Digital Output Signal
Swing
DDO0 and RCO/DDO1
VOD 100Ω load differential
See Figure
300 450 600 mVp-p –
DDO0 to DDO1 skew DDskew – – 156 – ps 1
DDO0 to RCO skew DRskew 2970 Mb/s, 1485 Mb/s – 28 – ps 2
270 Mb/s – 37 – ps 2
Serial Output Jitter on DDO0
(RCO/DDO1 disabled)
tOJ 270 Mb/s – 0.02 0.07 UI 3
1485 Mb/s – 0.06 0.10 UI 4
2970 Mb/s – 0.10 0.15 UI 4
Serial Output Jitter on DDO0
and DDO1
(Both DDO0 and DDO1enabled)
tOJ 270 Mb/s – 0.02 0.07 UI 3
1485 Mb/s – 0.06 0.10 UI 4
2970 Mb/s – 0.11 0.16 UI 4
Additive Jitter tAJ Bypass mode, 2970 Mb/s
DDO0 enabled
–15 – ps –
Bypass mode, 2970 Mb/s
DDO0 and DDO1 enabled
–20 – ps –
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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Loop Bandwidth BWLOOP 2.97 Gb/s, KBB = VCC –1.75 – MHz –
2.97 Gb/s, KBB = FLOAT – 3.5 – MHz –
2.97 Gb/s, KBB = GND,
<0.1dB Peaking
–7.0 – MHz –
1.485 Gb/s, KBB = VCC –0.875 – MHz –
1.485 Gb/s, KBB = FLOAT – 1.75 – MHz –
1.485 Gb/s, KBB = GND,
<0.1dB Peaking
–3.5 – MHz –
270 Mb/s, KBB = VCC –0.16 – MHz –
270 Mb/s, KBB = FLOAT – 0.32 – MHz –
270 Mb/s, KBB = GND,
<0.1dB Peaking
–0.64 – MHz –
NOTES:
1. DDO0 to DDO1 skew alignment as defined here:
.
2. DDO0 to RCO skew alignment as defined here:
3. KBB = Float, PRN = 223-1, input jitter = 40psp-p.
4. KBB = Float, PRN = 223-1, input jitter = 20psp-p.
Table 2-2: AC Electrical Characteristics (Continued)
VCC = 3.3V ±5%, TA = 0°C to 70°C, unless otherwise shown. Typical values: VCC = 3.3V and TA =25°C
Parameter Symbol Conditions Min Ty p Max Units Notes
DDO0
DDO1
DD
SKEW
DDO0
RCO
DR SKEW
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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Figure 2-1: Serial Digital Input Signal Swing
Figure 2-2: Serial Digital Output Signal Swing
V
SID
V
SID
2
V
SID
2
V
SID
2
+
0
V
SID
2
_
V
SID
2
V
CC
_
V
SID
2
V
CC
_
V
CC
V
DD
Single-Ended Swing (DDIx)
Single-Ended Swing (DDIx)
Differential Swing (DDIx-DDIx)
V
OD
V
OD
2
V
OD
2
V
OD
2
+
0
V
OD
2
_
V
OD
2
V
CC
_
V
OD
2
V
CC
_
V
CC
V
DD
Single-Ended Swing (DDO0, DDO1, RCO)
Single-Ended Swing (DDO0,DDO1, RCO)
Differential Swing (DDO0-DDO0)
(DDO1-DDO1)
(RCO-RCO)
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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3. Input/Output Circuits
Figure 3-1: TTL Inputs
Figure 3-2: Loop Filter
Figure 3-3: Crystal Input
V
REF
LF+ LF-
5K
10p
250R 250R
5K
XTAL+
XTAL-
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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Figure 3-4: Crystal Output Buffer
Figure 3-5: Serial Data Outputs, Serial Clock Outputs
Figure 3-6: KBB
Figure 3-7: Indicator Outputs: SD/HD, LOCKED, LOS
1K
1K
XTAL OUT-
XTAL OUT+
50
DDO0 / RCO/DDO1 DDO0 / RCO/DDO1
50
KBB
V
TH2
V
TH1
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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Figure 3-8: Standard Select/Indication Bi-directional Pins
Figure 3-9: Serial Data Inputs
24k
SS[2:0]
AUTO/MAN
50
DDI[3:0]
DDI[3:0]
1k 1k
50
DDI_VTT
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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4. Detailed Description
The GS2975A is a Multi-Rate Serial Digital Reclocker designed to automatically recover
the embedded clock from a digital video signal and re-time the incoming video data.
The GS2975A will recover the embedded clock signal and re-time the data from a
SMPTE 424M, SMPTE 292M, or SMPTE 259M-C compliant digital video signal.
Using the functional block diagram (page 2) as a guide, Slew Rate Phase Lock Loop
(S-PLL) on page 16 to on page 21 describes each aspect of the GS2975A in detail.
4.1 Slew Rate Phase Lock Loop (S-PLL)
The term “slew” refers to the output phase of the PLL in response to a step change at the
input. Linear PLLs have an output phase response characterized by an exponential
response whereas an S-PLL’s output is a ramp response (see Figure 4-1). Because of this
non-linear response characteristic, traditional small signal analysis is not possible with
an S-PLL.
Figure 4-1: PLL Characteristics
0.2
0.1
0.0
INPUT
OUTPUT
SLEW PLL RESPONSE
PHASE (UI)
0.2
0.1
0.0
INPUT
OUTPUT
LINEAR (CONVENTIONAL) PLL RESPONSE
PHASE (UI)
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of an
S-PLL is independent of the transition density of the input data. Pseudo-random data has
a transition density of 0.5 verses a pathological signal which has a transition density of
0.05. The loop bandwidth of a linear PLL will change proportionally with this change in
transition density. With an S-PLL, the loop bandwidth is defined by the jitter at the data
input. This translates to infinite loop bandwidth with a zero jitter input signal. This
allows the loop to correct for small variations in the input jitter quickly, resulting in very
low output jitter. The loop bandwidth of the GS2975A’s PLL is defined at 0.2UI of input
jitter.
The PLL consists of two acquisition loops. First is the Frequency Acquisition (FA) loop.
This loop is active when the device is not locked and is used to achieve lock to the
supported data rates. Second is the phase acquisition (PA) loop. Once locked, the PA loop
tracks the incoming data and makes phased corrections to produce a re-clocked output.
4.2 VCO
The internal VCO of the GS2975A is an LC oscillator. It is trimmed at the time of
manufacture to capture all data rates over temperature and operation voltage ranges.
Integrated into the VCO is a series of programmable dividers used to achieve all serial
data rates, as well as additional dividers for the frequency acquisition loop.
4.3 Charge Pump
During frequency acquisition, the charge pump has two states, “pump-up” and
“pump-down,” which is produced by a leading or lagging phase difference between the
input and the VCO frequency.
During phase acquisition, there are two levels of “pump-up” and two levels of “pump
down” produced for leading and lagging phase difference between the input and VCO
frequency. This is to allow for greater precision of VCO control.
The charge pump produces these signals by holding the integrated frequency
information on the external loop-filter capacitor, CLF. The instantaneous frequency
information is the result of the current flowing through an internal resistor connected to
the loop-filter capacitor.
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
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4.4 Frequency Acquisition Loop — The Phase-Frequency Detector
An external crystal of 14.140MHz is used as a reference to keep the VCO centered at the
last known data rate. This allows the device to achieve a fast synchronous lock,
especially in cases where a known data rate is interrupted. The crystal reference is also
used to clock internal timers and counters. To keep the optimal performance of the
reclocker over all operating conditions, the crystal frequency must be 14.140MHz,
+/-50ppm. The GO1535 meets this specification and is available from Gennum.
The GO1535 requires an external resistor to be placed in series with the crystal. The
optimal value of this resistor can range from 100 to 150 ohms, and this value will depend
upon the design. For systems which expect to see a higher noise floor, the higher resistor
value is recommended. The higher resistor value will work to decrease the loop gain of
the oscillator, as well as attenuate noise.
The VCO is divided by a selected ratio which is dependant on the input data rate. The
resultant is then compared to the crystal frequency. If the divided VCO frequency and
the crystal frequency are within 1% of each other, the PLL is considered to be locked to
the input data rate.
4.5 Phase Acquisition Loop — The Phase Detector
The phase detector is a digital quadrature phase detector. It indicates whether the input
data is leading or lagging with respect to a clock that is in phase with the VCO (I-clk) and
a quadrature clock (Q-clk). When the phase acquisition loop (PA loop) is locked, the
input data transition is aligned to the falling edge of I-clk and the output data is re-timed
on the rising edge of I-clk. During high input jitter conditions (>0.25UI), Q-clk will
sample a different value than I-clk. In this condition, two extra phase correction signals
will be generated which instructs the charge pump to create larger frequency
corrections for the VCO.
Figure 4-2: Phase Detector Characteristics
When the PA loop is active, the crystal frequency and the incoming data rate are
compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the
system jumps to the FA loop.
i-PHASE ALIGNMENT
EDGE
DATA RE-TIMING
EDGE
q-PHASE ALIGNMENT
EDGE
0.25UI 0.8UI
I-clk
q-clk
INPUT DATA
WITH JITTER
RE-TIMED
OUTPUT DATA
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
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4.6 4:1 Input Mux
The 4:1 input mux allows the connection of four independent streams of video/data.
There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be
selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a given state
at DDI_SEL[1:0].
The DDI inputs are designed to be DC interfaced with the output of the GS2974 Cable
Equalizer. There are on-chip 50Ω termination resistors which come to a common point
at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of
the capacitor to ground. This terminates the transmission line at the inputs for optimum
performance.
If only one input pair is used, connect the unused positive inputs to +3.3V and leave the
unused negative inputs floating. This helps to eliminate crosstalk from potential noise
that would couple to the unused input pair.
4.7 Automatic and Manual Data Rate Selection
The GS2975A can be configured to manually lock to a specific data rate or automatically
search for and lock to the incoming data rate. The AUTO/MAN pin selects automatic
data rate detection mode (Auto mode) when HIGH and manual data rate selection mode
(Manual mode) when LOW.
In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern
indicates the data rate that the PLL is locked to (or previously locked to). The “search
algorithm” cycles through the data rates and starts over if that data rate is not found (see
Figure 4-3).
Figure 4-3: Data Rate Search Pattern
Table 4-1: Bit Pattern for Input Select
DDI_SEL[1:0] Selected Input
00 DDI0
01 DDI1
10 DDI2
11 DDI3
270Mb/s
2.970(2.697)Gb/s
1.485(1.4835)Gb/s
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
20 of 27
In Manual mode, the data rate can be programmed and the SS[2:0] pins become inputs.
In this mode, the search algorithm is disabled and the PLL will only lock to the data rate
selected.
Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in Manual
mode) or the data rate that the PLL has locked to (in Auto mode).
4.8 Bypass Mode
In Bypass mode, the GS2975A passes the data at the inputs directly to the outputs. There
are two pins that control the bypass function: BYPASS and AUTOBYPASS.
When BYPASS is set HIGH, the GS2975A will be in Bypass mode.
When AUTOBYPASS is set HIGH, the GS2975A will be configured to enter Bypass mode
only when the PLL has not locked to a data rate. When BYPASS is set HIGH,
AUTOBYPASS will be ignored.
When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW, the serial
digital output DDO0/DDO0 or DDO1/DDO1 will produce invalid data.
4.9 DVB-ASI Operation
The GS2975A will also re-clock DVB-ASI at 270 Mb/s. In auto mode, the device will
automatically lock to the incoming 270Mb/s signal. In manual mode, the SS[2:0] pins
must be set to 010 (270 Mb/s) to ensure proper operation.
4.10 Lock and LOS
The LOCKED signal is an active high output which indicates when the PLL is locked.
The internal lock logic of the GS2975A includes a system which monitors the Frequency
Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic
lock.
The LOS (Loss of Signal) output is an active HIGH output which indicates the absence of
data transitions at the DDIx input. In order for this output to be asserted, transitions must
not be present for a period of tLA = 5 - 10μs. After this output has been asserted, LOS will
de-assert within tLD = 0 - 5μs after the appearance of a transition at the DDIx input.
Table 4-2: Data Rate Indication/Selection Bit Pattern
SS[2:0] Data Rate (Mb/s)
010 270
101 1485 (1483.5)
110 2970 (2967)
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
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Figure 4-4: LOS signal timing
NOTE: LOS is sensitive to transitions appearing at the input, and does not distinguish
between transitions caused by input data, and transitions due to noise.
4.11 Output Drivers and Output Mute
The GS2975A offers a choice of dual reclocked data outputs or one data output and one
recovered clock output. Table 4-3 shows the correlation of the output pins to the
corresponding input select pins.
DATA
LOS
t
LA
t
LD
Table 4-3: Configuration of Output Drivers and Output Mute Pins
DDO_MUTE RCO_MUTE DATA/CLOCK DDO0 RCO/DDO1
11 0DATACLOCK
1 1 1 DATA DATA
01 0MUTECLOCK
0 1 1 MUTE MUTE
10 XDATAPower Down
0 0 X MUTE Power Down
NOTE:
MUTE = Outputs latched at previous data bit.
Power down = Outputs pulled to Vcc through 50Ω resistor.
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
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5. Typical Application Circuit
Figure 5-1: GS2975A Typical Application Circuit
NOTE: The GS2975A is drop-in compatible with the GS2975 application circuit. In the
GS2975 application circuit pin 37 is connected to ground. If the GS2975A is dropped into
the GS2975 application circuit, the RCO/DDO1 and RCO/DDO1 pins will output the
recovered clock.
DDI_SEL1
DDO_MUTE
DDI_SEL0
LOCKED
SD/HD
3.3V
3.3V
3.3V
3.3V
10n
10n
10n
10n
47n
GS2975A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DDI0
DDI0_VT
DDI0
GND
DDI1
DDI1_VT
DDI1
GND
DDI2
DDI2_VT
DDI2
GND
DDI3
DDI3_VT
DDI3
GND
DDI_SEL0
DDI_SEL1
BYPASS
AUTOBYPASS
AUTO/MAN
VCC_VCO
VEE_VC0
SS0
SS1
SS2
NC
LOCKED
LOS
VCC_DIG
VEE_DIG
GND
SD/HD
KBB
DDO_MUTE
RCO_MUTE
RSV
RCO/DDO1
VCC_RCO
VEE_RCO
GND
DDO0
RSV
DDO0
VCC_DDO
VEE_DDO
GND
XTAL_OUT+
XTAL_OUT-
XTAL+
XTAL-
NC
VEE_CP
VCC_CP
LF-
LF+
NC
10n
(14.140MHz)
10n
10n
10n
DATA INPUT 1
DATA INPUT 0
DATA INPUT 3
DATA INPUT 2
DATA OUTPUT
Zo = 50
Zo = 50
Zo = 50
Zo = 50
Zo = 50
3.3V
10n
100
GO1535
Note: All resistors in ohms and all capacitors in Farads.
NC
NC
NC
NC
NC
RCO/DDO1
CLOCK OUTPUT
Zo = 50
LOS
RCO_MUTE
DATA/CLOCK DATA/CLOCK
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
23 of 27
6. Package & Ordering Information
6.1 Package Dimensions
A
B
9.00
4.50
4.50
9.00
2X
2X
0.15
C
0.15
C
0.10
C
0.08
C
64X
SEATING PLANE
0.90 +/- 0.10
+0.03
0.02-0.02
0.20 REF
C
7.10+/-0.15
3.55
0.40+/-0.05
7.10+/-0.15
3.55
0.25+/-0.05
64X 0.10
C
AB
C
0.05
0.50
ALL DIMENSIONS IN MM
PIN 1 AREA CENTRE TAB
45°
45°
0.3+/-0.05
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
24 of 27
6.2 Recommended PCB Footprint
The center pad of the PCB footprint should be connected to the ground plane by a
minimum of 36 vias.
NOTE: Suggested dimensions only. Final dimensions should conform to customer
design rules and process optimization.
NOTE: All dimensions
are in millimeters.
7.10
7.10
8.70
8.70
0.50 0.25
0.55
CENTER PAD
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
25 of 27
6.3 Packaging Data
6.4 Marking Diagram
Parameter Value
Package Type 9mm x 9mm 64-pin QFN
Moisture Sensitivity Level (per JEDEC J-STD-020C)3
Junction to Case Thermal Resistance,
θ
j-c 9.1°C/W
Junction to Air Thermal Resistance,
θ
j-a (at zero
airflow)
21.5°C/W
Junction to Board Thermal Resistance, θj-b 5.6°C/W
Psi,
Ψ
0.2°C/W
Pb-free and RoHS Compliant Yes
GS2975A
XXXXE3
YYWW
Pin 1 ID
XXXXE3
YYWW
YYWW - Date Code
YY - 2-digit year
WW - 2-digit week number
XXXX - Lot/Work Order ID
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
26 of 27
6.5 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both
standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed
using the maximum Pb-free reflow profile shown in Figure 6-1. The recommended
standard Pb reflow profile is shown in Figure 6-2.
Figure 6-1: Maximum Pb-free Solder Reflow Profile (Preferred)
Figure 6-2: Standard Pb Solder Reflow Profile
6.6 Ordering Information
25°C
150°C
200°C
217°C
260°C
250°C
Time
Temperature
8 min. max
60-180 sec. max
60-150 sec.
20-40 sec.
3°C/sec max
6°C/sec max
25°C
100°C
150°C
183°C
230°C
220°C
Time
Temperature
6 min. max
120 sec. max
60-150 sec.
10-20 sec.
3°C/sec max
6°C/sec max
Part Number Package Temperature Range
GS2975A GS2975ACNE3 Pb-free 64-pin QFN 0°C to 70°C
GS2975A GS2975ACNTE3Z Pb-free 64-pin QFN
2,500pc Reel
0°C to 70°C
OTTAWA
232 Herzberg Road, Suite 101
Kanata, Ontario K2K 2A1
Canada
Phone: +1 (613) 270-0458
Fax: +1 (613) 270-0429
CALGARY
3553 - 31st St. N.W., Suite 210
Calgary, Alberta T2L 2K7
Canada
Phone: +1 (403) 284-2672
UNITED KINGDOM
North Building, Walden Court
Parsonage Lane,
Bishop’s Stortford Hertfordshire, CM23 5DB
United Kingdom
Phone: +44 1279 714170
Fax: +44 1279 714171
INDIA
#208(A), Nirmala Plaza,
Airport Road, Forest Park Square
Bhubaneswar 751009
India
Phone: +91 (674) 653-4815
Fax: +91 (674) 259-5733
SNOWBUSH IP - A DIVISION OF GENNUM
439 University Ave. Suite 1700
Toronto, Ontario M5G 1Y8
Canada
Phone: +1 (416) 925-5643
Fax: +1 (416) 925-0581
E-mail: sales@snowbush.com
Web Site: http://www.snowbush.com
MEXICO
288-A Paseo de Maravillas
Jesus Ma., Aguascalientes
Mexico 20900
Phone: +1 (416) 848-0328
JAPAN KK
Shinjuku Green Tower Building 27F
6-14-1, Nishi Shinjuku
Shinjuku-ku, Tokyo, 160-0023
Japan
Phone: +81 (03) 3349-5501
Fax: +81 (03) 3349-5505
E-mail: gennum-japan@gennum.com
Web Site: http://www.gennum.co.jp
TAI W AN
6F-4, No.51, Sec.2, Keelung Rd.
Sinyi District, Taipei City 11502
Taiwan R.O.C.
Phone: (886) 2-8732-8879
Fax: (886) 2-8732-8870
E-mail: gennum-taiwan@gennum.com
GERMANY
Hainbuchenstraße 2
80935 Muenchen (Munich), Germany
Phone: +49-89-35831696
Fax: +49-89-35804653
E-mail: gennum-germany@gennum.com
NORTH AMERICA WESTERN REGION
Bayshore Plaza
2107 N 1st Street, Suite #300
San Jose, CA 95131
United States
Phone: +1 (408) 392-9454
Fax: +1 (408) 392-9427
E-mail: naw_sales@gennum.com
NORTH AMERICA EASTERN REGION
4281 Harvester Road
Burlington, Ontario L7L 5M4
Canada
Phone: +1 (905) 632-2996
Fax: +1 (905) 632-2055
E-mail: nae_sales@gennum.com
KOREA
8F Jinnex Lakeview Bldg.
65-2, Bangidong, Songpagu
Seoul, Korea 138-828
Phone: +82-2-414-2991
Fax: +82-2-414-2998
E-mail: gennum-korea@gennum.com
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make changes to
the product at any time without notice to improve reliability, function or
design, in order to provide the best product possible.
GS2975A HD-LINX® III Multi-Rate SDI Automatic
Reclocker with Dual Differential Outputs
Data Sheet
41487 - 4 April 2009
27 of 27
27
Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of
the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent
infringement.
All other trademarks mentioned are the properties of their respective owners.
GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.
© Copyright 2006 Gennum Corporation. All rights reserved.
www.gennum.com
GENNUM CORPORATE HEADQUARTERS
4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada
Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055
E-mail: corporate@gennum.com www.gennum.com
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION
