16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C SST34HF162C16Mb Dual-Bank Flash + 2/4 Mb SRAM MCP ComboMemory EOL Data Sheet FEATURES: * Flash Organization: 1M x16 - 16 Mbit: 12 Mbit + 4 Mbit * Concurrent Operation - Read from or Write to SRAM while Erase/Program Flash * SRAM Organization: - 2 Mbit:128K x16 - 4 Mbit: 256K x16 * Single 2.7-3.3V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: (typical values @ 5 MHz) - Active Current: Flash 10 mA (typical) SRAM 6 mA (typical) - Standby Current: 10 A (typical) * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Read Access Time - Flash: 70 ns - SRAM: 70 ns * Erase-Suspend / Erase-Resume Capabilities * Latched Address and Data * Fast Erase and Word-Program (typical): - Sector-Erase Time: 18 ms - Block-Erase Time: 18 ms - Chip-Erase Time: 35 ms - Program Time: 7 s * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard Command Set * Packages Available - 48-ball LBGA (10mm x 12mm) * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST34HF162C/164C ComboMemory devices integrate a 1M x16 CMOS flash memory bank with either 128K x16 or 256K x16 CMOS SRAM memory bank in a multichip package (MCP). These devices are fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF162C/164C devices are ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF162C/164C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Program time of 7 sec. The entire flash memory bank can be erased and programmed word-by-word in 4 seconds (typically) for the SST34HF162C/164C, when using interface features such as Toggle Bit or Data# Polling (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 5/07 1 to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF162C/164C devices contain on-chip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signal, BES#, selects the SRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. See Figure 1 for memory organization. Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF162C/ 164C are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. See Figure 2 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. http://store.iiic.cc/ 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Device Operation Flash Program Operation The SST34HF162C/164C use BES# and BEF# to control operation of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES# is low the SRAM is activated for Read and Write operation. BEF# and BES# cannot be at low level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES# bank enables are raised to VIHC (Logic High) or when BEF# is high. These devices are programmed on a word-by-word basis. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. Concurrent Read/Write Operation 3. The internal Program operation is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed typically within 7 s. The SST34HF162C/164C provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. See Figures 7 and 8 for WE# and BEF# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during an internal Program operation are ignored. CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Flash Sector- /Block-Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with a Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Block- or SectorErase operation are ignored except Erase-Suspend and Erase-Resume. See Figures 12 and 13 for timing waveforms. Flash Read Operation The Read operation of the SST34HF162C/164C is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6). (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 2 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Flash Chip-Erase Operation vent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. The SST34HF162C/164C provide a Chip-Erase operation, which allows the user to erase all sectors/blocks to the "1" state. This is useful when the device must be quickly erased. Flash Data# Polling (DQ7) The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 5 for the command sequence, Figure 11 for timing diagram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When the device is in an internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or BEF#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or BEF#) pulse. See Figure 9 for Data# Polling (DQ7) timing diagram and Figure 19 for a flowchart. Flash Erase-Suspend/-Resume Operations The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing a one-byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode within 20 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at "1". While in Erase-Suspend mode, a Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended, the system must issue an Erase-Resume command. The operation is executed by issuing a one-byte command sequence with Erase Resume command (30H) at any address in the one-byte sequence. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The toggle bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to "1" if a Read operation is attempted on an Erase-suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of a Write operation. See Figure 10 for Toggle Bit timing diagram and Figure 19 for a flowchart. Flash Write Operation Status Detection The SST34HF162C/164C provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. TABLE 1: WRITE OPERATION STATUS Status Normal Operation The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to pre(c)2007 Silicon Storage Technology, Inc. DQ7 DQ6 DQ2 Standard Program DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle S71269-02-EOL 3 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Product Identification TABLE 1: WRITE OPERATION STATUS DQ7 DQ6 DQ2 Read From Erase Suspended Sector/ Block 1 1 Toggle Read From Non-Erase Suspended Sector/ Block Data Data Data Program DQ7# Toggle No Toggle Status EraseSuspend Mode The Product Identification mode identifies the device as SST34HF162C or SST34HF164C and the manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Tables 4 and 5 for software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 20 for the ID Entry command sequence flowchart. T1.0 1269 Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. Data Protection TABLE 2: PRODUCT IDENTIFICATION The SST34HF162C/164C provide both hardware and software features to protect nonvolatile data from inadvertent writes. ADDRESS DATA BK0000H 00BFH BK0001H 734BH Manufacturer's ID Device ID Hardware Data Protection SST34HF162C/164C Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. T2.1 1269 Note: BK = Bank Address (A19-A18) VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Product Identification Mode Exit Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 5 for software command codes, Figure 15 for timing waveform and Figure 20 for a flowchart. Software Data Protection (SDP) The SST34HF162C/164C provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF162C/164C are shipped with the Software Data Protection permanently enabled. See Table 5 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15DQ8 are "Don't Care" during any SDP command sequence. (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 4 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet SRAM Operation BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 3, for further details. With BES# low and BEF# high, the SST34HF162C/164C operate as either 128K x16 or 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The SST34HF162C/164C SRAM is mapped into the first 128 KWord address space. When BES# and BEF# are high, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 4 for SRAM Read and Write data byte control modes of operation. SRAM Write The SRAM Write operation of the SST34HF162C/164C is controlled by WE# and BES#, both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE# whichever occurs first. The write time is measured from the last falling edge of BES# or WE# to the first rising edge of BES# or WE#. Refer to the Write cycle timing diagrams, Figures 4 and 5, for further details. SRAM Read The SRAM Read operation of the SST34HF162C/164C is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. FUNCTIONAL BLOCK DIAGRAM Address Buffers AMSF1- A0 AMSS2- A0 SuperFlash Memory (Bank 1) BEF# LBS# UBS# WE# OE# BES# SuperFlash Memory (Bank 2) Control Logic I/O Buffers Address Buffers DQ15 - DQ0 2/4 Mbit SRAM 1269 B1.1 Notes: 1. AMSF = Most significant flash address AMSF = A19 for SST34HF162C/164C 2. AMSS = Most significant SRAM address AMSS = A16 for SST34HF162C and A17 for SST34HF164C (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 5 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet 32 KWord Blocks; 2 KWord Sectors Block 31 Block 30 Block 29 Block 28 Block 27 Bank 2 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Bank 1 FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 02000H 01FFFH 00000H Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 1269 F01.0 FIGURE 1: DUAL-BANK MEMORY ORGANIZATION (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 6 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TOP VIEW (balls facing down) SST34HF162C/164C 6 5 4 BES# VSS DQ1 A1 A2 A4 A19 A9 A10 DQ5 DQ2 A0 A3 A7 NC A14 OE# DQ7 DQ4 DQ0 A6 A18 NC A15 3 A5 A11 A8 DQ3 DQ12 A12 LBS# A13 A17 UBS# BEF# DQ10 VDDF DQ6 DQ15 DQ8 1 WE# VDDS A16 VSS DQ9 DQ11 DQ13 DQ14 A B C D E F G H 1269 48-lbga P1.1 2 FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM) TABLE 3: PIN DESCRIPTION Symbol Pin Name Functions AMSS1 to A0 Address Inputs To provide flash address, A19-A0. To provide SRAM address, AMSS-A0 DQ15-DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE#, BES#, and BEF# are high. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8 LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0 VSS Ground VDDF VDDS Power Supply (Flash) 2.7-3.3V Power Supply to Flash only Power Supply (SRAM) 2.7-3.3V Power Supply to SRAM only NC No Connection Unconnected pins T3.1 1269 1. AMS = Most Significant Address AMS = A16 for SST34HF162C and A17 for SST34HF164C (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 7 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TABLE 4: OPERATIONAL MODES SELECTION FOR SRAM BEF#1 BES#1,2 OE#2 WE#2 LBS#2 UBS#2 DQ15-0 Full Standby VIH VIH X X X X HIGH-Z HIGH-Z HIGH-Z X X X X X Output Disable VIH VIL VIH VIH X X HIGH-Z HIGH-Z HIGH-Z VIL X X VIH VIH VIL VIH VIH VIH X X HIGH-Z HIGH-Z HIGH-Z Flash Read VIL VIH VIL VIH X X DOUT DOUT DQ15-8=HIGH-Z Flash Write VIL VIH VIH VIL X X DIN DIN DQ15-8=HIGH-Z Flash Erase VIL VIH VIH VIL X X X X X SRAM Read VIH VIL VIL VIH VIL VIL DOUT DOUT DOUT VIH VIL HIGH-Z DOUT DOUT VIL VIH DOUT HIGH-Z HIGH-Z Mode DQ15-8 X X X X SRAM Write Product Identification3 VIH VIL VIL VIH X VIL VIL VIH VIL VIL DIN DIN DIN VIH VIL HIGH-Z DIN DIN VIL VIH DIN HIGH-Z HIGH-Z X X Manufacturer's ID4 Device ID4 T4.1 1269 1. 2. 3. 4. Do not apply BEF# = VIL and BES# = VIL at the same time X can be VIL or VIH, but no other value. Software mode only With A19-A18 = VIL; SST Manufacturer's ID = BFH, is read with A0=0, SST34HF162C/164C Device ID = 734BH, is read with A0=1 (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 8 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TABLE 5: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 Data AAH Program 555H AAH 2AAH 55H 555H A0H WA3 Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAH 55H SAX4 30H 4 50H 10H Block-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H BAX Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H 555H AAH 2AAH 55H BKX6 555H 90H Software ID Exit 555H AAH 2AAH 55H 555H F0H Software ID Exit XXH F0H Software ID Entry5 T5.0 1269 1. 2. 3. 4. Address format A11-A0 (Hex), Addresses A19-A12 can be VIL or VIH, but no other value, for the command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence WA = Program word address SAX for Sector-Erase; uses A19-A10 address lines BAX for Block-Erase; uses A19-A15 address lines 5. The device does not remain in Software Product Identification mode if powered down. 6. A19 and A18 = VIL (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 9 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. VDD = VDDF and VDDS 2. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 3. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Extended Ambient Temp VDD 0C to +70C 2.7-3.3V -20C to +85C 2.7-3.3V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 16 and 17 (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 10 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TABLE 6: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V) Limits Symbol Parameter IDD1 Active VDD Current Min Max Units Address input = VILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open Test Conditions Read OE#=VIL, WE#=VIH Flash 15 mA BEF#=VIL, BES#=VIH SRAM 10 mA BEF#=VIH, BES#=VIL 45 mA Concurrent Operation Write2 BEF#=VIH, BES#=VIL WE#=VIL Flash 40 mA BEF#=VIL, BES#=VIH, OE#=VIH SRAM 30 mA BEF#=VIH, BES#=VIL ISB Standby VDD Current 30 A VDD = VDD Max, BEF#=BES#=VIHC ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 A VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7 VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOLF Flash Output Low Voltage VOHF Flash Output High Voltage VOLS SRAM Output Low Voltage VOHS SRAM Output High Voltage 0.2 VDD-0.2 0.4 2.2 V VDD=VDD Max V IOL=100 A, VDD=VDD Min V IOH=-100 A, VDD=VDD Min V IOL =1 mA, VDD=VDD Min V IOH =-500 A, VDD=VDD Min T6.1 1269 1. See Figure 16 2. IDD active while Erase or Program is in progress. TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ Parameter 1 TPU-WRITE1 Minimum Units Power-up to Read Operation 100 s Power-up to Write Operation 100 s T7.0 1269 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (Ta = 25C, f=1 Mhz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 20 pF Input Capacitance VIN = 0V 16 pF T8.0 1269 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: FLASH RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1 Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR 1 ILTH1 Data Retention Latch Up JEDEC Standard 78 T9.0 1269 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 11 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet AC CHARACTERISTICS TABLE 10: SRAM READ CYCLE TIMING PARAMETERS Symbol Parameter Min 70 Max Units TRCS Read Cycle Time TAAS Address Access Time 70 ns TBES Bank Enable Access Time 70 ns TOES Output Enable Access Time 35 ns TBYES UBS#, LBS# Access Time 70 ns TBLZS1 BES# to Active Output 0 ns TOLZS1 Output Enable to Active Output 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 ns TBHZS 1 TOHZS1 TBYHZS 1 TOHS ns BES# to High-Z Output 25 ns Output Disable to High-Z Output 25 ns 35 ns UBS#, LBS# to High-Z Output Output Hold from Address Change 10 ns T10.0 1269 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: SRAM WRITE CYCLE TIMING PARAMETERS Symbol Parameter Min TWCS Write Cycle Time 70 Max Units TBWS Bank Enable to End-of-Write 60 ns TAWS Address Valid to End-of-Write 60 ns TASTS Address Set-up Time 0 ns TWPS Write Pulse Width 60 ns TWRS Write Recovery Time 0 ns TBYWS UBS#, LBS# to End-of-Write 60 ns TODWS Output Disable from WE# Low TOEWS Output Enable from WE# High 0 ns TDSS Data Set-up Time 30 ns TDHS Data Hold from Write Time 0 ns 30 ns ns T11.0 1269 (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 12 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TABLE 12: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V Symbol Parameter Min TRC Read Cycle Time 70 Max Units TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time TCLZ1 BEF# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 BEF# High to High-Z Output TOHZ1 OE# High to High-Z Output TOH1 Output Hold from Address Change ns 35 ns ns ns 20 ns 20 ns 0 ns T12.0 1269 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units TBP Program Time TAS Address Setup Time 0 TAH Address Hold Time 40 ns TCS WE# and BEF# Setup Time 0 ns TCH WE# and BEF# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP BEF# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 BEF# Pulse Width High 30 ns TDS Data Setup Time 30 ns Data Hold Time 0 TDH 1 12 s ns ns TIDA1 Software ID Access and Exit Time 150 ns TES Erase-Suspend Latency 20 s TBR1 Bus# Recovery Time 1 s TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms T13.1 1269 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 13 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TRCS ADDRESSES AMSS-0 TOHS TAAS TBES BES# TBLZS TBHZS TOES OE# TOLZS TOHZS TBYES UBS#, LBS# TBYLZS TBYHZS DQ15-0 DATA VALID 1269 F03.1 Note: AMSS = Most Significant Address AMSS = A16 for SST34HF162C and A17 SST34HF164C FIGURE 3: SRAM READ CYCLE TIMING DIAGRAM TWCS ADDRESSES AMSS3-0 TASTS TWPS TWRS WE# TAWS TBWS BES# TBYWS UBS#, LBS# TODWS DQ15-8, DQ7-0 TDSS NOTE 2 TOEWS TDHS VALID DATA IN NOTE 2 1269 F04.1 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES# goes low coincident with or after WE# goes low, the output will remain at high impedance. If BES# goes high coincident with or before WE# goes high, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A16 for SST34HF162C and A17 for SST34HF164C FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1 (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 14 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TWCS ADDRESSES AMSS3-0 TWPS TWRS WE# TBWS BES# TAWS TASTS TBYWS UBS#, LBS# TDSS VALID DATA IN NOTE 2 DQ15-8, DQ7-0 TDHS NOTE 2 1269 F05.1 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A16 for SST34HF162C and A17 for SST34HF164C FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 TRC TAA ADDRESS A19-0 TCE BEF# TOE OE# VIH TOHZ TOLZ WE# DQ15-0 HIGH-Z TOH TCLZ DATA VALID TCHZ HIGH-Z DATA VALID 1269 F06.0 FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 15 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TBP 555 TAH ADDRESS A19-0 2AA 555 ADDR TWP WE# TWPH TAS OE# TCH BEF# TCS TDS TDH DQ15-0 XXAA XX55 XXA0 VALID DATA WORD (ADDR/DATA) 1269 F07.0 Note: X can be VIL or VIH, but no other value. FIGURE 7: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM TBP 555 TAH ADDRESS A19-0 2AA 555 ADDR TCP BEF# TAS TCPH OE# TCH WE# TDS TCS TDH DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) VALID 1269 F08.0 Note: X can be VIL or VIH, but no other value. FIGURE 8: FLASH BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 16 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet ADDRESS A19-0 TCE BEF# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1269 F09.0 FIGURE 9: FLASH DATA# POLLING TIMING DIAGRAM ADDRESS A19-0 TCE BEF# TOEH TOE OE# WE# TBR DQ6 VALID DATA TWO READ CYCLES WITH SAME OUTPUTS 1269 F10.0 FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 17 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TSCE SIX-BYTE CODE FOR CHIP-ERASE 555 ADDRESS A19-0 2AA 555 555 2AA 555 BEF# OE# TWP WE# XXAA DQ15-0 XX55 XX80 XXAA XX55 XX10 VALID 1269 F11.0 Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.) X can be VIL or VIH, but no other value. FIGURE 11: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A19-0 555 2AA 555 555 2AA BAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 1269 F12.0 Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 12: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 18 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A19-0 555 2AA 555 555 2AA TSE SAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 VALID 1269 F13.0 Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 13: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM Three-Byte Sequence For Software ID Entry ADDRESS A14-0 555 2AA 555 0000 0001 BEF# OE# TIDA TWP WE# TWPH DQ15-0 XXAA XX55 TAA XX90 00BF Device ID 1269 F14.0 Note: X can be VIL or VIH, but no other value. Device ID - 734BH for SST34HF162C/164C FIGURE 14: FLASH SOFTWARE ID ENTRY AND READ (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 19 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Three-Byte Sequence for Software ID Exit and Reset 555 ADDRESS A14-0 DQ15-0 2AA XXAA 555 XX55 XXF0 TIDA BEF# OE# TWP WE# TWHP 1269 F15.0 Note: X can be VIL or VIH, but no other value FIGURE 15: FLASH SOFTWARE ID EXIT (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 20 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1269 F16.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 16: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1269 F17.0 FIGURE 17: A TEST LOAD EXAMPLE (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 21 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Address/Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1269 F18.0 Note: X can be VIL or VIH, but no other value. FIGURE 18: PROGRAM ALGORITHM (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 22 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Read byte/word Read DQ7 Wait TBP, TSCE, TSE or TBE Read same byte/word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1269 F19.0 FIGURE 19: WAIT OPTIONS (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 23 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Software Product ID Entry Command Sequence Software ID Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX90H Address: 555 Load data: XXF0H Address: 555H Wait TIDA Wait TIDA Read Software ID Return to normal operation 1269 F20.0 Note: X can be VIL or VIH, but no other value. FIGURE 20: SOFTWARE PRODUCT ID COMMAND FLOWCHARTS (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 24 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1269 F21.0 Note: X can be VIL or VIH, but no other value. FIGURE 21: ERASE COMMAND SEQUENCE (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 25 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet PRODUCT ORDERING INFORMATION Device Speed SST34HF162C - XXX Suffix1 - XX Suffix2 - XXXX Package Attribute E1 = non-Pb Package Modifier K = 48 balls Package Type LB = LBGA (10mm x 12mm x 1.4mm, 0.50mm ball size) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Minimum Endurance 4 =10,000 cycles Read Access Speed 70 = 70 ns Version C = SRAM SRAM Density 2 = 2 Mbit 4 = 4 Mbit Flash Density 16 = 16 Mbit Voltage H = 2.7-3.3V Product Series 34 = Dual-Bank Flash + SRAM ComboMemory 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST34HF162C SST34HF162C-70-4C-LBK SST34HF162C-70-4C-LBKE SST34HF162C-70-4E-LBK SST34HF162C-70-4E-LBKE Valid combinations for SST34HF164C SST34HF164C-70-4C-LBK SST34HF164C-70-4C-LBKE SST34HF164C-70-4E-LBK SST34HF164C-70-4E-LBKE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 26 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet PACKAGING DIAGRAMS TOP VIEW BOTTOM VIEW 12.00 0.20 7.0 1.0 6 6 5 5 5.0 4 4 10.00 0.20 3 3 2 2 1 1 1.0 0.50 0.05 (48X) A B C D E F G H H G F E D C B A A1 CORNER A1 CORNER SIDE VIEW 1.4 Max 0.12 SEATING PLANE 1mm 0.40 0.05 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.4 mm ( 0.05 mm) 48-lbga-LBK-10x12-500mic-2 48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM SST PACKAGE CODE: LBK (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 27 http://store.iiic.cc/ 5/07 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C EOL Data Sheet TABLE 14: REVISION HISTORY Number Description Date 00 * Initial Release Aug 2004 01 * * * * * Adding 4 Mbit SRAM parts and associated MPNs Removed Pb-free MPNs for SST34HF162C devices Clarifed values for Low Power Consumption on page 1 Added 5 MHz specifications for Active VDD Current (IDD) to Table 6 on page 11 Data sheet status changed to "Preliminary Specifications" Sep 2004 02 * * Changed document status from "Preliminary Specification" to "Data Sheet" Added RoHS compliance information on page 1 and in the "Product Ordering Information" on page 26 Added the solder reflow temperature to the "Absolute Maximum Stress Ratings" on page 10. Added Pb-free MPNs for all devices End-of-Life data sheet for all valid combination in S71269 Recommended replacement devices are SST34HF1641J found in S71336 May 2007 * * * * Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2007 Silicon Storage Technology, Inc. S71269-02-EOL 28 http://store.iiic.cc/ 5/07