STW4810CRAE/LF - STMicroelectronics

34.807IRELESS

IMPORTANT NOTICE

Dear customer,

As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a

new company, ST-NXP Wireless.

As a result, the following changes are applicable to the attached document.

●Company name - STMicroelectronics NV is replaced with ST-NXP Wireless.

●Copyright - the copyright notice at the bottom of the last page “© STMicroelectronics

reserved”.

●Web site - http://www.st.com is replaced with http://www.stnwireless.com

●Contact information - the list of sales offices is found at http://www.stnwireless.com

under Contacts.

If you have any questions related to the document, please contact our nearest sales office.

Thank you for your cooperation and understanding.

ST-NXP Wireless

34.807IRELESS

www.stnwireless.com

September 2007 Rev 9 1/78

STw4810

Power management for multimedia processors

Features

■2 Step-down converters

– 1 to 1.5V with 15 steps at 600mA

– 1.8V at 600mA for general purpose usage

■3 Low-drop output regulators for different uses

– PLL analog supplies:

1.05V, 1.2V, 1.3V 1.8V - 10mA

– Processor analogue functions:

2.5V - 10mA

– Auxiliary device:

1.5V, 1.8V, 2.5V, 2.8V - 150 mA

■USB OTG module

– Full and low speed USB OTG transceiver

– Charge-pump (5V, 100mA) for USB cable

■Mass memory cards (SD/MMC/SDIO)

– 1 linear regulator: 1.8V, 2.85V, 3V - 150mA

– Level shifter

■Miscellaneous

– 32 kHz control for multimedia processor

– Processor supply monitoring

– Processor reset control

– 2 Serial I2C interfaces

Application

■ST NOMADIKTM STn88x x

■Multimedia processor

■Mobile phones, PDA, videophone

Description

STw4810 is a power management companion

chip for multimedia processors used in portable

applications. It supplies the multimedia processor

including its memories and peripherals. STw4810

supports the main mass memory standard cards.

SDIOTM is also supported and allows to connect

multimedia peripherals like cameras.

6x6x1.2mm

0.5m m pit ch

TFBGA 84

4.6x4.6x1.0mm

0.4m m pit ch

VFBGA 84

STw4810CHD

STw4810CRA

www.st.com

Contents STw4810

2/78

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 Ball c onnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2 Digi tal control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2.1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.2.2 POWER OFF / VDDOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.5 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.2.6 IT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2.7 Clock switching and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3 Power management modu le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.1 Bandgap, biasing and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.2 VCORE regulator: DC/DC step-down regulator . . . . . . . . . . . . . . . . . . . 35

4.3.3 VIO_VMEM regulator: DC/DC step- down regulator . . . . . . . . . . . . . . . 35

4.3.4 VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3.5 VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3.6 VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.7 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.8 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3.9 Thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.4 USB OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.4.2 Modes and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.4.3 USB enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.5 SD/MMC/SDIO module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

STw4810 Contents

3/78

5 Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.2 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.3.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.2 VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.3.3 VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.3.4 VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . 52

5.3.5 LDO regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5.3.6 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4 Digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.4.1 CMOS input/output static characteristics: I2C interface . . . . . . . . . . . . . 57

5.4.2 CMOS input/output dynamic characteristics: I2C interface . . . . . . . . . . 58

5.4.3 CMOS input/output static characteristics: VIO level . . . . . . . . . . . . . . . 59

5.4.4 CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . 61

5.4.5 CMOS input/output static characteristics: VMMC level . . . . . . . . . . . . . 62

5.5 USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.6 SD/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.1 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.1 TFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.2 VFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

List of tables STw4810

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List of tables

Table 1. STw4810 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. STw4810 balls function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 4. Register address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5. Register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Register general information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Power control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. USB register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Vendor ID and Product ID: Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11. USB control register 1 (address = 04h set and 05h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. USB control register 2 (Address = 06h set and 07h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. USB Interrupt source register (address = 08h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. USB interrupt latch registers (address = 0Ah set and 0Bh clearh). . . . . . . . . . . . . . . . . . . 25

Table 15. USB interrupt mask false register (address = 0Ch and 0Dh) . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16. USB interrupt mask true register (address = 0Eh and 0Fh) . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 17. USB EN register (address = 10h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. SD MMC control register (11h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. Power control register - General information (Address = 1Eh). . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Power control register - General information (Address = 1Fh) . . . . . . . . . . . . . . . . . . . . . . 28

Table 21. Power control register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22. Power control register at address 05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 23. Power control register at address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 24. Power control register at address 07h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 25. Power control register at address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 26. Power control register at address 09h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 27. Power control register at address 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 28. Twarning register (Address = 20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 29. Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 30. Thermal threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 31. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0 . . . . . . . . 42

Table 32. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1 . . . . . . . . 42

Table 33. Data receiver via USB control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 34. STw4810 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 35. Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 36. Operating conditions (Temp range: -30 to +85 °C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 37. VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 38. VCORE DC/DC step-down converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 39. VIO_VMEM DC/DC step-down converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 40. LDO regulators - VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 41. LDO regulators - VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 42. LDO regulators - VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 43. Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 44. CMOS input/output static characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 45. CMOS input/output dynamic characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 46. VIO level: USB and control I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 47. VIO level: MMC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 48. CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

STw4810 List of tables

5/78

Table 49. CMOS input/output static characteristics VMMC level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 50. USB OTG transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 51. SD/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 52. Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 53. Recommended coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 55. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions . . . . . . . . . . . . . . . . . . 72

Table 56. VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch . . . . . . . . . . . . . . . . . . . . 74

Table 57. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

List of figures STw4810

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List of figures

Figure 1. Typical mobile multimedia system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. STw4810 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 4. Switching POWER to sleep timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. VDDOK block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7. Control interface: I2C format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Control interface: I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Clock switching between master and internal clock (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10. Block diagram of biasing and references of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11. Thermal threshold temperatures for ‘it_warn’ bit and VDDOK ball. . . . . . . . . . . . . . . . . . . 38

Figure 12. USB OTG transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 13. SD MMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 14. Propagation and clock/data skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 15. STw4810 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 16. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing . . . . . . . . . . . . . . . . . . . . . 73

Figure 17. VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

STw4810 Overview

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1 Overview

The STw4810 power management device has the following features:

●Power management module

– 1 Step-down converter for processor core (1 to 1.5 V with 15 steps at 600 mA)

– 1 Step-down converter (1.8 V at 600 mA) for general purpose usage such as

processor input/output supply, external memory, DDR and SDRAM and

peripherals

– 1 Low-drop output regulator f or analog supplies, such as PLL (1.05 V, 1.2 V, 1.3 V,

1.8 V at 10 mA)

– 1 Low-drop output regulator for processor analogue functions (2.5 V at 10 mA)

– 1 Low-drop output regulator for auxiliary devices (1.5 V, 1.8 V, 2.5 V, 2.8 V at

150 mA)

●USB OTG module

– Full and low speed USB OTG transceiver

– 1 Linear regulators (3.1 V at 40 mA) supplying transceiver

– 1 Charge-pump (5 V at 100 mA) supplying VBUS line of the USB cable

●Mass memory cards (SD/MMC/SDIO)

– 1 Linear regulator (1.8 V, 2.85 V, 3 V at 150 mA)

– Level shifter

●Miscellaneous

– 32 kHz control for multimedia processor

– Proces so r suppl y mon itoring

– Processor reset control

– 2 Serial I2C interfaces

Figure 1. Typical mobile multimedia system

Functional block diagram STw4810

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2 Functional block diagram

Figure 2. STw4810 block diagram

VPLL_LDO

1.05V,1.2V,1.3V,1.8V,

VAUX

VCORE

VBAT_VCORE

VMINUS_VCORE

VPLL

VANA_LDO

2.5V, 10mA VANA

VBAT_VPLL_ANA

VBAT_VIO_VMEM

VLX_VIO_VMEM

VMINUS_VIO_VMEM

VIO_VMEM

1.8V- 600mA

VREF_VIO_VMEM

VREF_VCORE

VREF_VPLL

SOFT_START

VAUX_LDO

1.5V,1.8V2.5V,2.8V,

VREF_18

BG Buffer

BIAS

VREF_VAUX

Thermal

shutdown

VBAT_ANA

Internal

oscillator

clock

switching

and

control

MASTER_CLK

SCL

SDA I2C

interface

VBAT_DIG

VMINUS_DIG

General

control

PON

VDDOK

PORn

PWREN

SW_RESETn

Control

registers

USB

control

USB OTG transceiver interface VBAT_USB

VBUS

Charge

pump

VUSB

3.1V - 40mA

5V - 100mA

Driver

USBOEn

USBVP

USBVM

USBRCV

Control

SD/MMC/

SD/ MMC/SDIO interface

1.8/2.85/3V-150mA

VBAT_MMC

VMMC

Driver

Level

shifter LATCHCLK

CLKOUT

DATAOUT0

CMDOUT

DATAOUT[3:1]

MCCLK

MCFBCLK

MCCMDDIR

MCDAT0DIR

MCDAT2DIR

MCCMD

MCDATA[3:1]

MCDATA0

REQUEST_MC

VBAT_VAUX

CLK32K

CLK32K_IN

PORn_VBAT

VMINUS_ANA

1V=>1.5 V- 600mA

VLX_VCORE

TCXO_EN Monitoring

IT_WAKE_UP

GPO1

GPO2

I2C

Mux

USBSCL

USBSDA

USBINTn

MCDAT31DIR

VMINUS_USB

Level

shifter Pull

up &

down

SDIO control

10mA

150mA

STw4810 Ball information

9/78

3 Ball information

3.1 Ball connections

3.2 Ball functions

STw4810 includes the following ball types

●VDDD/VDDA: digital/analog power supply

●VSSD/VSSA: digital/analog ground supply

●DO/DI/DIO: Digital Output / Digital Input / Digital Input Output

●DOz: Digital Output with high impedance capability

●AO/AI/AIO: Analog Output / Analog Input / Analog Input-Output

●G: to be connected to ground

●O: to be left open

●Int-Ref: Associated to internal reference

Table 2

details the ballout.

Table 1. STw4810 ball connections

12345678910

ACLK32K_IN VMINUS_

VIO_VMEM

VLX_VIO_

VMEM VBAT_VIO_

VMEM VIO_VMEM VAUX VANA VPLL VREF_18 VCORE

B“Reserved” REQUEST_

MC VMINUS_

VIO_VMEM VBAT_VIO_

VMEM VMINUS_

ANA VBAT_

VAUX “Reserved” “Reserved” “Reserved” VMINUS_

VCORE

CTCXO_EN IT_WAKE_

UP VMINUS_

DIG VLX_VIO_

VMEM “Reserved” VBAT_ANA VBAT_

VPLL_ANA PON VMINUS_

VCORE VLX_

VCORE

DVBAT_DIG MASTER_

CLK “reserved” VLX_

VCORE VBAT_

VCORE

EDATAOUT0 DATAOUT

<1> DATAOUT

<2> ID DP DN

FDATAOUT

<3> CMDOUT LATCHCLK “Reserved” VBAT_USB VUSB

GCLKOUT MCCLK MCCMD

DIR “Reserved” USBSCL VBUS

HMCCMD MCDATA

<3> MCDATA

<1> MCDATA31

DIR MCFBCLK PWREN SDA USBINTn USBSDA CP

JMCDATA

<2> VDDOK PORN VBAT_

MMC GPO1 SCL USBVP USBVM VMINUS_

USB CN

KMCDATA0 MCDAT0

DIR CLK32K SW_

RESET VMMC GPO2 USBRCV USBOEn MCDAT2

DIR “Reserved”

Ball information STw4810

10/78

Table 2. STw4810 balls function

Ball Ball name Ball type Description

General supplies

D1 VBAT_DIG VDDD-VBAT Battery supply for digital/oscillator

C3 VMINUS_DIG VSSD Ground for digital and oscillator

C6 VBAT_ANA VDDA-VBAT Battery supply for analog

B5 VMINUS_ANA VSSA Ground for analog

F9 VBAT_USB VDDA-VBAT Battery supply for USB block

J9 VMINUS_USB VSSA Ground for USB block

A9 VREF_18 Int-Ref Internal reference

Control balls

C8 PON DI(VBAT)

Pull Down 1.5MΩPower-on and reset

K4 SW_RESETn DI(VIO_VMEM)

Pull Up 1.5MΩ

Software reset, reset all applications when

SW_RESETn = 0

J2 VDDOK DO(VIO_VMEM) Supply monitoring for mult imedia processors.

Interruption for high temperature warning

J3 PORn DO(VIO_ V MEM ) Multimed ia proc es so r Resetn

H6 PWREN DI(VIO_VMEM)

Pull Up 1.5MΩSleep mode from multimedia processor

C1 TCXO_EN DI(VIO_VMEM)

Pull Down 1.5MΩRequest of master clock from modem part

B2 REQUEST_MC DO(VIO_VMEM) R equest to master clock oscillator

J6 SCL DI(VIO_VMEM) Clock for Main I2C interface

H7 SDA DIO(V IO_VMEM) SDA for Main I2C interface

D2 MASTER_CLK AI

Pull Down 1.5MΩ26 MHz, 13 MHz or 19.2 MHz from modem

A1 CLK32K_IN DI(VIO_VMEM)

Pull Down 1.5MΩ32 kHz input

K3 CLK32K DO(VIO_VMEM) 32 kHz to multimedia processor

STw4810 Ball information

11/78

Regulator balls

B4 VBAT_VIO_VMEM VDDA-VBAT Battery power supply for step down

VIO_VMEM

B3 VMINUS_VIO_VMEM VSSA Ground for step down VIO_VMEM

C4 VLX_VIO_VMEM AIO BUCK of step down VIO_VMEM

A5 VIO_VMEM AI VIO_VMEM Feed back input

D10 VBAT_VCORE VDDA-VBAT Battery power supply for step down VCORE

B10

C9 VMINUS_VCORE VSSA Ground for step down VCORE

C10

D8 VLX_VCORE AIO BUCK of step-down VCORE

A10 VCORE AI VCORE sense

C7 VBAT_VPLL_ANA VDDA-VBAT Battery supply for VPLL, VANA

A7 VANA AO VANA output

A8 VPLL AO VPLL output

A6 VAUX AO VAUX output

B6 VBAT_VAUX VDDA-VBAT Battery supply for VAUX

USB balls

C2 IT_WAKE_UP DO(VBAT-DIG) Interrupt to modem for wake-up due to USB

plug

K8 USBOEn DIO(VIO_VMEM)

Pull Down 1.5MΩ

Output enable of the differential driver in the

USB mode

J7 USBVP DIO(VIO_VMEM)

Pull Down 1.5MΩ

Data input in the USB transmit mode, positive

data input the single-ended transmit mode, or

TXD in UART mode

J8 USBVM DIO(VIO_VMEM)

Pull Down 1.5MΩ

Single-ended zero input in the USB transmit

mode, negative data input in the single-ended

transmit mode, or RXD in the UART mode

K7 USBRCV DO(VIO_VMEM) Differential receiver output

E9 DP AIO(VUSB) Positive data line in the USB mode, or serial

data input in the UART mode

E10 DN AIO(VUSB) Negative data line in the USB mode, or serial

data output in the UART mode.

E8 ID AI(VBAT-USB) ID ball of the USB detector used for protocol

identification.

H10 CP AIO(VBUS) C plus flying capacitor

(VBUS level 4.4 to 5.25)

Table 2. STw4810 balls function (continued)

Ball Ball name Ball type Description

Ball information STw4810

12/78

J10 CN AIO(VBUS) C minus flying capacitor (VBUS Level)

G10 VBUS AIO(VBUS) USB cable supply (VBUS Level)

F10 VUSB AIO Decoupling capacitor for USB internal regulator

G9 USBSCL DI(VIO_VMEM) Clock for dedicated USB I2C

H9 USBSDA DIO(VIO_VMEM) SDA for dedicated USB I2C

H8 USBINTn DO(VIO_VMEM) Interrupt to multimedi a proc ess or for USB or

accessory plug

SD MMC balls

G3 MCCMDDIR DI(VIO_VMEM)

Pull Down 1.5MΩ

CMD direction.

- “high”: CMD signal from processor to card

- “Low”: CMD signal from card to processor

K2 MCDAT0DIR DI(VIO_VMEM)

Pull Down 1.5MΩ

DATA0 direction

- “high”: DATA0 signal from processor to card

- “Low”: DATA0 signal from card to processor

K9 MCDAT2DIR DI(VIO_VMEM)

Pull Down 1.5MΩ

DATA2 direction

- “high”: DATA2 signal from processor to card

- “Low”: DATA2 signal from card to processor

H4 MCDAT31DIR DI(VIO_VMEM)

Pull Down 1.5MΩ

DATA(3,1) direction

- “high”: DATA(3,1) signal from processor to

card

- “Low”: DATA(3,1) signal from card to

processor

G2 MCCLK DI(VIO_VMEM)

Pull Down 1.5MΩ

Host clock, between processor and STw4810,

to the card (processor clock).

H5 MCFBCLK DO(VIO_VMEM) Host feedback clock between STw4810 and

processor, to re-synchronize data in processor.

H1 MCCMD DIO(VIO_VMEM)

Pull Up 1.5MΩBidirectional command/response signal

between processor and STw4810.

K1 MCDATA0 DIO(VIO_VMEM)

Pull Up1.5MΩ

Bidirectional data0 between processor and

STw4810

J1 MCDATA[3:1] DIO(VIO_VMEM)

Pull Up 1.5MΩ

Bidirectional data [3:1] between processor and

STw4810.

F3 LATCHCLK DI(VMMC)

Pull Down 1.5MΩ

Host feedback clock to STw4810, to re-

synchron ize data in proc essor.

G1 CLKOUT DO(VMMC) Host clock, between STw4810 and card

(processor clock).

F2 CMDOUT DIO(VMMC)

Pull Up 1.5MΩ

Bidirectional command/response signal

between STw4810 and processor.

E1 DATAOUT0 DIO(VMMC)

Pull Up 1.5MΩBidirectional data0 between STw4810 and card

Table 2. STw4810 balls function (continued)

Ball Ball name Ball type Description

STw4810 Ball information

13/78

E2 DATAOUT[3:1] DIO(VMMC)

Pull Up 1.5MΩBidirectional data[3:1] between STw4810 and

card.

J4 VBAT_MMC VDDA-VBAT Battery supply for VMMC

K5 VMMC AIO VMMC supply output

Other balls

J5 GPO1 AO General purpose output

K6 GPO2 AO General purpose output

D3 “Reserved” G To be connect ed to ground

K10

“Reserved” O To be left open

Table 2. STw4810 balls function (continued)

Ball Ball name Ball type Description

Functional description STw4810

14/78

4 Functional description

4.1 Introduction

The STw4810 integrates all the power supplies for a multimedia processor as well as

memories and peripherals:

●Two switched mode power supply regulators: one for the multimedia processor core,

one for multimedia processor I/Os and memories

●Three low-drop output regulators for multimedia processor analog supplies (PLL and

others) and auxiliary components

●USB OTG FS/LS physical interface

●MMC card power supplies and level shifters

●Multimedia processor supply monitoring / power-on reset and power supply alarms /

interrupt management

●Two serial I2C communication interfaces; one to control the de vices (SDA, SCL) and

one to control the USB (USBSDA, USBSCL).

4.2 Digital control module

This module describes the interfaces used to program the device and the related registers.

4.2.1 State machine

Description of each states: (

Figure 3.

)

Off: In this mode the STw4810 is switched off. Off is when PON=0, when battery level is

under 2.4 V or when thermal shutdown is activated. There is no multimedia processor power

supply. The only activ e cell is the USB cable detection and VBAT level detection.

OSC_START: Oscillator is enabled and the power up module is waiting f or the rising edge of

the internal signal OSC_OK to start power up sequence. This state duration is 300 µs.

START_BIAS: Bias, ref erence and thermal shut-down are enabled, a counter is activated to

wait for rising edge of internal signals PDN_regulators. This state duration has a typical

value of 7.77 ms and a worst case value of 9.46 ms.

START_PM: after a 1 ms wait, multimedia processor power supplies are available

(VIO_VMEM, VCORE, VPLL, and VANA). The device can allow I2C communication, output

power supply monitoring and application (USB,SD/MMC).

OFF2: STw4810 is waiting for the 32 kHz multimedia processor signal. This state has an

indeterminate duration. If 32kHz is present during the states describes above, it has no

effect. The 32 kHz signal is taken into account by STw4810 only when the ‘VDDOK’ ball is

hig h, that is at the end of START_PM state.

Reset: STw4810 forces a reset during 10*32 kHz period before setting PORn high.

INT_OSC: The STw4810 can work without MASTER_CLK via its internal oscillator. The

device waits for an external clock detection before switching to the external clock. When

receiving a rising edge on PWREN ball (coming from multimedia processor) or on

TCXO_EN ball (coming from modem), STw4810 answers by asserting to “1” the

STw4810 Functional description

15/78

REQUEST_MC ball. STw4810 remains in internal oscillator mode until it receives the

external clock signal on MASTER_CLK ball.

EXT_CLK: When MASTER_CLK is detected, the STw4810 uses this clock as ref erence and

s witches off its internal oscillator to save quiescent. MASTERCLK should remain connected

up to sleep mode.

Sleep: Sleep mode is required by multimedia processor by setting a PWREN at low level.

Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and

wait f or PWREN at high level (

Figure 4

Wake-up: From sleep mode, the multimedia processor requests to switch back to Normal

mode. Thus the de vice restarts its internal oscillator and then switches regulators from sleep

to normal mode and informs multimedia processor with VDDOK at high level (

Figure 4

Note: By default VAUX is in stand by mode, pdn_vaux = 0 (Table 18). It can be programmed in

normal mode only by asserted pdn_vaux bit to “1”.

Functional description STw4810

16/78

Figure 3. Start-up timing

All regulators are started with PDN_regulators but can be switched off from the beginning or

during application by software (

Table 27

)

PON ball

PDN__OSC

PDN_regulators

VDDOK ball

CLK32K_IN ball

PORn ball

PWREN ball

OFF

START_PM

Reset

1ms

INT_OSC

TCXO_EN ball

Internal_OSC

11*(1/32kHz)

OFF2

MASTER_CLK ball

REQUEST_MC ball

VBAT

300µs

9.38ms (11ms wc)

Reset

START_BIAS

7.77ms (9.46ms wc)

“or”

Delays are worst case maximum delays

Voutput(s) ball

VPLL / VIO_VMEM

VCORE

CLK32K ball

(*)

(*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null

PWREN unmasked

STw4810 Functional description

17/78

Figure 4. Switching POWER to sleep timing

Registers reset

In the event of a har dware rese t coming from the modem, P ON ball s et to “0”, all registers

are reset at initial value when PON ball goes back to “1” level.

A software reset from multimedia processor of STw4810, through SW_RESETn ball set to

“0”, reset all registers except power control register (at address 1E & 1F).

Main clock oscillator control

REQUEST_MC is an OR output gate between PWREN (coming from multimedia processor)

and TCXO_EN (coming from modem supply), it is synchronized on 32 kHz, except during

power-up where PWREN is masked and considered as high.

REQUEST_MC enabled or disabled the master clock oscillator device.

PDN_regulators

VDDOK

CLK32K

PWREN

Sleep regulators

HPM SLEEP HPM

MASTER_CLK

Internal_OSC

PDN_intOSC

int_OSC_detect

~100µs

REQUEST_MC

Functional description STw4810

18/78

4.2.2 POWER OFF / VDDOK

●In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM

detected, or ‘it_twarn’ bit set to “1” (

Table 18

), then multimedia processor is reset

(PORn low during a minimum time of 312.5 µs) and restarted with no time-out. (see

Figure 5

). In case of VDDOK falling edge because PWREN balls equals “0”, there is no

reset (PORn still high).

●In case of PON falling edge (STw4810 switched off from modem) multimedia processor

is also reset with no time-out. We consider that clean switch off between modem and

multimedia processor is done by software directly.

Figure 5. VDDOK block diagram

4.2.3 Sleep mode

STw4810 goes into sleep mode by different ways.

Whether VCORE, VIO_VMEM and V AUX are programmed to sleep mode or not is indicated

Table 27

Digital block

vcore_monitor

vio_monitor &VDDOK

it_twarn

Reg status

read operation

or PON fa lling edge

or PORN_VBAT.

mask_twarn

VDDOK

PORn 312.5 µs

(10* 32 Khz)

Under voltage detection

Operating voltage threshold value reached

PWREN

STw4810 Functional description

19/78

4.2.4 I2C Interface

The device suppo r ts two I2C bus interfaces. One main i nterface (SDA,SCL) contro ls power

managem ent and all pr ogrammable functions, the second inte rface (USBS DA , USBSCL) is

dedicated to USB control. STw4810 allows to work with only the main I2C interface to

control all the functions, including the USB, via USB_I2C_CTRL bit of power control register

(

Table 27

). I2C Interface is used to read status information from inside the device.

Flags, interrupt and write registers are used to configure the device functions (threshold,

clock division, output voltage, etc....). By default, the main I2C interface (SCL,SDA) controls

the main registers and USB I2C interface (USBSCL, USBSDA) controls USB registers.

Figure 6. I2C interface block diagram

Both I2C are configured as slave serial interface compatible with I2C registered trademar k

of Phillips Inc. (version 2.1).

I2C interface description

STw4810 I2C is a slave serial interf ace with a serial data line (SD A or USBSD A) and a serial

clock line (SCL or USBSCL):

– SCL / USBSCL: input clock used to shift data

– SDA / USBSDA: input/output bidirectional data transfers

It is composed of:

– One filter to reject spikes on the bus data line and preserve data integrity

– Bidirectional data transfers up to 400kbit/s (Fast-mode) via SDA or USBSDA

signal

The SDA or USBSDA signal contains the input/output control and data signals that are

shifted in the device, MSB first. The first bit must be high (START) followed by the Device ID

(7 bits) and Read/Write bit control (1 indicates read access, a logical 0 indicates a write

access).

– Device ID in write mode: 5Ah (01011010)

– Device ID in read mode: 5Bh (01011011)

Then STw4810 sends an acknowledge at the end of an 8 bits transfer. The next 8 bits

correspond to the register address f ollowed by another acknowledge. The 8 bits data field is

sent last, followed by a last acknowledge.

Main registers

SDA

USBSCL

SCL

MUX

SDA or USBSDA

SCL or USBSCL

USBSDA USB registers

SDA

SCL

usb_i2c_ctrl

Functional description STw4810

20/78

I2C interface modes

Figure 7. Control interface: I2C format

Figure 8. Control interface: I2C timing

Table 3. Device ID

b7 b6 b5 b4 b3 b2 b1 b0

AdrID6 AdrID5 AdrID4 AdrID3 AdrID2 AdrID1 AdrID0 R/W

Table 4. Register address

b7 b6 b5 b4 b3 b2 b1 b0

RegADR7 RegADR6 RegADR5 RegADR4 RegADR3 RegADR2 RegADR1 RegADR0

Table 5. Register data

b7 b6 b5 b4 b3 b2 b1 b0

DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

DEVICE ADDRESS

0 1 0 1 1 0 1 0 REGn ADDRESS

REGn Data In

WRITE

SINGLE BYTE

START

ACK ACK

ACK

STOP

DEVICE ADDRESS

0 1 0 1 1 0 1 0 REGn ADDRESS

START

ACK ACK

DEVICE ADDRESS

0 1 0 1 1 0 1 1 REGn Data Out

START

ACK NO ACK

RANDOM ADDR

SINGLE BYTE

READ

DEVICE ADDRESS

0 1 0 1 1 0 1 0

REGn ADDRESS

START

ACK ACK DEVICE ADDRESS

0 1 0 1 1 0 1 1

START

Reg n Data Out ACK NO A CK

STOP

m+1 data bytes

ACK Reg n + m D ata Out

RANDOM ADDR

MULTI BYTE

READ

ACK

StopStart repeatedStop

tbuf thd_statftlow

thigh

thd_dat tsu_dat

Start

SDA

SCL

tsu_sta

thd_sta tsu_sto

USBSDA

USBSCL

STw4810 Functional description

21/78

4.2.5 Control registers

Control registers have the following functions:

– Select level of regulation for multimedia processor supply

– Control the USB interface

– Control the SD/MMC/SDIO interface

– Control the state machine

Table 6. Register general information

Address Comment I2C control

00h to 10h USB Registers (

Table 9

Table 17

) USBSDA / USBSCL or SDA / SCL (1)

11h SD MMC Control register (

Table 18

) SDA / SCL

12h to 1Dh Test registers

1Eh to 1Fh Power control registers (

Table 19

Table 27

) SDA / SCL

20h twarning register (

Table 28

) SDA / SCL

1. Controlled by USB_I2C_CTRL bit of Power control register (

Table 27

)

Table 7. Register summary

RegisterAddr.7 6543210

Vendor ID 00h1 0000011

01h0 0000100

Product ID 02h0 0010000

03h0 1000000

USB control

05h Not used uart_en oe_int_

en bdis_

acon_en not used dat_se0 suspend speed

USB control

07h vb us_ chr g vbus_

dischrg vbus_

drv id_gnd dn_

pulldown dp_

pulldown dn_

pullup dp_

pullup

USB interrupt

source 08h cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_vld vbus_vld

USB interrupt

latch 0Ah

0Bh cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_vld vbus_vld

USB interrupt

mask false 0Ch

0Dh cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_vld vbus_vld

USB interrupt

mask true 0Eh

0Fh cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_vld vbus_vld

USB EN 10h Not used usb_en not used

SD MMC control 11h pdn_ vaux it_warn

monitori

ng_vio_

vmem_

vcore

gpo2 gpo1 sel_vmmc<1:0> pdn_

vmmc

Twarning 20h Not used mask_

twarn

Functional description STw4810

22/78

Registers controlled by I2C USB bus

The registers described in this chapter are controlled through the USB serial I2C interface,

USBSC L and USBSDA balls.

These registers could also be controlled through the main I2C interface, SCL and SDA balls

by setting to “1” USB-I2C_CTRL bit in Power control register (

Table 23

Note: A bit of register 1 is set at “1” by writing a “1” at address 04h, is reset at “0” b y writing a “1” at

address 05h. This is also applicable for USB Control Register 2 (06h, 07h), USB Interrupt

True register (0Eh, 0Fh). Writing “0” at any address has not effect on the content of any

Table 8. Power control register

Power control 1Fh Not used reg address 2 bits

Power control 1 Eh reg address 3 bits data din/dout 4 bits ena write

Table 9. USB register address

Address Register Type

00h - 01h Vendor ID R

02h - 03h Product ID R

04h set USB Control Register 1 R/W

05h clearh USB Control Register 1 R/W

06h set USB Control Register 2 R/W

07h clearh USB Control Register 2 R/W

08h USB Interrupt Source R

09h Not used

0Ah set USB Interrupt Latch R/W

0Bh clearh USB Interrupt Latch R/W

0Ch set USB Interrupt Mask False R/W

0Dh clearh USB Interrupt Mask False R/W

0Eh set USB Interrupt Mask True R/W

0Fh clearh USB Interrupt Mask True R/W

10h USB_EN R/W

STw4810 Functional description

23/78

USB control register 1

Table 10. Vendor ID and Product ID: Read only

Name Address Register Value

Vendor ID 00h 83h

Vendor ID 01h 04h

Product ID 02h 10h

03h 40h

Table 11. USB control register 1 (address = 04h set and 05h clearh)

Bit name Not

used uart_en oe_int_

en bdis_

acon_en not used dat_se0 suspend speed

Type - R/W R/W R/W - R/W R/W R/W

Bits Name Value Settings Default

6 uart_en 0

1Inactive

UART logic buffers are enabled 0

5 oe_int_en 0

1Inactive

Allow to send interruption through USBOEn 0

4 bdis_acon_en 0

1Inactive (default)

Enable A-device to connect if B-device disconnect

detected: 0

2 dat_se0 0

1VP_VM USB mode

DAT_SE0 USB mode 0

1 suspend 0

1Inactive (default)

Put transceiver in low power mode 0

0 speed 0

Set rise and fall times of transmit

Low speed

Full speed 0

Functional description STw4810

24/78

USB control register 2

Table 12. USB control register 2 (Address = 06h set and 07h clearh)

Bit name vbus_

chrg vbus_

dischrg vbus_

drv id_gnd dn_

pulldown

dp_

pulldow

dn_

pullup dp_

pullup

Type R/W R/W R/W R/W R/W R/W R/W R/W

Bits Name Value Settings Default

7 vbus_chrg 0

1Inactive

Charge VBUS through a resistor 0

6 vbus_dischrg 0

1Inactive

Discharge VBUS through a resistor to ground. 0

5 vbus_drv 0

1Inactive

Provide power to VBUS 0

4 id_gnd 0

1Inactive

Connect ID ball to ground 0

3 dn_pulldown 0

1Inactive

Conne ct DN pul l-down 0

2 dp_pulldown 0

1Inactive

Conne ct DP pul l-d o w n 0

1 dn_pullup 0

1Inactive

Conne ct DN pul l-up 0

0 dp_pullup 0

1Inactive

Conne ct DP pul l-u p 0

STw4810 Functional description

25/78

USB interrupt source register

USB latch register

USB interrupt latch register bits indicate which sources have generate an interrupt.

Table 13. USB Interrupt source register (address = 08h)

Bit name cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_

vld vbus_

vld

Type RRRRRRRR

Bits Name Value Settings Default

7cr_int 0

1Inactive

DP ball is above the carkit interrupt threshold 0

6 bdis_acon 0

Inactive

Set when bdis_acon_en is set, and transceiver

asserts dp_pullup after detecting B-device

disconnect.

5 id_float 0

1Inactive

ID ball float ing 0

4 dn_hi 0

1Inactive

DN ball is high 0

3 id_gnd_forced 0

1Inactive

ID ball gro und ed 0

2 dp_hi 0

1Inactive

DP assert ed during SRP, 0

1 sess_vld 0

1Session valid comparator threshold <0.8V or >4.4V

0.8V < Session valid comparator threshold < 4.4V 0

0vbus_vld 0

1A-device VBUS valid comparator threshold <4.4V

A-device VBUS valid comparator threshold >4.4V 0

Table 14. USB interrupt latch registers (address = 0Ah set and 0Bh clearh)

Bit name cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_

vld vbus_

vld

Default 00000000

Type R/W R/W R/W R/W R/W R/W R/W R/W

Functional description STw4810

26/78

USB interrupt mask false register

USB interrupt mask false register bits enable transition from true to false.

USB interrupt mask true register

USB interrupt mask true register bits enable interrupts on transition from false to true.

USB EN register

Table 15. USB interrupt mask false register (address = 0Ch and 0Dh)

Bit name cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_vl

dvbus_vl

Default 00000000

Type R/W R/W R/W R/W R/W R/W R/W R/W

Table 16. USB interrupt mask true register (address = 0Eh and 0Fh)

Bit name cr_int bdis_

acon id_float dn_hi id_gnd_

forced dp_hi sess_vl

dvbus_vl

Type R/W R/W R/W R/W R/W R/W R/W R/W

Table 17. USB EN register (address = 10h)

Bit name Not used usb_en not used

Type ------R/W-

Bits Name Value Settings Default

1 usb_en 0

1Inactive

Enable USB PHY 0

STw4810 Functional description

27/78

Registers controlled by main I2C bus

I²C controlled registers are controlled through the main serial I2C interface, SCL and SDA

balls.

SD MMC control register

In Flash OTP two registers allow to program STw4810 energy management part.

These two registers are at address 1E and 1F and must be programmed with 1F register

first followed by 1E register.

Table 18. SD MMC control register (11h)

Bit name pdn_

vaux it_warn

monitori

ng_vio_

vmem_

vcore

gpo2 gpo1 sel_vmmc<1:0> pdn_

vmmc

Type R/W R(1) R(1)

1. These bits are reset (0) after reading

R/W R/W R/W R/W

Bits Name Value Settings Default

7 pdn_vaux 0

1Inactive

Enable LDO vaux 0

6it_warn 0

1Below tem per a ture thresh old

Above temperature threshold 0

5monitoring_vio_

vmem_vcore 0

1Outputs in the good range

Outputs lower than expected on vio_vmem or vcore 0

4 gpo2 0

1Output GPO2 HZ

Output GPO 2 Lo w 0

3 gpo1 0

1Output GPO1 HZ

Output GPO1 low 0

[2:1] sel_vmmc<1:0>

1.8V selection

2.85V selection

3V selection

0pdn_vmmc 0

1Inactive

Enable SD/MMC or SDIO function. 0

Functional description STw4810

28/78

Power control register at address 1Eh

Power control register at address 1Fh

Power control register mapping

Caution: Only the latest value written in register at address 1E/1F can be read.

Table 19. Power control register - General information (Address = 1Eh)

Bit name reg address 3 bits LSB’s data din/dout 4 bits EN

Type R/W R/W R/W

Bits Name Value Settings Default

[7:5] reg address 3

bits See

Table 21

“Address” co lumn (LSB’s). 0

[4:1] data din/

dout 4 bits See

Table 21

control register 0

0EN 0

1Read enabled

Write enab l ed 0

Table 20. Power control register - General information (Address = 1Fh)

Bit name Not used reg addres s 2 bits

MSB’s

Type R/W

Bits Name Value Settings Default

[9:8] reg address 2

bits MSB’s See

Table 21

“Address” column (MSB’s). 0

Table 21. Power control register mapping

Address 1Fh Address 1Eh

Comments

reg address

Not used 2 bits

MSB’s

3 bits

LSB’s

data din/dout

4 bits EN

1514131211109876543210

00h to 04h Test purpose

05h to 0Ah Setting See

Table 22

Table 27

0Bh to 1E Te st purpose

STw4810 Functional description

29/78

Power control register at address 05h

Table 22. Power control register at address 05h

Address 1Fh Address 1Eh

15141312111098765 43210

Not used 00101 vcore_sel [3:0] EN

Bits Name Value Settings Default

[4:1] vcore_sel [3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

= 1.00V

= 1.05V

= 1.10V

= 1.15V

= 1.20V (default)

= 1.22V

= 1.24V

= 1.26V

= 1.28V

= 1.30V

= 1.32V

= 1.34V

= 1.36V

= 1.38V

= 1.40V

= 1.50V

0100

Functional description STw4810

30/78

Power control register at address 06h

Power control register at address 07h

Table 23. Power control register at address 06h

Address 1Fh Address 1Eh

15141312111098765 4 3 2 1 0

Not used 00110

vpll_sel

[0] vaux_sel

<1:0> usb_

i2c_ctrl EN

Bits Name Value Settings Default

4vpll_sel[1:0]

on 06h and 07h

address

= 1.05V

= 1.2V

= 1.3V

= 1.8V

[3:2] vaux_sel[1:0]

= 1.5V

= 1.8V

= 2.5V

= 2.8V

1 usb_i2c_ctrl 0

1USB I2C interface controls USB registers

Main I2C interface controls USB registers 0

Table 24. Power control register at address 07h

Address 1Fh Address 1Eh

15141312111098765 4 3 2 1 0

Not used 00111en_vpllnot

used en_

vcore vpll_sel

[1] EN

Bits Name Value Settings Default

4 en_vpll 0

1Disabled / VPLL = OFF

Enabled / VPLL = ON(1)

1. No soft start feature at supply enabled after a disabled/enabled sequence

2 en_vcore 0

1Disabled / VCORE = OFF

Enabled / VCORE = ON(1) 1

1 vpll_sel[1] - See

Table 23

STw4810 Functional description

31/78

Power control register at address 08h

Power control register at address 09h

Table 25. Power control register at address 08h

Address 1Fh Address 1Eh

15141312111098765 43210

Not used 01000

en_clk

square

en_mo

nitorin

en_

vana not

used EN

Bits Name Value Settings Default

4 en_clock_squarer 0

1Disabled

Enabled (sine wave signal input) 0

3 en_monitoring 0

1Disabled / MONITORING = OFF

Enabled / VCORE & VIO_VMEM monitoring = ON 1

2 en_vana 0

1Disabled / VANA = OFF

Enabled / VANA = ON 1

Table 26. Power control register at address 09h

Address 1Fh Address 1Eh

15141312111098765 43210

Not used 01001

vaux_

sleep not

used not

used EN

Bits Name Value Settings Default

4 vaux_sleep 0

When PWREN is low:

VAUX stays in normal mode

VAUX goes in sleep mode (default) 1

2 Not used Reserved 1

1 Not used Reserved 1

Functional description STw4810

32/78

Power control register at address 0Ah

Twarning register

Table 27. Power control register at address 0Ah

Address 1Fh Address 1Eh

15141312111098765 43210

Not used 01010

vaux_

force_

sleep

not

used

vio_

vmem_

force_

sleep

vcore_

force_

sleep EN

Bits Name Value Settings Default

4 vaux_force_sleep 0

10: VAUX in normal mode

1: VAUX goes in sleep mode (for any PWREN level) 0

2vio_vmem_force_

sleep 0

0: VIO_VMEM in normal mode

1: VIO_VMEM goes in sleep mode (for any PWREN

level) 0

1 vcore_force_sleep 0

10: VCORE stays in normal mode

1: VCORE goes i n slee p mod e (f or any PWREN level) 0

Table 28. Twarning register (Address = 20h)

Bit name Not used mask_

twarn

Type -R/W

Bits Name Value Settings Default

0 mask_twarn 0

1Inactive

Mask TWARN interruption (it_twarn bit) through

VDDOK 0

STw4810 Functional description

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4.2.6 IT generation

STw4810 has three interrupt balls:

IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is

plugged this interrupt is activated to wake up the host or the modem, depends of application

(active low).

USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor

VDDOK: This ball has two functions:

- When high, it indicates that VIO_VMEM and VCORE output voltages are within the right

range and that the device internal temperature is below the maximum allowed temperature.

- When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated

properly or PWREN = “0”, or that the temperature is above the allowed threshold (see

Thermal shut-down

section). The interruption source in the application register (address

11h) needs to be checked.

4.2.7 Clock switching and control

This block generates the clock used by the DC/DC converter (USB charge pump, step-down

VIO_VMEM and step-down VCORE). STw4810 is able to sustain the master clock

frequen ci es of 26 MHz, 19.2 MHz and 13 MHz. It can als o sus tai n dedi ca ted MAS TER_ C LK

signal in the frequency range of 750KHz to 1MHz. If the clock is not detected the internal

oscillator is automatically selected.

Note: When present the Master clock should remain connected up to sleep mode.

Figure 9. Clock switching between master and internal clock (1)

INT_OSC

PON

INT_OSC_OK

MASTER_CLK_OK

PDN_INT_OSC

CONTROL_SWITCH

STEP_DOWN_CLK

Third rising edge after switching

internal clock external clocktransition

* Phase delay is less than 90 between int and ext clock

MASTER_DIV_CLK

Functional description STw4810

34/78

4.3 Power management module

STw4810 includes several regulators that supply the multimedia processor and its

peripherals. All regulators can work in different modes depending on the processor needs.

When th e STw4810 is in ‘low current mode’”, the output curren t is reduced to save energy

via the lower quiescent current. The nominal mode is called high power mode (HPM). The

mode is selected by PWREN signal according to both multimedia processor and STw4810

state.

When PWREN = “0”, sleep mode is sele cted. HPM is selected as default when PWREN =

“1”.

Each regulator has a dedicated battery power supply. It can be powered down by a signal

called PDN_regulator_name as shown in the

Figure 2: STw4810 block diagram

. In this

mode, the regulator is switched off and only a leakage current is present (max. 1µA).

VCORE, VAUX and VPLL output voltages are programmable, through main I2C interface,

using the “Regulator”_SEL[x:0] bits of the power control registers (

Table 22

Table 27

In addition, an output current limitation prevents high current delivery in case of output short

circuit.

All multi media pr ocessor power sup plies have the same sof t start to prevent leak age in the

multimedia processor device during the start-up phase. There is an exception with VAUX

which can be started independently.

4.3.1 Bandgap, biasing and references

Figure 10. Block diagram of biasing and references of the device

All internal

references

VREF_18

All internal

biasing

Bias generat or

Voltage reference

contro l

STw4810 Functional description

35/78

4.3.2 VCORE regulator: DC/DC step-down regulator

This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down

regulator that generates the regulated pow er supply with very high efficiency. The 15 voltage

levels enable dynamic voltage and frequency scaling suitable for any supply voltage of

CMOS process, they also follow the processor process roadmap. The regulated output

voltage levels are adjustable by the power control registers (

Table 22

), via the main I2C

interface (SDA, SCL).

The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to

generate the switching clock of the SMPS. When this clock is not available, regulators run

the internal RC oscillator.

The DC/DC step-down regulator has the following main features;

●Programmable output voltage, 15 levels from 1.0 V to 1.5 V (VCORE_SEL [3:0] bits of

power control register -

Table 22

)

●3 power domains:

– ‘Normal mode’ when multimedia processor is in run mode, 600 mA full load

– ‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current

capability.

Fast switching from low current to normal mode.

The regulator is in ‘low current mode’ when multimedia processor is in sleep

mode. PWREN signal indicates that the multimedia processor is about to s witch to

run mode. VDDOK signal indicates to the multimedia processor that all supplies

are in the specified range.

Note: The definition of sleep mode is given in section 4.2.3: Sleep mode.

●‘Po wer down mode’ or ‘standby mode’ when regulator is switched off, no consumption

(EN_VCORE bit of power control register -

Table 28

)

●Soft start circuitry at start up, from power off to normal mode, when PON ball changes

from “0” to “1”.

●Default setting defined by start-up configuration.

4.3.3 VIO_VMEM regulator: DC/DC step- down regulator

VIO_VMEM step-down regulator has the same structure than VCORE.

The VIO_VMEM regulator supplies the IOs of the multimedia processor and its peripherals.

This regulator can be used to supply the memories working with the multimedia processor,

such as DDR-SDRAM. A switched mode power supply - voltage down converter is used to

generate the 1.8 V regulated power supply with very high efficiency.

The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to

generate th e S MP S switchi ng clo ck. Wh en th is c lock is n ot available, regul ator s ca n run the

internal RC oscillat or.

Main features

●Fixed 1.8 V output voltage

●Two power domains:

– ‘Normal mode’ when multimedia processor is in run mode - 600 mA full load

– ‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current

capability.

Functional description STw4810

36/78

Fast switching from low current to normal mode.

The regulator is in ‘low current mode’ when multimedia processor is in sleep

mode. PWREN signal indicates that the multimedia processor is about to s witch to

run mode. VDDOK signal indicates to the multimedia processor that all supplies

are in the specified range.

Note: The definition of sleep mode is given in 4.2.3: Sl eep mode section.

●Soft start circuitry at start up, from power off to normal mode, when PON ball changes

from “0” to “1”.

●Default setting defined by start-up configuration.

4.3.4 VPLL

This LDO is dedicated to the multimedia processor PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V) power

supply with 10 mA max full load (Power Control Registers -

Table 27

and

Table 28

Main features

●Programmable output voltage, (VPLL_SEL[1:0] bits of power control register -

Table 27

and

Table 28

)

●Two power domains:

– ‘Nor m al mode’ 10 m A full load

– ‘Power down mode’ or ‘standby mode’ when regulators are switched off and there

is no power consumption (EN_VPLL bit of power control register -

Table 28

)

●Soft start circuitry at start up, from power off to normal mode, when PON ball changes

from “0” to “1”.

●Default setting defined by start-up configuration.

4.3.5 VANA

This LDO is dedic ated to the mul timedia p rocessor an alogue funct ion (2.5 V ) power supply

with 10 mA full load.

Main features:

●2.5 V output voltage,

●Two power domains

– ‘Nor m al mode’ 10 m A full load

– ‘Power down mode’ or ‘standby mode’ when regulators are switched off and there

is no power consumption (EN_VANA bit of power control register -

Table 29

●Default setting defined by start-up configuration.

STw4810 Functional description

37/78

4.3.6 VAUX

This LDO is dedicated either to the multimedia processor input/output signals or to the

auxiliary devices. Power supply values are 1.5 V,1.8 V, 2.5 V, 2.8 V with 150 mA full load and

0.5 mA in sleep mode. In case of 1.5 V on the output, this LDO can be supplied by using

VIO_VMEM DC/DC converter (1.8 V). One pad feed-back is used.

Main features:

●Programmable output voltage, 4 levels

(VAUX_SEL[1:0] bits of Power control register -

Table 27

)

●Three power domains:

– ‘Normal mode’ when multimedia processor is in run mode, 150 mA full load

– ‘Low current mode’ when multimedia processor is in sleep mode, 0.5 mA current

capability.

Fast switching from low current to normal mode.

Note: Definition of sleep mode is given in 4.2.3: Sleep mode section.

– ‘Power down mode’ or ‘standby mode’ when regulator is switched off, no power

consumption (PDN_VAUX bit of SD MMC control register -

Table 18

)

●Default setting defined by start-up configuration

4.3.7 Power supply monitoring

This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM

drop below the threshold, the multimedia processor is reset.

This feature can be desactivated by setting EN_MONITORING bit of Power control register

(

Table 29

) to “0”.

4.3.8 Power supply domains

Table 29

lists the register bits that control STw4810 supply domains for each supply.

Note: More details on VMMC supply are given in Section 4.5

Table 29. Power supply domains

Supply

name Description

Supply domains

Normal Sleep Power down

VCORE STEP-DOWN 15 values

VCORE_SEL[3:0] VCORE_SLEEP

VCORE_FORCE_SLEEP EN_VCORE

VIO_VMEM STEP-DO WN 1 .8 V VIO_MEM_SLEEP

VIO_VMEM_FORCE_SLEEP

VPLL LDO 4 values

VPLL_SEL[1:0] EN_VPLL

VANA LDO 2.5 V EN_VANA

VAUX LDO 4 values

VAUX_SEL[1:0] VAUX_SLEEP

VAUX_FORCE_SLEEP PDN_VAUX

VMMC LDO 3 values

SEL_VMMC[1:0] PDN_VMMC

Functional description STw4810

38/78

4.3.9 Thermal shut-down

A thermal sensor is used to monitor the die temperature.

●As soon as the die temperature exceeds the thermal w arning rising threshold, VDDOK

ball goes to “0” and ‘it_warn’ bit is set to “1” (SD MMC control register -

Table 18

). The

IC turns back VDDOK ball to “1” and ‘it_warn’ bit to “0” when the device temperature

drops below the thermal warning falling threshold of the thermal sensor.

●A second thermal detection level, thermal shutdown threshold, puts all STw4810

supplies OFF, the supplies goes back to goes back to ON state when the temperature

is under the thermal shutdown threshold and after a new startup phase.

Figure 11. Thermal threshold temperatures for ‘it_warn’ bit and VDDOK ball

Table 30. Thermal threshold values

Description Min Typ Max Unit

Thermal warning threshold

Rising threshold 134 140 149 °C

Falling threshold 117 123 131 °C

Thermal shutdown threshold

Threshold 149 155 164 °C

‘it_w arn’ bit

VDDOK ball

Temperature

Rising warning

threshold Shutdown

threshold

All supplies

are turn “OFF”

STw4810 Functional description

39/78

4.4 USB OTG module

This transceiver complies with the USB specification:

●Universal Serial Bus spe ci fi ca t ion revision 2.0

●‘On the Go’ supplement to the USB specification revision 1.0-a

●Car kit interface specification (see: OTG transceiver specification revision 0.92)

The USB OTG transceiver has two modes: USB mode and U ART mode. It includes:

●Full and low speed transceiver (12 Mbit/s and 1.5 Mbit/s data rate)

●Support data line and VBUS pulsing session request

●Host Negotiation Protocol (HNP) command and status register

●Charge pump regulator (5 V at 100 mA) to supply VBUS line of the USB cable

●VBUS pull-up and pull-down resistors as defined by Session Request Protocol (SRP)

●VBUS threshol d com parator s

●VUSB LDO internal regulator which provides power supply for the bus driver and

receiver.

●ID line detector and interrupt generator

●Dedicated I²C serial control interface

Functional description STw4810

40/78

4.4.1 Block diagram

Figure 12. USB OTG transceiver block diagram

VUSB

VBAT_USB

VUSB_LDO

VBAT_DIG

VMINUS_DIG

out_diff_Rx

Control

Registers

TRANCEIVER

VBAT_USB

CP CN

VBUS

CHARGE

PUMP

5V - 100mA

OE_TP_INT

DAT_VP

SEO_VM

RCV

suspend

id_float

id_gnd

vbus_vld

sess_vld

vbus_session_end

VBUS_MONITOR

DP_MONITOR

VBUS > 4.4 V

2V < VBUS < 4.4 V

VBUS < 0.8V

ID Detector

Diff Tx

Diff Rx

SE_DP

SE_DN

DECODER

SINGLE

RXD

speed

dat_se0

bdis_acon_en

oe_int_en

uart_en

dp_pullup

dn_pullup

dp_pulldown

dn_pulldown

id_gnd_forced

vbus_drv

vbus_dischrg

vbus_chrg

dp_hi

id_gnd

dn_hi

bdis_acon

Gnd

RA_BUS_IN

CLK

REF

RPU_DN

RPU_DP

RPD_DN

RPD_DP

R_VBUS_SRP

R_VBUS_PD

vbus_chrg

vbus_dischrg

dn_pullup

dn_pulldown

id_gnd

dp_pullup

dp_pulldown

USBVP

USBVM

USBOEn

USBRCV

cr_int

Interrupt

Control

vbus_vld

sess_vld

id_float

cr_int

USB_INTn

USBSCL

USBSDA

suspend

vbus_drv

ENDED

IT_WAKE_UP

Plug detect

Management sess_vld

RID_PU

4.7 R

SCL

SDA

DP < [0.4 to 0.6] V

5.7 R

0.85*ID

0.15*ID

100 mA

usb_i2c_ctrl

SW_RESETn

usb_en

VBAT_DIG

VBAT_USB

STw4810 Functional description

41/78

VBUS monitoring

These comparators monitor the VBUS voltage. The y detect the current status of the VBUS

line:

●VBUS > 4.4 V means VBUS_VALID

●2 V<VBUS<4.4 V means SESSION_VALID

●VBUS<0.8 V means SESSION_END

These three bits generate an interrupt when active (see USB interrupt registers).

VUSB LDO: Internal regulator which provides power supply for the bus driver and receiver.

ID detector: This block detects the status of the ID line. It is capable of detecting three

different states of line: ball is floating ID_FLOAT high, ball is tied to ground ID_GND high and

ball ID is grounded via resistor. This detection generates interrupts (see USB interrupt

registers).

Transceiver: The driver can operate in sev eral different modes. It can act as a classical low-

speed and full-speed differential driver, as two independent single-ended drivers or as a

single-ended driver in UART mode. This block contains one differential receiver for the USB

mode of operation and two single-ended receivers for USB signaling and UART mode.

DP monitor: This block is used to detect car kit peripheral (0.6 V on DP).

Pull up and pull down resistor: Configurable integrated pull-up and pull-down resistor of

data line and VBUS.

4.4.2 Modes and operations

Power modes

The transc eiver power modes are:

●Active power mode

●Suspended power mode

●Power down mode

In suspended power mode the differential transmitter and receiver are turned off to save

power but the USB interface is still active (pull-up and pull-down on, VBUS on). In power

down mode, only the serial interface is active and the transceiver is able to detect SRP. In

power down mode, ID ball sensing can be turned on/off via a control bit in the control

registers.

USB modes

The two transceiver modes are:

●DAT_SEO mode (dat_se0 = 1 in USB control register 1 -

Table 11

)

●VP_VM mode (dat_se0 = 0 in USB control register 1 -

Table 11

)

Functional description STw4810

42/78

Data transmission The transceiver transmits USB data in the following conditions for USB

control register 1 (

Table 31

Table 32

uart_en=0; oe_int_en=0

If oe_int_en = 1 and suspend=1 (USB control register 1 -

Table 11

), the USBOEn ball

becomes an output used to generate an IT to multimedia processor.

Table 31. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0

USB mode

(DAT_SE0)

Inputs Outputs

Comments

USBVP USBVM DP DN USBRCV

1 (DAT_SE0 mode) 0 0 0 1 Not used Single ended data (zero sent)

1 (DAT_SE0 mode) 1 0 1 0 Not used Single ended data (1 sent)

1 (DAT_SE0 mode) x 1 0 0 Not used Force single ended zero

0 (VP_VM mode) 0 0 0 0 DIFF_RX

DAT_VP drives the level of DP

SE0_VM drives the level of DN

0 (VP_VM mode) 1 0 1 0 DIFF_RX

0 (VP_VM mode) 0 1 0 1 DIFF_RX

0 (VP_VM mode) 1 1 1 1 DIFF_RX

Table 32. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1

USB mode (dat_se0)

Inputs Outputs

Comments

USBVP USBVM DP DN USBRCV

1 (DAT_SE0 mode) 0 0 0 1 not used Single ended data (zero sent)

1 (DAT_SE 0 mode) 1 0 1 0 not used Single ended data (1 sent)

1 (DAT_SE0 mode) x 1 0 0 not used Force single ended zero

0 (VP_VM mode) 0 0 0 0 0 (off)

Driver are suspended

0 (VP_VM mode) 1 0 1 0 0 (off)

0 (VP_VM mode) 0 1 0 1 0 (off)

0 (VP_VM mode) 1 1 1 1 0 (off)

STw4810 Functional description

43/78

The transceiver receives USB data in the following conditions:

uart_en = 0 (USB control register 1); oe_int_en = 1

UART mode

UART mode is entered by setting the ‘uart_en’ bit to 1 (USB control register 1 -

Table 11

The transceiver contains two digital logic level translators between the following balls:

●TXD signal: from USBVM to DN

●RXD signal: from DP to USBVP

When not in UART mode the level translators are disabled.

Table 33. Data receiver via USB control register 1

USB mode (dat_se0) Suspend

Inputs Outputs

DP DN USBVP USBVM USBRCV

1 (DAT_S E0 mo de) 0 0 0 Diff rcv 1 1 not used

1 (DAT_S E0 mo de) 0 1 0 1 0 not us ed

1 (DAT_S E0 mo de) 0 0 1 0 0 not us ed

1 (DAT_S E0 mo de) 0 1 1 Diff rcv 1 0 not used

1 (DAT_S E0 mo de) 1 0 0 0 1 not us ed

1 (DAT_S E0 mo de) 1 1 0 1 0 not us ed

1 (DAT_S E0 mo de) 1 0 1 0 0 not us ed

1 (DAT_S E0 mo de) 1 1 1 1 0 not us ed

0 (VP_VM mode) 0 0 0 0 0 diff rcv 1

0 (VP_VM mode) 0 1 0 1 0 1

0 (VP_VM mode) 0 0 1 0 1 0

0 (VP_VM mode) 0 1 1 1 1 diff rcv 1

0 (VP_VM mode) 1 0 0 0 0 not used

0 (VP_VM mode) 1 1 0 1 0 not used

0 (VP_VM mode) 1 0 1 0 1 not used

0 (VP_VM mode) 1 1 1 1 1 not used

Functional description STw4810

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VBUS monitoring and control

The monitoring is made of three comparators that determine if the VBUS voltage is at a valid

level for operation:

●VBUS valid: It corresponds to the minimum le vel on VBUS. Any v oltage on VBUS below

the threshold is considered to be a fault. During power-up, it is expected that this

comparator output is ignored.

●VBUS session valid: This threshold is necessary for session request protocol to detect

the VBUS pulsing.

●VBUS session end: Session is ended. In this USB block, a B-device session end

threshold is defined within the range [0.2; 0.8] V. The reason for a low 0.2 V limit is that

the leakage current could charge the VBUS up to 0.2 V (maximum).

When the A-device (default master) is power supplied and does not supply VBUS, it

presents an input impedance RA_BUS_IN on VBUS of no more than 100 kΩ. If the A-device

respo nds to the VBUS p ulsing meth od of SRP, t hen the input i mpedance RA_BUS_IN may

not be lower than 40 kΩ.

When the A-device supplies power, the rise time TA_VBUS_RISE on VBUS to go from 0 to

4.4 V is less than 100 ms when driving 100 mA and with an external load capacitance of

10 µF (in addition to VBUS decoupling capacitance). If VBUS does not reach this voltage

within TA_VBUS_RISE maximum time, it indicates that the B-device is drawing more current

that the A-device is capable of providing and an over-current condition exists. In this case,

the A-device turns VBUS off and terminates the session.

VBUS capacitance

A dual-role device must have a VBUS capacitance CDRD_VBUS value comprised between

1 µF and 6.5 µF (see charge pump specification). The limit on the decoupling capacitance

allows a B-device to differentiate between a powered-down dual-role device and a powered-

down standard host. The capacitance on a host is higher than 96 µF.

Data line pull-down resistance

When an A-device is idle or acting as host, it activates the pull-down resistors RPD on both

DP and DN lines.

When an A-device is acting as peripheral, it disables RPD on DP, not DN.

The A-device can disable both pull-down resistors during the interval of a packet

transmission when acting as either host or peripheral.

The two bits of USB control register, dn_pulldown and dp_pulldown (

Table 12

) are used to

connect/disconnect the pull-down resistors.

When the line is not used, the pull-down is activated and the maximum level on this ball

should not exceed 0.342 V.

Data line pull-up resistance

Full-speed and low-speed devices are differentiated by the position of the pull-up resistor

from the peripheral device. A pull-up resistor is connected to DP line for a full-speed device

and a pull-up resistor is connected to DN line for a low-speed device. The pull-up resistor

value is in the range of 900 Ω to 1600 Ω when the bus is idle and 1425 Ω to 3100 Ω when the

upstream device is transmitting.

STw4810 Functional description

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The two bits of USB control register dp_pullup and dn_pullup (

Table 12

) are used to

connect/disconnect pull-up resistors.

Session Request Protocol (SRP)

To save pow er, the O TG supplement allows an A-de vice to lea v e the VBUS turned off when

the bus is not being used. If the B-device wants to use the bus when VBUS is turned off,

then it requires the A-device to supply power on VBUS using the Session Request Protocol

(SRP).

●Initial conditions

The B-device does not attempt to start a new session until it has determined if the A-device

has detected the end of the previous session. The B-device must ensure that VBUS is below

VBUS_SESSION_END before requesting a new session.

Additionally, the B-device switches a pull-down resistor (R_VBUS_PD) from VBUS to

ground in order to quicken the discharge process as long as the B-device does not draw

more than 8 mA from VBUS. R_VBUS_PD is activated by bit ‘vbus_dischrg’ of USB control

Table 12

When the B-device detects that VBUS is below the VBUS_SESSION_END and that both

DP and DN have been low (SEO) for at least 2 ms, then any previous session on the A-

device is over and a new session can start.

●Data-line pulsing

To indicate a request for a new session using the data line pulsing, the B-device turns on the

DP pull-up resistor for 5 ms to 10 ms (only at full speed, no DN pulsing). The DP pull-up

resistor is connected to VUSB (regulator output voltage). Timing is controlled by the USB

digital control.

●VBUS pulsi ng

To indicate a request for a new session using the VBUS pulsing method, the B-device waits

for the initial conditions and then drives VBUS. VBUS is driv en for a long enough period for a

capacitance on VBUS that is smaller than 2x6.5 µF to be charged to 2.1 V while a

capacitance on VBUS higher than 97 µF is not charged above 2.0 V. In this USB block, the

VBUS_SESSION_VALID threshold is used to determine if an A-device is DRD (dual role

device) or a standard host.

The B-device VBUS pulsing block is designed so that the maximum dra wn current does not

exceed 8 mA. In this USB block, the pull-up is 600 Ω +/- 30% .

If a B-device is attached to a standard device, the pull-up must be disconnected after the

defined timing to prevent damage of standard hosts not designed to withstand a voltage

externally applied to VBUS.

●Session Request Protocol (SRP)

If the B-device is in correct condition to start a new session, it first performs data line

pulsing, followed by VBUS pulsing. When VBUS next crosses the SESSION VALID

threshold, the B- device considers a session to be in progress and asserts the DP or DN

data line within 100 ms. After SRP initialization, the B- device is set up to wait for at least 5

seconds f or the A-device to respond before informing the user that the consumption attempt

has failed.

Functional description STw4810

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●Host Negotiation Protocol (HNP)

At the start of a session, the A-device has the role of host as default. During a session, the

host role can be transferred back and forth between the A-device and the B-device any

number of times using the Host Negotiation Protocol (HNP). The process for this exchange

of host role is described in the “On the Go Supplement to the USB 2.0 Specification” (rev

1.0).

ID detector

In either active or suspended power mode, the ID detector detects the condition of the ID

line and differentiates between the following three conditions:

– ID ball floating: (e.g. with USB B-device connected)

– ID ball shorted to ground: (e.g. with USB A-device connected)

– ID ball connected to ground through resistor RACC_ID: (e.g.with an accessory).

The transceiver pulls the ID ball to VID_HI (VBAT) through a resistance of RID_PU when an

accessory is plugged in. In this case, the ID ball is externally connected to ground via

Racc_ID resistor.

Two comparators are used to detect the ID vo ltage: VID_GND and VID_FLOAT.

The ID detector also has a switch that can be used to ground the ID ball. This switch is

controlled by id_gnd bit of USB control register 2 (

Table 12

); This pull-down i s use d for

CEA_KARKIT purposes.

Car kit interrupt detector

The transceiver is able to detect when the DP line is below the Carkit Interrupt threshold

‘cr_int’, (see USB interrupt register) (refer to OTG specifications, Rev 0.92, §2.7, p13).

Charge pump

From VBAT_USB, the char ge pump s upplie s VBUS, ‘vbus_dr v’ bit of USB contr ol regi ster 2

(

Table 12

) is used to enable/disable the charge pump.

LDO USB

From VBAT_USB, a LDO provides VUSB supply, ‘usb_en’ bit of USB_EN register (

Table 17

)

is used to enable/disable the VUSB LDO.

STw4810 Functional description

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4.4.3 USB enable control

STw4810 OFF

In this state, the ov erall system is able to detect USB connection through IT_W AKE_UP ball

and with VBUS session valid comparator and ID detection ON.

IT_WAKE_UP is activated (low level) in either of the two following cases:

– When Mini A connector cable is connected and ID goes low

– When activity on VBUS, i.e. a mini B is connected and is able to communicate.

This mode is used to wake-up the modem platform. In this configuration, USBINTn

ball is not enabled.

STw4810 ON, USB driver not enabled

The USBINTn is now enabled.

If the USB cable is already connected while STw4810 is starting, the USB driver will be

enabled when power management is ready.

●Wake-up USB driver conditions

– A plug-in on a mini A-de vice and active ID detector

– B de vice is connected and ready to start data transfer, VBUS is driven high

(session valid high)

– Activity on USB registers (00h to 0Fh -

Table 9

Table 16

). Multimedia processor

ready to wake-up and set-up USB PHY.

– Possibility to force PHY high (enable) when writing usb_en = 1 in USB EN register

(

Table 17

)

●Set condition: one among the following possibilities

– External it_wake_up =0

– usb_en = 1 by writing to I²C USB interface

– Access to any other USB register (00h to 0Fh)

●Power down USB driver conditions in order to set the USB driver to power down mode:

– it_wake_up = 1, and only then

– Set usb_en bit of USB EN register (

Table 17

) to “0”

Functional description STw4810

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4.5 SD/MMC/SDIO module

This block provides the power supply (1.8 V, 2.85 V or 3 V) and signal shifting functions

required to connect any of the f ollowing peripherals to the multimedia processor:

–SD card

– MMC cards, low and 52 MHz high speed

– SDIO cards (except SDIO card version 1.0 / Vsupply range: [3.1; 3.6] V

Cards detection is automatically done by the multimedia processor system. Following a card

detection, the multimedia processor starts the SD/MMC application by writing in the SD

MMC control re gister (

Table 18

) to start LDO VMMC and then starts the protocol

initialization.

The module includes:

– 1.8 V, 2.85 V or 3 V voltage regulators (150 mA)

– Five bidirectional level shifter channels compatible with 1.8 V, 2.85 V or 3 V

– Two unidirectional lines f or clock: multimedia processor to card and feedback clock

to multimedia processor for synchronization.

– Four control signals for channel direction

Figure 13. SD MMC block diagram

SD/ MMC/SDIO INTERFACE

1.8V,2.85V,3V

VBAT_VMMC

VMMC

DRIVER

Level

Shifter

LATCHCLK

CLKOUT

DATAOUT0

MCCLK

MCFBCLK

MCCMDDIR

MCDATA0DIR

MCDATA31DIR

MCCMD

MCDATA[3:1]

MCDATA0

SD, MMC

SDIO OR

CARDS

CMDOUT

5 * RB

DATAOUT[3:1]

Vsdc2

EMIF

Dz Dz

MCDATA2DIR

3 * RA

150mA

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5 Electrical and timing characteristics

Otherwise specified parameters are defined for T = 25°C. / VBAT = 3.6 V

5.1 Absolute maximum rating

5.2 Package dissipation

5.3 Power supply

Note: STw4810 has different ways to go in sleep mode.

The different possibilities for VCORE, VIO_VMEM and VAUX to be programmed to sleep

mode are given in

Table 30

and

Table 27

In all the following tables:

– “Normal mode” is defined as “SLEEP = ‘0’”

– “Sleep mode” is defined as “SLEEP = ‘1’”

Use

Table 27

to refer to each Vxxx supply (VCORE or VIO_VMEM or VAUX).

Table 34. STw4810 absolute maximum ratings

Symbol Description Values Units

Maximum p ower s upply -0.5 to 7 V

Ta Maximum operating ambient temperature -30 to 85 °C

VESD Electrostatic discharge model Human body model(1)

1. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM

-2 to +2 kV

Charge device

model(2)

2. CDM tests have been performed in compliance with CDM ANSI-ESD STM 5.3.1-1999

-450 to +750 V

Table 35. Package dissipation

Symbol Description Min. Typ. Max. Units

TFBGA 84 6x6x1.2mm 0.5mm ball pitch

RTHJ-A Thermal resistance Junction to Ambient 70 °C/W

VFBGA84 4.6x4.6x1.0mm 0.4mm ball pitch

RTHJ-A Thermal resistance Junction to Ambient 76 °C/W

Electrical and timing characteristics STw4810

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5.3.1 Operating conditions

5.3.2 VREF18

Table 36. Operating conditions (Temp range: -30 to +85 °C)

Symbol Description Test conditions Min. Typ. Max. Units

VBAT Power supply 2.7 4.8 V

IQSLEEP Quiescent Current Sleep mode 170 250 µA

IQSTDBY Off mode 4 µA

Table 37. VREF18

Symbol Description Test conditions Min. Typ. Max. Units

VBAT Suppl y vol tag e 2.7 4.8 V

VREF_18 Output v ol tag e 1.78 1.8 1.84 V

PSRR Power supply

rejection ratio Vpp = 0.3 V

f ≤ 100 kHz 60 dB

Noise 100 Hz ≤ f ≤ 100 kHz 30 µV

tSSettling time 7.77 9.46 ms

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5.3.3 VCORE DC/DC step-down converter

Table 38. VCORE DC/DC step-down converter

Symbol Description Test conditions Min. Typ. Max. Units

VCORE regulator in normal mode (SLEEP = ‘0’) / Otherwise specified; VCORE = 1.2 V

VBAT Input power supply Battery voltage 2.7 3.6 4.8 V

VRIPPLE Output voltage

ripple 10 mVpp

VOUT Programmable

output voltage

VCORE_SEL[3:0]

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100 (default)

0011

0010

0001

0000

-3.7%

-4.25%

-5%

1.50

1.40

1.38

1.36

1.34

1.32

1.30

1.28

1.26

1.24

1.22

1.20

1.15

1.10

1.05

1.00

+3.7%

+4.25%

+5%

IOUT Out put cu rrent 600 mA

PEFF Power efficiency VBAT = 3.6 V

IOUT = 200 mA 86 %

LIR Line regulati on VBAT: [2.7; 4.8]V 10 mV

LDR(1) Load regulation IOUT: [0.1; 600] mA 10 mV

ISHORT Sh ort circuit

current limitation(2) 0.9 1.2 1.4 A

IQQuiescent current IOUT = 0 mA 130 250 µA

ILKG Power-down

current ‘en_vcore’ = 0 1 µA

PSRR(1) Power supply

rejection Vpp = 0.3 V

[0; 20] kHz 40 dB

LIRT Transient line

regulation ΔVBAT = 300 mV

tR = tF = 10 µs 7mV

LDRT Transient load

regulation IOUT = [1; 600] mA

tR = tF = 100 ns 70 mV

Electrical and timing characteristics STw4810

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5.3.4 VIO_VMEM DC/DC step-down converter

VCORE regulator in sleep mode (SLEEP= ‘1’)

VBAT Input power supply Battery voltage 2.7 3.6 4.8 V

VRIPPLE VCORE output

voltage ripple 10 mVpp

LIR Line regulati on VBAT: [2.7; 4.8]V 10 mV

LDR Load regulati on IOUT: [0.1; 5] mA 10 mV

IOUT VCORE output

current 5mA

PEFF Power efficiency VBAT= 3.6 V

IOUT: [0.1; 5] mA 85 %

IQQuiescent current IOUT = 0 mA 20 30 µA

LIRT Transient line

regulation

ΔVBAT= 300 mV

tR = tF = 10 µs 7mV

1. Guaranteed by design

2. Guaranteed by design

Table 38. VCORE DC/DC step-down converter (continued)

Symbol Description Test conditions Min. Typ. Max. Units

Table 39. VIO_VMEM DC/DC step-down converter

Symbol Description Test conditions Min. Typ. Max. Units

VIO_VMEM regulator in normal mode (SLEEP = ‘0’)

VBAT Input power supply Battery vol tag e 2.7 3.6 4.8 V

VOUT Out put voltage (1) -3% 1.8 +3% V

VRIPPLE Output ripple 10 mVpp

LIR Line regulati on VBAT: [2.7; 4.8]V 10 mV

LDR(2) Load regulation IOUT: [0.1; 600] mA 10 mV

IOUT Out put cu rrent 600 mA

PEFF Power efficiency VBAT = 3.6 V,

VIO = 1.8 V

IOUT= 100 mA 90 %

ISHORT Sh ort circuit

current limitation(2) 0.9 1.2 1.4 A

IQQuiescent current IOUT = 0 mA 130 250 µA

PSRR(2) Power supply

rejection Vpp = 0.3 V

[0; 20] kHz 40 dB

LIRT Transient line

regulation ΔVBAT = 300 mV

tR = tF = 10 µs 7mV

LDRT Transient load

regulation IOUT= [1; 600] mA

tR = tF = 100 ns 70 mV

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VIO_VMEM regulator in sleep mode (SLEEP=’1’)

VBAT Input power supply Battery vol tag e 2.7 3.6 4.8 V

VRIPPLE Output ripple 10 mVpp

LIR Line regulati on VBAT: [2.7; 4.8]V 10 mV

LDR Load regulati on IOUT: [0.1; 5] mA 10 mV

IOUT Out put cu rrent 5mA

PEFF Power efficiency VBAT = 3.6 V

IOUT = [0.1; 5] mA 85 %

IQQuiescent current IOUT = 0 mA 15 µA

LIRT Transient line

regulation ΔVBAT = 300 mV

tR = tF = 10 µs 7mV

1. Including output voltage temperature coefficient, DC line and load regulations, voltage reference accuracy,

industrial manufacturing tolerances and ripple voltage due to switching

2. Guaranteed by design

Table 39. VIO_VMEM DC/DC step-down converter (continued)

Symbol Description Test conditions Min. Typ. Max. Units

Electrical and timing characteristics STw4810

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5.3.5 LDO regulators

VPLL

Table 40. LDO regulators - VPLL

Symbol Description Test conditions Min. Typ. Max. Units

VPLL regulator in normal mode / otherwise specified, VPLL = 1.8 V

VBAT Input power supply Battery vol tag e 2.7 3.6 4.8 V

VOUT Out put voltage

VPLL_SEL[1:0]

11 (default)

-3% 1.8

1.3

1.2

1.05

+3% V

IOUT Out put cu rrent 3.5 10 mA

ISHORT Short-circuit

limitation 95 130 165 mA

IQQuiescent current IOUT = 0 mA 30 40 µA

ILKG Power-down

current EN_VPLL = 0 1µA

PSRR(1)

1. Guaranteed by design

Power supply

rejection

Vpp = 0.3 V

f < 10 kHz

10 kHz < f

<100 kHz

45 dB

LIR Line regulati on VBAT: [2.7; 4.8]V 5mV

LDR Load regulati on IOUT: [0.1; 10] mA 10 mV

LIRT Transient line

regulation

ΔVBAT = 300 mV

tR = tF = 10 µs 1mV

LDRT Transient load

regulation IOUT = [0.1; 10] mA

tR = tF = 1 µs 1mV

En(1) Noise density at 1 KHz

BW = 100 Hz 250 nVrms

-------------

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VANA

VAUX

Table 41. LDO regulators - VANA

Symbol Description Test conditions Min. Typ. Max. Units

VANA regulator in normal mode

VBAT Input power supply Battery vol tag e 2.7 3.6 4.8 V

VOUT Out put voltage -5% 2.5 +5% V

IOUT Out put cu rrent 10 mA

ISHORT Short-circuit

limitation 39 51 64 mA

IQQuiescent current IOUT = 0 mA 30 µA

ILKG Power-down

current EN_VANA = 0 1µA

PSRR(1)

1. Guaranteed by design

Power supply

rejection Vpp = 0.3 V

f < 10 kHz 45 dB

LIR Line regulati on VBAT: [2.7; 4.8] V 5mV

LDR Load regulati on IOUT: [0.1; 10] mA 5mV

LIRT Transient line

regulation

ΔVBAT = 300 mV

tR = tF = 10 µs 3mV

LDRT Transient load

regulation IOUT = [0.1; 10] mA

tR = tF = 1 µs 15 mV

Table 42. LDO regulators - VAUX

Symbol Description Test conditions Min. Typ. Max. Units

VAUX regulator in normal mode (PDN_VAUX= 1, SLEEP= ‘0’)

VBAT Input power supply

VOUT = 1.5V 1.7 4.8 V

VOUT = 1.8/2.5 V 2.7 3.6 4.8 V

VOUT = 2.8 V 3 3.6 4.8

VOUT Out put voltage

VAUX_SEL[1:0]

00 (default)

-3% 1.5

1.8

2.5

2.8

+3% V

IOUT Out put cu rrent 150 mA

ISHORT Short-circuit

limitation 350 700 900 mA

IQQuiescent current IOUT = 0 mA 30 µA

ILKG Power-down

current PDN_VAUX = 0 1 µA

Electrical and timing characteristics STw4810

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PSRR(1) Power supply

rejection

VOUT=1.5 V

Vpp = 0.3 V

f < 10 kHz 32 dB

LIR Line regulati on VOUT=1.5 V

VBAT: [2.7; 4.8]V 5mV

LDR(1) Load regulation VOUT=1.5 V

IOUT= [0.1; 150] mA 10 mV

LIRT Transient line

regulation ΔVBAT = 300 mV

tR = tF = 10 µs 2mV

LDRT Transient load

regulation

IOUT = [10; 90%]

tR = tF = 1 µs 35 mV

tSSettling time 100 µs

VAUX regulator in sleep mode (PDN_VAUX= 1, SLEEP=’1’)

VBAT Input power supply

VOUT = 1.5V

VIO_VMEM supply 1.7 4.8 V

VOUT = 1.8/2.5 V 2.7 3.6 4.8 V

VOUT = 2.8 V 3 3.6 4.8

VOUT Out put voltage

VAUX_SEL[1:0]

00 (default)

-3% 1.5

1.8

2.5

2.8

+3% V

IOUT Out put cu rrent 500 µA

IQQuiescent current IOUT = 0 mA 15 µA

PSRR(1) Power supply

rejection

VOUT=1.5 V

Vpp = 0.3 V

f < 10 kHz 38 dB

LIR Line regulati on VOUT=1.5 V

VBAT: [2.7; 4.8]V 5mV

LDR Load regulati on VOUT=1.5 V

IOUT= [10; 90%] µA 10 mV

LIRT Transient line

regulation ΔVBAT = 300 mV

tR = tF = 10 µs 2mV

LDRT Transient load

regulation IOUT = [10; 90%] µA

tR = tF = 1 µs 35 mV

1. Guaranteed by design

Table 42. LDO regulators - VAUX (continued)

Symbol Description Test conditions Min. Typ. Max. Units

STw4810 Electrical and timing characteristics

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5.3.6 Power supply monitoring

This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM

drops below the threshold, the multimedia processor is reset.

5.4 Digital specifications

5.4.1 CMOS input/output static characteristics: I2C interface

Table 43. Power supply monitoring

Symbol Description Test conditions Min. Typ. Max. Units

Threshold

THCORE(1)

1. Guaranteed by design

Threshold VCORE -3% VCORE-

150 +3% mV

THVIO(1) Threshold

VIO_VMEM -3% 1.65 +3% V

Comparators

VBAT Suppl y vol tag e 2.7 3.6 4.8 V

tRES Response time 100 ns

HYFALL Hysteresis (input

voltage falling) 26 mV

HYRIS Hysteresis (input

voltage rising) +4 mV

Table 44. CMOS input/output static characteristics: I²C interface

Symbol Description Test conditions Min. Typ. Max. Units

I²C interface(1)

1. Vio is for VIO_VMEM

VIL Low level input

voltage 0.3*VIO V

VIH High level input

voltage 0.7*VIO V

IIL Low level input

current -1.0 1.0 µA

IIH High level input

current -1.0 1.0 µA

VOL Low level output

voltage

IOL = 3mA

(with open drain or

open colle cto r) 0.2*VIO V

VOH H i gh level output

voltage

IOL = 3mA

(with open drain or

open colle cto r) 0.8*VIO V

Electrical and timing characteristics STw4810

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5.4.2 CMOS input/output dynamic characteristics: I2C interface

Table 45. CMOS input/output dynamic characteristics: I²C interface

Symbol Description Min. Typ. Max. Units

I²C interface (

Figure 8

)

Fscl Clock frequency 400 Khz

thigh Clock pulse width high 600 ns

tlow Clock pulse width low 1300 ns

tr SDA, SCL, USBSDA, USBSCL r ise time 20+0.1*Cb (1)

1. Cb = total capacitance of one bus line in pF

300 ns

tf SDA, SCL, USBSDA, USBSCL fall time 20+0.1*Cb 300 ns

thd_sta Start condition hold time 600 ns

tsu_sta Start condition set up time 600 n s

thd_dat Data inpu t hol d time 0 ns

tsu_dat Data input set up time 250 ns

tsu_sto Stop condition set up time 600 ns

tbuf Bus free time 1300 ns

Cb Capacitive load for each bus line 400 pF

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5.4.3 CMOS input/output static characteristics: VIO level

USB and control I/Os

Table 46. VIO level: USB and control I/Os

Symbol Description Test conditions Min. Typ. Max. Units

SW_RESETn, VDDOK, PORN, PWREN, TCXO_EN, REQUEST_MC, CLK32K, CLK32K_IN,

USBOEN, USBVP, USBVM, USBRCV, USBINTn, MASTER_CLK

VIL(1)

1. Vio for VI O_VMEM

Low level input

voltage 0.3*Vio V

VIH High level input

voltage 0.7*Vio V

IIL Low level input

current -1.0 1.5 µA

IIH High level input

current -1.0 1.5 µA

CIN Input capacitance 10 pF

VOL Low level output

voltage IOL = 4 mA 0.2*Vio V

VOH H i gh level output

voltage IOL = 4 mA 0.8*Vio V

tOF Output fall time Capacitance 10pF 10 ns

tOR Output rise time Capacitance 10pF 10 ns

CI/O Driving capability 100 pF

Electrical and timing characteristics STw4810

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MMC Interface

Table 47. VIO level: MMC interface

Symbol Description Test conditions Min. Typ. Max. Units

MMC interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2,

MCDATA0DIR, MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1

VIL(1)

1. Vio for VI O_VMEM

Low level input

voltage 0.3*Vio V

VIH High level input

voltage 0.7*Vio V

IIL Low level input

current -1.0 1.5 µA

IIH High level input

current -1.0 1.5 µA

CIN Input capacitance 10 pF

VOL Low level output

voltage IOL = 15 mA 0.2*Vio V

VOH H i gh level output

voltage IOL =15 mA 0.8*Vio V

CI/O Driving capability

at 52 MHz 30 pF

STw4810 Electrical and timing characteristics

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5.4.4 CMOS input/output static characteristics: VBAT level

Table 48. CMOS input/output static characteristics: VBAT level

Symbol Description Test conditions Min. Typ. Max. Units

IT_WAKE_UP, PON, GPO1, GPO2

VIL Low level input

voltage PON 0.3*Vbat V

VIH High level input

voltage PON 0.7*Vbat V

IIL Low level input

current PON -1.0 1.5 µA

IIH High level input

current PON -1.0 1.5 µA

CIN Input capacitance 10 pF

VOL Low level output

voltage

IT_WAKE_UP,

GPO1, GPO2

IOL = 2mA 0.2*Vbat V

VOH H i gh level output

voltage

IT_WAKE_UP,

GPO1, GPO2

IOL = 2 mA 0.8*Vbat V

tOF Output fall time Capacitance 10pF 5 ns

tOR Output rise time Capacitance 10pF 50 ns

CI/O Driving capability 100 pF

Electrical and timing characteristics STw4810

62/78

5.4.5 CMOS input/output static characteristics: VMMC level

Table 49. CMOS input/output static characteristics VMMC level

Symbol Description Test conditions Min. Typ. Max. Units

DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT

VIL Low level input

voltage 0.3*VMMC

VIH High level input

voltage 0.7*VMMC

IIL Low level input

current -1.0 1.5 µA

IIH High level input

current -1.0 1.5 µA

CIN Input capacitance 10 pF

VOL Low level output

voltage IOL = 25 mA 0.2*VMMC

VOH H i gh level output

voltage IOL = 25 mA 0.8*VMMC

CI/O Driving capability 40 pF

STw4810 Electrical and timing characteristics

63/78

5.5 USB OTG transceiver

Table 50. USB OTG transceiver

Symbol Description Test conditions Min. Typ. Max. Units

UART mode

tRRise time CLOAD= [50;100] pF

[10; 90] % of

VOH-VOL

100 ns

tFFall time CLOAD= [50;100] pF

10......90% of

VOH-VOL

100 ns

tPLH Drive propagation

delay low => high CLOAD= [50;100] pF

50% of |VOH-VOL|100 ns

tPHL Drive propagation

delay high => low CLOAD= [50;100] pF

50% of |VOH-VOL|100 ns

USB full speed mode (DP & DN signals)

tRRise time

USBVP & USBVM :

- Trise & Tfall < 1 ns

- Skew < 0.66 ns

420ns

tFFall time 4 20 ns

DRFM Differential rise an fall

time matching 90 111 %

OSCV Output signal

crossover voltage 1.3 2 V

PDEL Propagation delay 18 ns

USB low speed mode (DP & DN signals)

tRRise time 75 300 ns

tFFall time 75 300 ns

DRFM Differential rise an fall

time matching 80 125 %

OSCV Output signal

crossover voltage 1.3 2 V

VBUS comparators

VBAT Input power supply Battery voltage 3.1 3.6 4.8 V

tRR Rising reacting time 1.7 µs

tFR Fall reacting time 2.1 µs

Threshold VBUS monitoring

VBval VBUS valid 4.4 4.5 4.6 V

VBses VBUS se ss ion v a lid 1.8 2 V

Electrical and timing characteristics STw4810

64/78

VBUS

RA_BUS_IN 40 100 kΩ

TA_VBUS_

RISE

VBUS = [0; 4.4] V ILOAD

= 100mA

External cap 10µF 100 ms

Data line pull-down resistance

RPD_DPDN 14 19 25 kΩ

Data line pull-up resistance

RPU_DP Bus idle

Bus driven 900

1425 1200

2300 1600

3100 Ω

RPU_DN Bus idle

Bus driven 900

1425 1200

2300 1600

3100 Ω

Pull-down on VBUS

RVBUS_PD 650 925 1200 Ω

Pull-up on VBUS

RVBUS_SRP 420 600 780 Ω

VID_GND ID_GND comparator

threshold 2.7 V < VBAT < 4.8 V 0.15*VBAT V

VID_HI (VBAT) Battery level 2.7 3.6 4.8 V

VID_FLOAT ID_FLOAT comparator

threshold 0.85*VBAT V

RPU_ID 70 100 130 kΩ

RPD_ID 10 kΩ

Carkit threshold detection

cR_INT Carkit interrupt

threshold 0.4 0.6 V

Transceiver

VOH_TXD_DAT TXD output high on DN ISOURCE = 500 µA 2.4 3.6 V

VOL_TXD_DAT TXD output low on DN ISINK = 2mA 0.4 V

VIH_RXD_DAT RXD input high on DP 2 V

VIL_RXD_DAT RXD input low on DP 0.8 V

Table 50. USB OTG transceiver (continued)

Symbol Description Test conditions Min. Typ. Max. Units

STw4810 Electrical and timing characteristics

65/78

Charge pump

VBAT Input power supply Battery voltage VUSB+0.1 3.6 4.8 V

VBUS Output vol tage Current load up to 100

mA 4.75 5 5.25 V

tSSettling time [0;4.8] V)

Ext. load: 100 mA +

External cap = 10µF 1.2 ms

IQ Qu ies c ent cu rrent No Load 2.7 mA

VRipple Amp litude outp ut rippl e

on VBUS Current load 8 mA

Current load 100mA 25

40 mV

IOUT Output current 100 mA

Eff Efficiency

VBAT = 3.0V

IOUT =100mA

VBAT= 3.6V.

IOUT = 8 mA.

VUSB regulator

VBAT(1) Input voltage Battery vol tag e:

VBAT min =

VOUT + 0.1V VUSB+0.1 3.6 5.5 V

VOUT Output voltage VBAT min=

VOUT + 0.1V 3.0 3.1 3.2 V

ISHORT Short circuit current

limitation 320 mA

IQQuies c ent cu rrent No load 70 µA

PSRR(2) Power supply rejection VBAT= VOUT+0.2V

f < 20 kHz 45 dB

NVOUT Output noise voltage VBAT= VOUT+0.2V

10Hz <f< 100kHz 100 µVrms

LIRT Transient line

regulation ΔVBAT = 300 mV

tR = tF = 10µs. 5mV

tSSettling time

OFF->ON IOUT = 0mA 25 µs

tDDischarge time

ON>OFF IOUT = 0mA 400 µs

1. From 4.8 V to 5.5 V, charge pump is “Off” and no OTG feature is provided

2. Guaranteed by design

Table 50. USB OTG transceiver (continued)

Symbol Description Test conditions Min. Typ. Max. Units

Electrical and timing characteristics STw4810

66/78

5.6 SD/MMC card interface

Table 51. SD/MMC card interface

Symbol Description Test conditions Min. Typ. Max. Units

VMMC regulator specifications (PDN_VMMC = 1)

VBAT Input voltage VOUT = 3 V

VOUT = 2.85 V

VOUT = 1.8 V

3.25

3.1

2.7 3.6 4.8 V

VOUT Out put voltage -3% 3

2.85

1.8 +3% V

IOUT Out put cu rrent 150 mA

ISHORT Sh ort circuit

current limitation 280 360 600 mA

IQ Quiescent current IOUT = 0 mA 30 µA

ILKG Power-down

current PDN_VMMC = 0 1 µA

PSRR(1) Power supply

rejection

IOUT = 150 mA

Vpp = 0.3 V

f < 20 kHz 45 dB

LIR(1) Line regulation VOUT=2.85 V

VBAT: [3.1; 4.8]V 5mV

LDR(1) Load regulation VOUT=2.85 V

IOUT= [1; 150] mA 10 mV

LIRT Transient line

regulation

VOUT=2.85 V

VBAT: 3.1 to 3.4V

tR = tF = 10 µs. 2mV

LDRT Transient load

regulation IOUT = [1; 150] mA

tR = tF = 1 µs 25 mV

tSSettling time

OFF->ON IOUT = 0 mA 100 µs

tDDischarge time

ON>OFF IOUT = 0 mA 1 ms

Bus line specifications

RA(2) Pull-up resistor To prevent bus

floating 1.5 MΩ

RB Pull-down resistor To prevent bus

floating 1.5 MΩ

fDT

Clock frequency

data transfert

mode With CL = 30pF 52 MHz

fID Clock frequency

identification mode With CL = 30pF 400 KHz

STw4810 Electrical and timing characteristics

67/78

TPHC Propagati on tim e

from Host to card

Figure 14

7ns

TPCH Propagati on tim e

from card to host

Figure 14

7ns

TSHC

Clock /data skew

time from host to

card

Figure 14

Refere nce is

CLKOUT +/- 0.5 ns

TSCH

Clock /data skew

time from card to

host

Figure 14

Refere nce is

MMCLK +/- 0.5 ns

TRRise time 3 ns

TFFall time 3 ns

C1LINE

Between

multimedia

processor &

STw4810

Bus line

capacitance

f < 52 Mhz 20(3) pF

C2LINE Between STw4810

& MMC card

Bus line

capacitance

f < 52 MHz 20 + 20(4) pF

1. Guaranteed by design

2. MMC interface pull up resistors are in EMIF06-HCM01F2 device (7 KΩ for CMD; 75 KΩ for Data wires)

3. 20 pF for equivalent board parasitic capacitance.

4. 20 pF for EMIF06 protection + 20 pF for board parasitic capacitance.

Table 51. SD/MMC card interface (continued)

Symbol Description Test conditions Min. Typ. Max. Units

Electrical and timing characteristics STw4810

68/78

Figure 14. Propagation and clock/data skew times

MCCLK

MCCMD

MCDATA[3:0]

MCFBCLK t

50%

2 ns

10%

90%

10%

90%

50%

PHC

CLKOUT

CMDOUT

DATAOUT[3:0]

LATCHCLK

PHC

MCCLK

MCCMD

MCDATA[3:0]

MCFBCLK

50%

2 ns

10%

90%

10%

90%

50%

PCH

CLKOUT

CMDOUT

DATAOUT[3:0]

LATCHCLK

PCH

MCDATA[3:0]

2 ns

10%

90%

SHC

MCCLK 50% CLKOUT

DATAOUT[3:0]

MCDATA[3:0]

2 ns

10%

90%

SCH

MCCLK

50%

CLKOUT

DATAOUT[3:0]

STw4810 Application information

69/78

6 Application information

6.1 Components list

Table 52. Components list

Name Typical

value Comments Function

C1 22µF

In the complete system application,

the sum of the capacitors connected

on each STw4810 ball must never be

less than 30% of the value indicated

in the typical value column of this

table. This includes all capacitor

parameters:

– production dispersion

– DC bias voltage applied

– temperature range of the complete

system application

– aging

VIO_VMEM output filter

C4 VCORE output filter

10µF

VBAT_VIOVMEM decoupling

C3 VBAT_ANA decoupling

C5 VBAT_VCORE decoupling

1µF

VPLL output filter

C7 VANA output filter

C8 VREF output filter

C10 VUSB output filter

C13 VAUX output filter

C9 470nF Flying capacitor for charge pump

C11 4.7µF VBUS output filter (tank charge pump capacitor)

C12 2.2µF VSD_MMC output filter

C13, C14,

C15, C16,

C17 1 µF Vbattery input voltage decoupling capacitors

L1 4.7µH See

Table 53

for recommended coils Coil VIOVMEM DC/DC

L2 Coil VCORE DC/DC

Table 53. Recommended coils

Supplier Part Number DCR (Ω)Irms

(1) (A)

1. Irms: 30% decrease of initial value

L x l x h (mm * mm * mm)

TDK

VLF3010AT-4R7MR70 0.28 0.7 2.8 * 2.6 * 1.0

VLF3012AT-4R7MR74 0.16 0.74 2.8 * 2.6 * 1.2

VLF4012AT-4R7M1R1 0.14 1.1 3.7 * 3.5 * 1.2

Coilcraft

DO1605T-472MX 0.15 1.1 5.5 * 4.2 * 1.8

DO3314-472ML 0.32 1.1 3.3 * 3.3 * 1.4

ME3320-472MX 0.19 1.1 3.2 * 2.5 * 2.0

Application information STw4810

70/78

Table 54. Other ST components

Name Order code Function

EMIF02 EMIF02USB05 USB ESD/EMI Protection

EMIF06 EMIF06-HMC01F2 MMC Interface ESD/EMI Protection

STw4810 Application information

71/78

6.2 Application schematics

Figure 15. STw4810 application schematics

VLX_VIOVMEM

USBVP

USBOEn

USBRCV

USBVM

MCCMDDIR

MCCMD

MCDAT0DIR

VUSB

SCL

SDA

PON

MCDAT0

MCCLK

VREF

LATCHCLK

DATOUT[3:1]

MCDAT31DIR

MCFBCLK

CMDOUT

MCDAT[3,1]

Multimedia processor

VCORE

PORn

CLK32K

PWREN

VDDOK

USB

VMINUS_VIOVMEM

VBAT_VIOVMEM

VIOVMEM_FB

VBAT_ANA

VMINUS_ANA

VBAT_VCORE

VLX_VCORE

VPLL

VANA

VBUS

ID ESD

EMI

filter

VMMC

MMC

SDIO

CLKOUT

Modem & system clock

CLK32Kin

MASTER_CLK

SW_RESETn

IT_WAKE_UP

C2 C3

C10

C11

C12

VBAT_MMC

VBAT_USB

VMINUS_USB

VBAT_VPLL_VANA

VMINUS_DIG

VBAT_DIG

DATAOUT0

VAUX

VBAT_VAUX C13

VMINUS_VCORE

USBINTn

REQUEST_MC

TCXO_EN

EMI

Filter

USBSCL

USBSDA

GPO1

GPO2

EMIF02

EMIF06-HMC01F2

MCDAT2DIR

MCDAT2

STw4810

CARD

C13(*)

C14(*)

C15(*)

C16(*)

C17(*)

(*) The usefulness of these capacitors depend of PCB layout

Package mechanical data STw4810

72/78

7 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST tradem ark.

ECOPACK specifications are available at: www.st.com.

7.1 TFBGA 84 balls

See

Figure 16: TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing

Table 55. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions(1)

1. These measurements conform to JEDEC standards

Drawing dimensions (mm) Min. Typ. Max.

A1.16

A1 0.20 0.25 0.30

A2 0.82

b 0.250.300.35

D 5.906.006.10

D1 4.50

E 5.906.006.10

E1 4.50

e 0.450.500.55

f 0.650.750.85

ddd 0.08

STw4810 Package mechanical data

73/78

Figure 16. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing

Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink

or metallized markings, or other feature of package body or integral heatslug. A

distinguishing feature is allowable on the bottom surface of the package to identify the

terminal A1 corner. Exact shape of each corner is optional.

Package mechanical data STw4810

74/78

7.2 VFBGA 84 balls

See

Figure 17: VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing

Table 56. VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch(1)

1. These measurements conform to JEDEC standards

Drawing dimensions (mm) Min. Typ. Max.

A0.864

A1 0.15 0.19 0.23

A2 0.615

A3 0.18

A4 0.435

b 0.210.250.29

D 4.554.604.65

D1 3.60

E 4.554.604.65

E1 3.60

e0.40

f0.50

ddd 0.08

eee 0.13

fff 0.04

STw4810 Package mechanical data

75/78

Figure 17. VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing

Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink

or metallized markings, or other feature of package body or integral heatslug. A

distinguishing feature is allowable on the bottom surface of the package to identify the

terminal A1 corner. Exact shape of each corner is optional.

Ordering information STw4810

76/78

8 Ordering information

Table 57. Order codes

Part number Package Packing

STw4810CHDR/LF TFBGA84- 6x 6 x 1.2 mm / 0.5 mm pitch Tray

STw4810CHDT/LF TFBGA84- 6x 6 x 1.2 mm / 0.5 mm pitch Tape and reel

STw4810CRAE/LF VFBGA 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch Tray

STw4810CRAT/LF VFBGA 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch Tape and reel

STw4810 Revision history

77/78

9 Revision history

Table 58. Document revision history

Date Revision Changes

24-Jan-2006 1Initial release.

07-Feb-2006 2

Modified document title.

Reviewed list of applications on cover page.

Replaced APE with multimedia processor.

Replaced fuse with analogue function.

Rename d VFUSE as VANA.

Modified figure 6 - Control interface - I2C format

09-Feb-2006 3 Correction of

Figure 13: SD MMC block diagram

Correction of

Figure 15: STw4810 application schematics

10-Mar-2006 4

Correction in

Section 4.2.3: Sleep mode on page 18

Removed formula and some text about sleep mode.

Table 26: Power control register at address 09h on page 31

Replaced bit 2 and 1 with “not used” and “reserved”.

25-Jul-2006 5

Update short circuit current limit in

Table 38: VCORE DC/DC step-

down converter

Table 39: VIO_VMEM DC/DC step-down converter

Updated short circuit minimum value in

Table 42: LDO regulators -

VAUX

and

Table 51: SD/MMC card interface

30-Nov-2006 Updated the ordering information.

15-Mar-2007 6 Co rrected VBAT maximum value in

Ta ble 36: Operating conditions

(Temp range: -30 to +85 °C)

23-Apr-2007 7 Updated

Figure 3: Start-up timing

and replaced all TBD references

with val ues in

Table 46

Table 47

Table 48

Table 49

Replaced ESD performance with VESD in

Table 34

08-Jun-2007 8 Updated the minimum ESD CDM value and removed the maximum

junction tempera ture an d maximu m po wer di ssipatio n temper ature in

Table 34: STw4810 absolute maximum ratings

03-Sep-2007 9 Updated

Section 4.3.9: T hermal shut-down

STw4810

78/78

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