34 .807IRELESS IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page "(c) STMicroelectronics 200x - All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.st.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices is found at http://www.stnwireless.com under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless 34 .807IRELESS www.stnwireless.com STw4810 Power management for multimedia processors Features 2 Step-down converters - 1 to 1.5V with 15 steps at 600mA - 1.8V at 600mA for general purpose usage 3 Low-drop output regulators for different uses - PLL analog supplies: 1.05V, 1.2V, 1.3V 1.8V - 10mA - Processor analogue functions: 2.5V - 10mA - Auxiliary device: 1.5V, 1.8V, 2.5V, 2.8V - 150 mA USB OTG module - Full and low speed USB OTG transceiver - Charge-pump (5V, 100mA) for USB cable Mass memory cards (SD/MMC/SDIO) - 1 linear regulator: 1.8V, 2.85V, 3V - 150mA - Level shifter Miscellaneous - 32 kHz control for multimedia processor - Processor supply monitoring - Processor reset control - 2 Serial I2C interfaces STw4810CHD TFBGA 84 6x6x1.2mm 0.5mm pitch STw4810CRA VFBGA 84 4.6x4.6x1.0mm 0.4mm pitch Description STw4810 is a power management companion chip for multimedia processors used in portable applications. It supplies the multimedia processor including its memories and peripherals. STw4810 supports the main mass memory standard cards. SDIOTM is also supported and allows to connect multimedia peripherals like cameras. Application ST NOMADIKTM STn88xx Multimedia processor Mobile phones, PDA, videophone September 2007 Rev 9 1/78 www.st.com 1 Contents STw4810 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Ball information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 3.1 Ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 Digital control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 4.4 4.5 2/78 4.2.1 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.2 POWER OFF / VDDOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.5 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 IT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.2.7 Clock switching and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.1 Bandgap, biasing and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.2 VCORE regulator: DC/DC step-down regulator . . . . . . . . . . . . . . . . . . . 35 4.3.3 VIO_VMEM regulator: DC/DC step- down regulator . . . . . . . . . . . . . . . 35 4.3.4 VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.5 VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.3.6 VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.7 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.8 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.3.9 Thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 USB OTG module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4.2 Modes and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.3 USB enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SD/MMC/SDIO module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 STw4810 5 Contents Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.4 6 7 5.3.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.2 VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.3 VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.4 VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.5 LDO regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.6 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.4.1 CMOS input/output static characteristics: I2C interface . . . . . . . . . . . . . 57 5.4.2 CMOS input/output dynamic characteristics: I2C interface . . . . . . . . . . 58 5.4.3 CMOS input/output static characteristics: VIO level . . . . . . . . . . . . . . . 59 5.4.4 CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . 61 5.4.5 CMOS input/output static characteristics: VMMC level . . . . . . . . . . . . . 62 5.5 USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.6 SD/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.2 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.1 TFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.2 VFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3/78 List of tables STw4810 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 4/78 STw4810 ball connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STw4810 balls function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register general information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 USB register address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Vendor ID and Product ID: Read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 USB control register 1 (address = 04h set and 05h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 23 USB control register 2 (Address = 06h set and 07h clearh) . . . . . . . . . . . . . . . . . . . . . . . . 24 USB Interrupt source register (address = 08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 USB interrupt latch registers (address = 0Ah set and 0Bh clearh) . . . . . . . . . . . . . . . . . . . 25 USB interrupt mask false register (address = 0Ch and 0Dh) . . . . . . . . . . . . . . . . . . . . . . . 26 USB interrupt mask true register (address = 0Eh and 0Fh) . . . . . . . . . . . . . . . . . . . . . . . . 26 USB EN register (address = 10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SD MMC control register (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power control register - General information (Address = 1Eh) . . . . . . . . . . . . . . . . . . . . . . 28 Power control register - General information (Address = 1Fh) . . . . . . . . . . . . . . . . . . . . . . 28 Power control register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power control register at address 05h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power control register at address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power control register at address 07h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power control register at address 08h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power control register at address 09h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power control register at address 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Twarning register (Address = 20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0 . . . . . . . . 42 Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1 . . . . . . . . 42 Data receiver via USB control register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STw4810 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Operating conditions (Temp range: -30 to +85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VREF18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 VCORE DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 VIO_VMEM DC/DC step-down converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 LDO regulators - VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LDO regulators - VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LDO regulators - VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CMOS input/output static characteristics: IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CMOS input/output dynamic characteristics: IC interface . . . . . . . . . . . . . . . . . . . . . . . . . 58 VIO level: USB and control I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 VIO level: MMC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 STw4810 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 55. Table 56. Table 57. Table 58. CMOS input/output static characteristics VMMC level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SD/MMC card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Recommended coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions . . . . . . . . . . . . . . . . . . 72 VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch . . . . . . . . . . . . . . . . . . . . 74 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5/78 List of figures STw4810 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. 6/78 Typical mobile multimedia system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STw4810 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Switching POWER to sleep timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VDDOK block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control interface: I2C format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control interface: I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clock switching between master and internal clock (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Block diagram of biasing and references of the device . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Thermal threshold temperatures for `it_warn' bit and VDDOK ball . . . . . . . . . . . . . . . . . . . 38 USB OTG transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SD MMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Propagation and clock/data skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 STw4810 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing . . . . . . . . . . . . . . . . . . . . . 73 VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 STw4810 1 Overview Overview The STw4810 power management device has the following features: Power management module - 1 Step-down converter for processor core (1 to 1.5 V with 15 steps at 600 mA) - 1 Step-down converter (1.8 V at 600 mA) for general purpose usage such as processor input/output supply, external memory, DDR and SDRAM and peripherals - 1 Low-drop output regulator for analog supplies, such as PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V at 10 mA) - 1 Low-drop output regulator for processor analogue functions (2.5 V at 10 mA) - 1 Low-drop output regulator for auxiliary devices (1.5 V, 1.8 V, 2.5 V, 2.8 V at 150 mA) USB OTG module - Full and low speed USB OTG transceiver - 1 Linear regulators (3.1 V at 40 mA) supplying transceiver - 1 Charge-pump (5 V at 100 mA) supplying VBUS line of the USB cable Mass memory cards (SD/MMC/SDIO) - 1 Linear regulator (1.8 V, 2.85 V, 3 V at 150 mA) - Level shifter Miscellaneous - 32 kHz control for multimedia processor - Processor supply monitoring - Processor reset control - 2 Serial I2C interfaces Figure 1. Typical mobile multimedia system 7/78 CLK32K_IN CLK32K 1V=>1.5V- 600mA MASTER_CLK 1.8V- 600mA VMINUS_DIG Internal oscillator clock switching and control VBAT_ANA VMINUS_ANA SOFT_START VREF_VIO_VMEM GPO1 BG VREF_VCORE VREF_VPLL VREF_VAUX GPO2 USBINTn SDA SCL Buffer VREF_18 BIAS Control registers VBAT_VPLL_ANA Thermal shutdown TCXO_EN REQUEST_MC PON VDDOK PORn PWREN SW_RESETn VCORE VIO_VMEM VBAT_DIG VMINUS_VCORE STw4810 block diagram VMINUS_VIO_VMEM Figure 2. VLX_VIO_VMEM Functional block diagram VBAT_VIO_VMEM 2 VLX_VCORE STw4810 VBAT_VCORE Functional block diagram VPLL_LDO 1.05V,1.2V,1.3V,1.8V, 10mA Monitoring VPLL VANA_LDO 2.5V, 10mA General PORn_VBAT control VANA VBAT_VAUX VAUX_LDO 1.5V,1.8V2.5V,2.8V, 150mA I2C interface VAUX VBAT_USB USB OTG transceiver interface USBSDA USBSCL I2C Mux USB control Control Charge pump 5V - 100mA CP CN VBUS 3.1V - 40mA VUSB IT_WAKE_UP SD/MMC/ SDIO control USBOEn USBVP USBVM USBRCV VMINUS_USB MCCMDDIR MCDAT0DIR MCDAT2DIR MCDAT31DIR MCCLK MCFBCLK MCCMD MCDATA0 MCDATA[3:1] 8/78 Driver Level shifter ID Pull up & down DP DN VBAT_MMC SD/ MMC/SDIO interface 1.8/2.85/3V-150mA Level shifter Driver VMMC LATCHCLK CLKOUT CMDOUT DATAOUT0 DATAOUT[3:1] STw4810 Ball information 3 Ball information 3.1 Ball connections Table 1. STw4810 ball connections 1 2 6 7 8 9 10 CLK32K_IN VMINUS_ VIO_VMEM VAUX VANA VPLL VREF_18 VCORE B "Reserved" REQUEST_ VMINUS_ VBAT_VIO_ MC VIO_VMEM VMEM VMINUS_ ANA VBAT_ VAUX "Reserved" "Reserved" "Reserved" VMINUS_ VCORE C TCXO_EN IT_WAKE_ UP VMINUS_ DIG "Reserved" VBAT_ANA VBAT_ VPLL_ANA PON VMINUS_ VCORE VLX_ VCORE D VBAT_DIG MASTER_ CLK "reserved" VLX_ VCORE VBAT_ VCORE VBAT_ VCORE E DATAOUT0 DATAOUT <1> DATAOUT <2> ID DP DN F DATAOUT <3> CMDOUT LATCHCLK "Reserved" VBAT_USB VUSB G CLKOUT MCCLK MCCMD DIR "Reserved" USBSCL VBUS H MCCMD MCDATA <3> MCDATA <1> MCDATA31 DIR MCFBCLK PWREN SDA USBINTn USBSDA CP J MCDATA <2> VDDOK PORN VBAT_ MMC GPO1 SCL USBVP USBVM VMINUS_ USB CN K MCDATA0 MCDAT0 DIR CLK32K SW_ RESET VMMC GPO2 USBRCV USBOEn MCDAT2 DIR "Reserved" A 3.2 3 VLX_VIO_ VMEM 4 5 VBAT_VIO_ VIO_VMEM VMEM VLX_VIO_ VMEM Ball functions STw4810 includes the following ball types VDDD/VDDA: digital/analog power supply VSSD/VSSA: digital/analog ground supply DO/DI/DIO: Digital Output / Digital Input / Digital Input Output DOz: Digital Output with high impedance capability AO/AI/AIO: Analog Output / Analog Input / Analog Input-Output G: to be connected to ground O: to be left open Int-Ref: Associated to internal reference Table 2 details the ballout. 9/78 Ball information Table 2. STw4810 STw4810 balls function Ball Ball name Ball type Description General supplies D1 VBAT_DIG VDDD-VBAT Battery supply for digital/oscillator C3 VMINUS_DIG VSSD Ground for digital and oscillator C6 VBAT_ANA VDDA-VBAT Battery supply for analog B5 VMINUS_ANA VSSA Ground for analog F9 VBAT_USB VDDA-VBAT Battery supply for USB block J9 VMINUS_USB VSSA Ground for USB block A9 VREF_18 Int-Ref Internal reference Control balls C8 PON DI(VBAT) Pull Down 1.5M Power-on and reset K4 SW_RESETn DI(VIO_VMEM) Pull Up 1.5M Software reset, reset all applications when SW_RESETn = 0 J2 VDDOK DO(VIO_VMEM) Supply monitoring for multimedia processors. Interruption for high temperature warning J3 PORn DO(VIO_VMEM) Multimedia processor Resetn H6 PWREN DI(VIO_VMEM) Pull Up 1.5M Sleep mode from multimedia processor C1 TCXO_EN DI(VIO_VMEM) Pull Down 1.5M Request of master clock from modem part B2 REQUEST_MC DO(VIO_VMEM) Request to master clock oscillator J6 SCL DI(VIO_VMEM) Clock for Main I2C interface H7 SDA DIO(VIO_VMEM) SDA for Main I2C interface D2 MASTER_CLK AI Pull Down 1.5M 26 MHz, 13 MHz or 19.2 MHz from modem A1 CLK32K_IN DI(VIO_VMEM) Pull Down 1.5M 32 kHz input K3 CLK32K DO(VIO_VMEM) 32 kHz to multimedia processor 10/78 STw4810 Table 2. Ball information STw4810 balls function (continued) Ball Ball name Ball type Description Regulator balls A4 B4 VBAT_VIO_VMEM VDDA-VBAT Battery power supply for step down VIO_VMEM A2 B3 VMINUS_VIO_VMEM VSSA Ground for step down VIO_VMEM A3 C4 VLX_VIO_VMEM AIO BUCK of step down VIO_VMEM A5 VIO_VMEM AI VIO_VMEM Feed back input D9 D10 VBAT_VCORE VDDA-VBAT Battery power supply for step down VCORE B10 C9 VMINUS_VCORE VSSA Ground for step down VCORE C10 D8 VLX_VCORE AIO BUCK of step-down VCORE A10 VCORE AI VCORE sense C7 VBAT_VPLL_ANA VDDA-VBAT Battery supply for VPLL, VANA A7 VANA AO VANA output A8 VPLL AO VPLL output A6 VAUX AO VAUX output B6 VBAT_VAUX VDDA-VBAT Battery supply for VAUX C2 IT_WAKE_UP DO(VBAT-DIG) Interrupt to modem for wake-up due to USB plug K8 USBOEn DIO(VIO_VMEM) Pull Down 1.5M Output enable of the differential driver in the USB mode J7 USBVP DIO(VIO_VMEM) Pull Down 1.5M Data input in the USB transmit mode, positive data input the single-ended transmit mode, or TXD in UART mode J8 USBVM DIO(VIO_VMEM) Pull Down 1.5M Single-ended zero input in the USB transmit mode, negative data input in the single-ended transmit mode, or RXD in the UART mode K7 USBRCV DO(VIO_VMEM) Differential receiver output E9 DP AIO(VUSB) Positive data line in the USB mode, or serial data input in the UART mode E10 DN AIO(VUSB) Negative data line in the USB mode, or serial data output in the UART mode. E8 ID AI(VBAT-USB) ID ball of the USB detector used for protocol identification. H10 CP AIO(VBUS) C plus flying capacitor (VBUS level 4.4 to 5.25) USB balls 11/78 Ball information Table 2. STw4810 STw4810 balls function (continued) Ball Ball name Ball type Description J10 CN AIO(VBUS) C minus flying capacitor (VBUS Level) G10 VBUS AIO(VBUS) USB cable supply (VBUS Level) F10 VUSB AIO Decoupling capacitor for USB internal regulator G9 USBSCL DI(VIO_VMEM) Clock for dedicated USB I2C H9 USBSDA DIO(VIO_VMEM) SDA for dedicated USB I2C H8 USBINTn DO(VIO_VMEM) Interrupt to multimedia processor for USB or accessory plug SD MMC balls G3 MCCMDDIR DI(VIO_VMEM) Pull Down 1.5M CMD direction. - "high": CMD signal from processor to card - "Low": CMD signal from card to processor K2 MCDAT0DIR DI(VIO_VMEM) Pull Down 1.5M DATA0 direction - "high": DATA0 signal from processor to card - "Low": DATA0 signal from card to processor K9 MCDAT2DIR DI(VIO_VMEM) Pull Down 1.5M DATA2 direction - "high": DATA2 signal from processor to card - "Low": DATA2 signal from card to processor H4 MCDAT31DIR DI(VIO_VMEM) Pull Down 1.5M DATA(3,1) direction - "high": DATA(3,1) signal from processor to card - "Low": DATA(3,1) signal from card to processor G2 MCCLK DI(VIO_VMEM) Pull Down 1.5M Host clock, between processor and STw4810, to the card (processor clock). H5 MCFBCLK DO(VIO_VMEM) Host feedback clock between STw4810 and processor, to re-synchronize data in processor. H1 MCCMD DIO(VIO_VMEM) Pull Up 1.5M Bidirectional command/response signal between processor and STw4810. K1 MCDATA0 DIO(VIO_VMEM) Pull Up1.5M Bidirectional data0 between processor and STw4810 H2 H3 J1 MCDATA[3:1] DIO(VIO_VMEM) Pull Up 1.5M Bidirectional data [3:1] between processor and STw4810. F3 LATCHCLK DI(VMMC) Pull Down 1.5M Host feedback clock to STw4810, to resynchronize data in processor. G1 CLKOUT DO(VMMC) Host clock, between STw4810 and card (processor clock). F2 CMDOUT DIO(VMMC) Pull Up 1.5M Bidirectional command/response signal between STw4810 and processor. E1 DATAOUT0 DIO(VMMC) Pull Up 1.5M Bidirectional data0 between STw4810 and card 12/78 STw4810 Table 2. Ball information STw4810 balls function (continued) Ball Ball name Ball type Description F1 E3 E2 DATAOUT[3:1] DIO(VMMC) Pull Up 1.5M Bidirectional data[3:1] between STw4810 and card. J4 VBAT_MMC VDDA-VBAT Battery supply for VMMC K5 VMMC AIO VMMC supply output J5 GPO1 AO General purpose output K6 GPO2 AO General purpose output B9 D3 "Reserved" G To be connected to ground B1 B7 B8 C5 F8 G8 K10 "Reserved" O To be left open Other balls 13/78 Functional description 4 Functional description 4.1 Introduction STw4810 The STw4810 integrates all the power supplies for a multimedia processor as well as memories and peripherals: 4.2 Two switched mode power supply regulators: one for the multimedia processor core, one for multimedia processor I/Os and memories Three low-drop output regulators for multimedia processor analog supplies (PLL and others) and auxiliary components USB OTG FS/LS physical interface MMC card power supplies and level shifters Multimedia processor supply monitoring / power-on reset and power supply alarms / interrupt management Two serial I2C communication interfaces; one to control the devices (SDA, SCL) and one to control the USB (USBSDA, USBSCL). Digital control module This module describes the interfaces used to program the device and the related registers. 4.2.1 State machine Description of each states: (Figure 3.) Off: In this mode the STw4810 is switched off. Off is when PON=0, when battery level is under 2.4 V or when thermal shutdown is activated. There is no multimedia processor power supply. The only active cell is the USB cable detection and VBAT level detection. OSC_START: Oscillator is enabled and the power up module is waiting for the rising edge of the internal signal OSC_OK to start power up sequence. This state duration is 300 s. START_BIAS: Bias, reference and thermal shut-down are enabled, a counter is activated to wait for rising edge of internal signals PDN_regulators. This state duration has a typical value of 7.77 ms and a worst case value of 9.46 ms. START_PM: after a 1 ms wait, multimedia processor power supplies are available (VIO_VMEM, VCORE, VPLL, and VANA). The device can allow I2C communication, output power supply monitoring and application (USB,SD/MMC). OFF2: STw4810 is waiting for the 32 kHz multimedia processor signal. This state has an indeterminate duration. If 32kHz is present during the states describes above, it has no effect. The 32 kHz signal is taken into account by STw4810 only when the `VDDOK' ball is high, that is at the end of START_PM state. Reset: STw4810 forces a reset during 10*32 kHz period before setting PORn high. INT_OSC: The STw4810 can work without MASTER_CLK via its internal oscillator. The device waits for an external clock detection before switching to the external clock. When receiving a rising edge on PWREN ball (coming from multimedia processor) or on TCXO_EN ball (coming from modem), STw4810 answers by asserting to "1" the 14/78 STw4810 Functional description REQUEST_MC ball. STw4810 remains in internal oscillator mode until it receives the external clock signal on MASTER_CLK ball. EXT_CLK: When MASTER_CLK is detected, the STw4810 uses this clock as reference and switches off its internal oscillator to save quiescent. MASTERCLK should remain connected up to sleep mode. Sleep: Sleep mode is required by multimedia processor by setting a PWREN at low level. Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and wait for PWREN at high level (Figure 4). Wake-up: From sleep mode, the multimedia processor requests to switch back to Normal mode. Thus the device restarts its internal oscillator and then switches regulators from sleep to normal mode and informs multimedia processor with VDDOK at high level (Figure 4). Note: By default VAUX is in stand by mode, pdn_vaux = 0 (Table 18). It can be programmed in normal mode only by asserted pdn_vaux bit to "1". 15/78 Functional description Figure 3. STw4810 Start-up timing OFF VBAT PON ball 9.38ms (11ms wc) 300s PDN__OSC START_BIAS START_PM 7.77ms (9.46ms wc) PDN_regulators 1ms VDDOK ball 11*(1/32kHz) CLK32K_IN ball (*) Reset PORn ball PWREN unmasked PWREN ball Internal_OSC MASTER_CLK ball TCXO_EN ball "or" REQUEST_MC ball OFF2 Reset INT_OSC VPLL / VIO_VMEM VCORE Voutput(s) ball CLK32K ball Delays are worst case maximum delays (*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null All regulators are started with PDN_regulators but can be switched off from the beginning or during application by software (Table 27) 16/78 STw4810 Functional description Figure 4. Switching POWER to sleep timing HPM PWREN HPM SLEEP ~100s Sleep regulators VDDOK PDN_regulators CLK32K PDN_intOSC int_OSC_detect REQUEST_MC Internal_OSC MASTER_CLK Registers reset In the event of a hardware reset coming from the modem, PON ball set to "0", all registers are reset at initial value when PON ball goes back to "1" level. A software reset from multimedia processor of STw4810, through SW_RESETn ball set to "0", reset all registers except power control register (at address 1E & 1F). Main clock oscillator control REQUEST_MC is an OR output gate between PWREN (coming from multimedia processor) and TCXO_EN (coming from modem supply), it is synchronized on 32 kHz, except during power-up where PWREN is masked and considered as high. REQUEST_MC enabled or disabled the master clock oscillator device. 17/78 Functional description 4.2.2 STw4810 POWER OFF / VDDOK In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM detected, or `it_twarn' bit set to "1" (Table 18), then multimedia processor is reset (PORn low during a minimum time of 312.5 s) and restarted with no time-out. (see Figure 5). In case of VDDOK falling edge because PWREN balls equals "0", there is no reset (PORn still high). In case of PON falling edge (STw4810 switched off from modem) multimedia processor is also reset with no time-out. We consider that clean switch off between modem and multimedia processor is done by software directly. Figure 5. PWREN VDDOK block diagram vcore_monitor vio_monitor Digital block & & VDDOK it_twarn mask_twarn register reset after read operation or PON falling edge or PORN_VBAT. Reg status Under voltage detection VDDOK Operating voltage threshold value reached PORn 312.5 s (10* 32 Khz) 4.2.3 Sleep mode STw4810 goes into sleep mode by different ways. Whether VCORE, VIO_VMEM and VAUX are programmed to sleep mode or not is indicated in Table 27. 18/78 STw4810 I2C Interface The device supports two I2C bus interfaces. One main interface (SDA,SCL) controls power management and all programmable functions, the second interface (USBSDA, USBSCL) is dedicated to USB control. STw4810 allows to work with only the main I2C interface to control all the functions, including the USB, via USB_I2C_CTRL bit of power control register (Table 27). I2C Interface is used to read status information from inside the device. Flags, interrupt and write registers are used to configure the device functions (threshold, clock division, output voltage, etc....). By default, the main I2C interface (SCL,SDA) controls the main registers and USB I2C interface (USBSCL, USBSDA) controls USB registers. Figure 6. I2C interface block diagram SCL SDA usb_i2c_ctrl Main registers SCL SDA USBSCL MUX 4.2.4 Functional description USBSDA SCL or USBSCL SDA or USBSDA USB registers Both I2C are configured as slave serial interface compatible with I2C registered trademark of Phillips Inc. (version 2.1). I2C interface description STw4810 I2C is a slave serial interface with a serial data line (SDA or USBSDA) and a serial clock line (SCL or USBSCL): - SCL / USBSCL: input clock used to shift data - SDA / USBSDA: input/output bidirectional data transfers It is composed of: - One filter to reject spikes on the bus data line and preserve data integrity - Bidirectional data transfers up to 400kbit/s (Fast-mode) via SDA or USBSDA signal The SDA or USBSDA signal contains the input/output control and data signals that are shifted in the device, MSB first. The first bit must be high (START) followed by the Device ID (7 bits) and Read/Write bit control (1 indicates read access, a logical 0 indicates a write access). - Device ID in write mode: 5Ah (01011010) - Device ID in read mode: 5Bh (01011011) Then STw4810 sends an acknowledge at the end of an 8 bits transfer. The next 8 bits correspond to the register address followed by another acknowledge. The 8 bits data field is sent last, followed by a last acknowledge. 19/78 Functional description Table 3. STw4810 Device ID b7 b6 b5 b4 b3 b2 b1 b0 AdrID6 AdrID5 AdrID4 AdrID3 AdrID2 AdrID1 AdrID0 R/W Table 4. Register address b7 b6 b5 b4 b3 b2 b1 b0 RegADR7 RegADR6 RegADR5 RegADR4 RegADR3 RegADR2 RegADR1 RegADR0 Table 5. Register data b7 b6 b5 b4 b3 b2 b1 b0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 I2C interface modes Figure 7. Control interface: I2C format DEVICE ADDRESS WRITE SINGLE BYTE ACK ACK REGn ADDRESS REGn Data In ACK 01011010 START RANDOM ADDR READ SINGLE BYTE STOP DEVICE ADDRESS ACK ACK REGn ADDRESS DEVICE ADDRESS 01011010 ACK REGn Data Out NO ACK 01011011 START START RANDOM ADDR READ MULTI BYTE ACK ACK REGn ADDRESS DEVICE ADDRESS ACK DEVICE ADDRESS 01011010 01011011 START ACK ACK Reg n Data Out NO ACK Reg n + m Data Out STOP START m+1 data bytes Figure 8. Control interface: I2C timing tbuf SDA USBSDA tsu_sta thd_sta tf SCL USBSCL tlow Stop 20/78 Start thd_dat tr tsu_dat tsu_sto thd_sta thigh Start repeated Stop STw4810 4.2.5 Functional description Control registers Control registers have the following functions: Table 6. - Select level of regulation for multimedia processor supply - Control the USB interface - Control the SD/MMC/SDIO interface - Control the state machine Register general information Address Comment I2C control USB Registers (Table 9 to Table 17) USBSDA / USBSCL or SDA / SCL (1) 11h SD MMC Control register (Table 18) SDA / SCL 12h to 1Dh Test registers 1Eh to 1Fh Power control registers (Table 19 to Table 27) SDA / SCL 20h twarning register (Table 28) SDA / SCL 00h to 10h 1. Controlled by USB_I2C_CTRL bit of Power control register (Table 27) Table 7. Register summary Register Addr. 7 6 5 4 3 2 1 0 00h 1 0 0 0 0 0 1 1 01h 0 0 0 0 0 1 0 0 02h 0 0 0 1 0 0 0 0 03h 0 1 0 0 0 0 0 0 Vendor ID Product ID USB control register 1 04h 05h Not used uart_en oe_int_ en bdis_ not used dat_se0 acon_en USB control register 2 06h 07h vbus_ chrg vbus_ dischrg vbus_ drv id_gnd dn_ dp_ dn_ pulldown pulldown pullup USB interrupt source 08h cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld USB interrupt latch 0Ah 0Bh cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld USB interrupt mask false 0Ch 0Dh cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld USB interrupt mask true 0Eh 0Fh cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vld vbus_vld USB EN 10h Not used SD MMC control 11h pdn_ vaux Twarning 20h Not used suspend speed usb_en it_warn monitori ng_vio_ vmem_ vcore gpo2 gpo1 sel_vmmc<1:0> dp_ pullup not used pdn_ vmmc mask_ twarn 21/78 Functional description Table 8. STw4810 Power control register Register Power control Addr. 15 14 13 1Fh Register Power control 12 11 10 Not used Addr. 1 Eh 7 6 5 9 8 reg address 2 bits 4 reg address 3 bits 3 2 1 data din/dout 4 bits 0 ena write Registers controlled by I2C USB bus The registers described in this chapter are controlled through the USB serial I2C interface, USBSCL and USBSDA balls. These registers could also be controlled through the main I2C interface, SCL and SDA balls by setting to "1" USB-I2C_CTRL bit in Power control register (Table 23). Table 9. USB register address Address Note: 22/78 Register Type 00h - 01h Vendor ID R 02h - 03h Product ID R 04h set USB Control Register 1 R/W 05h clearh USB Control Register 1 R/W 06h set USB Control Register 2 R/W 07h clearh USB Control Register 2 R/W 08h USB Interrupt Source R 09h Not used 0Ah set USB Interrupt Latch R/W 0Bh clearh USB Interrupt Latch R/W 0Ch set USB Interrupt Mask False R/W 0Dh clearh USB Interrupt Mask False R/W 0Eh set USB Interrupt Mask True R/W 0Fh clearh USB Interrupt Mask True R/W 10h USB_EN R/W A bit of register 1 is set at "1" by writing a "1" at address 04h, is reset at "0" by writing a "1" at address 05h. This is also applicable for USB Control Register 2 (06h, 07h), USB Interrupt register (0Ah,0Bh), USB Interrupt Mask False register (0Ch, 0Dh) and USB Interrupt Mask True register (0Eh, 0Fh). Writing "0" at any address has not effect on the content of any register. STw4810 Functional description Table 10. Vendor ID and Product ID: Read only Name Address Register Value Vendor ID 00h 83h Vendor ID 01h 04h 02h 10h 03h 40h Product ID USB control register 1 Table 11. USB control register 1 (address = 04h set and 05h clearh) Register Bit name Type Bits Name 7 6 5 Not used uart_en - R/W 4 3 2 1 oe_int_ bdis_ not used dat_se0 suspend en acon_en R/W R/W Value - R/W R/W Settings 0 speed R/W Default 6 uart_en 0 1 Inactive UART logic buffers are enabled 0 5 oe_int_en 0 1 Inactive Allow to send interruption through USBOEn 0 4 bdis_acon_en 0 1 Inactive (default) Enable A-device to connect if B-device disconnect detected: 0 2 dat_se0 0 1 VP_VM USB mode DAT_SE0 USB mode 0 1 suspend 0 1 Inactive (default) Put transceiver in low power mode 0 0 speed 0 1 Set rise and fall times of transmit Low speed Full speed 0 23/78 Functional description STw4810 USB control register 2 Table 12. USB control register 2 (Address = 06h set and 07h clearh) Register Bit name Type Bits 24/78 Name 7 6 5 4 3 2 1 0 vbus_ chrg vbus_ dischrg vbus_ drv id_gnd dn_ pulldown dp_ pulldow n dn_ pullup dp_ pullup R/W R/W R/W R/W R/W R/W R/W R/W Value Settings Default 7 vbus_chrg 0 1 Inactive Charge VBUS through a resistor 0 6 vbus_dischrg 0 1 Inactive Discharge VBUS through a resistor to ground. 0 5 vbus_drv 0 1 Inactive Provide power to VBUS 0 4 id_gnd 0 1 Inactive Connect ID ball to ground 0 3 dn_pulldown 0 1 Inactive Connect DN pull-down 0 2 dp_pulldown 0 1 Inactive Connect DP pull-down 0 1 dn_pullup 0 1 Inactive Connect DN pull-up 0 0 dp_pullup 0 1 Inactive Connect DP pull-up 0 STw4810 Functional description USB interrupt source register Table 13. USB Interrupt source register (address = 08h) Register Bit name 7 6 5 4 3 2 1 0 cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_ vld vbus_ vld R R R R R R R R Type Bits 7 Name Value cr_int Settings Default 0 1 Inactive DP ball is above the carkit interrupt threshold 0 0 1 Inactive Set when bdis_acon_en is set, and transceiver asserts dp_pullup after detecting B-device disconnect. 0 6 bdis_acon 5 id_float 0 1 Inactive ID ball floating 0 4 dn_hi 0 1 Inactive DN ball is high 0 3 id_gnd_forced 0 1 Inactive ID ball grounded 0 2 dp_hi 0 1 Inactive DP asserted during SRP, 0 1 sess_vld 0 1 Session valid comparator threshold <0.8V or >4.4V 0.8V < Session valid comparator threshold < 4.4V 0 0 vbus_vld 0 1 A-device VBUS valid comparator threshold <4.4V A-device VBUS valid comparator threshold >4.4V 0 USB latch register Table 14. Register Bit name Default Type USB interrupt latch registers (address = 0Ah set and 0Bh clearh) 7 6 5 4 3 2 1 0 cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_ vld vbus_ vld 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W USB interrupt latch register bits indicate which sources have generate an interrupt. 25/78 Functional description STw4810 USB interrupt mask false register Table 15. USB interrupt mask false register (address = 0Ch and 0Dh) Register Bit name Default Type 7 6 5 4 3 2 1 0 cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vl d vbus_vl d 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W USB interrupt mask false register bits enable transition from true to false. USB interrupt mask true register Table 16. USB interrupt mask true register (address = 0Eh and 0Fh) Register 7 6 5 4 3 2 1 0 Bit name cr_int bdis_ acon id_float dn_hi id_gnd_ forced dp_hi sess_vl d vbus_vl d Type R/W R/W R/W R/W R/W R/W R/W R/W USB interrupt mask true register bits enable interrupts on transition from false to true. USB EN register Table 17. USB EN register (address = 10h) Register 7 6 5 Bit name 1 26/78 3 2 Not used Type Bits 4 - Name usb_en - - Value 0 1 0 usb_en not used - - Settings Inactive Enable USB PHY 1 - R/W - Default 0 STw4810 Functional description Registers controlled by main I2C bus IC controlled registers are controlled through the main serial I2C interface, SCL and SDA balls. SD MMC control register Table 18. SD MMC control register (11h) Register 7 Bit name pdn_ vaux Type R/W 6 5 monitori ng_vio_ it_warn vmem_ vcore R(1) R(1) 4 3 2 1 0 gpo2 gpo1 sel_vmmc<1:0> pdn_ vmmc R/W R/W R/W R/W 1. These bits are reset (0) after reading Bits Name Value Settings Default 7 pdn_vaux 0 1 Inactive Enable LDO vaux 0 6 it_warn 0 1 Below temperature threshold Above temperature threshold 0 5 monitoring_vio_ vmem_vcore 0 1 Outputs in the good range Outputs lower than expected on vio_vmem or vcore 0 4 gpo2 0 1 Output GPO2 HZ Output GPO2 Low 0 3 gpo1 0 1 Output GPO1 HZ Output GPO1 low 0 00 01 10 11 1.8V selection 1.8V selection 2.85V selection 3V selection 00 0 1 Inactive Enable SD/MMC or SDIO function. 0 [2:1] sel_vmmc<1:0> 0 pdn_vmmc In Flash OTP two registers allow to program STw4810 energy management part. These two registers are at address 1E and 1F and must be programmed with 1F register first followed by 1E register. 27/78 Functional description STw4810 Power control register at address 1Eh Table 19. Power control register - General information (Address = 1Eh) Register 7 Bit name 6 3 [4:1] data din/ dout 4 bits 1 0 EN R/W R/W R/W Value reg address 3 bits 2 data din/dout 4 bits Name [7:5] Settings 0 1 EN 0 4 reg address 3 bits LSB's Type Bits 5 Default See Table 21 "Address" column (LSB's). 0 See Table 21 control register 0 Read enabled Write enabled 0 Power control register at address 1Fh Table 20. Power control register - General information (Address = 1Fh) Register 15 14 13 Bit name 12 11 10 9 reg address 2 bits MSB's Not used Type R/W Bits [9:8] 8 Name Value Settings reg address 2 bits MSB's Default See Table 21 "Address" column (MSB's). 0 Power control register mapping Table 21. Power control register mapping Address 1Fh Address 1Eh reg address 2 bits MSB's Not used 15 14 13 12 11 10 9 8 3 bits LSB's 7 6 5 4 3 2 00h to 04h 05h to 0Ah 0Bh to 1E Caution: 28/78 Comments data din/dout 4 bits EN 1 0 Test purpose Setting See Table 22 to Table 27 Test purpose Only the latest value written in register at address 1E/1F can be read. STw4810 Functional description Power control register at address 05h Table 22. Power control register at address 05h Address 1Fh 15 Bits [4:1] 14 13 12 11 Address 1Eh 9 8 7 6 5 Not used 0 0 1 0 1 Name Value vcore_sel [3:0] 10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 3 vcore_sel [3:0] Settings = 1.00V = 1.05V = 1.10V = 1.15V = 1.20V (default) = 1.22V = 1.24V = 1.26V = 1.28V = 1.30V = 1.32V = 1.34V = 1.36V = 1.38V = 1.40V = 1.50V 2 1 0 EN Default 0100 29/78 Functional description STw4810 Power control register at address 06h Table 23. Power control register at address 06h Address 1Fh 15 14 Bits 4 13 12 11 Address 1Eh 10 9 8 7 6 5 4 Not used 0 0 1 1 0 vpll_sel [0] Name Value vpll_sel[1:0] on 06h and 07h address [3:2] vaux_sel[1:0] 1 usb_i2c_ctrl 3 2 vaux_sel <1:0> 1 0 usb_ i2c_ctrl EN Settings Default 00 01 10 11 = 1.05V = 1.2V = 1.3V = 1.8V 11 00 01 10 11 = 1.5V = 1.8V = 2.5V = 2.8V 00 0 1 USB I2C interface controls USB registers Main I2C interface controls USB registers 0 Power control register at address 07h Table 24. Power control register at address 07h Address 1Fh 15 Bits 14 13 12 11 Address 1Eh 10 9 8 7 6 5 4 3 2 1 0 Not used 0 0 1 1 1 en_vpll not used en_ vcore vpll_sel [1] EN Name Value Settings 4 en_vpll 0 1 Disabled / VPLL = OFF Enabled / VPLL = ON(1) 1 2 en_vcore 0 1 Disabled / VCORE = OFF Enabled / VCORE = ON(1) 1 1 vpll_sel[1] - See Table 23 - 1. No soft start feature at supply enabled after a disabled/enabled sequence 30/78 Default STw4810 Functional description Power control register at address 08h Table 25. Power control register at address 08h Address 1Fh 15 14 13 12 11 Address 1Eh 10 9 8 7 6 5 4 3 Not used 0 1 0 0 0 Bits Name Value 4 en_clock_squarer 0 1 Disabled Enabled (sine wave signal input) 0 3 en_monitoring 0 1 Disabled / MONITORING = OFF Enabled / VCORE & VIO_VMEM monitoring = ON 1 2 en_vana 0 1 Disabled / VANA = OFF Enabled / VANA = ON 1 en_clk en_mo square nitorin r g 2 1 0 en_ vana not used EN Settings Default Power control register at address 09h Table 26. Power control register at address 09h Address 1Fh 15 Bits 14 13 12 11 Address 1Eh 10 9 8 7 6 5 4 3 2 1 0 Not used 0 1 0 0 1 vaux_ sleep not used not used not used EN Name Value Settings Default When PWREN is low: VAUX stays in normal mode VAUX goes in sleep mode (default) 1 Not used Reserved 1 Not used Reserved 1 4 vaux_sleep 2 1 0 1 31/78 Functional description STw4810 Power control register at address 0Ah Table 27. Power control register at address 0Ah Address 1Fh 15 14 13 12 11 Address 1Eh 10 9 8 1 7 0 6 1 5 4 3 0 vaux_ force_ sleep not used 2 1 vio_ vcore_ vmem_ force_ force_ sleep sleep 0 Not used 0 Bits Name Value 4 vaux_force_sleep 0 1 0: VAUX in normal mode 1: VAUX goes in sleep mode (for any PWREN level) 0 2 vio_vmem_force_ sleep 0 1 0: VIO_VMEM in normal mode 1: VIO_VMEM goes in sleep mode (for any PWREN level) 0 1 vcore_force_sleep 0 1 0: VCORE stays in normal mode 1: VCORE goes in sleep mode (for any PWREN level) 0 Settings EN Default Twarning register Table 28. Twarning register (Address = 20h) Register 7 6 Bit name Type 32/78 Bits Name Value 0 mask_twarn 0 1 5 4 3 2 1 0 Not used mask_ twarn - R/W Settings Inactive Mask TWARN interruption (it_twarn bit) through VDDOK Default 0 STw4810 4.2.6 Functional description IT generation STw4810 has three interrupt balls: IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged this interrupt is activated to wake up the host or the modem, depends of application (active low). USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor VDDOK: This ball has two functions: - When high, it indicates that VIO_VMEM and VCORE output voltages are within the right range and that the device internal temperature is below the maximum allowed temperature. - When low, it indicates that output regulators (VCORE or VIO_VMEM) are not regulated properly or PWREN = "0", or that the temperature is above the allowed threshold (see Thermal shut-down section). The interruption source in the application register (address 11h) needs to be checked. 4.2.7 Clock switching and control This block generates the clock used by the DC/DC converter (USB charge pump, step-down VIO_VMEM and step-down VCORE). STw4810 is able to sustain the master clock frequencies of 26 MHz, 19.2MHz and 13 MHz. It can also sustain dedicated MASTER_CLK signal in the frequency range of 750KHz to 1MHz. If the clock is not detected the internal oscillator is automatically selected. Note: When present the Master clock should remain connected up to sleep mode. Figure 9. Clock switching between master and internal clock (1) * Phase delay is less than 90 between int and ext clock internal clock transition external clock PON INT_OSC INT_OSC_OK MASTER_CLK_OK Third rising edge after switching PDN_INT_OSC CONTROL_SWITCH MASTER_DIV_CLK STEP_DOWN_CLK 33/78 Functional description 4.3 STw4810 Power management module STw4810 includes several regulators that supply the multimedia processor and its peripherals. All regulators can work in different modes depending on the processor needs. When the STw4810 is in `low current mode'", the output current is reduced to save energy via the lower quiescent current. The nominal mode is called high power mode (HPM). The mode is selected by PWREN signal according to both multimedia processor and STw4810 state. When PWREN = "0", sleep mode is selected. HPM is selected as default when PWREN = "1". Each regulator has a dedicated battery power supply. It can be powered down by a signal called PDN_regulator_name as shown in the Figure 2: STw4810 block diagram. In this mode, the regulator is switched off and only a leakage current is present (max. 1A). VCORE, VAUX and VPLL output voltages are programmable, through main I2C interface, using the "Regulator"_SEL[x:0] bits of the power control registers (Table 22 to Table 27). In addition, an output current limitation prevents high current delivery in case of output short circuit. All multimedia processor power supplies have the same soft start to prevent leakage in the multimedia processor device during the start-up phase. There is an exception with VAUX which can be started independently. 4.3.1 Bandgap, biasing and references Figure 10. Block diagram of biasing and references of the device BG VREF_18 Voltage reference control All internal references All internal biasing Bias generator 34/78 STw4810 4.3.2 Functional description VCORE regulator: DC/DC step-down regulator This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down regulator that generates the regulated power supply with very high efficiency. The 15 voltage levels enable dynamic voltage and frequency scaling suitable for any supply voltage of CMOS process, they also follow the processor process roadmap. The regulated output voltage levels are adjustable by the power control registers (Table 22), via the main I2C interface (SDA, SCL). The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to generate the switching clock of the SMPS. When this clock is not available, regulators run the internal RC oscillator. The DC/DC step-down regulator has the following main features; Programmable output voltage, 15 levels from 1.0 V to 1.5 V (VCORE_SEL [3:0] bits of power control register - Table 22) 3 power domains: - `Normal mode' when multimedia processor is in run mode, 600 mA full load - `Low current mode' when multimedia processor is in sleep mode, 5 mA current capability. Fast switching from low current to normal mode. The regulator is in `low current mode' when multimedia processor is in sleep mode. PWREN signal indicates that the multimedia processor is about to switch to run mode. VDDOK signal indicates to the multimedia processor that all supplies are in the specified range. Note: The definition of sleep mode is given in section 4.2.3: Sleep mode. `Power down mode' or `standby mode' when regulator is switched off, no consumption (EN_VCORE bit of power control register - Table 28) Soft start circuitry at start up, from power off to normal mode, when PON ball changes from "0" to "1". Default setting defined by start-up configuration. 4.3.3 VIO_VMEM regulator: DC/DC step- down regulator VIO_VMEM step-down regulator has the same structure than VCORE. The VIO_VMEM regulator supplies the IOs of the multimedia processor and its peripherals. This regulator can be used to supply the memories working with the multimedia processor, such as DDR-SDRAM. A switched mode power supply - voltage down converter is used to generate the 1.8 V regulated power supply with very high efficiency. The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to generate the SMPS switching clock. When this clock is not available, regulators can run the internal RC oscillator. Main features Fixed 1.8 V output voltage Two power domains: - `Normal mode' when multimedia processor is in run mode - 600 mA full load - `Low current mode' when multimedia processor is in sleep mode, 5 mA current capability. 35/78 Functional description STw4810 Fast switching from low current to normal mode. The regulator is in `low current mode' when multimedia processor is in sleep mode. PWREN signal indicates that the multimedia processor is about to switch to run mode. VDDOK signal indicates to the multimedia processor that all supplies are in the specified range. Note: The definition of sleep mode is given in 4.2.3: Sleep mode section. Soft start circuitry at start up, from power off to normal mode, when PON ball changes from "0" to "1". Default setting defined by start-up configuration. 4.3.4 VPLL This LDO is dedicated to the multimedia processor PLL (1.05 V, 1.2 V, 1.3 V, 1.8 V) power supply with 10 mA max full load (Power Control Registers - Table 27 and Table 28). Main features 4.3.5 Programmable output voltage, (VPLL_SEL[1:0] bits of power control register - Table 27 and Table 28) Two power domains: - `Normal mode' 10 mA full load - `Power down mode' or `standby mode' when regulators are switched off and there is no power consumption (EN_VPLL bit of power control register - Table 28) Soft start circuitry at start up, from power off to normal mode, when PON ball changes from "0" to "1". Default setting defined by start-up configuration. VANA This LDO is dedicated to the multimedia processor analogue function (2.5 V) power supply with 10 mA full load. Main features: 2.5 V output voltage, Two power domains 36/78 - `Normal mode' 10 mA full load - `Power down mode' or `standby mode' when regulators are switched off and there is no power consumption (EN_VANA bit of power control register - Table 29), Default setting defined by start-up configuration. STw4810 4.3.6 Functional description VAUX This LDO is dedicated either to the multimedia processor input/output signals or to the auxiliary devices. Power supply values are 1.5 V,1.8 V, 2.5 V, 2.8 V with 150 mA full load and 0.5 mA in sleep mode. In case of 1.5 V on the output, this LDO can be supplied by using VIO_VMEM DC/DC converter (1.8 V). One pad feed-back is used. Main features: Programmable output voltage, 4 levels (VAUX_SEL[1:0] bits of Power control register - Table 27) Three power domains: - `Normal mode' when multimedia processor is in run mode, 150 mA full load - `Low current mode' when multimedia processor is in sleep mode, 0.5 mA current capability. Fast switching from low current to normal mode. Note: Definition of sleep mode is given in 4.2.3: Sleep mode section. - `Power down mode' or `standby mode' when regulator is switched off, no power consumption (PDN_VAUX bit of SD MMC control register - Table 18) Default setting defined by start-up configuration 4.3.7 Power supply monitoring This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drop below the threshold, the multimedia processor is reset. This feature can be desactivated by setting EN_MONITORING bit of Power control register (Table 29) to "0". 4.3.8 Power supply domains Table 29 lists the register bits that control STw4810 supply domains for each supply. Table 29. Supply name Supply domains Description Normal Sleep Power down 15 values VCORE_SEL[3:0] VCORE_SLEEP VCORE_FORCE_SLEEP VIO_VMEM STEP-DOWN 1.8 V VIO_MEM_SLEEP VIO_VMEM_FORCE_SLEEP VPLL LDO 4 values VPLL_SEL[1:0] EN_VPLL VANA LDO 2.5 V EN_VANA VAUX LDO 4 values VAUX_SEL[1:0] VMMC LDO 3 values SEL_VMMC[1:0] VCORE Note: Power supply domains STEP-DOWN VAUX_SLEEP VAUX_FORCE_SLEEP EN_VCORE PDN_VAUX PDN_VMMC More details on VMMC supply are given in Section 4.5 37/78 Functional description 4.3.9 STw4810 Thermal shut-down A thermal sensor is used to monitor the die temperature. As soon as the die temperature exceeds the thermal warning rising threshold, VDDOK ball goes to "0" and `it_warn' bit is set to "1" (SD MMC control register - Table 18). The IC turns back VDDOK ball to "1" and `it_warn' bit to "0" when the device temperature drops below the thermal warning falling threshold of the thermal sensor. A second thermal detection level, thermal shutdown threshold, puts all STw4810 supplies OFF, the supplies goes back to goes back to ON state when the temperature is under the thermal shutdown threshold and after a new startup phase. Table 30. Thermal threshold values Description Min Typ Max Unit Rising threshold 134 140 149 C Falling threshold 117 123 131 C 149 155 164 C Thermal warning threshold Thermal shutdown threshold Threshold Figure 11. Thermal threshold temperatures for `it_warn' bit and VDDOK ball `it_warn' bit All supplies are turn "OFF" VDDOK ball Rising warning threshold 38/78 Shutdown threshold Temperature STw4810 4.4 Functional description USB OTG module This transceiver complies with the USB specification: Universal Serial Bus specification revision 2.0 `On the Go' supplement to the USB specification revision 1.0-a Car kit interface specification (see: OTG transceiver specification revision 0.92) The USB OTG transceiver has two modes: USB mode and UART mode. It includes: Full and low speed transceiver (12 Mbit/s and 1.5 Mbit/s data rate) Support data line and VBUS pulsing session request Host Negotiation Protocol (HNP) command and status register Charge pump regulator (5 V at 100 mA) to supply VBUS line of the USB cable VBUS pull-up and pull-down resistors as defined by Session Request Protocol (SRP) VBUS threshold comparators VUSB LDO internal regulator which provides power supply for the bus driver and receiver. ID line detector and interrupt generator Dedicated IC serial control interface 39/78 Functional description 4.4.1 STw4810 Block diagram Figure 12. USB OTG transceiver block diagram VBAT_USB CP CN VBAT_DIG CHARGE PUMP 5V - 100mA REF vbus_drv VBUS VBUS_MONITOR VBUS > 4.4 V vbus_vld sess_vld USBSDA SCL SDA SW_RESETn vbus_chrg VBAT_USB VBUS < 0.8V Gnd VUSB_LDO vbus_dischrg vbus_drv bdis_acon_en dn_pullup dp_pullup Control dn_pulldown Registers dp_pulldown id_gnd vbus_chrg vbus_dischrg speed uart_en dat_se0 oe_int_en suspend RA_BUS_IN 2V < VBUS < 4.4 V usb_i2c_ctrl USBSCL 100 mA R_VBUS_SRP USB_INTn vbus_vld sess_vld dn_hi Interrupt dp_hi Control bdis_acon Register id_gnd_forced id_float cr_int usb_en R_VBUS_PD CLK VMINUS_DIG vbus_session_end VUSB DP_MONITOR 5.7 R DP cr_int RXD TRANCEIVER RXD dp_pullup dn_pullup RPU_DN RPU_DP DAT_VP USBVP Diff Tx SEO_VM USBVM R DP < [0.4 to 0.6] V OE_TP_INT USBOEn DP out_diff_Rx Diff Rx DN SINGLE ENDED RCV SE_DP VP RPD_DP USBRCV RPD_DN suspend dn_pulldown DECODER VM SE_DN dp_pulldown VBAT_DIG VBAT_USB R Plug detect Management IT_WAKE_UP id_float sess_vld ID 4.7 R id_gnd 0.15*ID OR ID Detector 40/78 RID_PU 0.85*ID R id_gnd STw4810 Functional description VBUS monitoring These comparators monitor the VBUS voltage. They detect the current status of the VBUS line: VBUS > 4.4 V means VBUS_VALID 2 V<VBUS<4.4 V means SESSION_VALID VBUS<0.8 V means SESSION_END These three bits generate an interrupt when active (see USB interrupt registers). VUSB LDO: Internal regulator which provides power supply for the bus driver and receiver. ID detector: This block detects the status of the ID line. It is capable of detecting three different states of line: ball is floating ID_FLOAT high, ball is tied to ground ID_GND high and ball ID is grounded via resistor. This detection generates interrupts (see USB interrupt registers). Transceiver: The driver can operate in several different modes. It can act as a classical lowspeed and full-speed differential driver, as two independent single-ended drivers or as a single-ended driver in UART mode. This block contains one differential receiver for the USB mode of operation and two single-ended receivers for USB signaling and UART mode. DP monitor: This block is used to detect car kit peripheral (0.6 V on DP). Pull up and pull down resistor: Configurable integrated pull-up and pull-down resistor of data line and VBUS. 4.4.2 Modes and operations Power modes The transceiver power modes are: Active power mode Suspended power mode Power down mode In suspended power mode the differential transmitter and receiver are turned off to save power but the USB interface is still active (pull-up and pull-down on, VBUS on). In power down mode, only the serial interface is active and the transceiver is able to detect SRP. In power down mode, ID ball sensing can be turned on/off via a control bit in the control registers. USB modes The two transceiver modes are: DAT_SEO mode (dat_se0 = 1 in USB control register 1 - Table 11) VP_VM mode (dat_se0 = 0 in USB control register 1 - Table 11) 41/78 Functional description STw4810 Data transmission The transceiver transmits USB data in the following conditions for USB control register 1 (Table 31, Table 32): uart_en=0; oe_int_en=0 Table 31. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 0 USB mode (DAT_SE0) Inputs Outputs Comments USBVP USBVM DP DN 1 (DAT_SE0 mode) 0 0 0 1 Not used Single ended data (zero sent) 1 (DAT_SE0 mode) 1 0 1 0 Not used Single ended data (1 sent) 1 (DAT_SE0 mode) x 1 0 0 Not used Force single ended zero 0 (VP_VM mode) 0 0 0 0 DIFF_RX 0 (VP_VM mode) 1 0 1 0 DIFF_RX 0 (VP_VM mode) 0 1 0 1 DIFF_RX 0 (VP_VM mode) 1 1 1 1 DIFF_RX Table 32. USBRCV DAT_VP drives the level of DP SE0_VM drives the level of DN Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1 Inputs Outputs USB mode (dat_se0) Comments USBVP USBVM DP DN USBRCV 1 (DAT_SE0 mode) 0 0 0 1 not used Single ended data (zero sent) 1 (DAT_SE0 mode) 1 0 1 0 not used Single ended data (1 sent) 1 (DAT_SE0 mode) x 1 0 0 not used Force single ended zero 0 (VP_VM mode) 0 0 0 0 0 (off) 0 (VP_VM mode) 1 0 1 0 0 (off) 0 (VP_VM mode) 0 1 0 1 0 (off) 0 (VP_VM mode) 1 1 1 1 0 (off) Driver are suspended If oe_int_en = 1 and suspend=1 (USB control register 1 - Table 11), the USBOEn ball becomes an output used to generate an IT to multimedia processor. 42/78 STw4810 Functional description The transceiver receives USB data in the following conditions: uart_en = 0 (USB control register 1); oe_int_en = 1 Table 33. Data receiver via USB control register 1 Inputs USB mode (dat_se0) Outputs Suspend DP DN USBVP USBVM USBRCV 1 (DAT_SE0 mode) 0 0 0 Diff rcv 1 1 not used 1 (DAT_SE0 mode) 0 1 0 1 0 not used 1 (DAT_SE0 mode) 0 0 1 0 0 not used 1 (DAT_SE0 mode) 0 1 1 Diff rcv 1 0 not used 1 (DAT_SE0 mode) 1 0 0 0 1 not used 1 (DAT_SE0 mode) 1 1 0 1 0 not used 1 (DAT_SE0 mode) 1 0 1 0 0 not used 1 (DAT_SE0 mode) 1 1 1 1 0 not used 0 (VP_VM mode) 0 0 0 0 0 diff rcv 1 0 (VP_VM mode) 0 1 0 1 0 1 0 (VP_VM mode) 0 0 1 0 1 0 0 (VP_VM mode) 0 1 1 1 1 diff rcv 1 0 (VP_VM mode) 1 0 0 0 0 not used 0 (VP_VM mode) 1 1 0 1 0 not used 0 (VP_VM mode) 1 0 1 0 1 not used 0 (VP_VM mode) 1 1 1 1 1 not used UART mode UART mode is entered by setting the `uart_en' bit to 1 (USB control register 1 - Table 11). The transceiver contains two digital logic level translators between the following balls: TXD signal: from USBVM to DN RXD signal: from DP to USBVP When not in UART mode the level translators are disabled. 43/78 Functional description STw4810 VBUS monitoring and control The monitoring is made of three comparators that determine if the VBUS voltage is at a valid level for operation: VBUS valid: It corresponds to the minimum level on VBUS. Any voltage on VBUS below the threshold is considered to be a fault. During power-up, it is expected that this comparator output is ignored. VBUS session valid: This threshold is necessary for session request protocol to detect the VBUS pulsing. VBUS session end: Session is ended. In this USB block, a B-device session end threshold is defined within the range [0.2; 0.8] V. The reason for a low 0.2 V limit is that the leakage current could charge the VBUS up to 0.2 V (maximum). When the A-device (default master) is power supplied and does not supply VBUS, it presents an input impedance RA_BUS_IN on VBUS of no more than 100 k. If the A-device responds to the VBUS pulsing method of SRP, then the input impedance RA_BUS_IN may not be lower than 40 k. When the A-device supplies power, the rise time TA_VBUS_RISE on VBUS to go from 0 to 4.4 V is less than 100 ms when driving 100 mA and with an external load capacitance of 10 F (in addition to VBUS decoupling capacitance). If VBUS does not reach this voltage within TA_VBUS_RISE maximum time, it indicates that the B-device is drawing more current that the A-device is capable of providing and an over-current condition exists. In this case, the A-device turns VBUS off and terminates the session. VBUS capacitance A dual-role device must have a VBUS capacitance CDRD_VBUS value comprised between 1 F and 6.5 F (see charge pump specification). The limit on the decoupling capacitance allows a B-device to differentiate between a powered-down dual-role device and a powereddown standard host. The capacitance on a host is higher than 96 F. Data line pull-down resistance When an A-device is idle or acting as host, it activates the pull-down resistors RPD on both DP and DN lines. When an A-device is acting as peripheral, it disables RPD on DP, not DN. The A-device can disable both pull-down resistors during the interval of a packet transmission when acting as either host or peripheral. The two bits of USB control register, dn_pulldown and dp_pulldown (Table 12) are used to connect/disconnect the pull-down resistors. When the line is not used, the pull-down is activated and the maximum level on this ball should not exceed 0.342 V. Data line pull-up resistance Full-speed and low-speed devices are differentiated by the position of the pull-up resistor from the peripheral device. A pull-up resistor is connected to DP line for a full-speed device and a pull-up resistor is connected to DN line for a low-speed device. The pull-up resistor value is in the range of 900 to 1600 when the bus is idle and 1425 to 3100 when the upstream device is transmitting. 44/78 STw4810 Functional description The two bits of USB control register dp_pullup and dn_pullup (Table 12) are used to connect/disconnect pull-up resistors. Session Request Protocol (SRP) To save power, the OTG supplement allows an A-device to leave the VBUS turned off when the bus is not being used. If the B-device wants to use the bus when VBUS is turned off, then it requires the A-device to supply power on VBUS using the Session Request Protocol (SRP). Initial conditions The B-device does not attempt to start a new session until it has determined if the A-device has detected the end of the previous session. The B-device must ensure that VBUS is below VBUS_SESSION_END before requesting a new session. Additionally, the B-device switches a pull-down resistor (R_VBUS_PD) from VBUS to ground in order to quicken the discharge process as long as the B-device does not draw more than 8 mA from VBUS. R_VBUS_PD is activated by bit `vbus_dischrg' of USB control register 2, (Table 12). When the B-device detects that VBUS is below the VBUS_SESSION_END and that both DP and DN have been low (SEO) for at least 2 ms, then any previous session on the Adevice is over and a new session can start. Data-line pulsing To indicate a request for a new session using the data line pulsing, the B-device turns on the DP pull-up resistor for 5 ms to 10 ms (only at full speed, no DN pulsing). The DP pull-up resistor is connected to VUSB (regulator output voltage). Timing is controlled by the USB digital control. VBUS pulsing To indicate a request for a new session using the VBUS pulsing method, the B-device waits for the initial conditions and then drives VBUS. VBUS is driven for a long enough period for a capacitance on VBUS that is smaller than 2x6.5 F to be charged to 2.1 V while a capacitance on VBUS higher than 97 F is not charged above 2.0 V. In this USB block, the VBUS_SESSION_VALID threshold is used to determine if an A-device is DRD (dual role device) or a standard host. The B-device VBUS pulsing block is designed so that the maximum drawn current does not exceed 8 mA. In this USB block, the pull-up is 600 +/- 30%. If a B-device is attached to a standard device, the pull-up must be disconnected after the defined timing to prevent damage of standard hosts not designed to withstand a voltage externally applied to VBUS. Session Request Protocol (SRP) If the B-device is in correct condition to start a new session, it first performs data line pulsing, followed by VBUS pulsing. When VBUS next crosses the SESSION VALID threshold, the B- device considers a session to be in progress and asserts the DP or DN data line within 100 ms. After SRP initialization, the B- device is set up to wait for at least 5 seconds for the A-device to respond before informing the user that the consumption attempt has failed. 45/78 Functional description STw4810 Host Negotiation Protocol (HNP) At the start of a session, the A-device has the role of host as default. During a session, the host role can be transferred back and forth between the A-device and the B-device any number of times using the Host Negotiation Protocol (HNP). The process for this exchange of host role is described in the "On the Go Supplement to the USB 2.0 Specification" (rev 1.0). ID detector In either active or suspended power mode, the ID detector detects the condition of the ID line and differentiates between the following three conditions: - ID ball floating: (e.g. with USB B-device connected) - ID ball shorted to ground: (e.g. with USB A-device connected) - ID ball connected to ground through resistor RACC_ID: (e.g.with an accessory). The transceiver pulls the ID ball to VID_HI (VBAT) through a resistance of RID_PU when an accessory is plugged in. In this case, the ID ball is externally connected to ground via Racc_ID resistor. Two comparators are used to detect the ID voltage: VID_GND and VID_FLOAT. The ID detector also has a switch that can be used to ground the ID ball. This switch is controlled by id_gnd bit of USB control register 2 (Table 12); This pull-down is used for CEA_KARKIT purposes. Car kit interrupt detector The transceiver is able to detect when the DP line is below the Carkit Interrupt threshold `cr_int', (see USB interrupt register) (refer to OTG specifications, Rev 0.92, 2.7, p13). Charge pump From VBAT_USB, the charge pump supplies VBUS, `vbus_drv' bit of USB control register 2 (Table 12) is used to enable/disable the charge pump. LDO USB From VBAT_USB, a LDO provides VUSB supply, `usb_en' bit of USB_EN register (Table 17) is used to enable/disable the VUSB LDO. 46/78 STw4810 4.4.3 Functional description USB enable control STw4810 OFF In this state, the overall system is able to detect USB connection through IT_WAKE_UP ball and with VBUS session valid comparator and ID detection ON. IT_WAKE_UP is activated (low level) in either of the two following cases: - When Mini A connector cable is connected and ID goes low - When activity on VBUS, i.e. a mini B is connected and is able to communicate. This mode is used to wake-up the modem platform. In this configuration, USBINTn ball is not enabled. STw4810 ON, USB driver not enabled The USBINTn is now enabled. If the USB cable is already connected while STw4810 is starting, the USB driver will be enabled when power management is ready. Wake-up USB driver conditions - A plug-in on a mini A-device and active ID detector - B device is connected and ready to start data transfer, VBUS is driven high (session valid high) - Activity on USB registers (00h to 0Fh - Table 9 to Table 16). Multimedia processor ready to wake-up and set-up USB PHY. - Possibility to force PHY high (enable) when writing usb_en = 1 in USB EN register (Table 17) Set condition: one among the following possibilities - External it_wake_up =0 - usb_en = 1 by writing to IC USB interface - Access to any other USB register (00h to 0Fh) Power down USB driver conditions in order to set the USB driver to power down mode: - it_wake_up = 1, and only then - Set usb_en bit of USB EN register (Table 17) to "0" 47/78 Functional description 4.5 STw4810 SD/MMC/SDIO module This block provides the power supply (1.8 V, 2.85 V or 3 V) and signal shifting functions required to connect any of the following peripherals to the multimedia processor: - SD card - MMC cards, low and 52 MHz high speed - SDIO cards (except SDIO card version 1.0 / Vsupply range: [3.1; 3.6] V Cards detection is automatically done by the multimedia processor system. Following a card detection, the multimedia processor starts the SD/MMC application by writing in the SD MMC control register (Table 18) to start LDO VMMC and then starts the protocol initialization. The module includes: - 1.8 V, 2.85 V or 3 V voltage regulators (150 mA) - Five bidirectional level shifter channels compatible with 1.8 V, 2.85 V or 3 V - Two unidirectional lines for clock: multimedia processor to card and feedback clock to multimedia processor for synchronization. - Four control signals for channel direction Figure 13. SD MMC block diagram SD/ MMC/SDIO INTERFACE VBAT_VMMC MCCMDDIR MCDATA0DIR MCDATA2DIR MCDATA31DIR VMMC 1.8V,2.85V,3V 150mA CLKOUT MCCLK DRIVER 3 * RA RC 3 * RA Rs Shifter MCCMD MCDATA0 MCDATA[3:1] MCFBCLK 48/78 SD, MMC SDIO OR CARDS Level 5 * RB Vsdc2 EMIF CMDOUT DATAOUT0 DATAOUT[3:1] LATCHCLK Dz Dz STw4810 5 Electrical and timing characteristics Electrical and timing characteristics Otherwise specified parameters are defined for T = 25C. / VBAT = 3.6 V 5.1 Absolute maximum rating Table 34. STw4810 absolute maximum ratings Symbol Description Values Units -0.5 to 7 V -30 to 85 C -2 to +2 kV -450 to +750 V Maximum power supply Ta Maximum operating ambient temperature Human body VESD Electrostatic discharge model model(1) Charge device model(2) 1. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM 2. CDM tests have been performed in compliance with CDM ANSI-ESD STM 5.3.1-1999 5.2 Package dissipation Table 35. Package dissipation Symbol Description Min. Typ. Max. Units TFBGA 84 6x6x1.2mm 0.5mm ball pitch RTHJ-A Thermal resistance Junction to Ambient 70 C/W 76 C/W VFBGA84 4.6x4.6x1.0mm 0.4mm ball pitch RTHJ-A Thermal resistance Junction to Ambient 5.3 Power supply Note: STw4810 has different ways to go in sleep mode. The different possibilities for VCORE, VIO_VMEM and VAUX to be programmed to sleep mode are given in Table 30 and Table 27. In all the following tables: - "Normal mode" is defined as "SLEEP = `0'" - "Sleep mode" is defined as "SLEEP = `1'" Use Table 27 to refer to each Vxxx supply (VCORE or VIO_VMEM or VAUX). 49/78 Electrical and timing characteristics 5.3.1 Operating conditions Table 36. Symbol VBAT IQSLEEP Operating conditions (Temp range: -30 to +85 C) Description Min. Typ. 2.7 Sleep mode 170 Max. Units 4.8 V 250 A 4 A Max. Units 4.8 V 1.84 V Quiescent Current Off mode VREF18 Table 37. Symbol VREF18 Description Test conditions Min. Typ. VBAT Supply voltage 2.7 VREF_18 Output voltage 1.78 PSRR Power supply rejection ratio Vpp = 0.3 V f 100 kHz 60 dB Noise 100 Hz f 100 kHz 30 V tS 50/78 Test conditions Power supply IQSTDBY 5.3.2 STw4810 Settling time 1.8 7.77 9.46 ms STw4810 5.3.3 Electrical and timing characteristics VCORE DC/DC step-down converter Table 38. Symbol VCORE DC/DC step-down converter Description Test conditions Min. Typ. Max. Units VCORE regulator in normal mode (SLEEP = `0') / Otherwise specified; VCORE = 1.2 V VBAT Input power supply Battery voltage VRIPPLE Output voltage ripple VOUT Programmable output voltage 2.7 3.6 4.8 10 VCORE_SEL[3:0] 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 (default) 0011 0010 0001 0000 -3.7% -4.25% -5% 1.50 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 1.15 1.10 1.05 1.00 V mVpp +3.7% V +4.25% +5% IOUT Output current PEFF Power efficiency VBAT = 3.6 V IOUT = 200 mA LIR Line regulation VBAT: [2.7; 4.8]V 10 mV LDR(1) Load regulation IOUT: [0.1; 600] mA 10 mV ISHORT Short circuit current limitation(2) 1.2 1.4 A IQ Quiescent current IOUT = 0 mA 130 250 A ILKG Power-down current `en_vcore' = 0 1 A PSRR(1) Power supply rejection Vpp = 0.3 V [0; 20] kHz LIRT Transient line regulation VBAT = 300 mV tR = tF = 10 s 7 mV LDRT Transient load regulation IOUT = [1; 600] mA tR = tF = 100 ns 70 mV 600 86 0.9 40 mA % dB 51/78 Electrical and timing characteristics Table 38. Symbol STw4810 VCORE DC/DC step-down converter (continued) Description Test conditions Min. Typ. Max. Units 2.7 3.6 4.8 V VCORE regulator in sleep mode (SLEEP= `1') VBAT Input power supply Battery voltage VRIPPLE VCORE output voltage ripple LIR Line regulation VBAT: [2.7; 4.8]V 10 mV LDR Load regulation IOUT: [0.1; 5] mA 10 mV IOUT VCORE output current 5 mA PEFF Power efficiency VBAT= 3.6 V IOUT: [0.1; 5] mA 85 IQ Quiescent current IOUT = 0 mA 20 LIRT Transient line regulation VBAT= 300 mV tR = tF = 10 s 7 10 mVpp % 30 A mV 1. Guaranteed by design 2. Guaranteed by design 5.3.4 VIO_VMEM DC/DC step-down converter Table 39. Symbol VIO_VMEM DC/DC step-down converter Description Test conditions Min. Typ. Max. Units VIO_VMEM regulator in normal mode (SLEEP = `0') 52/78 VBAT Input power supply Battery voltage 2.7 3.6 4.8 V VOUT Output voltage (1) -3% 1.8 +3% V VRIPPLE Output ripple LIR Line regulation VBAT: [2.7; 4.8]V 10 mV LDR(2) Load regulation IOUT: [0.1; 600] mA 10 mV IOUT Output current 600 mA PEFF Power efficiency 10 VBAT = 3.6 V, VIO = 1.8 V IOUT= 100 mA mVpp 90 % ISHORT Short circuit current limitation(2) IQ Quiescent current IOUT = 0 mA PSRR(2) Power supply rejection Vpp = 0.3 V [0; 20] kHz LIRT Transient line regulation VBAT = 300 mV tR = tF = 10 s 7 mV LDRT Transient load regulation IOUT= [1; 600] mA tR = tF = 100 ns 70 mV 0.9 1.2 1.4 A 130 250 A 40 dB STw4810 Electrical and timing characteristics Table 39. Symbol VIO_VMEM DC/DC step-down converter (continued) Description Test conditions Min. Typ. Max. Units 2.7 3.6 4.8 V VIO_VMEM regulator in sleep mode (SLEEP='1') VBAT Input power supply Battery voltage VRIPPLE Output ripple LIR Line regulation VBAT: [2.7; 4.8]V 10 mV LDR Load regulation IOUT: [0.1; 5] mA 10 mV IOUT Output current 5 mA PEFF Power efficiency VBAT = 3.6 V IOUT = [0.1; 5] mA IQ Quiescent current IOUT = 0 mA LIRT Transient line regulation VBAT = 300 mV tR = tF = 10 s 10 mVpp 85 % 15 7 A mV 1. Including output voltage temperature coefficient, DC line and load regulations, voltage reference accuracy, industrial manufacturing tolerances and ripple voltage due to switching 2. Guaranteed by design 53/78 Electrical and timing characteristics 5.3.5 STw4810 LDO regulators VPLL Table 40. Symbol LDO regulators - VPLL Description Test conditions Min. Typ. Max. Units 4.8 V +3% V 3.5 10 mA 130 165 mA 30 40 A 1 A VPLL regulator in normal mode / otherwise specified, VPLL = 1.8 V VBAT Input power supply Battery voltage VOUT Output voltage VPLL_SEL[1:0] 11 (default) 10 01 00 IOUT Output current ISHORT Short-circuit limitation IQ Quiescent current IOUT = 0 mA ILKG Power-down current EN_VPLL = 0 PSRR(1) Power supply rejection Vpp = 0.3 V f < 10 kHz 10 kHz < f <100 kHz LIR Line regulation VBAT: [2.7; 4.8]V 5 mV LDR Load regulation IOUT: [0.1; 10] mA 10 mV LIRT Transient line regulation VBAT = 300 mV tR = tF = 10 s 1 mV LDRT Transient load regulation IOUT = [0.1; 10] mA tR = tF = 1 s 1 mV En(1) Noise density at 1 KHz BW = 100 Hz 1. Guaranteed by design 54/78 2.7 -3% 95 3.6 1.8 1.3 1.2 1.05 55 45 dB dB 250 nVrms ------------Hz STw4810 Electrical and timing characteristics VANA Table 41. Symbol LDO regulators - VANA Description Test conditions Min. Typ. Max. Units VANA regulator in normal mode VBAT Input power supply Battery voltage 2.7 3.6 4.8 V VOUT Output voltage -5% 2.5 +5% V IOUT Output current 10 mA ISHORT Short-circuit limitation 64 mA IQ Quiescent current IOUT = 0 mA 30 A ILKG Power-down current EN_VANA = 0 1 A PSRR(1) Power supply rejection Vpp = 0.3 V f < 10 kHz LIR Line regulation VBAT: [2.7; 4.8] V 5 mV LDR Load regulation IOUT: [0.1; 10] mA 5 mV LIRT Transient line regulation VBAT = 300 mV tR = tF = 10 s 3 mV LDRT Transient load regulation IOUT = [0.1; 10] mA tR = tF = 1 s 15 mV 39 51 45 dB 1. Guaranteed by design VAUX Table 42. Symbol LDO regulators - VAUX Description Test conditions Min. Typ. Max. Units 4.8 V V VAUX regulator in normal mode (PDN_VAUX= 1, SLEEP= `0') VOUT = 1.5V VBAT Input power supply VOUT = 1.8/2.5 V VOUT = 2.8 V VOUT Output voltage IOUT Output current ISHORT Short-circuit limitation IQ Quiescent current ILKG Power-down current VAUX_SEL[1:0] 00 (default) 01 10 11 1.7 2.7 3.6 4.8 3 3.6 4.8 -3% 1.5 1.8 2.5 2.8 +3% V 150 mA 900 mA IOUT = 0 mA 30 A PDN_VAUX = 0 1 A 350 700 55/78 Electrical and timing characteristics Table 42. Symbol STw4810 LDO regulators - VAUX (continued) Description Test conditions Min. Typ. Max. Units PSRR(1) Power supply rejection VOUT=1.5 V Vpp = 0.3 V f < 10 kHz LIR Line regulation VOUT=1.5 V VBAT: [2.7; 4.8]V 5 mV LDR(1) Load regulation VOUT=1.5 V IOUT= [0.1; 150] mA 10 mV LIRT Transient line regulation VBAT = 300 mV tR = tF = 10 s 2 mV LDRT Transient load regulation IOUT = [10; 90%] mA tR = tF = 1 s 35 mV tS Settling time 100 s 32 dB VAUX regulator in sleep mode (PDN_VAUX= 1, SLEEP='1') VBAT Input power supply VOUT = 1.5V VIO_VMEM supply 1.7 VOUT = 1.8/2.5 V 2.7 VOUT = 2.8 V V 3.6 4.8 V 3 3.6 4.8 -3% 1.5 1.8 2.5 2.8 +3% VOUT Output voltage IOUT Output current IQ Quiescent current IOUT = 0 mA PSRR(1) Power supply rejection VOUT=1.5 V Vpp = 0.3 V f < 10 kHz LIR Line regulation VOUT=1.5 V VBAT: [2.7; 4.8]V 5 mV LDR Load regulation VOUT=1.5 V IOUT= [10; 90%] A 10 mV LIRT Transient line regulation VBAT = 300 mV tR = tF = 10 s 2 mV LDRT Transient load regulation IOUT = [10; 90%] A tR = tF = 1 s 35 mV 1. Guaranteed by design 56/78 VAUX_SEL[1:0] 00 (default) 01 10 11 4.8 V 500 A 15 A 38 dB STw4810 5.3.6 Electrical and timing characteristics Power supply monitoring This block monitors the VCORE and VIO_VMEM output voltage. If VCORE or VIO_VMEM drops below the threshold, the multimedia processor is reset. Table 43. Power supply monitoring Symbol Description Test conditions Min. Typ. Max. Units -3% VCORE150 +3% mV -3% 1.65 +3% V 2.7 3.6 4.8 V Threshold THCORE(1) Threshold VCORE THVIO(1) Threshold VIO_VMEM Comparators VBAT Supply voltage tRES Response time 100 ns HYFALL Hysteresis (input voltage falling) 26 mV HYRIS Hysteresis (input voltage rising) +4 mV 1. Guaranteed by design 5.4 Digital specifications 5.4.1 CMOS input/output static characteristics: I2C interface Table 44. CMOS input/output static characteristics: IC interface Symbol Description Test conditions Min. Typ. Max. Units 0.3*VIO V IC interface(1) VIL Low level input voltage VIH High level input voltage 0.7*VIO IIL Low level input current -1.0 1.0 A IIH High level input current -1.0 1.0 A VOL Low level output voltage IOL = 3mA (with open drain or open collector) 0.2*VIO V VOH High level output voltage IOL = 3mA (with open drain or open collector) 0.8*VIO V V 1. Vio is for VIO_VMEM 57/78 Electrical and timing characteristics 5.4.2 STw4810 CMOS input/output dynamic characteristics: I2C interface Table 45. CMOS input/output dynamic characteristics: IC interface Symbol Description Min. Typ. Max. Units 400 Khz IC interface (Figure 8) Fscl Clock frequency thigh Clock pulse width high 600 tlow Clock pulse width low 1300 ns (1) tr SDA, SCL, USBSDA, USBSCL rise time 20+0.1*Cb tf SDA, SCL, USBSDA, USBSCL fall time thd_sta Start condition hold time 600 ns tsu_sta Start condition set up time 600 ns thd_dat Data input hold time 0 ns tsu_dat Data input set up time 250 ns tsu_sto Stop condition set up time 600 ns tbuf Bus free time 1300 ns Cb Capacitive load for each bus line 1. Cb = total capacitance of one bus line in pF 58/78 ns 20+0.1*Cb 300 ns 300 ns 400 pF STw4810 5.4.3 Electrical and timing characteristics CMOS input/output static characteristics: VIO level USB and control I/Os Table 46. Symbol VIO level: USB and control I/Os Description Test conditions Min. Typ. Max. Units SW_RESETn, VDDOK, PORN, PWREN, TCXO_EN, REQUEST_MC, CLK32K, CLK32K_IN, USBOEN, USBVP, USBVM, USBRCV, USBINTn, MASTER_CLK VIL(1) Low level input voltage VIH High level input voltage 0.7*Vio IIL Low level input current -1.0 1.5 A IIH High level input current -1.0 1.5 A CIN Input capacitance 10 pF VOL Low level output voltage IOL = 4 mA 0.2*Vio V VOH High level output voltage IOL = 4 mA tOF Output fall time Capacitance 10pF 10 ns tOR Output rise time Capacitance 10pF 10 ns CI/O Driving capability 100 pF 0.3*Vio V V 0.8*Vio V 1. Vio for VIO_VMEM 59/78 Electrical and timing characteristics STw4810 MMC Interface Table 47. Symbol VIO level: MMC interface Description Test conditions Min. Typ. Max. Units MMC interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2, MCDATA0DIR, MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1 VIL(1) Low level input voltage VIH High level input voltage 0.7*Vio IIL Low level input current -1.0 1.5 A IIH High level input current -1.0 1.5 A CIN Input capacitance 10 pF VOL Low level output voltage IOL = 15 mA 0.2*Vio V VOH High level output voltage IOL =15 mA CI/O Driving capability at 52 MHz 1. Vio for VIO_VMEM 60/78 0.3*Vio V V 0.8*Vio V 30 pF STw4810 5.4.4 Electrical and timing characteristics CMOS input/output static characteristics: VBAT level Table 48. Symbol CMOS input/output static characteristics: VBAT level Description Test conditions Min. Typ. Max. Units 0.3*Vbat V IT_WAKE_UP, PON, GPO1, GPO2 VIL Low level input voltage PON VIH High level input voltage PON 0.7*Vbat IIL Low level input current PON -1.0 1.5 A IIH High level input current PON -1.0 1.5 A CIN Input capacitance 10 pF VOL Low level output voltage IT_WAKE_UP, GPO1, GPO2 IOL = 2mA 0.2*Vbat V VOH High level output voltage IT_WAKE_UP, GPO1, GPO2 IOL = 2 mA tOF Output fall time Capacitance 10pF 5 ns tOR Output rise time Capacitance 10pF 50 ns CI/O Driving capability 100 pF V 0.8*Vbat V 61/78 Electrical and timing characteristics 5.4.5 STw4810 CMOS input/output static characteristics: VMMC level Table 49. Symbol CMOS input/output static characteristics VMMC level Description Test conditions Min. Typ. Max. Units DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT 62/78 VIL Low level input voltage VIH High level input voltage 0.7*VMMC IIL Low level input current -1.0 1.5 A IIH High level input current -1.0 1.5 A CIN Input capacitance 10 pF VOL Low level output voltage IOL = 25 mA VOH High level output voltage IOL = 25 mA CI/O Driving capability 0.3*VMMC 0.2*VMMC 0.8*VMMC 40 pF STw4810 Electrical and timing characteristics 5.5 USB OTG transceiver Table 50. USB OTG transceiver Symbol Description Test conditions Min. Typ. Max. Units UART mode tR Rise time CLOAD= [50;100] pF [10; 90] % of VOH-VOL 100 ns tF Fall time CLOAD= [50;100] pF 10......90% of VOH-VOL 100 ns tPLH Drive propagation delay low => high CLOAD= [50;100] pF 50% of |VOH-VOL| 100 ns tPHL Drive propagation delay high => low CLOAD= [50;100] pF 50% of |VOH-VOL| 100 ns USB full speed mode (DP & DN signals) tR Rise time 4 20 ns tF Fall time 4 20 ns DRFM Differential rise an fall time matching 90 111 % OSCV Output signal crossover voltage 1.3 2 V PDEL Propagation delay 18 ns USBVP & USBVM : - Trise & Tfall < 1 ns - Skew < 0.66 ns USB low speed mode (DP & DN signals) tR Rise time 75 300 ns tF Fall time 75 300 ns DRFM Differential rise an fall time matching 80 125 % OSCV Output signal crossover voltage 1.3 2 V 4.8 V VBUS comparators VBAT Input power supply Battery voltage 3.1 3.6 tRR Rising reacting time 1.7 s tFR Fall reacting time 2.1 s Threshold VBUS monitoring VBval VBUS valid 4.4 VBses VBUS session valid 1.8 4.5 4.6 V 2 V 63/78 Electrical and timing characteristics Table 50. STw4810 USB OTG transceiver (continued) Symbol Description Test conditions Min. Typ. Max. Units 100 k 100 ms VBUS 40 RA_BUS_IN VBUS = [0; 4.4] V ILOAD TA_VBUS_ = 100mA RISE External cap 10F Data line pull-down resistance RPD_DPDN 14 19 25 k Data line pull-up resistance RPU_DP Bus idle Bus driven 900 1425 1200 2300 1600 3100 RPU_DN Bus idle Bus driven 900 1425 1200 2300 1600 3100 650 925 1200 420 600 780 Pull-down on VBUS RVBUS_PD Pull-up on VBUS RVBUS_SRP ID VID_GND ID_GND comparator threshold VID_HI (VBAT) Battery level VID_FLOAT ID_FLOAT comparator threshold 2.7 V < VBAT < 4.8 V 0.15*VBAT 2.7 3.6 V 4.8 0.85*VBAT RPU_ID 70 RPD_ID 100 V V 130 k 10 k Carkit threshold detection Carkit interrupt threshold 0.4 0.6 V VOH_TXD_DAT TXD output high on DN ISOURCE = 500 A 2.4 3.6 V VOL_TXD_DAT TXD output low on DN 0.4 V VIH_RXD_DAT RXD input high on DP VIL_RXD_DAT RXD input low on DP cR_INT Transceiver 64/78 ISINK = 2mA 2 V 0.8 V STw4810 Table 50. Electrical and timing characteristics USB OTG transceiver (continued) Symbol Description Test conditions Min. Typ. Max. Units VUSB+0.1 3.6 4.8 V 4.75 5 5.25 V Charge pump VBAT Input power supply Battery voltage VBUS Output voltage Current load up to 100 mA tS Settling time [0;4.8] V) Ext. load: 100 mA + External cap = 10F 1.2 ms IQ Quiescent current No Load 2.7 mA VRipple Amplitude output ripple Current load 8 mA on VBUS Current load 100mA 25 40 mV mV IOUT Output current Eff Efficiency 100 VBAT = 3.0V IOUT =100mA VBAT= 3.6V. IOUT = 8 mA. mA 85 % 60 % VUSB regulator VBAT(1) Input voltage Battery voltage: VBAT min = VOUT + 0.1V VOUT Output voltage VBAT min= VOUT + 0.1V ISHORT Short circuit current limitation IQ Quiescent current No load PSRR(2) Power supply rejection VBAT= VOUT+0.2V f < 20 kHz NVOUT Output noise voltage VBAT= VOUT+0.2V 10Hz <f< 100kHz LIRT Transient line regulation tS tD VUSB+0.1 3.6 5.5 V 3.0 3.1 3.2 V 320 mA 70 A 45 dB 100 Vrms VBAT = 300 mV tR = tF = 10s. 5 mV Settling time OFF->ON IOUT = 0mA 25 s Discharge time ON>OFF IOUT = 0mA 400 s 1. From 4.8 V to 5.5 V, charge pump is "Off" and no OTG feature is provided 2. Guaranteed by design 65/78 Electrical and timing characteristics 5.6 STw4810 SD/MMC card interface Table 51. Symbol SD/MMC card interface Description Test conditions Min. Typ. Max. Units 3.25 3.1 2.7 3.6 4.8 V -3% 3 2.85 1.8 +3% V 150 mA 600 mA VMMC regulator specifications (PDN_VMMC = 1) VOUT = 3 V VOUT = 2.85 V VOUT = 1.8 V VBAT Input voltage VOUT Output voltage IOUT Output current ISHORT Short circuit current limitation IQ Quiescent current IOUT = 0 mA 30 A ILKG Power-down current PDN_VMMC = 0 1 A PSRR(1) Power supply rejection IOUT = 150 mA Vpp = 0.3 V f < 20 kHz LIR(1) Line regulation VOUT=2.85 V VBAT: [3.1; 4.8]V 5 mV LDR(1) Load regulation VOUT=2.85 V IOUT= [1; 150] mA 10 mV LIRT Transient line regulation VOUT=2.85 V VBAT: 3.1 to 3.4V tR = tF = 10 s. 2 mV LDRT Transient load regulation IOUT = [1; 150] mA tR = tF = 1 s 25 mV tS Settling time OFF->ON IOUT = 0 mA 100 s tD Discharge time ON>OFF IOUT = 0 mA 1 ms 280 360 45 dB Bus line specifications 66/78 RA(2) Pull-up resistor To prevent bus floating 1.5 M RB Pull-down resistor To prevent bus floating 1.5 M fDT Clock frequency data transfert mode With CL = 30pF 52 MHz fID Clock frequency With CL = 30pF identification mode 400 KHz STw4810 Electrical and timing characteristics Table 51. Symbol SD/MMC card interface (continued) Description Test conditions Min. Typ. Max. Units TPHC Propagation time from Host to card Figure 14 7 ns TPCH Propagation time from card to host Figure 14 7 ns TSHC Clock /data skew time from host to card Figure 14 Reference is CLKOUT +/- 0.5 ns TSCH Clock /data skew time from card to host Figure 14 Reference is MMCLK +/- 0.5 ns TR Rise time 3 ns TF Fall time 3 ns C1LINE Between multimedia processor & STw4810 20(3) pF C2LINE Bus line Between STw4810 capacitance & MMC card f < 52 MHz 20 + 20(4) pF Bus line capacitance f < 52 Mhz 1. Guaranteed by design 2. MMC interface pull up resistors are in EMIF06-HCM01F2 device (7 K for CMD; 75 K for Data wires) 3. 20 pF for equivalent board parasitic capacitance. 4. 20 pF for EMIF06 protection + 20 pF for board parasitic capacitance. 67/78 Electrical and timing characteristics STw4810 Figure 14. Propagation and clock/data skew times 2 ns 2 ns 2 ns MCCLK MCCMD MCDATA[3:0] MCFBCLK 90% 90% 50% 10% 10% TPHC DATAOUT[3:0] MCDATA[3:0] t 2 ns 2 ns 90% 10% 2 ns 90% 50% TSCH 90% 50% 10% TPCH t CLKOUT 10% MCCLK 50% DATAOUT[3:0] TPCH 68/78 CLKOUT MCCLK 10% 50% TPHC MCCLK MCCMD MCDATA[3:0] MCFBCLK 50% t CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK TSHC 90% t MCDATA[3:0] STw4810 Application information 6 Application information 6.1 Components list Table 52. Components list Name Typical value Comments Function C1 VIO_VMEM output filter 22F C4 VCORE output filter C2 VBAT_VIOVMEM decoupling C3 10F C5 C6 C7 C8 1F C10 C13 In the complete system application, the sum of the capacitors connected on each STw4810 ball must never be less than 30% of the value indicated in the typical value column of this table. This includes all capacitor parameters: - production dispersion - DC bias voltage applied - temperature range of the complete system application - aging VBAT_ANA decoupling VBAT_VCORE decoupling VPLL output filter VANA output filter VREF output filter VUSB output filter VAUX output filter C9 470nF C11 4.7F C12 2.2F VSD_MMC output filter C13, C14, C15, C16, C17 1 F Vbattery input voltage decoupling capacitors L1 Flying capacitor for charge pump VBUS output filter (tank charge pump capacitor) Coil VIOVMEM DC/DC 4.7H See Table 53 for recommended coils L2 Coil VCORE DC/DC Table 53. Supplier TDK Coilcraft Recommended coils DCR () Irms(1) (A) L x l x h (mm * mm * mm) VLF3010AT-4R7MR70 0.28 0.7 2.8 * 2.6 * 1.0 VLF3012AT-4R7MR74 0.16 0.74 2.8 * 2.6 * 1.2 VLF4012AT-4R7M1R1 0.14 1.1 3.7 * 3.5 * 1.2 DO1605T-472MX 0.15 1.1 5.5 * 4.2 * 1.8 DO3314-472ML 0.32 1.1 3.3 * 3.3 * 1.4 ME3320-472MX 0.19 1.1 3.2 * 2.5 * 2.0 Part Number 1. Irms: 30% decrease of initial value 69/78 Application information Table 54. Other ST components Name 70/78 STw4810 Order code Function EMIF02 EMIF02USB05 USB ESD/EMI Protection EMIF06 EMIF06-HMC01F2 MMC Interface ESD/EMI Protection STw4810 6.2 Application information Application schematics Figure 15. STw4810 application schematics C4 VLX_VCORE VBAT_VCORE VMINUS_ANA VBAT_ANA VIOVMEM_FB PON CLK32Kin MASTER_CLK VLX_VIOVMEM VMINUS_VIOVMEM Modem & system clock VBAT_DIG VMINUS_DIG VBAT_VIOVMEM C2 C13(*) L2 C5 C3 VCORE L1 VMINUS_VCORE C1 C14(*) VBAT_VPLL_VANA C6 IT_WAKE_UP VPLL REQUEST_MC TCXO_EN C7 VANA C8 B9 VREF C15(*) VBAT_VAUX D3 C13 VAUX C16(*) VBAT_USB PWREN VDDOK PORn CLK32K SW_RESETn CN STw4810 Multimedia processor SDA USBVP USBOEn USBVM USBRCV ID ESD DP USBSCL DN MCDAT2DIR MCDAT2 R1 R1 EMI filter MCCLK MCFBCLK MCDAT0DIR MCDAT0 MCDAT31DIR MCDAT[3,1] C11 VBUS USBINTn MCCMDDIR MCCMD C10 VUSB USBSDA 3 C9 CP USB SCL VMINUS_USB EMIF02 (*) VBAT_MMC C17 C12 VMMC DATOUT[3:1] DATAOUT0 CMDOUT SD MMC 3 EMI Filter SDIO CARD CLKOUT LATCHCLK GPO1 GPO2 EMIF06-HMC01F2 (*) The usefulness of these capacitors depend of PCB layout 71/78 Package mechanical data 7 STw4810 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 7.1 TFBGA 84 balls See Figure 16: TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing. Table 55. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions(1) Drawing dimensions (mm) Min. Typ. A A1 1.16 0.20 A2 0.25 0.30 0.82 b 0.25 0.30 0.35 D 5.90 6.00 6.10 D1 E 4.50 5.90 E1 6.00 6.10 4.50 e 0.45 0.50 0.55 f 0.65 0.75 0.85 ddd 1. These measurements conform to JEDEC standards 72/78 Max. 0.08 STw4810 Package mechanical data Figure 16. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 73/78 Package mechanical data 7.2 STw4810 VFBGA 84 balls See Figure 17: VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing. Table 56. VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch(1) Drawing dimensions (mm) Min. Typ. A A1 0.864 0.15 0.19 A2 0.615 A3 0.18 A4 0.435 0.23 b 0.21 0.25 0.29 D 4.55 4.60 4.65 D1 E 3.60 4.55 4.60 E1 3.60 e 0.40 f 0.50 4.65 ddd 0.08 eee 0.13 fff 0.04 1. These measurements conform to JEDEC standards 74/78 Max. STw4810 Package mechanical data Figure 17. VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch drawing Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 75/78 Ordering information 8 STw4810 Ordering information Table 57. Order codes Part number 76/78 Package Packing STw4810CHDR/LF TFBGA84- 6x 6 x 1.2 mm / 0.5 mm pitch Tray STw4810CHDT/LF TFBGA84- 6x 6 x 1.2 mm / 0.5 mm pitch Tape and reel STw4810CRAE/LF VFBGA 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch Tray STw4810CRAT/LF VFBGA 84 - 4.6x 4.6 x 1 mm / 0.4 mm pitch Tape and reel STw4810 9 Revision history Revision history Table 58. Document revision history Date Revision 24-Jan-2006 1 Initial release. 07-Feb-2006 2 Modified document title. Reviewed list of applications on cover page. Replaced APE with multimedia processor. Replaced fuse with analogue function. Renamed VFUSE as VANA. Modified figure 6 - Control interface - I2C format 09-Feb-2006 3 Correction of Figure 13: SD MMC block diagram. Correction of Figure 15: STw4810 application schematics. 4 Correction in Section 4.2.3: Sleep mode on page 18 Removed formula and some text about sleep mode. Table 26: Power control register at address 09h on page 31 Replaced bit 2 and 1 with "not used" and "reserved". 10-Mar-2006 25-Jul-2006 5 30-Nov-2006 Changes Update short circuit current limit in Table 38: VCORE DC/DC stepdown converter, Table 39: VIO_VMEM DC/DC step-down converter. Updated short circuit minimum value in Table 42: LDO regulators VAUX and Table 51: SD/MMC card interface Updated the ordering information. 15-Mar-2007 6 Corrected VBAT maximum value in Table 36: Operating conditions (Temp range: -30 to +85 C). 23-Apr-2007 7 Updated Figure 3: Start-up timing and replaced all TBD references with values in Table 46, Table 47, Table 48, Table 49. Replaced ESD performance with VESD in Table 34. 08-Jun-2007 8 Updated the minimum ESD CDM value and removed the maximum junction temperature and maximum power dissipation temperature in Table 34: STw4810 absolute maximum ratings. 03-Sep-2007 9 Updated Section 4.3.9: Thermal shut-down. 77/78 STw4810 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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