SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DPower-On Reset Generator
DAutomatic Reset Generation After
Voltage Drop
DPrecision Voltage Sensor
DTemperature-Compensated Voltage
Reference
DProgrammable Delay Time by External
Capacitor
DSupply Voltage Range ...2 V to 6 V
DDefined RESET Output from VDD ≥1 V
DPower-Down Control Support for Static
RAM With Battery Backup
DMaximum Supply Current of 16 µA
DPower Saving Totem-Pole Outputs
DTemperature Range . . . Up to −55°C to
125°C
description
The TLC77xx family of micropower supply voltage
supervisors provide reset control, primarily in
microcomputer and microprocessor systems.
During power-on, RESET is asserted when VDD
reaches 1 V. After minimum VDD (≥2 V) is
established, the circuit monitors SENSE voltage
and keeps the reset outputs active as long as
SENSE voltage (VI(SENSE)) remains below the
threshold voltage. An internal timer delays return
of the output to the inactive state to ensure proper
system reset. The delay time, td, is determined b y
an external capacitor:
td = 2.1 × 104 × CT
Where
CT is in farads
td is in seconds
Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed
SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold
voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage
and the delay time, td, has expired.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
"&#"0 !)) '!!&"&#+
Copyright 1994 − 2003, Texas Instruments Incorporated
1
2
3
4
8
7
6
5
CONTROL
RESIN
CT
GND
VDD
SENSE
RESET
RESET
D, JG, P OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
NC
SENSE
NC
RESET
NC
NC
RESIN
NC
CT
NC
NC
CONTROL
NC
RESET
NC NC
NC
NC VDD
FK PACKAGE
(TOP VIEW)
GND
1
2
3
4
5
10
9
8
7
6
NC
CONTROL
RESIN
CT
GND
NC
VDD
SENSE
RESET
RESET
U PACKAGE
(TOP VIEW)
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control
support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor
contains additional logic intended for control of static memories with battery backup during power failure. By
driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL
driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is
automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the
battery.)
The TLC77xxI is characterized for operation over a temperature range of −40°C to 85°C; the TLC77xxQ is
characterized for operation over a temperature range of −40°C to 125°C; and the TLC77xxM is characterized
for operation over the full Military temperature range of −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TATHRESHOLD
VOLTAGE
(V) SMALL
OUTLINE (D)†CHIP
CARRIER (FK) CERAMIC DIP
(JG)
CERAMIC
DUAL
FLATPACK
(U)
PLASTIC DIP
(P)
THIN SHRINK
SMALL
OUTLINE
(PW)‡
1.1 TLC7701ID — — — TLC7701IP TLC7701IPWR
−40
°
C
2.25 TLC7725ID — — — TLC7725IP TLC7725IPWR
−40°C
to
85 C
2.63 TLC7703ID — — — TLC7703IP TLC7703IPWR
to
85°C2.93 TLC7733ID — — — TLC7733IP TLC7733IPWR
4.55 TLC7705ID — — — TLC7705IP TLC7705IPWR
1.1 TLC7701QD — — — TLC7701QP TLC7701QPWR
−40
°
C
2.25 TLC7725QD — — — TLC7725QP TLC7725QPWR
−40°C
to
125 C
2.63 TLC7703QD — — — TLC7703QP TLC7703QPWR
to
125°C2.93 TLC7733QD — — — TLC7733QP TLC7733QPWR
4.55 TLC7705QD — — — TLC7705QP TLC7705QPWR
−55°C
to
2.93 — TLC7733MFK TLC7733MJG — — —
to
125°C4.55 — TLC7705MFK TLC7705MJG TLC7705MU — —
†The D package is available taped and reeled. Add the suffix R to the device type when ordering (e.g., TLC7705QDR).
‡The PW package is only available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TLC7705QPWR).
FUNCTION TABLE
CONTROL RESIN VI(SENSE)>VIT+ RESET RESET
L L False H L
L L True H L
L H False H L
L H True L§H§
H L False H L
H L True H L
H H False H L
H H True H H§
§RESET and RESET states shown are valid for t > td.
logic symbol
¶
¶This symbol is in accordance with ANSI/IEEE Std 91−1984 and
IEC Publication 617-12.
6
1
3
2
7
SENSE
≥1
≥1
≥1RESET
5
COMP
SVITS<VIT Z1
Z2
Z3
RESIN
CT
CONTROL RESET
3
2
1
1
CX
×
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
1.1 V
R2‡
R1‡
RESET†
RESET†
VDD
GND
8
6
5
4
RESIN
CONTROL
SENSE
CT
3
1
2
7
1 MΩ
50 µA
†Outputs are totem-pole configuration. External pullup or pulldown resistors are not required.
‡Nominal values:
TLC7701
TLC7703
R1 (Typ) R2 (Typ)
TLC7733
TLC7705
750 k
910 k 290 k
450 kΩ
Ω
Ω
Ω
0∞
502 kΩ698 kΩ
TLC7725 600 k 600 k
ΩΩ
timing diagram
RESET
Output
Output
Undefined
VDD and VI(SENSE)
td
Threshold Voltages
Vres
VIT−
VIT+
ÎÎ
ÎÎ
td
t
t
VIT+
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, CONTROL, RESIN, SENSE (see Note 1) −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum low output current, IOL 10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum high output current, IOH −10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VDD) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VDD) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TL77xxI −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TL77xxQ −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TL77xxM −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 85°C
POWER RATING TA = 125°C
POWER RATING
D725 mW 5.8 mW/°C377 mW 145 mW
FK 1375 mW 11.0 mW/°C 715 mW 275 mW
JG 1050 mW 8.4 mW/°C 546 mW 210 mW
P1000 mW 8.0 mW/°C 520 mW 200 mW
PW 525 mW 4.2 mW/°C 273 mW 105 mW
U700 mW 5.5 mW/°C370 mW 150 mW
recommended operating conditions at specified temperature range
MIN MAX UNIT
Supply voltage, VDD 2 6 V
Input voltage, VI0 VDD V
High-level input voltage at RESIN and CONTROL‡, VIH 0.7×VDD V
Low-level input voltage at RESIN and CONTROL‡, VIL 0.2×VDD V
High-level output current, IOH
VDD ≥2.7 V
−2 mA
Low-level output current, IOL VDD ≥2.7 V 2 mA
Input transition rise and fall rate at RESIN and CONTROL, ∆t/∆V 100 ns/V
Operating free-air temperature range, TA
TLC77xxI −40 85
°C
Operating free-air temperature range, TATLC77xxQ −40 125 °C
Operating free-air temperature range, TATLC77xxM −55 125 °C
‡To ensure a low supply current, VIL should be kept <0.3 V and VIH > VDD −0.3 V.
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TLC77xx
UNIT
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VDD = 2 V 1.8
VOH
High-level output voltage
I
OH
= −20 µAVDD = 2.7 V 2.5
V
VOH High-level output voltage
IOH = −20 µA
VDD = 4.5 V 4.3 V
IOH = −2 mA VDD = 4.5 V 3.7
VDD = 2 V 0.2
VOL
Low-level output voltage
I
OL
= 20 µAVDD = 2.7 V 0.2
V
VOL Low-level output voltage
IOL = 20 µA
VDD = 4.5 V 0.2 V
IOL = 2 mA VDD = 4.5 V 0.5
TLC7701 1.04 1.1 1.16
Negative-going input threshold voltage,
TLC7725 2.18 2.25 2.32
V
IT−
Negative-going input threshold voltage,
SENSE (see Note 3)
TLC7703 V
DD
= 2 V to 6 V 2.56 2.63 2.70 V
VIT−
SENSE (see Note 3)
TLC7733
VDD = 2 V to 6 V
2.86 2.93 3
V
TLC7705 4.47 4.55 4.63
TLC7701 VDD = 2 V to 6 V 30 mV
TLC7725
V
hys
Hysteresis voltage, SENSE TLC7703,
VDD = 2 V to 6 V
70
mV
Vhys
Hysteresis voltage, SENSE
TLC7733, VDD = 2 V to 6 V 70 mV
TLC7705
Vres Power-up reset voltage‡IOL = 20 µA 1 V
RESIN VI = 0 V to VDD 2
II
Input current
CONTROL VI = VDD 7 15
µA
I
I
Input current
SENSE VI = 5 V 5 10 µ
A
SENSE, TLC7701 only VI = 5 V 2
RESIN = VDD,
I
DD
Supply current
RESIN = VDD,
SENSE = V
DD
≥ V
IT
max + 0.2 V 916µA
IDD
Supply current
CONTROL = 0 V, Outputs open
9
16
µA
IDD(d) Supply current during td
VDD = 5 V,
RESIN = VDD,
CONTROL = 0 V,
VCT = 0 ,
SENSE = VDD,
Outputs open 120 150 µA
CIInput capacitance, SENSE VI = 0 V to VDD 50 pF
†Typical values apply at TA = 25°C.
‡The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for
semiconductor symbology. Rise time of VDD ≥ 15 µs/V.
NOTES: 2. All characteristics are measured with CT = 0.1 µF.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be connected near the supply terminals.
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TLC77xxM
UNIT
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VDD = 2 V,
TA = 25°C 1.8
VDD = 2 V, TA = −55°C to 125°C 1.7
IOH = −20 A
VDD = 2.7 V
TA = 25°C 2.5
VOH
High-level output
IOH = −20 µA VDD = 2.7 V TA = −55°C to 125°C 2.3
V
VOH
High-level output
voltage
VDD = 4.5 V
TA = 25°C 4.3 V
voltage
VDD = 4.5 V TA = −55°C to 125°C 4.2
IOH = −2 mA
VDD = 4.5 V
TA = 25°C 3.7
IOH = −2 mA VDD = 4.5 V TA = −55°C to 125°C 3.6
VDD = 2 V
TA = 25°C 0.2
VDD = 2 V TA = −55°C to 125°C 0.2
IOL = 20 A
VDD = 2.7 V
TA = 25°C 0.2
VOL
Low-level output
IOL = 20 µA VDD = 2.7 V TA = −55°C to 125°C 0.2
V
VOL
Low-level output
voltage
VDD = 4.5 V
TA = 25°C 0.2 V
voltage
VDD = 4.5 V TA = −55°C to 125°C 0.2
IOL = 2 mA
VDD = 4.5 V
TA = 25°C 0.5
IOL = 2 mA VDD = 4.5 V TA = −55°C to 125°C 0.5
VIT−
Negative-going input threshold
TLC7733
VDD = 2 V to 6 V
2.86 2.93 3.1
V
VIT−
Negative-going input threshold
voltage, SENSE (see Note 3) TLC7705 VDD = 2 V to 6 V 4.3 4.5 4.8 V
Vhys Hysteresis voltage, SENSE VDD = 2 V to 6 V VDD = 2 V to 6 V 70 mV
Vres Power-up reset voltage‡IOL = 20 µA 1 V
RESIN VI = 0 V to VDD 2
II
Input current
CONTROL VI = VDD 7 15
µA
I
I
Input current
SENSE VI = 5 V 5 10 µ
A
SENSE, TLC7701 only VI = 5 V 2
RESIN = VDD,
I
DD
Supply current
RESIN = VDD,
SENSE = V
DD
≥ V
IT
max + 0.2 V
CONTROL = 0 V, Outputs open
916µA
IDD
Supply current
SENSE = VDD ≥ VITmax + 0.2 V
CONTROL = 0 V, Outputs open
9
16
µA
IDD(d)
Supply current during td
TLC7733 VCT = 0 ,
RESIN = VDD,
CONTROL = 0 V,
VDD = 3.3 V 250
A
IDD(d
)
Supply current during tdTLC7705
DD
CONTROL = 0 V,
SENSE = VDD,
Outputs open VDD = 5 V 120 150
µA
CIInput capacitance, SENSE VI = 0 V to VDD 50 pF
†Typical values apply at TA = 25°C.
‡The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for
semiconductor symbology. Rise time of VDD ≥ 15 µs/V.
NOTES: 2. All characteristics are measured with CT = 0.1 µF.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminals.
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics at VDD = 5 V, RL = 2 kΩ, CL = 50 pF, TA = 25°C (unless otherwise noted)
MEASURED TLC77xx
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
tdDelay time VI(SENSE) ≥ VIT+
RESET
and
RESET
RESIN = 0.7 × VDD,
CONTROL = 0.2 × VDD,
CT = 100 nF,
TA = Full range,
See timing diagram
1.1 2.1 4.2 ms
tPLH Propagation delay time,
low-to-high-level output
RESET
VIH = VIT+max + 0.2 V,
20
tPHL Propagation delay time,
high-to-low-level output
SENSE
RESET
VIH = VIT+max + 0.2 V,
VIL = VIT−min − 0.2 V,
RESIN = 0.7 × VDD,
5
s
tPLH Propagation delay time,
low-to-high-level output
SENSE
RESET
RESIN = 0.7
×
V
DD
,
CONTROL = 0.2 × VDD,
CT = NC†
5µs
tPHL Propagation delay time,
high-to-low-level output
RESET
CT = NC†
20
tPLH Propagation delay time,
low-to-high-level output
RESET
VIH = 0.7 VDD,
20 µs
tPHL Propagation delay time,
high-to-low-level output
RESIN
RESET
VIH = 0.7 × VDD,
VIL = 0.2 × VDD,
SENSE = VIT+max + 0.2 V,
40
ns
tPLH Propagation delay time,
low-to-high-level output
RESIN
RESET
SENSE = V
IT+
max + 0.2 V,
CONTROL = 0.2 × VDD,
CT = NC†
45 ns
tPHL Propagation delay time,
high-to-low-level output
RESET
CT = NC†
20 µs
tPLH Propagation delay time,
low-to-high-level output
CONTROL
RESET
VIH = 0.7 × VDD,
VIL = 0.2 × VDD,
SENSE = VIT+max + 0.2 V,
38 ns
tPHL Propagation delay time,
high-to-low-level output
CONTROL RESET
SENSE = V
IT+
max + 0.2 V,
RESIN = 0.7 × VDD,
CT = NC†38 ns
Low-level minimum pulse
duration to switch RESET
SENSE VIH = VIT+max + 0.2 V,
VIL = VIT−min − 0.2 V, 3
s
duration to switch RESET
and RESET RESIN VIL = 0.2 × VDD,
VIH = 0.7 × VDD 1
µs
trRise time RESET
and
10% to 90% 8
ns/V
tfFall time and
RESET 90% to 10% 4ns/V
†NC = No capacitor, and includes up to 100-pF probe and jig capacitance.
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics at VDD = 5 V, RL = 2 kΩ, CL = 50 pF
MEASURED TLC77xxM
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS TAMIN TYP MAX UNIT
tdDelay time VI(SENSE) ≥ VIT+ RESET
and
RESET
RESIN = 2.7 V,
CONTROL = 0.4 V,
CT = 100 nF,
See timing diagram
Full
range 1.1 2.1 4.2 ms
V = V max + 0.2 V,
25°C20
tPLH
Propagation delay
time, low-to-high-level
SENSE
RESET VIH = VIT+max + 0.2 V,
VIL = VIT−min − 0.2 V,
RESIN = 2.7 V,
Full
range 24 µs
t
PLH
time, low-to-high-level
output
SENSE
IL IT−
RESIN = 2.7 V,
CONTROL = 0.4 V,
†
25°C 5
output
RESET
CONTROL = 0.4 V,
CT = NC†Full
range 7µs
V = V max + 0.2 V,
25°C5
tPHL
Propagation delay
time, high-to-low-level
SENSE
RESET VIH = VIT+max + 0.2 V,
VIL = VIT−min − 0.2 V,
RESIN = 2.7 V,
Full
range 7µs
t
PHL
time, high-to-low-level
output
SENSE
IL IT−
RESIN = 2.7 V,
CONTROL = 0.4 V,
25°C 20
output
RESET
CONTROL = 0.4 V,
CT = NC†Full
range 24 µs
V = 2.7 V,
25°C20
tPLH
Propagation delay
time, low-to-high-level
RESIN
RESET VIH = 2.7 V,
VIL = 0.4 V,
SENSE = VIT+max + 0.2 V,
Full
range 24 µs
t
PLH
time, low-to-high-level
output
RESIN
IL
SENSE = V
IT+
max + 0.2 V,
CONTROL = 0.4 V,
†
25°C 45
output
RESET
CONTROL = 0.4 V,
CT = NC†Full
range 65 ns
V = 2.7 V,
25°C40
tPHL
Propagation delay
time, high-to-low-level
RESIN
RESET VIH = 2.7 V,
VIL = 0.4 V,
SENSE = VIT+max + 0.2 V,
Full
range 60 ns
t
PHL
time, high-to-low-level
output
RESIN
IL
SENSE = V
IT+
max + 0.2 V,
CONTROL = 0.4 V,
25°C 20
output
RESET
CONTROL = 0.4 V,
CT = NC†Full
range 24 µs
Propagation delay
25°C 38
tPLH
Propagation delay
time, low-to-high-leve
l
output
CONTROL
RESET
VIH = 2.7 V,
VIL = 0.4 V,
SENSE = VIT+max + 0.2 V,
Full
range 58 ns
Propagation delay
CONTROL RESET
IL
SENSE = V
IT+
max + 0.2 V,
RESIN = 2.7 V,
25°C 38
tPHL
Propagation delay
time, high-to-low-leve
l
output
RESIN = 2.7 V,
CT = NC†Full
range 58 ns
Low-level minimum
SENSE VIH = VIT+max + 0.2 V,
VIL = VIT−min − 0.2 V,
Full
3
s
Low-level minimum
pulse duration RESIN VIL = 0.4 V,
VIH = 2.7 V
Full
range 1µs
trRise time RESET
and
10% to 90%
Full
8
ns/V
tfFall time
and
RESET 90% to 10%
Full
range 4
ns/V
†NC = No capacitor, and includes up to 100-pF probe and jig capacitance.
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
DUT
RL
(see Note A) CL
(see Note B)
5 V
NOTES: A. For switching characteristics, RL = 2 kΩ.
B. CL = 50 pF includes jig and probe capacitance.
Figure 1. RESET AND RESET Output Configurations
VIT−
tw(L) tw(L)
VIT+max + 200 mV2.7 V VIT+
VIT−min − 200 mV
(a) RESIN (b) SENSE
0.4 V
1.5 V
tw(L)
0.7 × VDD
0.2 × VDD
0.5 × VDD
M suffixed devices
I, Q, and Y suffixed devices
Figure 2. Input Pulse Definition Waveforms
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
Normalized Input Threshold Voltage −
1.005
−40
1.004
1.003
1.002
1.001
1
0.999
0.998
0.997 −20 0 20 40 60 80 100 120
TA − Temperature − °C
VIT−(TA)/VIT− (25 C)
°
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
TEMPERATURE
Figure 4
10
−0.5
9
8
7
6
5
4
3
2
0.5 1.5 2.5 3.5 4.5 5.5 6.5
VDD − Supply Voltage − V
1
0
−1
RESIN = VDD = −1 V to 6.5 V
SENSE = GND
CONTROL = GND
CT = Open = 100 pF
TA = 25°C
− Supply Current − AµIDD
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
Figure 5
4.5
5
4
3.5
3
2.5
2
1.5
1
0.5
0 −5 −10 −15 −20 −25 −40
IOH − High-Level Output Current − mA
0
−0.5
−1
VDD = 4.5 V
RESIN = 4.5 V
SENSE = 0.5 V
CONTROL = 0 V
CT = Open = 100 pF
− High-Level Output Voltage − VVOH
5
125°C
85°C
25°C
−40°C
−55°C
0°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
−30 −35
Figure 6
−5
6
5
4
3
2
0 5 10 15 20 25 30
IOL − Low-Level Output Current − mA
1
0
−1
VDD = 4.5 V
RESIN = 4.5 V
SENSE = 5 V
CONTROL = 0 V
CT = Open = 100 pF
− Low-Level Output Voltage − VVOL
−40°C
−55°C
125°C
85°C
25°C
0°C
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 7
−1
4
2
0
−2
−4
0123456
VI − Input Voltage at SENSE − V
−6
−8
−10
−55°C
125°C
VDD = 4.5 V
CT = Open = 100 pF
8
6
− Input Current − AµII
−55°C
125°C
INPUT CURRENT
vs
INPUT VOLTAGE AT SENSE
Figure 8
0
7
6
5
4
3
50 100 150 200
Sense Threshold Overdrive − mV
2
1
0
− Minimum Pulse Duration at SENSE − sµtw
MINIMUM PULSE DURATION AT SENSE
vs
SENSE THRESHOLD OVERDRIVE
250 300 350 400
VDD = 2 V
Control = 0.4 V
RESIN = 1.4 V
CT = Open = 100 pF
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
TLC77xx
GND
0.1 µF
RESETRESIN
RESETSENSE
CONTROLCT
GND
RESET
VDD
TMS70C20
NC
100 kΩ
RESET
VDD
VDD
0.1 µF
Figure 9. Reset Controller in a Microcomputer System
VDD
GND
RESET
SENSE
CONTROL CT
RESET
GND
CS
VDD
TLC77xx
RESET
CSH1
ADD0−15
GND R/W
16
8A0−A15
D0−D7DATA0−7
R/W
32K 8
CMOS RAM
TMS370
VDD
RESIN
0.1 µF
0.1 µF
0.1 µF
Figure 10. Data Retention During Power Down Using Static CMOS RAMs
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°−ā8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,20)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°−15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE
4040082/B 03/95
0.310 (7,87)
0.290 (7,37)
0.010 (0,25) NOM
0.400 (10,60)
0.355 (9,02)
58
41
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54) 0°−ā15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/E 08/96
14 PIN SHOWN
Seating Plane
1,20 MAX
1
A
7
14
0,19
4,50
4,30
8
6,20
6,60
0,30
0,75
0,50
0,25
Gage Plane
0,15 NOM
0,65 M
0,10
0°−ā8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
SLVS087L − DECEMBER 1994 − REVISED FEBRUARY 2003
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
U (S-GDFP-F10) CERAMIC DUAL FLATPACK
4040179/B 03/95
1.000 (25,40)
0.080 (2,03)
0.250 (6,35)
0.250 (6,35)
0.019 (0,48)
0.025 (0,64)
0.300 (7,62)
0.045 (1,14)
0.006 (0,15)
0.050 (1,27)
0.015 (0,38)
0.005 (0,13)
0.026 (0,66)
0.004 (0,10)
0.246 (6,10)
0.750 (19,05)
110
56
0.250 (6,35)
0.350 (8,89)0.350 (8,89)
0.250 (6,35)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-9750901Q2A ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC
5962-9750901QPA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC
5962-9751301Q2A ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC
5962-9751301QHA ACTIVE CFP U 10 1 None A42 SNPB Level-NC-NC-NC
5962-9751301QPA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC
TLC7701ID ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM
TLC7701IDR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM
TLC7701IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7701IPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7701IPWLE OBSOLETE TSSOP PW 8 None Call TI Call TI
TLC7701IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7701QD ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7701QDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7701QP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7701QPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7701QPWLE PREVIEW TSSOP PW 8 None Call TI Call TI
TLC7701QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7703ID ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM
TLC7703IDR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM
TLC7703IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7703IPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7703IPWLE OBSOLETE TSSOP PW 8 None Call TI Call TI
TLC7703IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7703QD ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7703QDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7703QP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7703QPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7703QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7705ID ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7705IDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7705IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7705IPWLE OBSOLETE TSSOP PW 8 None Call TI Call TI
TLC7705IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7705MFKB ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC
PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2005
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC7705MJG ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC
TLC7705MJGB ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC
TLC7705MUB ACTIVE CFP U 10 1 None A42 SNPB Level-NC-NC-NC
TLC7705QD ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7705QDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7705QP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7705QPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7705QPWLE OBSOLETE TSSOP PW 8 None Call TI Call TI
TLC7705QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7725ID ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7725IDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7725IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7725IPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7725IPWLE OBSOLETE TSSOP PW 8 None Call TI Call TI
TLC7725IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7725IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7725QD ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7725QDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7725QP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7725QPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7725QPWLE OBSOLETE TSSOP PW 8 None Call TI Call TI
TLC7725QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7733ID ACTIVE SOIC D 8 75 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7733IDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7733IDRG4 PREVIEW SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7733IP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7733IPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7733IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLC7733IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC7733MFKB ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC
TLC7733MJG ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC
TLC7733MJGB ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC
TLC7733QD ACTIVE SOIC D 8 75 Pb-Free CU NIPDAU Level-2-260C-1YEAR/
PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2005
Addendum-Page 2
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
(RoHS) Level-1-220C-UNLIM
TLC7733QDR ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLC7733QP ACTIVE PDIP P 8 50 Pb-Free
(RoHS) CU NIPDAU Level-NC-NC-NC
TLC7733QPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM
TLC7733QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Mar-2005
Addendum-Page 3
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
MECHANICAL DATA
MCFP001A – JANUARY 1995 – REVISED DECEMBER 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
U (S-GDFP-F10) CERAMIC DUAL FLATPACK
4040179/B 03/95
0.080 (2,03)
0.250 (6,35)
0.019 (0,48)
4 Places
0.300 (7,62) MAX
0.045 (1,14)
0.008 (0,20)
0.050 (1,27)
0.015 (0,38)
0.005 (0,13) MIN
0.026 (0,66)
0.004 (0,10)
0.246 (6,10)
110
56
0.250 (6,35)
0.350 (8,89)0.350 (8,89)
0.250 (6,35)
0.050 (1,27)
Base and Seating Plane
0.280 (7,11)
0.230 (5,84)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
8
4
0.015 (0,38)
Gage Plane
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
MAX
0.430 (10,92)
4040082/D 05/98
0.200 (5,08) MAX
0.125 (3,18) MIN
5
0.355 (9,02)
0.020 (0,51) MIN
0.070 (1,78) MAX
0.240 (6,10)
0.260 (6,60)
0.400 (10,60)
1
0.015 (0,38)
0.021 (0,53)
Seating Plane
M
0.010 (0,25)
0.100 (2,54)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’ s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of T I products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
