SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 D Power-On Reset Generator D Automatic Reset Generation After D D D D D D D Reference Programmable Delay Time by External Capacitor Supply Voltage Range . . . 2 V to 6 V Defined RESET Output from VDD 1 V Power-Down Control Support for Static RAM With Battery Backup Maximum Supply Current of 16 A Power Saving Totem-Pole Outputs Temperature Range . . . Up to -55C to 125C CONTROL RESIN CT GND 8 2 7 3 6 4 5 VDD SENSE RESET RESET U PACKAGE (TOP VIEW) 1 2 3 4 5 NC CONTROL RESIN CT GND description 10 9 8 7 6 NC VDD SENSE RESET RESET FK PACKAGE (TOP VIEW) NC CONTROL NC VDD NC The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. NC RESIN NC CT NC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC GND NC During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD ( 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor: td = 2.1 x 104 x CT Where CT is in farads td is in seconds 1 NC SENSE NC RESET NC RESET NC Voltage Drop D Precision Voltage Sensor D Temperature-Compensated Voltage D, JG, P OR PW PACKAGE (TOP VIEW) Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time, td, has expired. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1994 - 2003, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 description (continued) In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) The TLC77xxI is characterized for operation over a temperature range of -40C to 85C; the TLC77xxQ is characterized for operation over a temperature range of -40C to 125C; and the TLC77xxM is characterized for operation over the full Military temperature range of - 55C to 125C. AVAILABLE OPTIONS PACKAGED DEVICES TA THRESHOLD VOLTAGE (V) SMALL OUTLINE (D) CHIP CARRIER (FK) CERAMIC DIP (JG) CERAMIC DUAL FLATPACK (U) PLASTIC DIP (P) THIN SHRINK SMALL OUTLINE (PW) -40C to 85 C 85C -40C to 125 C 125C -55C to 125C 1.1 TLC7701ID -- -- -- TLC7701IP TLC7701IPWR 2.25 TLC7725ID -- -- -- TLC7725IP TLC7725IPWR 2.63 TLC7703ID -- -- -- TLC7703IP TLC7703IPWR 2.93 TLC7733ID -- -- -- TLC7733IP TLC7733IPWR 4.55 TLC7705ID -- -- -- TLC7705IP TLC7705IPWR 1.1 TLC7701QD -- -- -- TLC7701QP TLC7701QPWR 2.25 TLC7725QD -- -- -- TLC7725QP TLC7725QPWR 2.63 TLC7703QD -- -- -- TLC7703QP TLC7703QPWR 2.93 TLC7733QD -- -- -- TLC7733QP TLC7733QPWR 4.55 TLC7705QD -- -- -- TLC7705QP TLC7705QPWR 2.93 -- TLC7733MFK TLC7733MJG -- -- -- 4.55 -- TLC7705MFK TLC7705MJG TLC7705MU -- -- The D package is available taped and reeled. Add the suffix R to the device type when ordering (e.g., TLC7705QDR). The PW package is only available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TLC7705QPWR). FUNCTION TABLE CONTROL L logic symbol RESIN VI(SENSE)>VIT+ RESET RESET L False H L L L True H L L H False L H True H L L H H L False H L H L True H L 1 H H False H 2 H H True H L H 1 COMP SENSE RESIN 7 S S<VIT VIT 2 1 CT CONTROL 3 1 RESET and RESET states shown are valid for t > td. x Z1 Z2 CX 1 1 Z3 5 6 RESET RESET 3 This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 functional block diagram 8 CONTROL 1 6 RESET 5 RESET 50 A RESIN SENSE VDD 2 7 R1 1 M R2 1.1 V 4 3 CT GND Outputs are totem-pole configuration. External pullup or pulldown resistors are not required. Nominal values: R1 (Typ) R2 (Typ) TLC7701 0 TLC7725 600 k 600 k TLC7703 698 k 502 k TLC7733 750 k 450 k TLC7705 910 k 290 k timing diagram VDD and VI(SENSE) VIT+ Threshold Voltages VIT+ VIT- Vres RESET Output II II t td td Output Undefined t POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range, CONTROL, RESIN, SENSE (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 7 V Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 mA Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: TL77xxI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C TL77xxQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C TL77xxM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 85C POWER RATING TA = 125C POWER RATING D 725 mW 5.8 mW/C 377 mW 145 mW FK 1375 mW 11.0 mW/C 715 mW 275 mW JG 1050 mW 8.4 mW/C 546 mW 210 mW P 1000 mW 8.0 mW/C 520 mW 200 mW PW 525 mW 4.2 mW/C 273 mW 105 mW U 700 mW 5.5 mW/C 370 mW 150 mW recommended operating conditions at specified temperature range MIN MAX UNIT Supply voltage, VDD 2 6 V Input voltage, VI 0 VDD V High-level input voltage at RESIN and CONTROL, VIH 0.7xVDD Low-level input voltage at RESIN and CONTROL, VIL High-level output current, IOH Low-level output current, IOL VDD 2.7 V Input transition rise and fall rate at RESIN and CONTROL, t/V Operating free-air temperature range, TA 0.2xVDD V -2 mA 2 mA 100 ns/V TLC77xxI -40 85 TLC77xxQ -40 125 -55 125 Operating free-air temperature range, TA TLC77xxM To ensure a low supply current, VIL should be kept < 0.3 V and VIH > VDD - 0.3 V. 4 V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 C C SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise noted) TLC77xx PARAMETER VOH VOL VIT - High-level output voltage Low-level output voltage TEST CONDITIONS MIN TYP MAX 1.8 IOH = - 20 A VDD = 2 V VDD = 2.7 V 4.3 IOH = - 2 mA VDD = 4.5 V VDD = 4.5 V VDD = 2 V VDD = 2.7 V 0.2 IOL = 20 A 0.2 IOL = 2 mA VDD = 4.5 V VDD = 4.5 V Negative-going input threshold voltage, SENSE (see Note 3) 2.5 V 3.7 0.2 1.04 1.1 1.16 TLC7725 2.18 2.25 2.32 2.56 2.63 2.70 TLC7733 2.86 2.93 3 TLC7705 4.47 4.55 4.63 TLC7701 V 0.5 TLC7701 TLC7703 UNIT VDD = 2 V to 6 V V VDD = 2 V to 6 V 30 mV VDD = 2 V to 6 V 70 mV TLC7725 Vhys TLC7703, Hysteresis voltage, SENSE TLC7733, TLC7705 Vres II IOL = 20 A Power-up reset voltage Input current RESIN VI = 0 V to VDD CONTROL SENSE VI = VDD VI = 5 V SENSE, TLC7701 only VI = 5 V 1 V 2 7 15 5 10 A 2 IDD Supply current RESIN = VDD, SENSE = VDD VITmax + 0.2 V CONTROL = 0 V, Outputs open IDD(d) Supply current during td VDD = 5 V, RESIN = VDD, CONTROL = 0 V, VCT = 0 , SENSE = VDD, Outputs open 9 16 A 120 150 A CI Input capacitance, SENSE VI = 0 V to VDD 50 pF Typical values apply at TA = 25C. The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. Rise time of VDD 15 s/V. NOTES: 2. All characteristics are measured with CT = 0.1 F. 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 F) should be connected near the supply terminals. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise noted) TLC77xxM PARAMETER VOH High-level output voltage TEST CONDITIONS IOH = - 20 A A IOH = - 2 mA VOL Low-level output voltage IOL = 20 A A IOL = 2 mA VIT - Negative-going input threshold voltage, SENSE (see Note 3) Vhys Vres Hysteresis voltage, SENSE Power-up reset voltage II IDD Input current IDD(d) 1.8 2.5 VDD = 2.7 V TA = 25C TA = - 55C to 125C 4.3 VDD = 4.5 V TA = 25C TA = - 55C to 125C TA = 25C TA = - 55C to 125C 3.7 VDD = 4.5 V TA = 25C TA = - 55C to 125C 0.2 VDD = 2 V 0.2 VDD = 2.7 V TA = 25C TA = - 55C to 125C 0.2 VDD = 4.5 V TA = 25C TA = - 55C to 125C TA = 25C TA = - 55C to 125C 0.5 VDD = 4.5 V VDD = 2 V to 6 V RESIN VI = 0 V to VDD CONTROL SENSE VI = VDD VI = 5 V SENSE, TLC7701 only VI = 5 V VDD = 2 V to 6 V Supply current during td TLC7705 VCT = 0 , RESIN = VDD, CONTROL = 0 V, SENSE = VDD, Outputs open UNIT 1.7 2.3 V 4.2 3.6 0.2 0.2 V 0.2 0.5 2.86 2.93 3.1 4.3 4.5 4.8 70 V mV 1 V 2 7 15 5 10 A 2 RESIN = VDD, SENSE = VDD VITmax + 0.2 V CONTROL = 0 V, Outputs open TLC7733 MAX TA = 25C TA = - 55C to 125C VDD = 2 V to 6 V IOL = 20 A Supply current TYP VDD = 2 V, TLC7733 TLC7705 MIN 9 VDD = 3.3 V 16 A 250 A A VDD = 5 V 120 150 CI Input capacitance, SENSE VI = 0 V to VDD 50 pF Typical values apply at TA = 25C. The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. Rise time of VDD 15 s/V. NOTES: 2. All characteristics are measured with CT = 0.1 F. 3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 F) should be placed near the supply terminals. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 switching characteristics at VDD = 5 V, RL = 2 k, CL = 50 pF, TA = 25C (unless otherwise noted) MEASURED PARAMETER td Delay time tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output tPHL FROM (INPUT) TO (OUTPUT) VI(SENSE) VIT+ RESET and RESET SENSE RESET Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tr Rise time tf Fall time TYP MAX 1.1 2.1 4.2 VIH = VIT+max + 0.2 V, VIL = VIT-min - 0.2 V, RESIN = 0.7 x VDD, CONTROL = 0.2 x VDD, CT = NC UNIT ms 5 ss 5 20 RESET RESIN RESET CONTROL Low-level minimum pulse duration to switch RESET and RESET RESIN = 0.7 x VDD, CONTROL = 0.2 x VDD, CT = 100 nF, TA = Full range, See timing diagram MIN 20 Propagation delay time, high-to-low-level output tPLH TEST CONDITIONS 20 RESET Propagation delay time, high-to-low-level output tPLH TLC77xx RESET VIH = 0.7 x VDD, VIL = 0.2 x VDD, SENSE = VIT+max + 0.2 V, CONTROL = 0.2 x VDD, CT = NC 40 ns 45 VIH = 0.7 x VDD, VIL = 0.2 x VDD, SENSE = VIT+max + 0.2 V, RESIN = 0.7 x VDD, CT = NC SENSE VIH = VIT+max + 0.2 V, VIL = VIT-min - 0.2 V, 3 RESIN VIL = 0.2 x VDD, VIH = 0.7 x VDD 1 RESET and RESET s 20 s 38 ns 38 ns ss 10% to 90% 8 90% to 10% 4 ns/V NC = No capacitor, and includes up to 100-pF probe and jig capacitance. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 switching characteristics at VDD = 5 V, RL = 2 k, CL = 50 pF MEASURED PARAMETER td Delay time TLC77xxM FROM (INPUT) TO (OUTPUT) VI(SENSE) VIT+ RESET and RESET RESET tPLH Propagation delay time, low-to-high-level output SENSE RESET RESET tPHL Propagation delay time, high-to-low-level output SENSE RESET RESET tPLH Propagation delay time, low-to-high-level output RESIN RESET RESET tPHL Propagation delay time, high-to-low-level output RESIN RESET tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output CONTROL Low-level minimum pulse duration tr Rise time RESET TEST CONDITIONS RESIN = 2.7 V, CONTROL = 0.4 V, CT = 100 nF, See timing diagram VIH = VIT+max + 0.2 V, VIL = VIT-min - 0.2 V, RESIN = 2.7 V, CONTROL = 0.4 V, CT = NC VIH = VIT+max + 0.2 V, VIL = VIT-min - 0.2 V, RESIN = 2.7 V, CONTROL = 0.4 V, CT = NC VIH = 2.7 V, VIL = 0.4 V, SENSE = VIT+max + 0.2 V, CONTROL = 0.4 V, CT = NC VIH = 2.7 V, VIL = 0.4 V, SENSE = VIT+max + 0.2 V, CONTROL = 0.4 V, CT = NC VIH = 2.7 V, VIL = 0.4 V, SENSE = VIT+max + 0.2 V, RESIN = 2.7 V, CT = NC VIH = VIT+max + 0.2 V, VIL = VIT-min - 0.2 V, VIL = 0.4 V, VIH = 2.7 V SENSE RESIN RESET and RESET 10% to 90% tf Fall time 90% to 10% NC = No capacitor, and includes up to 100-pF probe and jig capacitance. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TA Full range MIN TYP MAX 1.1 2.1 4.2 25C 20 Full range 24 25C 5 Full range 7 25C 5 Full range 7 25C 20 Full range 24 25C 20 Full range 24 25C 45 Full range 65 25C 40 Full range 60 25C 20 Full range 24 25C 38 Full range 58 25C 38 Full range 58 Full range Full range UNIT ms s s s s s ns ns s ns ns 3 ss 1 8 ns/V 4 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION 5V DUT RL (see Note A) CL (see Note B) NOTES: A. For switching characteristics, RL = 2 k . B. CL = 50 pF includes jig and probe capacitance. Figure 1. RESET AND RESET Output Configurations I, Q, and Y suffixed devices tw(L) 0.7 x VDD 0.5 x VDD 0.2 x VDD M suffixed devices tw(L) tw(L) 2.7 V 1.5 V 0.4 V VIT+max + 200 mV VIT+ VIT-min - 200 mV VIT- (a) RESIN (b) SENSE Figure 2. Input Pulse Definition Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 NORMALIZED INPUT THRESHOLD VOLTAGE vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 10 1.005 9 1.004 8 I DD - Supply Current - A Normalized Input Threshold Voltage - VIT- (TA )/V IT- (25 C) TYPICAL CHARACTERISTICS 1.003 1.002 1.001 1 0.999 7 6 5 4 3 RESIN = VDD = -1 V to 6.5 V SENSE = GND CONTROL = GND CT = Open = 100 pF TA = 25C 2 1 0.998 0.997 -40 0 -20 0 20 40 60 80 100 -1 -0.5 120 0.5 TA - Temperature - C 1.5 4 0C 3.5 -55C 125C 3 2.5 85C 2 25C 1.5 -40C 1 VDD = 4.5 V RESIN = 4.5 V SENSE = 0.5 V CONTROL = 0 V CT = Open = 100 pF -1 0 -5 -10 -15 -20 -25 -30 -35 -40 VOL - Low-Level Output Voltage - V VOH - High-Level Output Voltage - V 4.5 5 5 6.5 4 VDD = 4.5 V RESIN = 4.5 V SENSE = 5 V CONTROL = 0 V CT = Open = 100 pF 125C 85C 25C 0C 3 2 -40C 1 -55C 0 -1 -5 0 5 10 Figure 6 Figure 5 POST OFFICE BOX 655303 15 20 25 IOL - Low-Level Output Current - mA IOH - High-Level Output Current - mA 10 5.5 6 5 -0.5 4.5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 0 3.5 Figure 4 Figure 3 0.5 2.5 VDD - Supply Voltage - V * DALLAS, TEXAS 75265 30 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 TYPICAL CHARACTERISTICS INPUT CURRENT vs INPUT VOLTAGE AT SENSE 8 VDD = 4.5 V CT = Open = 100 pF 6 125C 4 I I - Input Current - A -55C 2 0 -2 125C -4 -55C -6 -8 -10 -1 0 1 2 3 4 5 6 VI - Input Voltage at SENSE - V Figure 7 MINIMUM PULSE DURATION AT SENSE vs SENSE THRESHOLD OVERDRIVE t w - Minimum Pulse Duration at SENSE - s 7 VDD = 2 V Control = 0.4 V RESIN = 1.4 V CT = Open = 100 pF 6 5 4 3 2 1 0 0 50 100 150 200 250 300 350 400 Sense Threshold Overdrive - mV Figure 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 APPLICATION INFORMATION VDD 0.1 F 100 k 0.1 F VDD VDD TLC77xx RESIN RESET SENSE RESET CT RESET RESET TMS70C20 NC CONTROL GND GND Figure 9. Reset Controller in a Microcomputer System VDD 0.1 F VDD TLC77xx RESIN 0.1 F 0.1 F SENSE RESET CONTROL VDD CT RESET CSH1 CS RESET 32K 8 CMOS RAM GND TMS370 16 ADD0 -15 8 DATA0 -7 A0 -A15 D0 -D7 R/W R/W GND GND Figure 10. Data Retention During Power Down Using Static CMOS RAMs 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0- 8 A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 MECHANICAL DATA FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 25 5 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. 14 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 MECHANICAL DATA JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE 0.400 (10,20) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.063 (1,60) 0.015 (0,38) 0.100 (2,54) 0-15 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 MECHANICAL DATA P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0- 15 0.010 (0,25) M 0.010 (0,25) NOM 4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX 0,10 PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SLVS087L - DECEMBER 1994 - REVISED FEBRUARY 2003 MECHANICAL DATA U (S-GDFP-F10) CERAMIC DUAL FLATPACK 0.250 (6,35) 0.246 (6,10) 0.006 (0,15) 0.004 (0,10) 0.080 (2,03) 0.050 (1,27) 0.045 (1,14) 0.026 (0,66) 0.300 (7,62) 0.350 (8,89) 0.250 (6,35) 1 0.350 (8,89) 0.250 (6,35) 10 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.250 (6,35) 5 6 0.025 (0,64) 0.005 (0,13) 1.000 (25,40) 0.750 (19,05) 4040179 / B 03/95 NOTES: A. B. C. D. E. 18 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9750901Q2A ACTIVE LCCC FK 20 1 None 5962-9750901QPA ACTIVE CDIP JG 8 1 None Lead/Ball Finish MSL Peak Temp (3) POST-PLATE Level-NC-NC-NC A42 SNPB Level-NC-NC-NC 5962-9751301Q2A ACTIVE LCCC FK 20 1 None 5962-9751301QHA ACTIVE CFP U 10 1 None POST-PLATE Level-NC-NC-NC A42 SNPB Level-NC-NC-NC 5962-9751301QPA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC TLC7701ID ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM TLC7701IDR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM TLC7701IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 150 None CU NIPDAU Level-1-220C-UNLIM None Call TI TLC7701IPW ACTIVE TSSOP PW 8 TLC7701IPWLE OBSOLETE TSSOP PW 8 TLC7701IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLC7701QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7701QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7701QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 150 None CU NIPDAU Level-1-220C-UNLIM None Call TI 2000 None CU NIPDAU Level-1-220C-UNLIM TLC7701QPW ACTIVE TSSOP PW 8 TLC7701QPWLE PREVIEW TSSOP PW 8 TLC7701QPWR ACTIVE TSSOP PW 8 Call TI Call TI TLC7703ID ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM TLC7703IDR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM TLC7703IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 150 None CU NIPDAU Level-1-220C-UNLIM None Call TI TLC7703IPW ACTIVE TSSOP PW 8 TLC7703IPWLE OBSOLETE TSSOP PW 8 TLC7703IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLC7703QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7703QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7703QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC7703QPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM TLC7703QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLC7705ID ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7705IDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7705IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC7705IPWLE OBSOLETE TSSOP PW 8 None Call TI TLC7705IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU TLC7705MFKB ACTIVE LCCC FK 20 1 None Addendum-Page 1 Call TI Call TI Level-1-220C-UNLIM POST-PLATE Level-NC-NC-NC PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TLC7705MJG ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC TLC7705MJGB ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC TLC7705MUB ACTIVE CFP U 10 1 None A42 SNPB Level-NC-NC-NC TLC7705QD ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7705QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7705QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 150 None CU NIPDAU Level-1-220C-UNLIM None Call TI TLC7705QPW ACTIVE TSSOP PW 8 TLC7705QPWLE OBSOLETE TSSOP PW 8 TLC7705QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLC7725ID ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7725IDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7725IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC7725IPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM TLC7725IPWLE OBSOLETE TSSOP PW 8 TLC7725IPWR ACTIVE TSSOP PW 8 2000 TLC7725IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) TLC7725QD ACTIVE SOIC D 8 75 TLC7725QDR ACTIVE SOIC D 8 TLC7725QP ACTIVE PDIP P Call TI None Call TI None CU NIPDAU Call TI Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC 150 None CU NIPDAU Level-1-220C-UNLIM None Call TI TLC7725QPW ACTIVE TSSOP PW 8 TLC7725QPWLE OBSOLETE TSSOP PW 8 TLC7725QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLC7733ID ACTIVE SOIC D 8 75 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7733IDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7733IDRG4 PREVIEW SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7733IP ACTIVE PDIP P 8 Call TI 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC7733IPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM TLC7733IPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLC7733IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLC7733MFKB ACTIVE LCCC FK 20 1 None TLC7733MJG ACTIVE CDIP JG 8 1 None TLC7733MJGB ACTIVE CDIP JG 8 1 TLC7733QD ACTIVE SOIC D 8 75 Addendum-Page 2 POST-PLATE Level-NC-NC-NC A42 SNPB Level-NC-NC-NC None A42 SNPB Level-NC-NC-NC Pb-Free CU NIPDAU Level-2-260C-1YEAR/ PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TLC7733QDR ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1YEAR/ Level-1-220C-UNLIM TLC7733QP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC TLC7733QPW ACTIVE TSSOP PW 8 150 None CU NIPDAU Level-1-220C-UNLIM TLC7733QPWR ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM Lead/Ball Finish (RoHS) MSL Peak Temp (3) Level-1-220C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 MECHANICAL DATA MCER001A - JANUARY 1995 - REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MCFP001A - JANUARY 1995 - REVISED DECEMBER 1995 U (S-GDFP-F10) CERAMIC DUAL FLATPACK Base and Seating Plane 0.250 (6,35) 0.246 (6,10) 0.045 (1,14) 0.026 (0,66) 0.008 (0,20) 0.004 (0,10) 0.080 (2,03) 0.050 (1,27) 0.300 (7,62) MAX 1 0.019 (0,48) 0.015 (0,38) 10 0.050 (1,27) 0.280 (7,11) 0.230 (5,84) 5 6 4 Places 0.005 (0,13) MIN 0.350 (8,89) 0.250 (6,35) 0.350 (8,89) 0.250 (6,35) 4040179 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MPDI001A - JANUARY 1995 - REVISED JUNE 1999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) 0.355 (9,02) 8 5 0.260 (6,60) 0.240 (6,10) 1 4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gage Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.430 (10,92) MAX 0.010 (0,25) M 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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