Integrated
Circuit
Systems, Inc.
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Recommended Application:
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS97ULP877, 98ULPA877A
• Ideal for DDR2 400,533, and 667
Product Features:
• 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
with parity check functionality
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
• Supports LVCMOS switching levels on CSR and
RESET inputs
• Low voltage operation
VDD = 1.7V to 1.9V
• Available in 96 BGA package
• Drop-in replacement for ICSSSTUA32864
• Green packages available
25-Bit Configurable Registered Buffer for DDR2
Pin Configuration
96 Ball BGA
(Top View)
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
65
4
3
21
Functionality Truth Table
Inputs Outputs,
Dn,
RST DCS CSR CK CK DODT, Qn QCS QODT,
DCKE QCKE
HLL↑↓ LLL L
HLL↑↓ HH L H
H L L L or H L or H X Q0Q0Q0
HLH↑↓ LLL L
HLH↑↓ HH L H
H L H L or H L or H X Q0Q0Q0
HHL↑↓ LLH L
HHL↑↓ HHH H
H H L L or H L or H X Q0Q0Q0
HHH↑↓ LQ
0HL
HHH↑↓ HQ
0HH
H H H L or H L or H X Q0Q0Q0
L X or X or X or X or X or L L L
Floating Floating Floating Floating Floating
2
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Ball Assignments
Register A (C0 = 0, C1 = 1)
C0 = 0, C1 = 0
Register B (C0 = 1, C1 = 1)
25 bit 1:1 Register
14 bit 1:2 Registers
6
Q15Q2GNDGNDD15D2
B
Q16Q3VDDVDDD16D3
C
Q17Q5VDDVDDD17D5
E
Q18Q6GNDGNDD18D6
F
Q19Q8GNDGNDD19D8
K
Q20Q9VDDVDDD20D9
L
NCQCSDCS
QERR
CSR
CK
RST
GNDGNDCK
H
NCQODTGNDGNDDODT
D
NCQCKEVDDVREFPPODCKE
A
Q24Q13VDDVDDD24D13
R
Q25Q14VDDVREFD25D14
T
ZOLZOHVDDVDD
J
C0C1VDDVDDPAR_IN
G
Q21Q10GNDGNDD21D10
M
Q22Q11VDDVDDD22D11
N
Q23Q12GNDGNDD23D12
P
54321
6
Q2BQ2A
GNDGNDNC
D2
B
Q3BQ3A
VDDVDDNC
D3
C
Q5BQ5A
VDDVDDNCD5
E
Q6BQ6A
GNDGNDNC
D6
F
Q8B
Q9B
QCSBGNDGNDCK
H
QODTBQODTAGNDGNDDODT
D
QCKEBQCKEAVDDVREFPPODCKE
Q13B
Q14B
ZOLZOHVDDVDD
J
C0C1
VDDVDD
PAR_IN
G
Q10B
Q11B
Q12B
5
Q8A
Q9A
Q13A
Q14A
Q10A
Q11A
Q12A
4
VDD
GND
VDD
GND
VDD
GND
VDD
3
VREF
GND
VDD
GND
VDD
GND
VDD
2
NC
NC
NC
NC
NC
NC
NC
1
D8
D9
D10
D11
D12
D14
D13
A
K
L
M
N
P
R
T
QCSADCS
QERR
CSRCK
RST
652143
Q13BQ13ANCD13 VDDVDD
R
Q10BQ10ANCD10 GNDGND
M
Q9BQ9ANCD9 VDDVDD
L
Q8BQ8ANCD8 GNDGND
K
QCSBQCSA
CK GNDGND
H
Q6BQ6ANCD6 GNDGND
F
Q5BQ5ANCD5 VDDVDD
E
ZOLZOHVDDVDD
J
QODTBQODTANCDODT VDDVDD
N
QCKEBQCKEANCDCKE VDDVREF
T
Q4BQ4AD4 GNDGND
D
Q3BQ3ANCD3 VDDVDD
C
Q2BQ2ANCD2 GNDGND
B
Q1BQ1APPOD1 VDDVREF
A
C0C1
PAR_IN VDDVDD
G
Q12BQ12ANCD12 GNDGND
P
DCS
QERR
CSRCK
RST
3
ICSSSTUB32866B
Advance Information
1165A—3/21/07
General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUB32866B operates
from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
A - Pair Configuration (CO1 = 0, CI1 = 1 and CO2 = 0, CI2 = 1)
Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register.
The second register produces to PPO and QERR signals. The QERR of the first register is left floating. The valid
error information is latched on the QERR output of the second register. If an error occurs QERR is latched low for
two cycles or until Reset is low.
B - Single Configuration (CO = 0, C1 = 0)
The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers
are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when
RST is low all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be
held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied,
RST must be held in the low state during power up.
In the DDR-II RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK.
Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared
and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when
coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until
the input receivers are fully enabled, the design of the ICSSSTUB32866B must ensure that the outputs will remain
low, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and
CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority
over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the
CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for
the other D data inputs. Package options include 96-ball LFBGA (MO-205CC).
Parity and Standby Functionality Truth Table
Rst DCS CSR CK CK Sum of Inputs = H
(D1 - D25) PAR_IN PPO QERR
HLX↑↓ Even LLH
HLX↑↓ Odd L H L
HLX↑↓ Even H H L
HLX↑↓ Odd H L H
HHL↑↓ Even LLH
HHL↑↓ Odd H H L
HHH↑↓ XXPPO
0QERR0
H X X L or H L or H X X PPO0QERR0
LX or
Floating
X or
Floating
X or
Floating
X or
Floating X or Floating X or
Floating LH
3. PAR_IN arrives two clock cycles after the data to which it applies when CO = 1.
Inputs Outputs
4. Assume QERR is high at the CK↑ and CK↓ crossing. If QERR is low it stays latched low for two
clock cycles on until Rst is low.
1. CO = 0 and CI = 0, Data inputs are D2, D3, D5, D6, D8 - D25.
CO = 0 and CI = 1, Data inputs are D2, D3, D5, D6, D8 - D14
CO = 1 and CI = I, Data inputs are D1 - D6, D8 - D10, D12, D13
2. PAR_IN arrives one clock cycle after the data to which it applies when CO = 0.
4
ICSSSTUB32866B
Advance Information
1165A—3/21/07
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Ball Assignment
5
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Block Diagram for 1:1 mode (positive logic)
O
1Q1A
R
1D
C1
RST
CK
CK
V
REF
D1
DCKE
DODT
DCS
TO 21 OTHER CHANNELS
CSR
QOTDA
R
D
C1
QCSA#
R
1D
C1
QCKEA
R
D
C1
Q1B
(1)
NOTE:
1. Disabled in 1:1 configuration.
6
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Block Diagram for 1:2 mode (positive logic)
O
1Q1
A
Q1
B
R
1D
C1
RST
CK
CK
V
REF
D1
DCKE
DODT
DCS
TO 10 OTHER CHANNELS
CSR
R
1D
C1
R
1D
C1
R
1D
C1
QCS
A
#
QCS
B
#
QODT
A
QODT
B
QCKE
A
QCKE
B
(1)
NOTE:
1. Disabled in 1:1 configuration.
(1)
(1)
(1)
7
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
D
CK
R
G2
RST
J1
CK
H1
CK
Parity
22
22
D2
A2
D2•D3,
D5•D6,
D8•D25
D2•D3,
D5•D6,
D8•D25
LPS0
D2•D3,
D5•D6,
D8-D25
22
PAR_IN G1
1
0
22
R
CK
2•Bit
Counter
A3, T3
VREF
0
1
C0 G6
C1 G5
LPS1
(internal node)
CE
D
CK
R
D
CK
R
D
CK
R
D
CK
R
0
1
CE
Q
QQ
Q
Q
Q2 Q3,
Q5 Q6,
Q8 Q25
(internal node)
PPO
QERR
Generator
Figure 6 Parity l ogic diagram for 1:1 reg ister config uratio n (positive logic): C0=0, C1=0
8
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
Figure 7 — Parity logic diagram for 1:2 register-A configuration (positive logic); C0=0, C1=1
D
CK
R
G2
RST
J1
CK
H1
CK
Parity
Generator
11
11
D2
A2
PPO
QERR
D2•D3,
D5•D6,
D8•D14
D2•D3,
D5•D6,
D8•D14
LPS0
(internal node)
D2•D3,
D5•D6,
D8-D14
11
PAR_IN G1
1
0
R
CK
2•Bit
Counter
A3, T3
VREF
0
1
C0 G6
C1 G5
LPS1
(internal node)
CE
D
CK
R
D
CK
R
D
CK
R
D
CK
R
0
1
CE
Q2A•Q3A,
Q5A•Q6A,
Q8A•Q14A
11
Q2B•Q3B,
Q5B•Q6B,
Q8B•Q14B
11
Q
QQQ
Q
9
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
D
CK
R
G2
RST
J1
CK
H1
CK
Parity
Generator
11
11
D2
A2
PPO
QERR
D1•D6,
D8•D13
D1•D6,
D8•D13
LPS0
(internal node)
D1•D6,
D8-D13 11
PAR_IN G1
1
0
R
CK
2•Bit
Counter
A3, T3
VREF
0
1
C0 G6
C1 G5
LPS1
(internal node)
CE
D
CK
R
D
CK
R
D
CK
R
D
CK
R
0
1
CE
Q1A•Q6A,
Q8A•Q13A
11
Q1B•Q6B,
Q8B•Q13B
11
Q
QQQ
Q
Fi gure 8 Parity logic diagram for 1:2 register-B configuration (positive logic); CO=1, C1=1
10
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
‡
CK
D1•D25 †
RST
tsu
tpd
CK to PPO
th
tsu th
tpdm , t pdmss
CK to Q
DCS
CSR
CK
Q1•Q25
PAR_IN †
nn + 1n + 2
PPO
n + 3 n + 4
tPHL
CK to QERR
QERR ‡
tPHL , t PLH
CK to QERR
tact
H, L, or X H or L
Data to QERR Latency
After RST is switched from low to high, all data and PAR _IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error.
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
ACT
Figure 9 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST Switches from L to H
11
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
CK
D1•D25
RST
tsu
tpd
CK to PPO
th
tsu th
tpdm , t pdmss
CK to
DCS
CSR
CK
Q1•Q25
PAR_IN
n n + 1 n + 2
PPO
n + 3 n + 4
QERR †
tPHL or t PLH
CK to QERR
Unknown input
event H or L
Output signal is dependent on
the prior unknown input event
Data to PPO Latency
Data to QERR Latency
Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST being held high
Figure 10
If the data is clocked in on the n clock pulse , the QERR output signal will be gene rated on the n+ 2 clock pulse, and it will be valid on
the n+3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RST is driven low.
12
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
CK †
D1•D25 †
RST
DCS †
CSR †
CK †
Q1•Q25
PAR_IN †
PPO
QERR
tinact
tRPHL
RST to Q
tRPHL
RST to PPO
tRPLH
RST to QERR
H, L, or X H or L
Figure 11 — Timing diagram for SSTU32866 used as a single device; C0=0, C1=0;
RST switches from H to L
After RST is switched from high to low, all data and clock unouts signals must be set and held at valid logic levels (not floating) for
a minimum time of t max.
INACT
13
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
CK
D1•D14 †
RST
tsu
tpd
CK to PPO
th
tsu th
tpdm , t pdmss
CK to Q
DCS
CSR
CK
Q1•Q14
PAR_IN †
n n + 1 n + 2
PPO
n + 3 n + 4
tPHL
CK to QERR
QERR# ‡
(not used)
tPHL , t PLH
CK to QERR
tact
H, L, or X H or L
Data to QERR#
Latency
Figure 12 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST switches from L to H
After RST is switched from low to high, all data and PAIR_I N inputs signals must be set and held low for a minimum time of t
max, to avoid false error
If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on
the n+2 clock pulse.
ACT
†
‡
14
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
†
CK
D1•D14
RST
tsu
tpd
CK to PPO
th
tsu th
tpdm , t pdmss
CK to Q
DCS
CSR
CK
Q1•Q14
PAR_IN
n n + 1 n + 2
PPO
n + 3 n + 4
QERR †
(not used)
tPHL or t PLH
CK to QERR
Unknown input
event H or L
Output signal is dependent on
the prior unknown input event
Data to QERR
Latency
Data to PPO
Latency
Figure 13 — Timing diagram for the first SSTU32866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST being held high
If the data is clocked in on the clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be vali d o n
the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RST is driv en low .
15
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
† from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a
minimum time of t
INACT
max
CK †
D1•D14 †
RST#
DCS# †
CSR# †
CK# †
Q1•Q14
PAR_IN †
PPO
QERR#
(not used)
tinact
tRPHL
RST# to Q
tRPHL
RST# to PPO
tRPLH
RST# to QERR#
H, L, or X H or L
After is switchedRST#
Figure 14 — Timing diagram for the first SSTU32 866 (1:2 register-A configuration) device used in
pair; C0=0, C1=1; RST# switches from H to L
16
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
‡ PAR_IN is driven from PPO of the first SSTU32866 device .
§ If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse.
CK
D1•D14 †
RST#
tsu
tpd
CK to PPO
th
tsu th
tpdm , t pdmss
CK to Q
DCS#
CSR#
CK#
Q1•Q14
PAR_IN †‡
n n + 1 n + 2
PPO
(not used)
n + 3 n + 4
tPHL
CK to QERR#
QERR# §
tPHL , t PLH
CK to QERR#
tact
H, L, or X H or L
Data to QERR# Latency
Figure 15 — Timing diagram for the second SSTU32866 (1:2 register-B configuration) device used in
pair; C0=1, C1 =1; RST# switches from L to H
After RST# switched from low to high, all data and PAR_IN inputs signals must be set and held low for a minimum time of t
max, to avoid false error.
ACT
†
17
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
18
ICSSSTUB32866B
Advance Information
1165A—3/21/07
2. Device standard (cont'd)
CK †
D1•D14 †
RST#
DCS# †
CSR# †
CK# †
Q1•Q14
PAR_IN †
PPO
(not used)
QERR#
tinact
tRPHL
RST# to Q
tRPHL
RST# to PPO
tRPLH
RST# to QERR#
H, L, or X H or L
†
Figure 17— Timing diagram for the second SSTU32866 (1:2 register-B configura tion) device used i
n
pair; C0=1, C1=1; RST# switches from H to L
After RST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a
munimum time of t max.
INACT
19
ICSSSTUB32866B
Advance Information
1165A—3/21/07
:TUPNIATAD:TUPTUOATADOCIC
,6D,5D,3D,2D
52D-8D
,6D,5D,3D,2D
52D-8D 00
,6D,5D,3D,2D
41D-8D
,6D,5D,3D,2D
41D-8D 01
-8D,6
D-1D
31D,21D,01D
-8D,6D-1D
31D,21D,01D 11
* Register Configurations
20
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Recommended Operating Conditions
PARAMETER MIN TYP MAX UNITS
VDDQ 1.7 1.8 1.9
VREF 0.49 x VDD 0.5 x VDD 0.51 x VDD
VTT VREF - 0.04 VREF VREF + 0.04
VIInput Voltage 0 VDDQ
VIH
(
DC
)
DC Input High Voltage VREF + 0.125
VIH
(
AC
)
AC Input High Voltage VREF + 0.250
VIL
(
DC
)
DC Input Low Voltage VREF - 0.125
VIL
(
AC
)
AC Input Low Voltage VREF - 0.250
VIH Input High Voltage Level 0.65 x VDDQ
VIL Input Low Voltage Level 0.35 x VDDQ
VICR Common mode Input Range 0.675 1.125
VID Differential Input Voltage 0.600
IOH -8
IOL 8
TA070°C
1Guaranteed by design, not 100% tested in production.
mA
Note: RST and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless
R
ST is low.
V
DESCRIPTION
I/O Supply Voltage
Reference Voltage
Operating Free-Air Temperature
RST,
C0, C1
CK, CK
Low-Level Output Current
Termination Voltage
High-Level Output Current
Data Inputs
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V
Input Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +2.5V
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . . . . ±50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . ±50mA
Continuous Output Current. . . . . . . . . . . . . . . ±50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . ±100mA
Package Thermal Impedance3. . . . . . . . . . . . . . . 36°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
21
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN MAX
dV/dt_r 1 4 V/ns
dV/dt_f 1 4 V/ns
dV/dt_Δ
1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER V
DD
= 1.8V ± 0.1V UNIT
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 1.8 +/-0.1V (unless otherwise stated)
SYMBOL PARAMETERS VDD MIN TYP MAX UNITS
VIK II = -18mA -1.2
VOH IOH = -6mA 1.7V 1.2
VOL IOL = 6mA 1.7V 0.5
IIAll Inputs(2) VI = VDD or GND 1.9V -5 5 µA
Standby (Static)
RESET
= GND 100 µA
Operating (Static)(3) VI = VIH(AC) or VIL(AC),
RESET = VDD 40 mA
Dynamic operating
(clock only)
RESET = VDD,
VI = VIH(AC) or VIL(AC),
CLK and CLK switching
50% duty cycle.
39 µA/clock
MHz
Dynamic Operating
(per each data input)
1:1 mode
19
Dynamic Operating
(per each data input)
1:2 mode
35
Data Inputs 2.5 3.5
CLK and
CLK
23
RESET 2.5
CONDITIONS
V
µA/ clock
MHz/data
IDD
IO = 0
1.9V
IDDD 1.8V
RESET = VDD,
VI = VIH(AC) or VIL (AC),
CLK and CLK switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
pF
VICR = 1.25V, VI
(
PP
)
= 360mV
VI = VDD or GND
Ci
VI = VREF ±350mV
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - PAR_IN leakage current is ±17μA due to weak pull-down resistor. Allows this device to be used as replacement
for SSTUB32864B (has no parity).
3 - Static operating current will be greater than 40mA if both CLK and CLK are pulled HIGH or LOW.
22
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol Parameter Measurement
Conditions MIN MAX Units
fmax Max input clock frequency 410 MHz
tPDM
Propagation delay, single
bit switchin
g
CK↑ to CK↓ QN 1.1 1.9 ns
tP
D
Propagation delay CK↑ to CK↓ to PPO 0.5 1.8 ns
tLH
Low to High propagation
delay 1.2 3 ns
tHL
High to low propagation
delay 12.4ns
tPDMSS
Propagation delay
simultaneous switchin
g
CK↑ to CK↓ QN - 2 ns
tPHL
High to low propagation
delay RESET ↓ to QN↓3ns
tPHL
High to low propagation
delay RESET ↓ to PPO↓3ns
tPLH
Low to High propagation
delay RESET ↓ to QERR↑3ns
2. Guaranteed by design, not 100% tested in production.
CK↑ to CK↓ to QERR
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN MAX
fclock Clock frequency 410 MHz
tWPulse duration, CK, CK HIGH or LOW 1 ns
tACT Differential inputs active time (See Notes 1 and 2) 10 ns
tINACT Differential inputs inactive time (See Notes 1 and 3) 15 ns
tsu Setup time
DCS before CK↑, CK↓,
CSR high; CSR before CK↑,
CK↓, DCS high
0.8 ns
tsu Setup time DCS before CK↑, CK↓,
CSR
low 0.5 ns
tsu Setup time DODT, DCKE and data before
CK↑,
CK
↓0.5 ns
tsu Setup time PAR_IN before CK↑, CK↓0.5 ns
Hold time DCS, DODT, DCKE and Q
after CK↑,
CK
↓0.4 ns
Hold time PAR_IN after CK↑, CK↓0.4 ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/
CLK
signal input slew rate of 1V/ns.
SYMBOL
Notes:
tH
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 1.8V ±0.1V UNITSPARAMETERS
23
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM.
CL=30pF RL= 1000Ω
DUT
Out
RL=100Ω
CK Inputs
TL=50ΩTL=350ps,50Ω
Test Point
VDD
0V
VDD/2
LVCMOS
RST#
Input
IDD
VDD/2
tINACT tACT
10%
90%
CK#
VICR VID
tPLH tPHL
Output
VOH
VOL
VICR
VTT VTT
VOH
VOL
VIH
VIL
tRPHL
VDD/2
VTT
LVCMOS
RST#
Input
Output
VICR VID
VICR
Input
tW
VREF
VIH
VIL
VREF
Input
VICR VID
tSU tH
CK#
CK
VDD
RL= 1000Ω
Test Point
Test Point
CK
(1)
(2)
CK#
CK
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Figure 6 ⎯ Parameter Measurement Information (VDD = 1.8V ± 0.1V)
24
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO =
50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
CL=10pF
RL=50Ω
DUT
Out Test Point
VDD
VOH
80%
20%
VOL
Output
dv_f
dt_f
CL=10pF RL=50Ω
DUT
Out Test Point
VOL
20%
80%
VOH
Output
dv_r
dt_r
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
HIGH-TO-LOW SLEW-RATE MEASUREMENT
LOAD CIRCUIT - LOW-TO-HIGH SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
(1)
(1)
Figure 7 ⎯ Output Slew-Rate Measurement Information (VDD = 1.8V ± 0.1V)
25
ICSSSTUB32866B
Advance Information
1165A—3/21/07
CL=10pF
(1)
RL=1KΩ
DUT
Out Test Point
VDD
VOH
VCC
Output
Waveform 2
LVCMOS
RESET#
tPLH
VCC/2
0.15V 0V
0V
VOH
Output
Waveform 2
0.15V 0V
VICR
tHL
VICR VI(PP)
Timing Inputs
VCC
VICR
tHL
Timing Inputs VICR VI(PP)
Output
Waveform 1 VCC/2
VOL
Load Circuit, error output measurements
Voltage Waveforms, open-drain output LOW-to-HIGH with respect to RESET# input
Voltage Waveforms, open-drain output HIGH-to-LOW with respect to clock inputs
Voltage Waveforms, open-drain output LOW-to-HIGH with respect to clock inputs
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO =
50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
26
ICSSSTUB32866B
Advance Information
1165A—3/21/07
CL=5pF (1)
RL=1KΩ
DUT
Out Test Point
VTT
VICR
tHL
VI(PP)
Output VTT
CLK
CLK
VICR
tHL
Partial parity out load circuit
Partial parity out voltage waveform, propagation
delay time with respect to CLK input
VTT =VDD/2
VI(P-P) = 600mV
tPLH and tPHL are the same as tPD
VTT =VDD/2
tPLH and tPHL are the same as tPD
VIH =VREF + 250mV (AC voltage levels) for differential inputs. VIH =VDD for LVCMOS inputs.
VIL =VREF - 250mV (AC voltage levels) for differential inputs. VIL =VDD for LVCMOS inputs.
VIH
Output
VDD/2
Input
LVCMOS RESET
VIL
VOH
VOL
VTT
tPHL
Partial parity out voltage waveform, propagation
delay time with respect to RESET input
27
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Ordering Information
ICSSSTUB32866Bz(LF)T
D E T e HORIZ VERT TOTAL d h b c
Min/Max Min/Max Min/Max
13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 0.25/0.41 0.75 0.75
11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 0.25/0.35 0.875 0.875
MO-205
10-0055C
* Source Ref.: JEDEC Publication 95,
ALL DIMENSIONS IN MILLIMETERS
REF. DIMENSIONS ----- BALL GRID ----- Max.
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
Example:
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
H = LFBGA (standard size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXX y z (LF) T
SEATING
PLANE
0.12 C
C
A
B
C
D
A1
D
E
TOP VIEW
T
hTYP
dTYP
4321
Numeric Designations
for Horizontal Grid
bREF
cREF TYP
-e-
TYP
-e-
D1
E1
Alpha Designations
for Vertical Grid
(Letters I, O, Q, and
S not used)
28
ICSSSTUB32866B
Advance Information
1165A—3/21/07
Revision History
Rev. Issue Date Description Page #
0.1 10/3/2005 Initial Release -
0.2 1/13/2006 Updated Package Dimensions. 27
0.3 1/16/2006 Updated Package Dimensions. 27
0.4 10/25/2006 Added DC table notes 2 and 3 21
