LM4947 LM4947 Mono Class D and Stereo Audio Sub-System with OCL Headphone Amplifierand National 3D Literature Number: SNAS349C LM4947 Mono Class D and Stereo Audio Sub-System with OCL Headphone Amplifier and National 3D General Description Features The LM4947 is an audio subsystem capable of efficiently delivering 500mW (Class D operation) of continuous average power into a mono 8 bridged-tied load (BTL) with 1% THD +N, 37mW (Class AB operation) power channel of continuous average power into stereo 32 single-ended (SE) loads with 1% THD+N, or an output capacitor-less (OCL) configuration with identical specification as the SE configuration, from a 3.3V power supply. The LM4947 has six input channels: one pair for a two-channel stereo signal, the second pair for a secondary two-channel stereo input, and the third pair for a differential single-channel mono input. Additionally, the two sets of stereo inputs may be configured as a single stereo differential input (differential left and differential right). The LM4947 features a 32-step digital volume control and eight distinct output modes. The digital volume control, 3D enhancement, and output modes are programmed through a two-wire I2C compatible interface that allows flexibility in routing and mixing audio channels. The RF suppression circuitry in the LM4947 makes it wellsuited for GSM mobile phones and other portable applications in which strong RF signals generated by an antenna (and long output traces) may couple audibly into the amplifier. The LM4947 is designed for cellular phones, PDAs, and other portable handheld applications. It delivers high quality output power from a surface-mount package and requires only eight external components in the OCL mode (two additional components in SE mode). I2C Control Interface I2C programmable National 3D Audio I2C controlled 32 step digital volume control (-59.5dB to +18dB) Three independent volume channels (Left, Right, Mono) Eight distinct output modes Small, 25-bump micro SMD packaging "Click and Pop" suppression circuitry Thermal shutdown protection Low shutdown current (0.1A, typ) RF suppression Differential mono and stereo inputs Stereo input mux Applications Mobile Phones PDAs Key Specifications THD+N at 1kHz, 500mW into 8 BTL (3.3V) 1.0% (typ) THD+N at 1kHz, 37mW into 32 SE (3.3V) 1.0% (typ) Single Supply Operation (VDD) 2.7 to 5.5V I2C Single Supply Operation 2.2 to 5.5V Boomer(R) is a registered trademark of National Semiconductor Corporation. (c) 2007 National Semiconductor Corporation 201735 www.national.com LM4947 Mono Class D and Stereo Audio Sub-System with OCL Headphone Amplifier and National 3D November 9, 2007 LM4947 Typical Application 201735d3 FIGURE 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less 201735d4 FIGURE 2. Typical Audio Amplifier Application Circuit-Single Ended www.national.com 2 LM4947 Connection Diagrams 25-Bump micro SMD 201735d2 Top View micro SMD Marking 20173507 Top View XY - Date Code TT - Die Traceability G - Boomer Family XX - H1 3 www.national.com LM4947 Pin Descriptions Bump Name A1 RIN2 Right Input Channel 2 or Right Differential Input - A2 LIN1 Left Input Channel 1 or Left Differential Input + A3 MIN+ A4 RHP3D1 Right Headphone 3D Input 1 A5 RHP3D2 Right Headphone 3D Input 2 B1 RIN1 Right Input Channel 1 or Right Differential Input + B2 LIN2 Left Input Channel 2 or Left Differential Input - B3 MIN- Mono Channel Inverting Input B4 LHP3D1 Left Headphone 3D Input 2 B5 LHP3D2 Left Headphone 3D Input 1 C1 ADDR Address Identification C2 SDA Serial Data Input C3 SCL Serial Clock Input C4 CBYPASS Half-Supply Bypass Capacitor C5 VOC Headphone return bias output D1 AVDD Analog Power Supply D2 LSVDD Loudspeaker Power Supply D3 I2CVDD I2C Interface Power Supply D4 AVDD D5 RHP Right Headphone Output E1 LS- Loudspeaker Output Negative E2 GND Ground E3 LS+ Loudspeaker Output Positive E4 GND Ground E5 LHP www.national.com Description Mono Channel Non-inverting Input Analog Power Supply Left Headphone Output 4 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Storage Temperature Input Voltage ESD Susceptibility (Note 3) ESD Machine model (Note 6) Junction Temperature (TJ) Solder Information 215C 220C JA (typ) - TLA25CBA 6.0V -65C to +150C -0.3 to VDD +0.3 2.0kV 200V 150C 65C/W Operating Ratings Temperature Range Supply Voltage (VDD) -40C to 85C 2.7V VDD 5.5V 2.2V VDD 5.5V Supply Voltage (I2C) 2.7V VDD 5.5V Supply Voltage (Loudspeaker VDD) Electrical Characteristics 3.3V (Notes 2, 7) The following specifications apply for VDD = 3.3V, TA = 25C, and all gains are set for 0dB unless otherwise specified. Symbol IDDQ ISD VOS PO Parameter Quiescent Supply Current Shutdown Current Output Offset Voltage Output Power Conditions THD+N Units (Limits) Limits (Note 5) Output Modes 2, 4, 6 VIN = 0V; No load, OCL = 0 (Table 2) 4.5 6.5 mA (max) Output Modes 1, 3, 5, 7 VIN = 0V; No load, BTL, OCL = 0 (Table 2) 6.5 8 mA (max) Output Mode 0 0.1 1 A (max) VIN = 0V, Mode 7, Mono 2 15 mV (max) VIN = 0V, Mode 7, Headphones 2 15 mV (max) MONO OUT; RL = 8 THD+N = 1%; f = 1kHz, BTL, Mode 1 500 400 mW (min) ROUT and LOUT; RL = 32 THD+N = 1%; f = 1kHz, SE, Mode 4 37 33 mW (min) MONOOUT f = 1kHz, POUT = 250mW; Total Harmonic Distortion Plus Noise LM4947 Typical (Note 4) 0.03 % 0.02 % Speaker; Mode 1 39 V Speaker; Mode 3 39 V Speaker; Mode 5 42 V Speaker; Mode 7 38 V Headphone; SE, Mode 2 15 V Headphone; SE, Mode 4 15 V Headphone; SE, Mode 6 17 V Headphone; OCL, Mode 2 12 V Headphone; OCL, Mode 4 15 V Headphone; OCL, Mode 6 17 V RL = 8, BTL, Mode 1 ROUT and LOUT f = 1kHz, POUT = 12mW; RL = 32, SE, Mode 4 A-weighted, 0dB inputs terminated, output referred NOUT Output Noise 5 www.national.com LM4947 Vapor Phase (60 sec.) Infrared (15 sec.) Thermal Resistance Absolute Maximum Ratings (Note 2) LM4947 Symbol Parameter Conditions LM4947 Typical (Note 4) Limits (Note 5) Units (Limits) VRIPPLE = 200mVPP; f = 217Hz, Power Supply Rejection Ratio Loudspeaker out 79 dB BTL, Output Mode 3 78 dB BTL, Output Mode 5 79 dB BTL, Output Mode 7 80 dB SE, Output Mode 2 78 dB SE, Output Mode 4 71 dB SE, Output Mode 6 71 dB OCL, Output Mode 2 83 dB OCL, Output Mode 4 74 dB OCL, Output Mode 6 74 dB Output Mode 1, 3, 5 86 % -49 dB -58 dB f = 1kHz, SE, Mode 4, RL = 32 -73 dB CB = 2.2F, OCL, RL = 32 90 ms 115 ms 0.2 dB RL = 32, CB = 2.2F, BTL All audio inputs terminated to GND; output referred Power Supply Rejection Ratio ROUT and LOUT CMRR BTL, Output Mode 1 VRIPPLE = 200mVPP; f = 217Hz, PSRR RL = 8, CB = 2.2F, BTL All audio inputs terminated to GND; output referred Class D Efficiency Common-Mode-Rejection Ratio f = 217Hz, VCM = 1Vpp, Mode 1, BTL, RL = 8 Headphone, PO = 12mW, XTALK TWU Crosstalk Wake-Up Time from Shutdown f = 1kHz, OCL, Mode 4, RL = 32 Headphone, PO = 12mW, CB = 2.2F, SE, RL = 32 Volume Control Step Size Error Input referred maximum attenuation -59.5 -60.25 -58.75 dB (min) dB (max) Input referred maximum gain +18 17.25 18.75 dB (min) dB (max) Output Mode 1, 3, 5 87 k (min) k (max) k (min) k (max) Digital Volume Range Mute Attenuation MONO_IN Input Impedance RIN and LIN Input Impedance www.national.com dB (min) Maximum gain setting 12 8 14 Maximum attenuation setting 100 75 125 6 LM4947 Electrical Characteristics 5V (Notes 2, 7) The following specifications apply for VDD = 5V, TA = 25C and all gains are set for 0dB unless otherwise specified. Symbol IDDQ Parameter Quiescent Supply Current ISD Shutdown Current VOS Output Offset Voltage PO Output Power Conditions Total Harmonic Distortion + Noise Units (Limits) Typical (Note 4) Limits (Note 5) Output Modes 2, 4, 6 VIN = 0V; No load, OCL = 0 (Table 2) 5.4 7.5 mA Output Modes 1, 3, 5, 7 VIN = 0V; No load, BTL, OCL = 0 (Table 2) 7.6 12 mA Output Mode 0 0.1 1 A (max) VIN = 0V, Mode 7, Mono 2 15 mV (max) VIN = 0V, Mode 7, Headphones 2 15 mV (max) MONOOUT; RL = 8 THD+N = 1%; f = 1kHz, BTL, Mode 1 1.19 W ROUT and LOUT; RL = 32 THD+N = 1%; f = 1kHz, SE, Mode 4 87 mW 0.04 % 0.01 % Speaker; Mode 1 38 V Speaker; Mode 3 38 V Speaker; Mode 5 39 V Speaker; Mode 7 36 V Headphone; SE, Mode 2 21 V Headphone; SE, Mode 4 21 V Headphone; SE, Mode 6 24 V Headphone; OCL, Mode 2 16 V Headphone; OCL, Mode 4 16 V Headphone; OCL, Mode 6 19 V MONOOUT f = 1kHz, POUT = 500mW; THD+N LM4947 RL = 8, BTL, Mode 1 ROUT and LOUT f = 1kHz, POUT = 30mW; RL = 32, SE, Mode 4 A-weighted, 0dB inputs terminated, output referred NOUT Output Noise 7 www.national.com LM4947 Symbol Parameter Conditions LM4947 Typical (Note 4) Limits (Note 5) Units (Limits) VRIPPLE = 200mVPP; f = 217Hz, Power Supply Rejection Ratio Loudspeaker out XTALK TWU 70 dB BTL, Output Mode 3 61 dB BTL, Output Mode 5 64 dB BTL, Output Mode 7 61 dB SE, Output Mode 2 72 dB SE, Output Mode 4 70 dB SE, Output Mode 6 65 dB OCL, Output Mode 2 76 dB OCL, Output Mode 4 72 dB OCL, Output Mode 6 70 dB Output Mode 1, 3, 5 86 % -49 dB Headphone, PO = 30mW, f = 1kHz, OCL, Mode 4 -55 dB Headphone, PO = 30mW, f = 1kHz, SE, Mode 4 -72 dB CB = 2.2F, OCL, RL = 32 116 ms RL = 32, CB = 2.2F, BTL All audio inputs terminated to GND; output referred Power Supply Rejection Ratio ROUT and LOUT CMRR BTL, Output Mode 1 VRIPPLE = 200mVPP; f = 217Hz, PSRR RL = 8, CB = 2.2F, BTL All audio inputs terminated to GND; output referred Class D Efficiency Common-Mode Rejection Ratio Crosstalk Wake-Up Time from Shutdown f = 1kHz, VCM = 1Vpp, 0dB gain, Mode 1, BTL, RL = 8 CB = 2.2F, SE, RL = 32 150 ms 0.2 dB Input referred maximum attenuation -59.5 dB Input referred maximum gain +18 dB Output Mode 1, 3, 5 90 dB (min) Maximum gain setting 11 k (min) k (max) Maximum attenuation setting 100 k (min) k (max) Volume Control Step Size Error Digital Volume Range Mute Attenuation MONO_IN Input Impedance RIN and LIN Input Impedance www.national.com 8 LM4947 I2C (Notes 2, 7) The following specifications apply for VDD = 5V and 3.3V, TA = 25C unless otherwise specified. Symbol Parameter Conditions LM4947 Typical (Note 4) Units (Limits) Limits (Note 5) t1 Clock Period 2.5 s (max) t2 Clock Setup Time 100 ns (min) t3 Data Hold Time 100 ns (min) t4 Start Condition Time 100 ns (min) t5 Stop Condition Time 100 ns (min) V (min) V (max) VIH SPI Input Voltage High 0.7xI2C VDD VIL SPI Input Voltage Low 0.3xI2C VDD is logic LOW; and X1 = 1, if ID_ENB is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can be changed to avoid any possible address conflicts. I2C Protocol Information The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR 201735f5 FIGURE 3. I2C Bus Format 201735f4 FIGURE 4. I2C Timing Diagram 9 www.national.com LM4947 Note 1: See AN-450 "Surface Mounting and their effects on Product Reliability" for other methods of soldering surface mount devices. Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 3: Human body model, 100pF discharged through a 1.5k resistor. Note 4: Typical specifications are specified at +25C and represent the most likely parametric norm. Note 5: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 6: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50). Note 7: All voltages are measured with respect to the ground pin, unless otherwise specified. Note 8: The given JA for an LM4947TL mounted on a demonstration board with a 9in2 area of 1oz printed circuit board copper ground plane. Note 9: Datasheet min/max specifications are guaranteed by design, test, or statistical analysis. www.national.com 10 LM4947 Typical Performance Characteristics THD+N vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 1, MONO THD+N vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 3, MONO 20173543 20173544 THD+N vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 5, MONO THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 2, OCL 20173545 20173546 THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 4, OCL THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 2, SE 20173547 20173548 11 www.national.com LM4947 THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 4, SE THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 6, OCL 20173549 20173550 THD+N vs Output Power VDD = 3.3V, RL = 32, f = 1kHz, Diff In Mode 6, SE THD+N vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 1, MONO 20173515 20173552 THD+N vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 5, MONO THD+N vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 3, MONO 20173553 www.national.com 20173554 12 LM4947 THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 2, OCL THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 2, SE 20173555 20173556 THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 4, OCL THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 4, SE 20173557 20173558 THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 6, SE THD+N vs Output Power VDD = 5V, RL = 32, f = 1kHz, Diff In Mode 6, OCL 20173559 20173560 13 www.national.com LM4947 THD+N vs Frequency VDD = 3.3V, RL = 8, PO = 250mW Diff In, Mode 1 THD+N vs Frequency VDD = 3.3V, RL = 8, PO = 250mW Diff In, Mode 5 20173525 20173526 THD+N vs Frequency VDD = 3.3V, RL = 8, PO = 250mW Diff In, Mode 3 THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 2, OCL 20173527 20173528 THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 2, SE THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4,7, OCL 20173529 www.national.com 20173530 14 LM4947 THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4,7, SE THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 6, OCL 20173531 20173532 THD+N vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 6, SE THD+N vs Frequency VDD = 5V, RL = 8, PO = 500mW Diff In, Mode 1 20173533 20173534 THD+N vs Frequency VDD = 5V, RL = 8, PO = 500mW Diff In, Mode 3 THD+N vs Frequency VDD = 5V, RL = 8, PO = 500mW Diff In, Mode 5 20173535 20173536 15 www.national.com LM4947 THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 2, OCL THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 2, SE 20173537 20173538 THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 4,7, OCL THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 4,7, SE 20173539 20173540 THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 6, OCL THD+N vs Frequency VDD = 5V, RL = 32, PO = 30mW Diff In, Mode 6, SE 20173541 www.national.com 20173542 16 LM4947 PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 1, MONO PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 2, OCL 20173516 20173517 PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 2, SE PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 3, MONO 20173518 20173519 PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 4, OCL PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 4, SE 20173520 20173521 17 www.national.com LM4947 PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 5, MONO PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 6, OCL 20173522 20173523 PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 6, SE PSRR vs Frequency VDD = 3.3V, AV = 0dB Mode 7, MONO 201735a4 201735a5 PSRR vs Frequency VDD = 5V, AV = 0dB Mode 1, MONO PSRR vs Frequency VDD = 5V, AV = 0dB Mode 2, OCL 201735a6 www.national.com 201735a7 18 LM4947 PSRR vs Frequency VDD = 5V, AV = 0dB Mode 2, SE PSRR vs Frequency VDD = 5V, AV = 0dB Mode 3, MONO 201735a8 201735a9 PSRR vs Frequency VDD = 5V, AV = 0dB Mode 4, OCL PSRR vs Frequency VDD = 5V, AV = 0dB Mode 4, SE 201735b0 201735b1 PSRR vs Frequency VDD = 5V, AV = 0dB Mode 5, MONO PSRR vs Frequency VDD = 5V, AV = 0dB Mode 6, OCL 201735b2 201735b3 19 www.national.com LM4947 PSRR vs Frequency VDD = 5V, AV = 0dB Mode 6, SE PSRR vs Frequency VDD = 5V, AV = 0dB Mode 7, MONO 201735b4 201735b5 Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 7, OCL Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 7, SE 201735d0 201735c9 Power Dissipation vs Output Power VDD = 3.3V, RL = 8, f = 1kHz Mode 1, 3, 5, MONO Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 2, 4, 6, OCL 201735c8 www.national.com 201735b6 20 LM4947 Power Dissipation vs Output Power VDD = 3.3V, RL = 32, f = 1kHz Mode 2, 4, 6, SE Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 7, OCL 201735c0 20173598 Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 7, SE Power Dissipation vs Output Power VDD = 5V, RL = 8, f = 1kHz Mode 1, 3, 5, MONO 201735c1 201735b7 Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 2, 4, 6, OCL Power Dissipation vs Output Power VDD = 5V, RL = 32, f = 1kHz Mode 2, 4, 6, SE 201735b8 201735b9 21 www.national.com LM4947 Crosstalk vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4, OCL Crosstalk vs Frequency VDD = 3.3V, RL = 32, PO = 12mW Mode 4, SE 20173573 20173574 Crosstalk vs Frequency VDD = 5V, RL = 32, PO = 30mW Mode 4, OCL Crosstalk vs Frequency VDD = 5V, RL = 32, PO = 30mW Mode 4, SE 20173575 20173576 Supply Current vs Supply Voltage No Load, Mode 7, OCL Supply Current vs Supply Voltage No Load, Mode 7, SE 201735c2 www.national.com 20173578 22 LM4947 Supply Current vs Supply Voltage No Load, Mode 1, 3, 5, MONO Supply Current vs Supply Voltage No Load, Mode 2, 4, 6, OCL 201735d1 201735c4 Supply Current vs Supply Voltage No Load, Mode 2, 4, 6, Headphone SE Output Power vs Supply Voltage RL = 8, Mode 1, 3, 5, MONO 20173581 20173587 Output Power vs Supply Voltage RL = 32, Mode 2, 4, 6, OCL Output Power vs Supply Voltage RL = 32, Mode 2, 4, 6, SE 201735c7 20173589 23 www.national.com LM4947 Output Power vs Supply Voltage RL = 32, Mode 7, OCL Output Power vs Supply Voltage RL = 32, Mode 7, SE 20173590 20173591 Efficiency vs Output Power VDD = 5V, RL = 8, Mode 1, 3, 5, BTL Efficiency vs Output Power VDD = 3.3V, RL = 8, Mode 1, 3, 5, BTL 20173513 www.national.com 201735c6 24 The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock. Each address bit must be stable while the clock level is HIGH. After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor). Then the master sends an acknowledge clock pulse. If the LM4947 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4947. The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH. After the data byte is sent, the master must check for another acknowledge to see if the LM4947 received the data. The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH. The data line should be held HIGH when not in use. I2C PIN DESCRIPTION SDA: This is the serial data input pin. SCL: This is the clock input pin. ID_ENB: This is the address select input pin. I2C COMPATIBLE INTERFACE The LM4947 uses a serial bus which conforms to the I2C protocol to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4947. The I2C address for the LM4947 is determined using the ID_ENB pin. The LM4947's two possible I2C chip addresses are of the form 111110X10 (binary), where X1 = 0, if ID_ADDR is logic LOW; and X1 = 1, if ID_ENB is logic HIGH. If the I2C interface is used to address a number of chips in a system, the LM4947's chip address can be changed to avoid any possible address conflicts. The bus format for the I2C interface is shown in Figure 3. The bus format diagram is broken up into six major sections: The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I2C bus to check the incoming address against their own address. I2C INTERFACE POWER SUPPLY PIN (I2CVDD) The LM4947's I2C interface is powered up through the I2CVDD pin. The LM4947's I2C interface operates at a voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system. TABLE 1. Chip Address A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 0 EC 0 ID_ADDR = 0 1 1 1 1 1 0 0 0 ID_ADDR = 1 1 1 1 1 1 0 1 0 Chip Address TABLE 2. Control Registers D7 D6 D5 D4 D3 D2 D1 D0 Mode Control 0 0 SE/Diff (select) 0 OCL (select) MC2 MC1 MC0 Programmable 3D 0 1 L2R2 L1R1 (select) (select) N3D3 N3D2 N3D1 N3D0 Mono Volume Control 1 0 0 MVC3 MVC2 MVC1 MVC0 Left Volume Control 1 1 0 LVC4 LVC3 LVC2 LVC1 LVC0 Right Volume Control 1 1 1 RVC4 RVC3 RVC2 RVC1 RVC0 MVC4 1. Bits MVC0 -- MVC4 control 32 step volume control for MONO input 2. Bits LVC0 -- LVC4 control 32 step volume control for LEFT input 3. Bits RVC0 -- RVC4 control 32 step volume control for RIGHT input 4. Bits MC0 -- MC2 control 8 distinct modes 5. Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function 6. N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0) 7. Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0 8. N3D1 selects between two different 3D configurations 9. SE/Diff-SE/Diff = 0 for SE mode; SE/Diff = 1 for Diff mode 25 www.national.com LM4947 Application Information LM4947 TABLE 3. Programmable National 3D Audio N3D3 N3D2 Low 0 0 Medium 0 1 High 1 0 Maximum 1 1 TABLE 4. Input/Output Control L2R2 L1R1 SE/DIFF Select LIN1 and RIN1 Stereo Pair 0 1 0 Select LIN2 and RIN2 Stereo Pair 1 0 0 Select LIN1+LIN2 and RIN1+RIN2 Stereo Pair 1 1 0 Sets Stereo Inputs to Differential x x 1 X = Don't Care www.national.com 26 Volume Step xVC4 xVC3 xVC2 xVC1 xVC0 Gain, dB 1 0 0 0 0 0 -59.50 2 0 0 0 0 1 -48.00 3 0 0 0 1 0 -40.50 4 0 0 0 1 1 -34.50 5 0 0 1 0 0 -30.00 6 0 0 1 0 1 -27.00 7 0 0 1 1 0 -24.00 8 0 0 1 1 1 -21.00 9 0 1 0 0 0 -18.00 10 0 1 0 0 1 -15.00 11 0 1 0 1 0 -13.50 12 0 1 0 1 1 -12.00 13 0 1 1 0 0 -10.50 14 0 1 1 0 1 -9.00 15 0 1 1 1 0 -7.50 16 0 1 1 1 1 -6.00 17 1 0 0 0 0 -4.50 18 1 0 0 0 1 -3.00 19 1 0 0 1 0 -1.50 20 1 0 0 1 1 0.00 21 1 0 1 0 0 1.50 22 1 0 1 0 1 3.00 23 1 0 1 1 0 4.50 24 1 0 1 1 1 6.00 25 1 1 0 0 0 7.50 26 1 1 0 0 1 9.00 27 1 1 0 1 0 10.50 28 1 1 0 1 1 12.00 29 1 1 1 0 0 13.50 30 1 1 1 0 1 15.00 31 1 1 1 1 0 16.50 32 1 1 1 1 1 18.00 1. x = M, L, or R 27 www.national.com LM4947 TABLE 5. Output Volume Control Table LM4947 TABLE 6. Output Mode Selection Output Mode Number MC2 MC1 MC0 Handsfree Mono Output Right HP Output Left HP Output 0 0 0 0 SD SD SD 1 0 0 1 2 x GM x M MUTE MUTE 2 0 1 0 SD GM x M GM x M 3 0 1 1 GL x L + GR x R MUTE MUTE 4 1 0 0 SD GR x R GL x L 5 1 0 1 GL x L + GR x R + 2(GM x M) MUTE MUTE 6 1 1 0 SD GR x R + GM x M GL x L + GM x M 7 1 1 1 GR x R + GL x L GR x R GL x L Note: L and R are selected by modes from Table 4. On initial POWER ON, the default mode is 000 M = Mono R = RIN L = LIN SD = Shutdown MUTE = Mute Mode GM = Mono volume control gain GR = Right stereo volume control gain GL = Left stereo volume control gain NATIONAL 3D ENHANCEMENT The LM4947 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo headphone listening. The LM4947 can be programmed for a "narrow" or "wide" soundstage perception. The narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial, theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed: low, medium, high, and maximum (Table 2), each level with an ever increasing aural effect, respectively. The difference between each level is 3dB. The external capacitors, shown in Figure 6, are required to enable the 3D effect. The value of the capacitors set the cutoff frequency of the 3D effect, as shown by Equations 1 and 2. Note that the internal 20k resistor is nominal (25%). f3DL(-3dB) = 1 / 2 * 20k * C3DL (1) f3DR(-3dB) = 1 / 2 * 20k * C3DR (2) Optional resistors R3DL and R3DR can also be added (Figure 7) to affect the -3dB frequency and 3D magnitude. 20173508 FIGURE 6. External RC Network with Optional R3DL and R3DR Resistors 20173509 FIGURE 5. External 3D Effect Capacitors www.national.com 28 f3DL(-3dB) = 1 / 2 * (20k + R3DL) * C3DL (3) f3DR(-3dB) = 1 / 2 * 20k + R3DR) * C3DR (4) f3dB (3D) = 1 / 2 (1 + M)(20k * C3D) CEquivalent (new) = C3D / 1 + M (6) (5) TABLE 7. Pole Locations AV (dB) f-3dB (3D) (Hz) 0 0 117 0.05 -0.4 0.25 -1.9 68 0.50 68 1.00 R3D (k) (optional) C3D (nF) 0 68 1 68 5 68 10 20 M Value of C3D to keep same pole location (nF) new Pole Location (Hz) 111 64.8 117 94 54.4 117 -3.5 78 45.3 117 -6.0 59 34.0 117 power dissipation for RHP and LHP is given by equation (9) and (10). From Equations (9) and (10), assuming a 5V power supply and a 32 load, the maximum power dissipation for LHP and RHP is 40mW, or 80mW total. PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8 LOAD Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1 trace resistance reduces the output power dissipated by an 8 load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible. Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing. PDMAX-LHP = (VDD)2 / (22 RL): Single-ended Mode (7) PDMAX-RHP = (VDD)2 / (22 RL): Single-ended Mode (8) The maximum internal power dissipation of the LM4947 occurs when all 3 amplifiers pairs are simultaneously on; and is given by Equation (11). PDMAX-TOTAL = PDMAX-SPKROUT + PDMAX-LHP + PDMAX-RHP (9) The maximum power dissipation point given by Equation (11) must not exceed the power dissipation given by Equation (12): PDMAX = (TJMAX - TA) / JA (10) The LM4947's TJMAX = 150C. In the ITL package, the LM4947's JA is 65C/W. At any given ambient temperature TA, use Equation (12) to find the maximum internal power dissipation supported by the IC packaging. Rearranging Equation (12) and substituting PDMAX-TOTAL for PDMAX' results in Equation (13). This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4947's maximum junction temperature. POWER DISSIPATION AND EFFICIENCY In general terms, efficiency is considered to be the ratio of useful work output divided by the total energy required to produce it with the difference being the power dissipated, typically, in the IC. The key here is "useful" work. For audio systems, the energy delivered in the audible bands is considered useful including the distortion products of the input signal. Sub-sonic (DC) and super-sonic components (>22kHz) are not useful. The difference between the power flowing from the power supply and the audio band power being transduced is dissipated in the LM4947 and in the transducer load. The amount of power dissipation in the LM4947 is very low. This is because the ON resistance of the switches used to form the output waveforms is typically less than 0.25. This leaves only the transducer load as a potential "sink" for the small excess of input power over audio band output power. The LM4947 dissipates only a fraction of the excess power requiring no additional PCB area or copper plane to act as a heat sink. The LM4947 also has a pair of single-ended amplifiers driving stereo headphones, RHP and LHP. The maximum internal TA = TJMAX - PDMAX-TOTAL JA (11) For a typical application with a 5V power supply and an 8 load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104C for the ITL package. TJMAX = PDMAX-TOTAL JA + TA (12) Equation (14) gives the maximum junction temperature TJMAX. If the result violates the LM4947's 150C, reduce the maximum junction temperature by reducing the power supply 29 www.national.com LM4947 AV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20k (see example below). LM4947 voltage or increasing the load resistance. Further allowance should be made for increased ambient temperatures. The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of Equation (11) is greater than that of Equation (12), then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce JA. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins. External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation. When adding a heat sink, the JA is the sum of JC, CS, and SA. (JC is the junction-to-case thermal impedance, CS is the case-to-sink thermal impedance, and SA is the sink-to-ambient thermal impedance). Refer to the Typical Performance Characteristics curves for power dissipation information at lower output power levels. ciency, full range speaker whose response extends below 40Hz. Bypass Capacitor Value Selection Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor connected to the BYPASS bump. Since CB determines how fast the LM4947 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4947's outputs ramp to their quiescent DC voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 1.0F along with a small value of Ci (in the range of 0.1F to 0.39F), produces a click-less and pop-less shutdown function. As discussed above, choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value should be in the range of 5 times to 7 times the value of Ci. This ensures that output transients are eliminated when power is first applied or the LM4947 resumes operation after shutdown. POWER SUPPLY BYPASSING As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 1F in parallel with a 0.1F filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response. However, their presence does not eliminate the need for a local 1.1F tantalum bypass capacitance connected between the LM4947's supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM4947's power supply pin and ground as short as possible. Connecting a 2.2F capacitor, CB, between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however, increases turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass capacitor values, especially CB, depends on desired PSRR requirements, click and pop performance (as explained in the section, Proper Selection of External Components), system cost, and size constraints. SELECTING EXTERNAL COMPONENTS Input Capacitor Value Selection Amplifying the lowest audio frequencies requires high value input coupling capacitor (Ci in Figures 1 & 2). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using large input capacitor. The internal input resistor (Ri), nominal 20k, and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found using Equation (15). fc = 1 / (2RiCi) (13) As an example when using a speaker with a low frequency limit of 150Hz, Ci, using Equation (15) is 0.053F. The 0.22F Ci shown in Figure 1 allows the LM4947 to drive high effi- www.national.com 30 LM4947 20173510 DEMO BOARD SCHEMATIC 31 www.national.com LM4947 Revision History Rev Date 1.0 06/16/06 Initial release. 1.1 06/19/06 Changed the Class D Efficiency (n) on Typical limit (from 79 to 86) on the 5V specification table. 1.2 06/22/06 Added more Typ Perf curves. 1.3 07/18/06 Replaced some of the curves. 1.4 08/29/06 Text edits. 1.5 10/18/06 Edited micro SMD pkg drawing, Figure 1, and Figure 2. Changed IDDQ typical and limit values on the 3.3V and 5.0V specification table. Removed CMRR SE condition and changed typical values for CMRR BTL on 3.3V and 5.0V specification table. Changed Mute Attenuation typical value on 5.0V specification table. 1.6 03/02/07 Edited the 3.3V and 5V EC tables. 1.7 03/02/07 Composed (CONFIDENTIAL) D/S for customer (SAMSUNG). 1.8 09/06/07 Edited Table 4. 1.9 11/09/07 Text edits. www.national.com Description 32 LM4947 Physical Dimensions inches (millimeters) unless otherwise noted 25 - Bump micro SMD Order Number LM4947TL NS Package Number TLA25BBA Dimensions are in millimeters X1 = 2.517 0.01 X2 = 2.517 0.01 X3 = 0.600 0.10 33 www.national.com LM4947 Mono Class D and Stereo Audio Sub-System with OCL Headphone Amplifier and National 3D Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH www.national.com/webench Audio www.national.com/audio Analog University www.national.com/AU Clock Conditioners www.national.com/timing App Notes www.national.com/appnotes Data Converters www.national.com/adc Distributors www.national.com/contacts Displays www.national.com/displays Green Compliance www.national.com/quality/green Ethernet www.national.com/ethernet Packaging www.national.com/packaging Interface www.national.com/interface Quality and Reliability www.national.com/quality LVDS www.national.com/lvds Reference Designs www.national.com/refdesigns Power Management www.national.com/power Feedback www.national.com/feedback Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www.national.com/led PowerWise www.national.com/powerwise Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors Wireless (PLL/VCO) www.national.com/wireless THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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