Am2602/9602 | pistinctive Characteristics: + Retriggerable 0 to 100% duty cycie. * 50ns to output pulse width range. Am2602 guaranteed pulse width change over tem- perature range. 100% reliability assurance testing including high tem- perature bake, temperature cycling, centrifuge and | Dual Retriggerable Resettable Monostable Multivibrator package hermeticity testing in compliance with MIL STD-883. Mixing privileges for obtaining price discounts. Refer to price list. e Electrically tested and optically inspected dice for the assemblers of hybrid products. | FUNCTIONAL DESCRIPTION The Am2602 and Am9602 are dual OC-level sensitive reset- table retriggerable monostable multivibrators which provide { an output pulse whose duration and accuracy depend on | external timing components. Provision is made tor triggering on the rising or falling edge i of an Input signal. All inputs are OC coupled making trigger- ing Independant of Input rise and fail times. Each time tha output from the OR trigger gate goes from a FALSE (LOW) to TRUE (HIGH) condition triggering occurs independent of the LOGIC DIAGRAM 2 Am 26002 6 9602 AMAT state of the monostable. al apt | The direct clear facility allows a timing cycle to be terminated Sa a t at any time during the cycle. A LOW signal on the C, input 4 3 | resets the monostable independent of other conditions. || The Am2602 is a selected Amd602 with a guaranteed pulse nd = Pin 8 width change of fess than 1% over the temperature range of 0C to +75C. i INTERNAL TIMING CIARCUITAY | Cx Cy Ax co i Vee 33 ! i aaio | Oo!y GND ORDERING INFORMATION ~ CONNECTION DIAGRAM . wot Top View Part Package Temperature we Order | Number Type Range ,O%* Number MOROSTABLE TC aT vee Amz602 Molded DiP 0C to pst AM260259A omc raf ojex teomnsraaue 2 Am2602 Hermetic DIP oe SQ: AM260259E Am2602 HermeticDIP = 3 AM260251E cos waa Am2602 Hermetic Flat Pak oO 1. 56C AM2G0251N Am2602 Dice . ie AM2602XXD ids wap VS ! Am9602 Molded AE to + 75C U6M960259X \ /| Amp602 = Herm Pp Sto +75C -U78960259X aye ves : Am9602 H eS DIF 55C to +125C U7B960251X-~ etc nook i Am9602 Hermdtic Flat Pak 55C to +125C U4L960251X Amgea2 Dice Note UXX8602XXD ech wt OND = T 2 Q +76C and -S5C to + 126C temperature ranges. i | Note: The dice suppiled will contain units which meet both 0C to 4-21 3 ;MAXIMUI INGS (Above which the useful lite may be impaired) Storage Tempe-ature 65C to +150 Temperature (Ambient) Under Bias 55C to +125 Supply Voitage to Ground Potential (Pin 16 to Pin 8) Continuous O.5V to +8 DC Voltage Apptied to Outputs for High Output State 0.5 V to +Vo Mm DC Input Voltage 0.5 Vito +55 Output Current Into Gutputs When Output is LOW 50a DC Input Current 30 mAta +58 Am200250/960259X T, = 0C to +75C Voc * 4.75 10 6.25 (COM grade] ELECTRICAL CHARACTERISTICS m260251/000251K Th = 55C to +125C Vic = 4.5040 5.50 V (MIL grade) DC Characteristics Over Operating Range {Note 1) Luaits Operating T, = MIN T, = +25C T, = MAX Parameters Range Test Conditions Min Max Min Typ Max Min Max Unit: - Output HIGH wow Veg = MIN, Igy = 0.96 mA 2.40 240 36 2.40 Volt Voltage Vou MIL Iq, = 8 x i, MAX. 0.40 0.2 0.40 0.40 Volt: valeee COM Noy = BX 1, MAX. 0.45 02 0.45 0.45 Von MIL 2.00 1.70 1.50 Volt: vate COM 1.90 1.80 1.60 Va Mit 0.85 0.85 Voltt Votage COM 0.85 0.85 Veco = MAX. 1.60 1.10 1.60 MIL Vin = 0.40 L&E = UN Veo = MIN. 1.24 ~0.97 1.24 out oad Vv, MAX. 1,60 1.00 1.60 ma Current COM Vy = 0.4sy pec = a = 100 zt Voc = MIN. -1.41 0.90 -1.41 ~1.4t i Reverse Input wou Veg 2 MAX..Viy 2 4.5 60 2 60 60 aA Current Ike MIL Vee = 5.0 V, Vo = 1.0V 8 25 mA Shon Circult COM Veg = 5.0V, Vo = 1.0V ~8 35 lp 9602)MiL. Voce = 5.0V GND Pins 5 and 11 45 a5 45 45 Power 9602 Got Ry = 10 ka 52 35 50 52 mA Supply 2602 COM Veo = MAX. GND Pins 5 and 11 Current 2602 MIL Ry = 10 ke 56 so 8 56 Switching Characteristics <7, = 25C) 2602 9602 MIL 9602 COM Parameters Test Conditions Min Typ Max Min Typ Max Unis tay Turn Of Delay Negative Trigger Input to True Output 25 35 25 40 ns tea Turn On Delay Negative Trigger Input to False Output Voc = 5.0, C, = 15 pF 2 35 25 40 as True Output Ry = Ska, C, = 0 pF 45 65 so 70 tye (min) | Minimum Gutput Pulse width | Ue Output (a) x * ne False Output (Q) 55 75 60 680 Veo = 5,0V, C= 15PF | aon 5 42 37 te Pulse Width A, = 10 kt, C, = 1000 pF | > 42 3.76 (3.08 3. 3.76 | 28 R, Timing Resistor over Temperature Range (Note 2) 5 50 5 50 a &,_ (Cp) | Detay trom C, to Q output LOW "#17 40617 '| ns Am2002 Min Typ Max Maximum changs In Puise Width True Output 05 1.0 at, (7) over temperature range 0C to +75C Veg = 5.0V, C, = 15 pF % Maximum change in Pulse Width True Output over Ry = 10 ka, C, = 1000 pF 40 7.0 temperature range 55C to +125C (Am2602 MIL) , Notes: 1. Teste are conducted with a 10 kO realstor placed between Pin 2 (14) and Voc unless otherwise noted. . Maximum permissible Ry when used below 0C ie 25 ki.Pmimiei Rieti ote operation. |. The ouiput pulse width T is defined ae follows: T= 0s2A,c, [1 + 22) " clrculte can be used: , A < 0.67, (Max) * % D,: any eflicon roe type diode, such topee q a FO700 T rat ae re mata T= 0.90 RC, [1 + $2) Where: Ale ink@, CG, in in pF, * ten ae . Input Trigger Puise Rules. tit tt, > dns SS oe Input to Pin & (11) wer TITRE Pin 4 (12) = LOW ae Pin 3 (13) = HIGH our TF. a 8. The retriggersbla pulse width le calculated as shown below: We A thet heay OBZ ALC, 1 + F7 + tye, OPERATION RULES 1. An external resistor A, and an extemal capacitor G, are required ae shown In the logic diagram. The vaiues of R, may vary from 50 ki? 10 50 ki! for 0C to +76C operation snd 5.0 ki to 25 kG for 65C to +125C operation. C, may vary trom 0 ta any value ne: |. Hf a thead value of A, Is used, the following values ere recommended: A, = 30 ki for 0C to +75C operation; A, = 10 kil for 55C to + 125C For Cy greater than 102 pF) Where: A, Is in kQ, C, In in pF, Tre in ns For C,< 10) pF see Fig. 2 |. If electrolytic type capacitora are to be used, it is recommended that they have low leakage. For capacitors with a high reverse leakage the following This clrcult also allows larger value of A to be used for jongar output puise width. Both circuits prevent reverse voltage across C,. The pulse width T for the circuits is detined as foliows T in In np. . To obtain variable pulse width, by remote trimming, the following circuil ta recommended . Under any operating condition, C, and R, (min) must be kept as close to the circuit as possible fo minimize stray cepacitance and reduce noise pickup. The retrigger puise width is equal to the pulse widih t,, plus m delay time. For putes widths greater oe 500ns, 1, can be approximated apt, NOTE: Retriggering wilt not occur if the retrigger pulee comes within 0.32 R,C, ior |. Reset Operation The Am2602/0602 have en active LOW reset facility. By applying a low to the reeset input, any timing cycle an be terminated or any new cycle inhibited until the low reset input is removed. Trigger Inputs will not produce api ary and odtamabia RAL OT) (n,Q) R, (min) < A, < A, (maxy Q,: Any NPN silicon device with sufficient h,, at low currents, such as 2N2511 ate ae fhe NE are te aon fo fire Input to Pin 4 (12) Pin 5 (11) = HIGH Pin 3 (13) = HIGH ; Jing after the initial trigper pulse on in the output when the rese! is held low DEFINITION OF TERMS SUBSCRIPT TEAMS: H HIGH, applying to a HIGH Jogic level or when used with Vee fo indicate high V. value. 1 (nput. L LOW, applying to LOW logic level or when used with Vo~ to indicate low V- value. @ Output. OPERATIONAL TERMS: \, Forward input load current. logy Output HIGH current, forced out of output in V>,, test. 'g, Output LOW current, forced into the output in Vo, test. 14 Reverse input toad current. Negative Current Current flowing out of the device. Positive Current Current flowing into the device. iq Minimum logic HIGH input voltage. Refer to figure 2. , Maximum logic LOW input voltage. Refer to figure 2. Yo, Minimum logic HIGH output voltage with output HiGH current Io, flowing out of output. Yo, Maximum logic LOW output valtage with output LOW current |g, inta output. FUNCTIONAL TERMS: , The asynchronous direct clear input. A LOW on this input resets tha monostabie independent of other conditions. Fan-Out The logic HIGH or LOW output drive capability in terms of Input Unit Loads. Ih The active LOW input of the monostables. With input |, LOW a HIGH to LOW transition on I, will cause triggering. J, The active HIGH input of the monostables. With |, HIGH a LOW to HIGH transition on 1, will cause triggering. input Unit Losd One TL gate input load. Q The TRUE output of the monostavies. Q The FALSE output of the monostabies Triggering The switching of the monostable fram the stable stale ta the unstable state and start of the timing cycle. SWITCHING TERMS: The propagation delay from a HIGH ta LOW transition on ty to the true (Q) output LOW to HIGH transition. _ The propagation delay from a HIGH to LOW transition on Th to the talse (Q) output HiGH to LOW transition. (min) The minimum true (Q) output puise width with Ry, = 5k2, == 0 pF. t,. The pulse width obtained with R, = t0k2, C, = 1000 pF. 4t,.(T} The maximum percentage change in pulse width of the true (Q) output for the Am2602 over the temperature range from the pulse width at 25C. 3 i vere4-24 TYPICAL PERCENT DEVIATION RELATIVE TO 25C a Onn Wek HO ose Am 2602 Normalized Output Pulse Width Versus Ambient Temperature -% 0 B 8 TS 100 125 Ta - AMBIENT TEMPERATURE - C Output Pulse Width (aT) Using Low Values of eT pw - a8 1 10 103 Cx pF NGTE: Above Cx = 10% pF Use Tey = 0.32 Cy Ax (1+0.7/R yg) Figure 1 Figure 2 SWITCHING TIME TEST CIRCUIT AND WAVEFORMS Iv, Yin 1.5V av 40 na. tog Yo 15v <_____. tra tow va 15v Vec = Pin 16 Gnd. = Pins INPUT PULSE f= 100 kHz Amp = 20V Width ~ 40 ns Gwe 10 ne Figure 3 vereTRUTH TABLE Am2602/9602 For Each Monostable c, Operation H Trigger H Trigger L Reset H = HIGH Voltage Level L = LOW Voltage Levei X = Don't Care HL = HIGH to LOW Valtage Levet transition LH = LOW to HIGH Voltage Level transition Table | MSi INTERFACING RULES Equivaient Interfacing Input Unit Load Digital Family HIGH LOW Advanced Micro Devices 9300/2500 Series 1 1 FSC Series 9300 1 1 Tl Series 54/7400 1 1 Signetics Series 6200 2 2 National Series DM 75/85 1 1 OTL Series 930 12 1 Table III Am2602/9602 LOADING RULES Fanout Input Output Output Input/Output Pin Ne.s UnitLoad HIGH Low Monostable1 C, 1 _ ad Cc, Ry 2 ~ _ _ om 3 1 _ , 4 1 _ T, 5 1 _ 6 _ 16 8 a ? _ 16 8 GND 8 _ _ _ Monostable2 9g _ 16 8 Q 10 _ 16 8 Io " 1 _ _ 1 12 1 > _ Cc. 13 1 ~~ c, A, 14 _ _ Cy 15 Veg 16 - _ Table 1! INPUT/OUTPUT INTERFACE CONDITIONS Voltage interlace Condilions LOW & HIGH 30 p- go 28F MiNiMUM LOGIC 26h "HIGH" OUTPUT 3 VOLTAGE > 24 4212p Yor, 2 20h 5 Seb Min Set MINtMUM LOGEC a, HIGH INPUT alae VOLTAGE 3 $2 y B tof Hg 2 ost MAXIMUM LOGIC = : LOW INPUT O8F vo, on VOLTAGE o4 REX TOCTe oe @2F Low: OUTPUT oo VOLTAGE DRIVING DEVICE DAIVEN DEVICE Current interface Conditions LOW OUTPUT DHIVING Low DN Gao > | tut = Current Interface Conditions OuTPUT ORV ING HIGH ORIVEN LOW DRIVING DEVICE DAIVEN DEVICE Figure 4 INPUT LOAD HIGH INPLIT (AD DRIVEN HIGH 4-25Am2602/9602 APPLICATIONS Yoo - Yoo - xs Bar xa Px2 1 2 1, 14 e op 2 ope ourpur OUTPUT - ineuT am2e02s 4 Am2802/ ap oo a a OVERRIDING ENABLE wel STL of y}.| Pulee Generator . Figure 6 q Delayed Pulse Generation The output frequency produced with the above configuration Figure 5 is determined by C,, and Ry,, while the pulse width is determined by C,, and Ry,. Monostable 1 forms an astable 3 multivtbrator with an output pulse width of approximately 25 ns, while monostable 2 extends the pulse width tc - the required vaiue. The flrat monostable determines the time T, before the Initiation of the output pulse. The second monostabie : delermines T,, the output pulse width. PHYSICAL DIMENSIONS Dual-in-Ling pa eS i, ots | ee bad r Flat Package 2 | 1B Cy MONS. 2 . a 4 i ; T 14 omy - e tt 13%, ADVANCED + 124 MICRO = L "e DEVICES INC. | & 901 Thompson Place - ae Sunnyvale | - California 94086 - (408} 732-2400 serine TWX: 910-339-0200 | = TELEX: 34-6306 426 Advanced Micro Devices Can not absume remponsibility tor usp of any circuitry described other than circuitry entirely embodied In an Advanced Micro Devices product. (2Preliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Stop Clock Stop Grant State STPCLK# Sampled Negated Normal (Re-entered after PLL stabilization) CLK AVAVAVAUAVAUAUAUA\\GAUAUAUAVAVAVAUB WAUAUAVAY AI313] BE[7:0|# S f ADS# S$ TL M/\O# % v_/ D/C# S S W/R# 5 s\ CACHE# $5 mr STPCLK+# SS $ D[63:0] 5 KEN# 5) BRDV# Figure 75. Stop Grant and Stop Clock Modes, Part 2 Chapter 5 Bus Cycles 169AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 INIT-Initiated Transition from Protected Mode to Real Mode INIT is typically asserted in response to a BIOS interrupt that writes to an I/O port. This interrupt is often in response to a Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar to port 64h in the keyboard controller) that asserts INIT. INIT is also used to support 80286 software that must return to Real mode after accessing extended memory in Protected mode. The assertion of INIT causes the processor to empty its pipelines, initialize most of its internal state, and branch to address FFFF_FFFOhthe same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the MMxX state, Model-Specific Registers (MSRs), the CD and NW bits of the CRO register, the time stamp counter, and other specific internal resources. Figure 76 shows an example in which the operating system writes to an I/O port, causing the system logic to assert INIT. The sampling of INIT asserted starts an extended microcode sequence that terminates with a code fetch from FFFF_FFF0h, the reset location. INIT is sampled on every clock edge but is not recognized until the next instruction boundary. During an I/O write cycle, it must be sampled asserted a minimum of three clock edges before BRDY# is sampled asserted if it is to be recognized on the boundary between the I/O write instruction and the following instruction. If INIT is asserted synchronously, it can be asserted for a minimum of one clock. If it is asserted asynchronously, it must have been negated for a minimum of two clocks, followed by an assertion of a minimum of two clocks. 170 Bus Cycles Chapter 5Preliminary Information AMD<ad\ 21850E/0November 1998 AMD-K6-2 Processor Data Sheet INIT Sampled Asserted Code Fetch CLK ADP DPD PPD PPS MN A133] CX % X BE[7:0]4 X S X ADSH LS SL MO# \ DICH __ \ wRe / 5 D[63:0] }+{ s (XXX }- KEN# V/ BRDY# / \ a INIT / \ Figure 76. INIT-Initiated Transition from Protected Mode to Real Mode Chapter 5 Bus Cycles 171AMDd@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 172 Bus Cycles Chapter 5Preliminary Information AMDZI 21850E/0November 1998 AMD-K6-2 Processor Data Sheet Power-on Configuration and Initialization On power-on the system logic must reset the AMD-K6-2 processor by asserting the RESET signal. When the processor samples RESET asserted, it immediately flushes and initializes all internal resources and its internal state, including its pipelines and caches, the floating-point state, the MMX and 3DNow! states, and all registers. Then the processor jumps to address FFFF_FFFOh to start instruction execution. Signals Sampled During the Falling Transition of RESET FLUSH# BF[2:0] BRDYC# FLUSH# is sampled on the falling transition of RESET to determine if the processor begins normal instruction execution or enters Tri-State Test mode. If FLUSH# is High during the falling transition of RESET, the processor unconditionally runs its Built-In Self Test (BIST), performs the normal reset functions, then jumps to address FFFF_FFFOh to start instruction execution. (See Built-In Self-Test (BIST) on page 217 for more details.) If FLUSH# is Low during the falling transition of RESET, the processor enters Tri-State Test mode. (See Tri-State Test Mode on page 218 and FLUSH# (Cache Flush) on page 103 for more details.) The internal operating frequency of the processor is determined by the state of the bus frequency signals BF[2:0] when they are sampled during the falling transition of RESET. The frequency of the CLK input signal is multiplied internally by a ratio defined by BF[2:0]. (See BF[2:0] (Bus Frequency) on page 92 for the processor-clock to bus-clock ratios.) BRDYC# is sampled on the falling transition of RESET to configure the drive strength of A[20:3], ADS#, HITM#, and W/R#. If BRDYC# is Low during the fall of RESET, these outputs are configured using higher drive strengths than the standard strength. If BRDYC# is High during the fall of RESET, the standard strength is selected. (See BRDYC# (Burst Ready Copy) on page 95 for more details.) Chapter 6 Power-on Configuration and Initialization 173AMD@ Preliminary Information AMD-K6-2 Processor Data Sheet 21850E/0November 1998 6.2 RESET Requirements During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and Vcc reach specification. (See CLK Switching Characteristics on page 255 for clock specifications. See Electrical Data on page 247 for Vcc specifications.) During a warm reset while CLK and Vcc are within specification, RESET must remain asserted for a minimum of 15 clocks prior to its negation. 6.3 State of Processor After RESET Output Signals Table 31 shows the state of all processor outputs and bidirectional signals immediately after RESET is sampled asserted. Table 31. Output Signal State After RESET Signal State Signal State A[31:3], AP Floating || LOCK# High ADS#, ADSC# High M/lO# Low APCHK# High PCD Low BE[7:0]# Floating || PCHK# High BREQ Low PWT Low CACHE# High SCYC Low D/C# Low SMIACT# High D[63:0], DP[7:0] Floating TDO Floating FERR# High VCC2DET Low HIT# High VCC2H/L# Low HITM# High W/R# Low HLDA Low - - Registers Table 32 on page 175 shows the state of all architecture registers and Model-Specific Registers (MSRs) after the processor has completed its initialization due to the recognition of the assertion of RESET. 174 Power-on Configuration and Initialization Chapter 6