DEMO MANUAL DC2048A LTC3330EUH Nanopower Buck-Boost DC/DC with Energy Harvesting Battery Life Extender Description Demonstration Circuit 2048A is a nanopower buckboost DC/DC with energy harvesting battery life extender featuring the LTC(R)3330. The LTC3330 integrates a high voltage energy harvesting power supply plus a DC/DC converter powered by a primary cell battery to create a single output supply for alternative energy applications. The energy harvesting power supply, consisting of an integrated low-loss full-wave bridge with a high voltage buck converter, harvests energy from piezoelectric, solar or magnetic sources. The primary cell input powers a buck-boost converter capable of operating down to 1.8V at its input. Either DC/DC converter can deliver energy to a single output. The buck operates when harvested energy is available, reducing the quiescent current drawn on the battery to essentially zero. The buck-boost takes over when harvested energy goes away. A low noise LDO post regulator and a supercapacitor balancer are also integrated, accommodating a wide range of output storage configurations. Voltage and current settings for both input and outputs are programmable via pin-strapped logic inputs. The LTC3330EUH is available in a 5mm x 5mm 32-lead QFN surface mount package with exposed pad. Design files for this circuit board are available at http://www.linear.com/demo/DC2048A L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Dust is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Board Photo 100 90 EFFICIENCY (%) 80 70 60 50 40 VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VOUT = 5V VIN = 6V, L = 22H, DCR = 0.19 30 20 10 0 1 10 100 1m ILOAD (A) 10m 100m DC2048A F02 Figure 2. Typical Efficiency of DC2048A. Buck Efficiency vs ILOAD Figure 1. DC2048A Demo Board dc2048afb 1 DEMO MANUAL DC2048A Performance Summary SYMBOL PARAMETER VIN Input Voltage Range Specifications are at TA = 25C CONDITIONS MIN MAX UNITS 3.0 18.0 V VBAT Battery Voltage Range 1.8 5.5 V VOUT 1.8V Output Voltage Range OUT0 = 0, OUT1 = 0, OUT2 = 0 1.728 1.872 V VOUT 2.5V Output Voltage Range OUT0 = 1, OUT1 = 0, OUT2 = 0 2.425 2.575 V VOUT 2.8V Output Voltage Range OUT0 = 0, OUT1 = 1, OUT2 = 0 2.716 2.884 V VOUT 3.0V Output Voltage Range OUT0 = 1, OUT1 = 1, OUT2 = 0 2.910 3.090 V VOUT 3.3V Output Voltage Range OUT0 = 0, OUT1 = 0, OUT2 = 1 3.200 3.400 V VOUT 3.6V Output Voltage Range OUT0 = 1, OUT1 = 0, OUT2 = 1 3.492 3.708 V VOUT 4.5V Output Voltage Range OUT0 = 0, OUT1 = 1, OUT2 = 1 4.365 4.635 V VOUT 5.0V Output Voltage Range OUT0 = 1, OUT1 = 1, OUT2 = 1 4.850 5.150 V LDO 1.2V LDO Voltage Range LDO0 = 0, LDO1 = 0, LDO2 = 0 1.176 1.224 V LDO 1.5V LDO Voltage Range LDO0 = 1, LDO1 = 0, LDO2 = 0 1.470 1.530 V LDO 1.8V LDO Voltage Range LDO0 = 0, LDO1 = 1, LDO2 = 0 1.764 1.836 V LDO 2.0V LDO Voltage Range LDO0 = 1, LDO1 = 1, LDO2 = 0 1.960 2.040 V LDO 2.5V LDO Voltage Range LDO0 = 0, LDO1 = 0, LDO2 = 1 2.450 2.550 V LDO 3.0V LDO Voltage Range LDO0 = 1, LDO1 = 0 ,LDO2 = 1 2.940 3.060 V LDO 3.3V LDO Voltage Range LDO0 = 0, LDO1 = 1, LDO2 = 1 3.234 3.366 V LDO LD0_IN LDO Voltage Range LDO0 = 1, LDO1 = 1, LDO2 = 1 LDO_IN V Operating Principle Refer to the block diagram within the LTC3330 data sheet for its operating principle. The LTC3330 combines a buck switching regulator and a buck-boost switching regulator to produce an energy harvesting solution with battery backup. The converters are controlled by a prioritizer that selects which converter to use based on the availability of a battery and/or harvestable energy. If harvested energy is available, the buck regulator is active and the buck-boost is off. With an optional LDO and supercapacitor balancer and an array of different configurations, the LTC3330 suits many applications. The synchronous buck converter is an ultralow quiescent current power supply tailored to energy harvesting applications. It is designed to interface directly to a piezoelectric or alternative A/C energy source, rectify and store the harvested energy on an external capacitor while maintaining a regulated output voltage. It can also bleed off any excess input power via an internal protective shunt regulator. An internal full-wave bridge rectifier accessible via AC1 and AC2 inputs, rectifies AC sources such as those from a piezoelectric element. The rectified output is stored on a capacitor at the VIN pin and can be used as an energy reservoir for the buck converter. The bridge rectifier has a total drop of about 800mV at typical piezo-generated currents, but is capable of carrying up to 50mA. When the voltage on VIN rises above the UVLO rising threshold the buck converter is enabled and charge is transferred from the input capacitor to the output capacitor. When the input capacitor voltage is depleted below the UVLO falling threshold the buck converter is disabled. These thresholds can be set according to Table 4 of the data sheet which offers UVLO rising thresholds from 4V to 18V with large or small hysteresis windows. Two internal rails, CAP and VIN2, are generated from VIN and are used to drive the high side PMOS and low side NMOS of the buck converter, respectively. Additionally the VIN2 dc2048afb 2 DEMO MANUAL DC2048A Operating Principle rail serves as logic high for output voltage select bits UV [3:0]. The VIN2 rail is regulated at 4.8V above GND while the CAP rail is regulated at 4.8V below VIN. These are not intended to be used as external rails. Bypass capacitors should be connected to the CAP and VIN2 pins to serve as energy reservoirs for driving the buck switches. When VIN is below 4.8V, VIN2 is equal to VIN and CAP is held at GND. VIN3 is an internal rail used by the buck and the buck-boost. When the LTC3330 runs the buck, VIN3 will be a Schottky diode drop below VIN2. When it runs as a buck-boost VIN3 is equal to BAT. The buck regulator uses a hysteretic voltage algorithm to control the output through internal feedback from the VOUT sense pin. The buck converter charges an output capacitor through an inductor to a value slightly higher than the regulation point. It does this by ramping the inductor current up to 250mA through an internal PMOS switch and then ramping it down to 0mA through an internal NMOS switch. When the buck brings the output voltage into regulation, the converter enters a low quiescent current sleep state that monitors the output voltage with a sleep comparator. During this operating mode, load current is provided by the buck output capacitor. When the output voltage falls below the regulation point, the buck regulator wakes up and the cycle repeats. This hysteretic method of providing a regulated output reduces losses associated with FET switching and maintains an output at light loads. The buck delivers a minimum of 100mA average load current when it is switching. VOUT can be set from 1.8V to 5.0V via the output voltage select bits OUT [2:0] according to Table 1 of the data sheet. The buck-boost uses the same hysteretic algorithm as the buck to control the output, VOUT, with the same sleep comparator. The buck-boost has three modes of operation; buck, buck-boost and boost. An internal mode comparator determines the mode of operation based on BAT and VOUT. In each mode, the inductor current ramps up to IPEAK which is programmable via IPK [2:0]. See Table 3 of the data sheet. An integrated low drop out regulator (LDO) is available with its own input, LDO_IN. It will regulate LDO_OUT to seven different output voltages based on the LDO [2:0] selection bits according to Table 2 of the data sheet. A mode is provided to turn the LDO into a current-limited switch in which the PMOS is always on. LDO_EN enables the LDO when high and when low, eliminates all quiescent current into LDO_IN. The LDO is designed to provide 50mA over a range of LDO_IN and LDO_OUT combinations. The LDO also features a 1ms soft-start for smooth output start-up. Power good comparators, PGVOUT and PGLDO, produce a logic high referenced to highest of VIN2, BAT and VOUT less a Schottky diode drop. PGVOUT and PGLDO will transition high the first time the respective converter reaches the programmed sleep threshold, signaling that the output is in regulation. The pin will remain high until the voltage falls to 92% of the desired regulated voltage. An integrated supercapacitor balancer with 165nA of quiescent current is available to balance a stack of two supercapacitors. Typically the input, SCAP, will be tied to VOUT to allow for increased energy storage at VOUT with supercapacitors. The BAL pin is tied to the middle of the stack and can source or sink 10mA to regulate the BAL pin's voltage to half that of the SCAP voltage. To disable the balancer and its associated quiescent current, the SCAP and BAL pins can be tied to ground. dc2048afb 3 DEMO MANUAL DC2048A Quick Start Procedure Using short twisted pair leads for any power connections, with all loads and power supplies off, refer to Figure 3 for the proper measurement and equipment setup. Follow the procedure below: 1. Before connecting PS1 to the DC2048A, PS1 must have its current limit set to 300mA and PS2 must have its current limit set to 500mA. For most power supplies with a current limit adjustment feature the procedure to set the current limit is as follows. Turn the voltage and current adjustment to minimum. Short the output terminals and turn the voltage adjustment to maximum. Adjust the current limit to 300mA for PS1 and 500mA for PS2. Turn the voltage adjustment to minimum and remove the short between the output terminals. The power supply is now current limited to 300mA and 500mA respectively. Verify that there is not a battery installed in the BH1 battery holder. 2. Initial Jumper, PS and LOAD settings: JP1 = 0 JP2 = 0 JP3 = 0 JP4 = 0 JP5 = 0 JP6 = 0 JP7 = 0 JP8 = 0 JP9 = 0 JP10 = 0 JP11 = OFF PS1 = OFF PS2 = OFF LOAD1 = OFF LOAD2 = OFF 3. Connect PS1 to the VIN terminals, then turn on PS1 and slowly increase voltage to 2.0V while monitoring the input current. If the current remains less than 5mA, increase PS1 to 5.0V. 4. Set LOAD1 to 50mA. Verify voltage on VOUT is within the VOUT 1.8V range in Table 1. Verify that the output ripple voltage is between 20mV and 60mV. Verify that PGVOUT is high. Decrease LOAD1 to 5mA.Verify that PGVOUT is high. Decrease PS1 to 0V. 5. Set JP1, JP2, JP3, JP4 to 1. Slowly increase PS1 to 16V and verify that VOUT is off. Increase PS1 to 19V and verify that VOUT is within the VOUT 1.8V range of Table 1. 6. Decrease PS1 to 0V and disconnect PS1 from VIN. Set the current limit of PS1 to 25mA as described above. 7. Connect PS1 to AC1 and slowly increase PS1 voltage to 2.0V while monitoring the input current. If the current remains less than 5mA, increase PS1 to 19V. Verify voltage on VOUT is within the VOUT 1.8V range in Table 1.Decrease PS1 to 0V, swap the AC1 connection to AC2 and repeat the test. Decrease PS1 to 0V and disconnect PS1 from AC2. 8. Set JP5 to 1, JP6 to 1, and JP7 to 1. Connect PS1 to the VIN turret. Increase PS1 to 19V and set LOAD1 to 50mA. Verify voltage on VOUT is within the VOUT 5.0V range in Table 1. Verify that the output ripple voltage is between 20mV to 60mV. Set PS1 to 0V and disconnect PS1. 9. Set JP1 to 1; JP2, JP3, JP4 and JP5 to 0; JP6 and JP7 to 1; PS1 to 0V and disconnect PS1. Connect PS2 to the BAT Terminals, then turn on PS2 and slowly increase voltage to 1.0V while monitoring the input current. If the current remains less than 5mA, increase PS2 to 2.0V. Verify voltage on VOUT is within the VOUT 3.0V range in Table 1. Verify that the output ripple voltage is between 20mV to 60mV. 10. Increase PS2 to 3.0V. Verify voltage on VOUT is within the VOUT 3.0V range in Table 1. Verify that the output ripple voltage is between 20mV to 60mV. 11. Increase PS2 to 5.0V. Verify voltage on VOUT is within the VOUT 3.0V range in Table 1. Verify that the output ripple voltage is between 20mV to 60mV. Decrease PS2 to 0V and disconnect PS2. 12. Set the current limit of PS1 to 300mA as described above. Connect PS1 to the VIN terminals. Set JP5 to 1, JP6 to 1 and JP7 to 1. Set PS1 to 14V.Connect a jumper lead from VOUT to LDO_IN. Verify that LDO is off. Move JP11 jumper to EN and verify that LDO_OUT is now 1.2V. Increase Load 2 to 50mA and verify than LDO is within the 1.2V range in Table 1. Verify that PGLDO is high. 13. Set JP8 to 1, JP9 to 1, JP10 to 1, verify that LDO_OUT is slightly below VOUT. Verify that PGLDO is low. dc2048afb 4 DEMO MANUAL DC2048A Quick Start Procedure 14. Add a jumper lead from VOUT to SCAP. Verify that BAL is approximately 1/2 of VOUT. 15. Set JP8 to 0, JP9 to 0 and JP10 to 0 and verify that LDO_OUT is now 1.2V. Quickly remove PS1 + lead from VIN and verify that LDO_OUT remains at 1.2V for approximately 5 seconds. 16. Turn off PS1, PS2, LOAD1 and LOAD2. Figure 3. Proper Measurement Equipment Setup dc2048afb 5 DEMO MANUAL DC2048A Connection to a Dust Mote (DC9003A-B) Figure 4. DC2048A with DustTM Mote Remove the battery from the BH1 holder on the bottom side of the DC2048A. Attach a Dust mote to J1 of the DC2048A, refer to Figure 4 for the proper setup. J1 is a keyed connector and is connected to the left side of the P1 connector on the Dust mote. Figure 12 is a schematic of the Dust mote and the DC2048A interconnections plus three extra connections which; 1) connect the SCAP to VOUT, 2) connect BAL to the middle of the supercapacitors and 3) connect EH_ON to OUT2. The DC2048A contains NC7SZ58P6X universal configurable 2-input logic gates that are input voltage tolerant and allow level shifting between the LTC3330 and the Dust mote. On the DC2048A set JP1 to 0, JP2 to 0, JP3 to 1, JP4 to 0, JP5 to 1, JP6 to 0, JP7 to 0, JP8, JP9 and JP10 to 0, JP11 to OFF. Piezoelectric Transducer Evaluation Mount a series connected MIDE V25W to a vibration source and connect the electrical connections to the AC1 and AC2 turrets. Activate the vibration source to an acceleration of 1G and a frequency of 60Hz. Figure 5 shows an open circuit voltage of 10.6V for the Mide V25W piezoelectric device that was tuned to 60Hz. In order to set the VIN_UVLO_RISING and VIN_UVLO_FALLING thresholds, the open circuit voltage of the piezoelectric device must be measured. The internal bridge network of the LTC3330 will have approximately 800mV drop at an input current of 300A. The peak power load voltage of a purely resistive source is at one half (1/2) of the rectified no load voltage. In this case, the optimal average input voltage regulation level would be 4.9V. Using a VIN_UVLO_RISING threshold of 6V and a VIN_UVLO_FALLING threshold of 5V (UV3 = 0, UV2 = 0, UV1 = 1, UV0 = 0) yields an average input voltage close to the theoretical optimal voltage. dc2048afb 6 DEMO MANUAL DC2048A Connection to a Dust Mote (DC9003A-B) Figure 6 is a plot of the output power and load voltage of the V25W piezoelectric transducer into a 42.2k load for various rms acceleration levels. The output power compares well with the input power that is charging CIN during the sleep cycle between VIN_UVLO_FALLING and VIN_UVLO_RISING thresholds at an acceleration force of 1grms, shown in Figure 7. VAC OC 10 1ms/DIV DC2048A F05 Figure 5. MIDE V25W Open Circuit AC Voltage with 1grms, 60Hz Acceleration Applied 700 600 6 POWER (W) LOAD VOLTAGE (VRMS) 42.2k LOAD 60Hz 5 POWER (W) 4 400 3 300 2 200 1 100 0 0.25 LOAD VOLTAGE (VRMS) 500 0.375 0.5 0.625 0.75 FORGE (g) 0.875 1 0 DC2048A F02 Figure 6. Mide V25W Output Power Into a 42.2k Load with 1grms, 60Hz Acceleration Applied to the Mide V25W Piezoelectric Transducer, [2 * sin(2 * 60Hz * t)] BH_ON 5V/DIV VOUT 1V/DIV VIN 2V/DIV 455s/DIV DC2048A F07 In Figure 7, the input capacitor is being recharged from the V25W piezoelectric transducer. The input capacitor is charging from 4.48V to 5.92V in 208 milli-seconds. The power delivered from the V25W is 648W. Assuming that the circuit is configured as shown in Figure 8, it will take a significant amount of time for the piezo transducer to charge the 0.09F supercapacitor on the output of the LTC3330. As used above, the 22F input capacitor is only 18F at an applied voltage of 5V, so every VIN_UVLO_RISING and FALLING event produces 26 micro-coulombs [(5.92V - 4.48V) * 18F)] that may be transferred from the input capacitor to the output capacitor, minus the losses of the buck regulator in the LTC3330. The buck regulator efficiency is approximately 90% at VIN equal to 5V and VOUT between 2.5V and 3.6V. Thus, for every UVLO event, 23.3 microcoulombs are added to the output supercapacitor. Given a 0.09F output supercapacitor charging to 3.6V, 324 millicoulombs are required to fully charge the supercapacitor. Assuming no additional load on the output, it takes 13,906 (.324/23.3e-6) UVLO events to charge the output supercapacitor to 3.6V. From Figure 7, it can be observed that each VIN_UVLO event takes 208ms so the total time to charge the output capacitor from 0V to 3.6V will be greater than 2900s. Figure 9 shows the no load charging of the output supercapacitor, which takes approximately 3300s. The above calculation neglects the lower efficiency at low output voltages and the time it takes to transfer the energy from the input capacitor to the output supercapacitor so predicting the actual value within -12% is to be expected. Figure 7. Mide V25W Charging the 18F Input Capacitance from 4.48V to 5.92V in 208ms dc2048afb 7 DEMO MANUAL DC2048A Connection to a Dust Mote (DC9003A-B) PIEZO MIDE V25W 22F 25V 4.7F, 6.3V AC1 AC2 VIN SW 1F 6V LTC3330 SWA CAP SWB VIN2 VOUT 22H 22H UV3 UV2 UV1 BAL UV0 BAT 22F 6V 180mF 2.5V SCAP 100F 10V 180mF 2.5V HZ202F PGVOUT EH_ON IPK2 IPK1 IPK0 OUT2 OUT1 OUT0 GND VIN3 1F 6V DC2048A F08 Figure 8. LTC3330 Circuit Charging Supercapacitor at No Load without a Battery (VOUT = 3.6V) EH_ON 5V/DIV VOUT 2V/DIV VIN 2V/DIV 500s/DIV DC2048A F09 Figure 9. Scope Shots of LTC3330 Charging Supercapacitor at No Load without a Battery (VOUT = 3.6V) dc2048afb 8 DEMO MANUAL DC2048A Connection to a Dust Mote (DC9003A-B) Figure 10 shows the LTC3330 with a supercapacitor on the output, a battery installed and the output voltage set to 3.6V. The scope shots in Figure 11 were taken after applying a pulsed load of 15mA for 10ms. With the battery attached and a pulsed load applied, the EH_ON signal will switch back and forth from high to low every time the VIN voltage transitions from the VIN_UVLO_RISING to VIN_UVLO_FALLING threshold. When the pulsed load is applied, the output capacitor is depleted slightly and the input capacitor must recharge the output cap. Because the input capacitance is much less than the output capacitance, the input capacitor will go through many UVLO transitions to charge the output capacitor back up to the sleep threshold. Once the output is charged to the output sleep threshold, the EH_ON signal will again be consistently high indicating that the energy harvesting source is powering the output. PIEZO MIDE V25W AC1 AC2 VIN SW 1F 6V 22F 25V 4.7F, 6V LTC3330 SWA CAP SWB VIN2 VOUT 22H 22H 100F 10V UV3 UV2 BAL UV0 + BAT PRIMARY CELL 3.2V 22F 6V 180mF 2.5V SCAP UV1 PULSED 15mA 10ms 180mF 2.5V HZ202F PGVOUT EH_ON IPK2 IPK1 IPK0 OUT2 OUT1 OUT0 GND VIN3 1F 6V DC2048A F10 Figure 10. LTC3330 Circuit with a Supercapacitor, a Battery Installed and a Pulsed Load Applied (VOUT = 3.6V) EH_ON 5V/DIV VOUT 50mV/DIV VIN 2V/DIV LOAD CURRENT 20mA/DIV 1s/DIV DC2048A F11 Figure 11. Charging a Supercapacitor with a Battery Installed and a Pulsed Load (VOUT = 3.6V) dc2048afb 9 DEMO MANUAL DC2048A Connection to a Dust Mote (DC9003A-B) Figure 12 shows the LTC3330 with an output supercapacitor, a Dust mote attached, a battery installed and EH_ON connected to OUT2. In this configuration, when EH_ON is low, VOUT will be set to 2.5V and when EH_ON is high, VOUT will be set to 3.6V. The first marker in Figure 13 is where the vibration source was activated; VIN then rises above the VIN_UVLO_RISING threshold. EH_ON will then go high causing VOUT to rise towards 3.6V (VOUT started at 2.5V because the battery had charged it up initially). At the same time EH_ON goes high, PGVOUT will go low, since the new VOUT level of 3.6V has not been reached. As the charge on VIN is being transferred to VOUT, VIN is discharging and when VIN reaches its UVLO_FALLING threshold, EH_ON will go low, causing the targeted VOUT to again be 2.5V. Given that the output capacitor is very large and the average load is less than the input power supplied by the Mide piezoelectric transducer, the output voltage will increase to the higher set-point of 3.6V over many cycles. During the transition from the BAT set-point of 2.5V to the energy harvester set-point of 3.6V, VOUT is above the 2.5V PGVOUT threshold, hence, PGVOUT will go high every time EH_ON goes low. This cycle will be repeated until VOUT reaches the PGVOUT threshold for the VOUT setting of 3.6V. When a pulse load is applied that is greater than the energy supplied by the input capacitor, VIN will drop below the VIN_UVLO_FALLING threshold, EH_ON will go low and the buck-boost regulator will be ready to support the load requirement from the battery, but will not start to switch until the supercapacitor is discharged to 2.5V. In this way, the circuit can store a lot of harvested energy and use it for an extended period of time before switching over to the battery energy. The supercapacitor could be sized to accommodate known repeated periods of time that the energy harvester source will not be available, such as overnight when a vibrating machine is turned off or in the case of a solar application, when the lights are turned off or the sun goes down. PIEZO MIDE V25W AC1 AC2 VIN SW 1F 6V 22F 25V 4.7F, 6V LTC3330 SWA CAP SWB VIN2 VOUT 22H 22H VOUT = 3.6V FOR EH_ON = 1 VOUT = 2.5V FOR EH_ON = 0 100F 10V UV3 UV2 BAL UV0 + 180mF 2.5V SCAP UV1 180mF 2.5V HZ202F BAT CR2032 22F 6V IPK2 PGVOUT IPK1 EHORBAT NC7SZ58P8X (x2) OUT2 OUT1 GND VIN3 TX PGOOD EH_ON IPK0 OUT0 VSUPPLY 1F 6V GND LINEAR TECHNOLOGY DC9003A-A/B DUST MOTE FOR WIRELESS MESH NETWORKS DC2048A F12 Figure 12. Dust Mote Setup with a Supercapacitor, a Battery and EH_ON Connected to OUT2 dc2048afb 10 DEMO MANUAL DC2048A Connection to a Dust Mote (DC9003A-B) While the EH_ON signal is low the buck-boost circuit will consume 750nA from the battery in the sleeping state. The effects of a pulsed load are shown in Figure 13 at approximately 1850s, where VIN is discharged and the EH_ON signal pulses low to high for a brief period of time, which occurred as a result of the Dust mote radio making a data transmission. Figure 14 shows the discharging of VOUT when the vibration source is removed and VIN drops below the UVLO_FALLING threshold causing EH_ON to go low. The supercapacitor on VOUT will discharge down to the new target voltage of 2.5V at which point the buck-boost regulator will turn on supplying power to the Dust mote. The discharging of the supercapacitor on VOUT provides an energy source for short term loss of the vibration source and extends the life of the battery. Figure 15 is the same Dust mote configuration as Figure 12 but without the output supercapacitor. Figure 16 shows the charging of the output without the supercapacitor attached. POVOUT 5V/DIV POVOUT 5V/DIV EH_ON 5V/DIV EH_ON 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VIN 200V/DIV VIN 200V/DIV 200s/DIV DC2048A F13 Figure 13. Mide 25W Charging Output Supercapacitor from 2.5V to 3.6V with Dust Mote Attached 200s/DIV DC2048A F14 Figure 14. Output Supercapacitor Discharging When the Vibration Source Is Switched Off dc2048afb 11 DEMO MANUAL DC2048A Connection to a Dust Mote (DC9003A-B) PIEZO MIDE V25W AC1 AC2 VIN SW 1F 6V 22F 25V 4.7F, 6V LTC3330 SWA CAP SWB VIN2 VOUT 22H 22H VOUT = 3.6V FOR EH_ON = 1 VOUT = 2.5V FOR EH_ON = 0 100F 10V UV3 UV2 SCAP UV1 BAL UV0 + VSUPPLY BAT CR2032 22F 6V IPK2 PGVOUT IPK1 EH_ON IPK0 EHORBAT NC7SZ58P8X (x2) OUT2 OUT1 OUT0 GND VIN3 TX PGOOD GND LINEAR TECHNOLOGY DC9003A-A/B DUST MOTE FOR WIRELESS MESH NETWORKS 1F 6V DC2048A F15 Figure 15. Dust Mote Setup without a Supercapacitor and with EH_ON Connected to OUT2 POVOUT 500V/DIV EH_ON 500V/DIV VOUT 1V/DIV VIN 200V/DIV 100ms/DIV DC2048A F16 Figure 16. Output Voltage Charging with Dust Mote Attached without Supercapacitor dc2048afb 12 DEMO MANUAL DC2048A Parts List ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER Required Circuit Components 1 1 BAT1 CR2032 COIN LI-ION BATTERY DURACELL, CR2032 2 1 BTH1 SMT, CR2032 BATTERY HOLDER MPD INC, BU2032SM-HD-GCT-ND 3 1 C1 SUPERCAP, 90mF, 5.5V, 20mm x 15mm CAP-XX, HZ202F 4 1 C2 CAP, CHIP, X5R, 150F, 20%, 10V, 1210 SAMSUNG, CL32A157MQVNNNE 5 2 C7, C8 CAP, CHIP, X5R, 22F, 20%, 6.3V, 1206 SAMSUNG, CL31A226MQHNNNE 6 2 C3, C6 CAP, CHIP, X5R, 1F, 10%, 6.3V, 0402 SAMSUNG, CL05A105KQ5NNNC 7 1 C11 CAP, CHIP, X5R, 10F, 10%, 6.3V, 0805 SAMSUNG, CL21A106KQFNNNE 8 1 C4 CAP, CHIP, X5R, 22F, 10%, 25V, 1210 SAMSUNG, CL32A226KAJNNNE 9 1 C5 CAP, CHIP, X5R, 4.7F, 10%, 6.3V, 0603 SAMSUNG, CL104A475KQ8NNNE 10 1 L1 INDUCTOR, 22H, 0.800A, 0.36, 3.9mm x 3.9mm COILCRAFT, LPS4018-223MLC 11 1 L2 INDUCTOR, 22H, 0.75A, 0.19, 4.8mm x 4.8mm COILCRAFT, LPS5030-223MLC 12 3 R2, R4, R6 RES, CHIP, 0, 0603 VISHAY, CRCW06030000Z0EA 13 0 R3, R5, R7 RES, CHIP, 0, 0603 VISHAY, CRCW06030000Z0EA 14 1 R10 RES, CHIP, 10M, 1/10W, 5%, 0603 VISHAY, CRCW060310M0JNEA 15 1 U1 ENERGY HARVESTING DC/DC WITH BATTERY LINEAR TECH, LTC3330EUH Additional Demo Board Circuit Components 1 0 C9, C10 (OPT) CAP, CHIP, X5R, 0.1F, 10%, 10V, 0402 TDK, C1005X5R1A104K 2 0 C12 SUPERCAP, 330mF, 55V, 60m MURATA, DMF3R5R5L334M3DAO 3 0 BTH2 SMT, CR2477 BATTERY HOLDER RENATA, SMTU2477-1 4 1 R1 RES,CHIP, 1k, 1/16W, 1%, 0402 VISHAY, CRCW04021K00FKED 5 0 R8, R9 RES, CHIP, 7.5k, 1/16W,1%,0402 VISHAY, CRCW04027K50FKED 6 3 U2, U3, U4 IC, UHS UNIV. CONFIG. TWO-INPUT GATES, SC70-6 FAIRCHILD, NC7SZ58P6X Hardware: For Demo Board Only 1 15 E1-E8, E12-E19 TURRET, 0.09 DIA MILL-MAX, 2501-2 2 3 E9-E11 TURRET, 0.061 DIA MILL-MAX, 2308-2 3 1 J1 HEADER, 12 PIN, DUST HEADER 2x6 SAMTEC, SMH-106-02-L-D-05 4 10 JP1-JP10 HEADER, 3 PINS, 2mm SAMTEC, TMM-103-02-L-S 5 1 JP11 HEADER, 4 PINS, 2mm SAMTEC, TMM-104-02-L-S 6 11 JP1-JP11 SHUNT 2MM SAMTEC, 2SN-BK-G dc2048afb 13 A B C D JP5 E5 E4 E3 E2 E1 PGVOUT + E12 E11 E10 E9 E8 E7 PGLDO EH_ON GND LDO_EN GND E6 BTH1 SMTU2032-LF BAT 1.8V-5.5V GND 3V - 19V VIN * AC2 * AC1 R1 BAT C4 22uF 1210 25V * CAUTION: 50mA MAX 0 1 GND 1K 22uF 6.3V C8 1206 0603 R10 10M 5% LDO_EN BTH2 SMTU2477N-LF OPT 5 PGVOUT PGLDO EH_ON JP11 26 VIN3 VIN3 PGVOUT PGLDO 0 1 JP9 LDO1 0 JP10 LDO0 1 DNP R3 DNP VOUT 13 SW 12 SWB 14 SWA 15 UV0 7 UV1 6 UV2 5 UV3 4 IPK0 17 C7 22uF 1206 6.3V 7.5k E13 E14 R9 OPT 0.1uF 10V C9 OPT GND 1.2V - LDO_IN 50mA LDO_OUT 0.1uF 10V C10 OPT 7.5k R8 OPT 4 BAL 0 0805 6.3V + 2 CUSTOMER NOTICE - BAL E17 E18 VOUT 1.8V - 5.0V LDO_IN E15 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 3 GND 1.8V - 5.0V 50mA E19 JP4 UV0 E16 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 UV3 2 JD 2 SCALE = NONE NC PCB DES. APP ENG. 3 - JD APPROVED DATE 7 - 29 - 13 LDO VOLTAGE SELECTION OUT2 OUT1 OUT0 VOUT 1.8V 0 0 0 0 2.5V 0 1 0 2.8V 1 0 3.0V 0 1 1 3.3V 1 0 0 3.6V 1 0 1 4.5V 1 1 0 5.0V 1 1 1 OUTPUT VOLTAGE SELECTION DESCRIPTION PRODUCTION FAB REV ECO 1 REVISION HISTORY DATE: N/A SIZE TECHNOLOGY 7 - 29 - 13 IC NO. 1 LTC3330EUH DEMO CIRCUIT 2048A SHEET 1 3 OF 2 REV. NANOPOWER BUCK - BOOST DC / DC WITH ENERGY HARVESTING BATTERY LIFE EXTENDER TITLE: SCHEMATIC 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only LDO2 LDO1 LDO 0 LDO_OUT 0 0 0 1.2V UVLO SELECTION 1 0 0 1.5V 0 UVLO 1 0 UVLO 1.8V UV2 UV1 UV0 RISING FALLING 0 1 1 2.0V 0 0 0 3V 4V 1 0 0 2.5V 0 0 1 4V 5V 1 0 1 3.0V 0 1 0 5V 6V 1 1 0 3.3V 0 1 1 6V 7V 1 1 1 = LDO_IN 1 0 0 7V 8V ILM SELECTION 0 5V 8V 1 1 INSTALL 0 9V 1 1 10V 5V 10V 1 1 1 IPK2 IPK1 IPK0 ILIM R3 0 0 0 12V R5 R7 5mA 11V R3 5V 0 0 1 12V R5 R6 10mA R3 0 1 0 14V 13V R4 R7 15mA R3 5V 0 1 1 14V R4 R6 25mA R2 0 0 1 16V 15V R5 R7 50mA R2 5V 0 1 1 16V R5 R6 100mA R2 0 1 1 18V R4 R7 150mA 17V R2 1 1 1 18V 5V R4 R6 250mA APPROVALS BAL SCAP C12 OPT 330mF 5.5V DMF3R5R5L334M3DTA0 21mm x 14mm VOUT JP3 UV1 VIN2 1 C11 10uF VOUT C1 90mF 5.5V HZ202F 20mm x 15mm JP2 UV2 R7 R6 LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. + LDO_IN C2 150uF 1210 6.3V JP1 0 1 DNP 0 3 Figure 17. DC2048A Demo Circuit Schematic 3. INSTALL SHUNTS ON JUMPERS AS SHOWN. 2. ALL CAPACITORS ARE IN MICROFARADS, 0402, 10%, 10V. 1. ALL RESISTORS ARE IN OHMS, 0402, 1%, 1/16W. 3 22uH L2 R5 R4 VIN3 UV3 22uH L1 0 1 0 R2 0 NOTES: UNLESS OTHERWISE SPECIFIED U1 LTC3330EUH 33 GND 29 EH_ON 25 LDO_EN 16 BAT 3 VIN2 11 CAP 10 VIN VIN2 EN EXT OFF LDO_EN LDO_EN BAT C6 1uF 6.3V 0603 6.3V 6.3V C3 1uF 9 AC2 8 AC1 JP8 0 JP7 0 4.7uF JP6 LDO2 1 OUT0 1 C5 0 OUT1 OUT2 32 1 EH_ON I 2 OUT1 31 4 27 LDO2 22 PGLDO OUT0 30 PGVOUT 28 LDO1 23 LDO_OUT BAL 20 1 1 I 2 IPK2 19 SCAP 2 LDO0 24 LDO_IN 21 OUT2 1 LDO_IN IPK1 18 LDO_IN 1 VIN3 2 1 + 14 3 5 A B C D DEMO MANUAL DC2048A Schematic Diagram dc2048afb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. A B C D L L L L H L I0 H L Y 5 Y= ( I 0 ) . ( I 2) + ( I 1 ) . ( I 2 ) I1 I2 U2, U3, U4 FUNCTION TABLE PGLDO LDO_EN EH_ON PGVOUT PGLDO LDO_EN EH_ON PGVOUT 3 I0 1 I1 6 I2 4 VOUT VCC 5 GND 2 VOUT 3 I0 1 I1 6 I2 VCC 5 GND Y 4 U3 NC7SZ58P6X Y 4 U2 NC7SZ58P6X 3 I0 1 I1 6 I2 4 +5V 11 SMH-106-02-L-D-05 3 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. 2 JD 2 SCALE = NONE NC PCB DES. APP ENG. APPROVALS I/O 2 9 12 V+ DUST HEADER 2X6 RSVD 7 8 EHORBAT VOUT 10 I/O 1 KEY 5 6 VBAT CUSTOMER NOTICE BAT GND 3 VSUPPLY 1 4 PGOOD J1 2 NC LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. BAT 3 Figure 18. DC2048A Demo Circuit Schematic OVERVOLTAGE TOLERANT BUFFERS TRANSLATE THE HIGH PULL-UP VOLTAGES FROM THE LTC3330 TO THE VOUT VOLTAGE DRIVING THE PROCESSOR I/O BUS, WHICH IS VOUT. Y 4 U4 NC7SZ58P6X (NO BUFFER IS NEEDED) LDO_EN LOGIC IS POWERED BY VOUT 2 VOUT VCC 5 GND 2 5 DATE: N/A SIZE TECHNOLOGY 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only 7 - 29 - 13 IC NO. 1 LTC3330EUH DEMO CIRCUIT 2048A SHEET 2 3 OF 2 REV. NANOPOWER BUCK - BOOST DC / DC WITH ENERGY HARVESTING BATTERY LIFE EXTENDER TITLE: SCHEMATIC VOUT 1 A B C D DEMO MANUAL DC2048A Schematic Diagram dc2048afb 15 DEMO MANUAL DC2048A DEMONSTRATION BOARD IMPORTANT NOTICE Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions: This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations. If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive. Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged. This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC application engineer. Mailing Address: Linear Technology 1630 McCarthy Blvd. Milpitas, CA 95035 Copyright (c) 2004, Linear Technology Corporation dc2048afb 16 Linear Technology Corporation LT 0315 REV B * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2014