M29F800AB70M1T - STMicroelectronics

1/21

PRELIMINARY DATA

January 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M29F800AT

M29F800AB

8 Mbit (1Mb x8 or 512Kb x16, Boot Block)

Single Supply Flash Memory

■SINGLE 5V±10% SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPERATIONS

■ACCESS TIME: 70ns

■PROGRAMMING TIME

–8µs per Byte/Word typical

■19 MEMORY BLOCKS

– 1 Boot Block (Top or Bottom Location)

– 2 Parameter and 16 Main Blocks

■PROGRAM/ERASE CONTROLLER

– Embedded Byte/Word Program algorithm

– Embedded Multi-Block/Chip Erase algorithm

– Status Register Polling and Toggle Bits

– Ready/Busy Output Pin

■ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■TEMPORARY BLOCK UNPROTECTION

MODE

■LOW POWER CONSUMPTION

– Standby and Automatic Standby

■100,000 PROGRAM/ERASE CYCLES per

BLOCK

■20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h

– M29F800AT Device Code: 00ECh

– M29F800AB Device Code: 0058h

TSOP48 (N)

12 x 20mm SO44 (M)

Figure 1. Logic Diagram

AI02198B

A0-A18

DQ0-DQ14

VCC

M29F800AT

M29F800AB

VSS

DQ15A–1

BYTE

M29F800AT, M29F800AB

2/21

Figure 2A. TSOP Connections

DQ3

DQ9

DQ2

DQ0

DQ6

DQ13

DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI02199

M29F800AT

M29F800AB

24 25

DQ8

DQ1

DQ11

A16

BYTE

VSS

A17

A10

A18

A12

A13

A11

A15

A14

Table 1. Signal Names

A0-A18 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

E Chip Enable

G Output Enable

W Write Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

SUMMARY DESCRIPTION

The M29F800A is an 8 Mbit (1Mb x8 or 512Kb

x16) non-volatile memorythat canbe read,erased

and reprogrammed. These operations canbe per-

formed using a single 5V supply. On power-up the

memory defaults to its Read mode where it can be

read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while olddata is erased.Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

Figure 2B. SO Connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

A18 RP

AI02101B

M29F800AT

M29F800AB

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

3/21

M29F800AT, M29F800AB

The blocks in the memory are asymmetrically ar-

ranged, see Tables 3A and 3B, Block Addresses.

The first or last 64 Kbytes have been divided into

four additional blocks. The 16 Kbyte Boot Block

can beused for small initialization code to start the

microprocessor, the two 8 Kbyte Parameter

Blocks can be used for parameter storage and the

remaining 32K isa small MainBlock where the ap-

plication may be stored.

Chip Enable, OutputEnable andWrite Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is offered in TSOP48 (12 x 20mm)

and SO44 packages. Access times of 70ns and

90ns are available. The memory is supplied with

all the bits erased (set to ’1’).

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A18). The Address Inputs

select thecells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output thedata stored atthe selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sentto the CommandInterfaceof theinternalstate

machine.

Data Inputs/Outputs (DQ8-DQ14). The Data In-

puts/Outputs output thedata stored atthe selected

address during a Bus Read operation when BYTE

is High, VIH. When BYTE is Low, VIL, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits. When reading the Status Register

these bits should be ignored.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, VIL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of theWord

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to include this pin when BYTE is Low except

when stated explicitly otherwise.

Table 2. Absolute Maximum Ratings (1)

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions forextended periods may affect device reliability. Referalso to theSTMicroelectronics SURE Program and other relevantqual-

ity documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C

Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C

Ambient Operating Temperature (Temperature Range Option 3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage –0.6 to 6 V

VCC Supply Voltage –0.6 to 6 V

VID Identification Voltage –0.6 to 13.5 V

M29F800AT, M29F800AB

4/21

Table 3A. M29F800AT Block Addresses

Size

(Kbytes) Address Range

(x8) Address Range

(x16)

16 FC000h-FFFFFh 7E000h-7FFFFh

8 FA000h-FBFFFh 7D000h-7DFFFh

8 F8000h-F9FFFh 7C000h-7CFFFh

32 F0000h-F7FFFh 78000h-7BFFFh

64 E0000h-EFFFFh 70000h-77FFFh

64 D0000h-DFFFFh 68000h-6FFFFh

64 C0000h-CFFFFh 60000h-67FFFh

64 B0000h-BFFFFh 58000h-5FFFFh

64 A0000h-AFFFFh 50000h-57FFFh

64 90000h-9FFFFh 48000h-4FFFFh

64 80000h-8FFFFh 40000h-47FFFh

64 70000h-7FFFFh 38000h-3FFFFh

64 60000h-6FFFFh 30000h-37FFFh

64 50000h-5FFFFh 28000h-2FFFFh

64 40000h-4FFFFh 20000h-27FFFh

64 30000h-3FFFFh 18000h-1FFFFh

64 20000h-2FFFFh 10000h-17FFFh

64 10000h-1FFFFh 08000h-0FFFFh

64 00000h-0FFFFh 00000h-07FFFh

Table 3B. M29F800AB Block Addresses

Size

(Kbytes) Address Range

(x8) Address Range

(x16)

64 F0000h-FFFFFh 78000h-7FFFFh

64 E0000h-EFFFFh 70000h-77FFFh

64 D0000h-DFFFFh 68000h-6FFFFh

64 C0000h-CFFFFh 60000h-67FFFh

64 B0000h-BFFFFh 58000h-5FFFFh

64 A0000h-AFFFFh 50000h-57FFFh

64 90000h-9FFFFh 48000h-4FFFFh

64 80000h-8FFFFh 40000h-47FFFh

64 70000h-7FFFFh 38000h-3FFFFh

64 60000h-6FFFFh 30000h-37FFFh

64 50000h-5FFFFh 28000h-2FFFFh

64 40000h-4FFFFh 20000h-27FFFh

64 30000h-3FFFFh 18000h-1FFFFh

64 20000h-2FFFFh 10000h-17FFFh

64 10000h-1FFFFh 08000h-0FFFFh

32 08000h-0FFFFh 04000h-07FFFh

8 06000h-07FFFh 03000h-03FFFh

8 04000h-05FFFh 02000h-02FFFh

16 00000h-03FFFh 00000h-01FFFh

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing BusRead and BusWriteop-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP). The Re-

set/Block Temporary Unprotect pin can be used to

apply a Hardware Reset to the memory or to tem-

porarily unprotect all blocks that have been pro-

tected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, VIH, the memory will be ready for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy

Output section, Table 14 and Figure 10, Reset/

Temporary Unprotect AC Characteristics for more

details.

Holding RP at VID will temporarily unprotect the

protected blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH toVID mustbe slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain outputthat can be used to identify

when the memory array can be read. Ready/Busy

is high-impedance during Read mode,Auto Select

mode and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 14 and Figure

10, Reset/Temporary Unprotect AC Characteris-

tics.

During Program or Erase operations Ready/Busy

is Low, VOL. Ready/Busy will remain Low during

Read/Reset commands or Hardware Resets until

the memory is ready to enter Read mode.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Byte/WordOrganizationSelect (BYTE). The Byte/

Word Organization Select pin is used to switch be-

tween the 8-bit and 16-bit Bus modes of the mem-

ory. When Byte/Word Organization Select is Low,

VIL, the memory is in 8-bit mode, when it is High,

VIH, the memory is in 16-bit mode.

5/21

M29F800AT, M29F800AB

Table 4A. Bus Operations, BYTE = VIL

Note: X = VIL or VIH.

Table 4B. Bus Operations, BYTE = VIH

Note: X = VIL or VIH.

Operation E G W Address Inputs

DQ15A–1, A0-A18 Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL,A1=V

IL,A9=V

ID,

Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = VIH,A1=V

IL,A9=V

ID,

Others VIL or VIH Hi-Z ECh (M29F800AT)

58h (M29F800AB)

Operation E G W Address Inputs

A0-A18 Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH X Hi-Z

Standby VIH X X X Hi-Z

Read Manufacturer

Code VIL VIL VIH A0 = VIL,A1=V

IL,A9=V

ID,

Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH,A1=V

IL,A9=V

ID,

Others VIL or VIH 00ECh (M29F800AT)

0058h (M29F800AB)

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the VCC Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, ICC4.

VSS Ground. TheVSS Groundis thereference for

all voltage measurements.

BUS OPERATIONS

There arefive standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Tables 4A and 4B, Bus Operations, for a summa-

ry. Typically glitches of less than 5ns on Chip En-

able or Write Enable are ignored by the memory

and do not affect bus operations.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, VIL, to Chip Enable

and Output Enable and keeping Write Enable

High, VIH. The Data Inputs/Outputs will output the

value, see Figure 7, Read Mode AC Waveforms,

and Table 11, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

M29F800AT, M29F800AB

6/21

dress Inputs. The Address Inputs are latched by

the CommandInterface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occursfirst. Output En-

able must remain High, VIH, during the whole Bus

Write operation. See Figures 8 and 9, Write AC

Waveforms, and Tables 12 and 13, Write AC

Characteristics, for details of the timing require-

ments.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, VIH.

Standby. When Chip Enable is High, VIH, the

Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is re-

duced to the Standby level.

When Chip Enable is at VIH the Supply Current is

reduced to the TTL Standby Supply Current, ICC2.

To further reduce the Supply Current to the CMOS

Standby Supply Current, ICC3, ChipEnable should

be held within VCC ±0.2V. For Standby current

levels see Table 10, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, ICC4, for Program or Erase operationsun-

til the operation completes.

Automatic Standby. If CMOSlevels (VCC ±0.2V)

are usedto drive the busand the busisinactivefor

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the CMOSStandby Supply Current, ICC3.

The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to

read the Electronic Signature and also to apply

and remove Block Protection. These bus opera-

tions are intended for use by programming equip-

ment and are not usually used in applications.

They require VID to be applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Tables 4A and 4B, Bus Operations.

Block Protection and BlocksUnprotection. Each

block can be separately protected against acci-

dental Program or Erase. Protected blocks can be

unprotected to allow data to be changed. Block

Protection and Block Unprotection operations

must only be performed on programming equip-

ment.

For further information refer to Application Note

AN1122, Applying Protection and Unprotection to

M29 Series Flash.

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. In this case, after at least 50ns,

an address transition or Chip Enable going Low is

required before reading correct data. The long

command sequences are imposed to maximize

data security.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. See either Table 5A, or 5B, depending

on the configuration that is being used, for a sum-

mary of the commands.

Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM. It also resets

the errors in the Status Register. Either one or

three Bus Write operations can be used to issue

the Read/Reset command.

If the Read/Reset command is issued during a

Block Erase operation orfollowing a Programming

or Erase errorthen the memory will takeup to10µs

to abort. During the abort period no valid data can

be read from the memory. Issuing a Read/Reset

command during a Block Erase operation will

leave invalid data in the memory.

Auto Select Command. The Auto Select com-

mand is used to read the Manufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until another com-

mand is issued.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A0 = VIL and A1 = VIL. The other address bits

may be set to either VIL or VIH. The Manufacturer

Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read

operation with A0 = VIH and A1 = VIL. The other

address bits may be set to either VIL or VIH. The

Device Codefor the M29F800AT is 00ECh and for

the M29F800AB is 0058h.

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = VIL,

A1 = VIH, and A12-A18 specifying the address of

the block. The other address bits may be set to ei-

ther VIL or VIH. If the addressed block is protected

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

7/21

M29F800AT, M29F800AB

Table 5A. Commands, 16-bit mode, BYTE = VIH

Table 5B. Commands, 8-bit mode, BYTE = VIL

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8-DQ14 and DQ15 are Don’t Care.

DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.

Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase Controller completes and the

memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus WriteOperations until the Timeout

Bit is set.

Erase Suspend. After theErase Suspend command readnon-erasing memory blocks as normal, issue AutoSelect and Program commands

on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

quires fourBus Write operations, the final writeop-

eration latches the address and data in theinternal

state machine and starts the Program/Erase Con-

troller.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the memory will ig-

nore all commands. It is not possible to issue any

command to abort or pause the operation. Typical

program timesare given inTable 6. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory will return to the Read mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset commandmust beissued to re-

set the error condition and return to Read mode.

Note thatthe Program command cannot change a

bit set at ’0’ backto ’1’and attempting to do so will

cause an error. One of the Erase Commands must

be used to set all the bits in a blockor in thewhole

memory from ’0’ to ’1’.

M29F800AT, M29F800AB

8/21

Chip Erase Command. The Chip Erase com-

mand can beused to erasethe entirechip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears tostart but will terminate withinabout100µs,

leaving the data unchanged. No error condition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

times are given in Table 6. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Write operation using the address of the

additional block. The Block Erase operation starts

the Program/Erase Controller about 50µs after the

last Bus Write operation. Oncethe Program/Erase

Controller starts it is not possible to select any

more blocks.Each additional block must therefore

be selectedwithin 50µs of the last block. The 50µs

timer restarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register for

details on how to identify if the Program/Erase

Controller has started the Block Erase operation.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un-

changed.No error conditionis given when protect-

ed blocks are ignored.

During the Block Erase operation the memory will

ignore all commands except the Erase Suspend

and Read/Reset commands. Typical block erase

times are given in Table 6. All Bus Read opera-

tions during the Block Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Block Erase operation has completedthe

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset commandmust beissued to re-

set the error condition and return to Read mode.

The Block Erase Command sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend

Command may be used to temporarily suspend a

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

(TA= 0 to 70°C, –40 to 85°C or –40 to 125°C)

Note: 1. TA=25°C, VCC =5V.

Parameter Min Typ (1) Typical after

100k W/E Cycles (1) Max Unit

Chip Erase (All bits in the memory set to ‘0’) 3 3 sec

Chip Erase 8 8 30 sec

Block Erase (64 Kbytes) 0.6 0.6 4 sec

Program (Byte or Word) 8 8 150 µs

Chip Program (Byte by Byte) 9 9 35 sec

Chip Program (Word by Word) 4.5 4.5 18 sec

Program/Erase Cycles (per Block) 100,000 cycles

9/21

M29F800AT, M29F800AB

The Program/Erase Controller will suspend within

15µs of the Erase Suspend Command being is-

sued. Once the Program/Erase Controller has

stopped the memory will be set to Read mode and

the Erasewill be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is suspended immediately and will start im-

mediately when the Erase Resume Command is

issued. It will not be possible to select any further

blocks for erasure after the Erase Resume.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. Reading from blocks that

are being erased will output the Status Register. It

is alsopossible to enter theAuto Select mode: the

memory will behave as in the Auto Select mode on

all blocks until a Read/Reset command returns the

memory to Erase Suspend mode.

Erase Resume Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resumed more than once.

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It isalso readduring EraseSus-

pend when an address within a block being erased

is accessed.

The bits in the Status Register are summarized in

Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operationsfrom the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 3, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

Table 7. Status Register Bits

Note: Unspecified data bits should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 – – 0

Program During Erase

Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No Toggle 0 1 Toggle 1

Non-Erasing Block Data read as normal 1

Erase Error Good Block Address 0 Toggle 1 1 No Toggle 0

Faulty Block Address 0 Toggle 1 1 Toggle 0

M29F800AT, M29F800AB

10/21

Figure 3. Data Polling Flowchart

READ DQ5&

DQ7

at VALID ADDRESS

START

READ DQ7

FAIL PASS

AI01369

DQ7

DATA YES

YES

DQ5

DQ7

DATA YES

Figure 4. Data Toggle Flowchart

READ

DQ5 & DQ6

START

READ DQ6

FAIL PASS

AI01370

DQ6

TOGGLE NO

YES

DQ5

YES

DQ6

TOGGLE

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation thememo-

ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

Figure 4, Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

Note thatthe Program command cannot change a

bit set at ’0’ backto ’1’and attempting to do so will

cause an error. One of the Erase Commands must

be used to set all the bits in a blockor in thewhole

memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional blocks to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

11/21

M29F800AT, M29F800AB

Figure 5. AC Testing Input Output Waveform

AI01275B

High Speed

1.5V

2.4V

Standard

0.45V

2.0V

0.8V

Figure 6. AC Testing Load Circuit

AI03027

1.3V

OUT

CL= 30pF or 100pF

CLincludes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 9. Capacitance

(TA=25°C, f = 1 MHz)

Note: Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6pF

OUT Output Capacitance VOUT =0V 12 pF

Table 8. AC Measurement Conditions

Parameter M29F800A

70 90

ACTest Conditions High Speed Standard

Load Capacitance (CL) 30pF 100pF

Input Rise and Fall Times ≤10ns ≤10ns

Input Pulse Voltages 0 to 3V 0.45 to 2.4V

Input and Output Timing Ref.Voltages 1.5V 0.8V and 2.0V

M29F800AT, M29F800AB

12/21

Table 10. DC Characteristics

(TA= 0 to 70°C, –40 to 85°C or –40 to 125°C)

Note: 1. Sampled only, not 100% tested.

2. TA=25°C, VCC =5V.

Symbol Parameter Test Condition Min Typ. (2) Max Unit

ILI Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

ICC1 Supply Current (Read) E=VIL,G=V

IH, f = 6MHz 10 20 mA

ICC2 Supply Current (Standby) TTL E=V

IH 1mA

CC3 Supply Current (Standby) CMOS E=V

CC ±0.2V,

RP = VCC ±0.2V 35 150 µA

ICC4 (1) Supply Current (Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

VOH Output High Voltage TTL IOH = –2.5mA 2.4 V

Output High Voltage CMOS IOH = –100µAV

CC –0.4 V

ID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO (1) Program/Erase Lockout Supply

Voltage 3.2 4.2 V

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

During Chip Erase and Block Eraseoperations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the blocksbeing erased. Once the operation

completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change ifthe addressed block has erased cor-

rectly.

13/21

M29F800AT, M29F800AB

Figure 7. Read Mode AC Waveforms

AI02981

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

Table 11. ReadAC Characteristics

(TA = 0 to 70°C, –40 to 85°C or –40 to 125°C)

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition M29F800A Unit

70 90

tAVAV tRC Address Valid to Next Address Valid E=V

IL,

G=V

IL Min 70 90 ns

tAVQV tACC Address Valid to Output Valid E=V

IL,

G=V

IL Max 70 90 ns

tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G=V

IL Max 70 90 ns

tGLQX (1) tOLZ Output Enable Low to Output Transition E=V

IL Min 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E=V

IL Max 30 35 ns

tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G=V

IL Max 20 20 ns

tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 20 20 ns

tEHQX

tGHQX

tAXQX tOH Chip Enable, Output Enable or

Address Transition to Output Transition Min 0 0 ns

tELBL

tELBH tELFL

tELFH Chip Enable to BYTE Low or High Max 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 20 20 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns

M29F800AT, M29F800AB

14/21

Figure 8. Write AC Waveforms, Write Enable Controlled

AI02183

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

Table 12. Write AC Characteristics, Write Enable Controlled

(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F800A Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 45 45 ns

tDVWH tDS Input Valid to Write Enable High Min 30 45 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns

tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs

15/21

M29F800AT, M29F800AB

Table 13. Write AC Characteristics, Chip Enable Controlled

(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F800A Unit

70 90

tAVAV tWC Address Valid to Next Address Valid Min 70 90 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 30 45 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns

tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 35 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs

Figure 9. Write AC Waveforms, Chip Enable Controlled

AI02184

A0-A18/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

M29F800AT, M29F800AB

16/21

Table 14. Reset/Block Temporary Unprotect AC Characteristics

(TA= 0 to 70 °C, –40 to 85 °C or –40 to 125 °C)

Note: 1. Sampled only, not 100% tested.

Symbol Alt Parameter M29F800A Unit

70 90

tPHWL (1)

tPHEL

tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 50 50 ns

tRHWL (1)

tRHEL (1)

tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,

Output Enable Low Min 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 ns

tPLYH (1) tREADY RP Low to Read Mode Max 10 10 µs

tPHPHH (1) tVIDR RP Rise Time to VID Min 500 500 ns

Figure 10. Reset/Block Temporary Unprotect AC Waveforms

AI02931

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

17/21

M29F800AT, M29F800AB

Table 15. OrderingInformation Scheme

Note: The last two characters of the ordering code may be replaced by a letter code for preprogrammed

parts, otherwise devices are shipped from the factory with the memorycontent erased (to FFFFh).

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the ST Sales Office nearest to you.

Example: M29F800AB 70 N 1 T

Device Type

M29

Operating Voltage

F=V

CC =5V±10%

Device Function

800A = 8Mbit (1Mb x8 or 512Kb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

M = SO44

Temperature Range

1=0to70°C

3 = –40 to 125 °C

6=–40to85°C

Option

T = Tape & Reel Packing

M29F800AT, M29F800AB

18/21

Table 16. Revision History

Date Revision Details

July 1999 First Issue

09/21/99 Removed 55ns speed option

ICC1 Typ.specification added (Table 10)

ICC3 Typ.specification added (Table 10)

10/04/99 ICC3 Test Condition change (Table 10)

11/12/99 Block Protection and Unprotection paragraph changed

01/14/00 Command Interface paragraph changed

19/21

M29F800AT, M29F800AB

Table 17. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.006

A2 0.95 1.05 0.037 0.041

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 11.90 12.10 0.469 0.476

e 0.50 – – 0.020 – –

L 0.50 0.70 0.020 0.028

α0°5°0°5°

N48 48

CP 0.10 0.004

Figure 11. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

Drawing is not to scale.

TSOP-a

N/2

DIE

LA1 α

M29F800AT, M29F800AB

20/21

Table 18. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data

Symbol mm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010

A2 2.25 2.35 0.089 0.093

B 0.50 0.020

C 0.10 0.25 0.004 0.010

D 28.10 28.30 1.106 1.114

E 13.20 13.40 0.520 0.528

e 1.27 – – 0.050 – –

H 15.90 16.10 0.626 0.634

L 0.80 – – 0.031 – –

α3°––3°––

N44 44

CP 0.10 0.004

Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline

Drawing is not to scale.

SO-b

LA1 α

21/21

M29F800AT, M29F800AB

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