INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4516B MSI Binary up/down counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except MR which must be LOW. When PL and CE are LOW, the counter changes on the LOW to HIGH transition of CP. Input UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when O0 and O3 are HIGH and CE is LOW. When counting down, TC is LOW when O0 to O3 and CE are LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of all other input conditions. DESCRIPTION The HEF4516B is an edge-triggered synchronous up/down 4-bit binary counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0 to P3), four parallel outputs (O0 to O3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). Fig.2 Pinning diagram. HEF4516BP(N): 16-lead DIL; plastic (SOT38-1) HEF4516BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4516BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING PL parallel load input (active HIGH) P0 to P3 parallel inputs CE count enable input (active LOW) CP clock pulse input (LOW to HIGH, edge triggered) UP/DN up/down count control input MR master reset input TC terminal count output (active LOW) O0 to O3 parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter Fig.3 Logic diagram (continued in Fig.4). January 1995 3 Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter Fig.4 Logic diagram (continued from Fig.3). January 1995 4 Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter FUNCTION TABLE CE CP MODE MR PL UP/DN L H X X X parallel load L L X H X no change L L L L count down L L H L count up H X X X X reset Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition Fig.5 State diagram. Logic equation for terminal count: TC = CE { ( UP/DN ) O 0 O 1 O 2 O 3 + UP/DN O 0 O 1 O 2 O 3 } AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) TYPICAL FORMULA FOR P (W) 5 1000 fi + (foCL) x VDD2 where 10 4500 fi + (foCL) x VDD2 fi = input freq. (MHz) 15 11 200 fi + (foCL) x VDD2 fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays CP On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 CP TC HIGH to LOW LOW to HIGH PL TC HIGH to LOW LOW to HIGH CE TC HIGH to LOW LOW to HIGH MR On, TC HIGH to LOW MR TC LOW to HIGH 45 90 ns 37 ns + (0,16 ns/pF) CL 155 310 ns 128 ns + (0,55 ns/pF) CL 65 130 ns 54 ns + (0,23 ns/pF) CL 45 90 ns 37 ns + (0,16 ns/pF) CL 525 ns 233 ns + (0,55 ns/pF) CL 94 ns + (0,23 ns/pF) CL 75 150 ns 67 ns + (0,16 ns/pF) CL 180 360 ns 153 ns + (0,55 ns/pF) CL 75 150 ns 64 ns + (0,23 ns/pF) CL 55 115 ns 47 ns + (0,16 ns/pF) CL 125 255 ns 98 ns + (0,55 ns/pF) CL 55 110 ns 44 ns + (0,23 ns/pF) CL 15 40 85 ns 32 ns + (0,16 ns/pF) CL 5 170 340 ns 143 ns + (0,55 ns/pF) CL 10 tPLH 5 10 tPHL 70 140 ns 59 ns + (0,23 ns/pF) CL 15 50 105 ns 42 ns + (0,16 ns/pF) CL 5 250 500 ns 223 ns + (0,55 ns/pF) CL 10 tPLH 110 220 ns 99 ns + (0,23 ns/pF) CL 15 80 160 ns 72 ns + (0,16 ns/pF) CL 5 250 500 ns 223 ns + (0,55 ns/pF) CL 10 tPHL 110 220 ns 99 ns + (0,23 ns/pF) CL 15 80 160 ns 72 ns + (0,16 ns/pF) CL 5 165 330 ns 138 ns + (0,55 ns/pF) CL 10 tPLH 65 135 ns 54 ns + (0,23 ns/pF) CL 15 50 100 ns 42 ns + (0,16 ns/pF) CL 5 145 290 ns 118 ns + (0,55 ns/pF) CL 10 tPHL 60 125 ns 49 ns + (0,23 ns/pF) CL 15 45 95 ns 37 ns + (0,16 ns/pF) CL 5 205 405 ns 178 ns + (0,55 ns/pF) CL 65 130 ns 54 ns + (0,23 ns/pF) CL 10 10 tPLH tPHL 15 45 85 ns 37 ns + (0,16 ns/pF) CL 5 225 450 ns 198 ns + (0,55 ns/pF) CL 75 150 ns 64 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 10 tPLH 15 January 1995 49 ns + (0,23 ns/pF) CL 210 ns 15 HIGH to LOW 118 ns + (0,55 ns/pF) CL 120 ns 260 tPHL 5 PL On 290 ns 60 105 5 10 15 LOW to HIGH 145 6 Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Output transition times HIGH to LOW LOW to HIGH SYMBOL MIN. 5 MAX. 60 120 ns TYPICAL EXTRAPOLATION FORMULA 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 10 tTHL tTLH 15 January 1995 TYP. 7 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter VDD V Minimum clock pulse width; LOW Minimum PL pulse width; HIGH Minimum MR pulse width; HIGH Recovery time for MR Recovery time for PL SYMBOL 5 10 tWCPL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. 95 45 ns 35 20 ns 15 25 15 ns 5 105 55 ns 10 tWPLH 45 25 ns 15 35 15 ns 5 120 60 ns 10 tWMRH 50 25 ns 15 40 20 ns 5 130 65 ns 45 20 ns 15 30 15 ns 5 150 75 ns 50 25 ns 10 10 tRMR tRPL 15 30 15 ns Set-up times 5 100 50 ns Pn PL 10 50 25 ns UP/DN CP CE CP tsu 15 40 20 ns 5 250 125 ns 100 50 ns 15 75 35 ns 5 120 60 ns 40 20 ns 10 10 tsu tsu 15 25 10 ns Hold times 5 10 -40 ns Pn PL 10 5 -20 ns 0 -20 ns 35 -90 ns 15 -35 ns 15 -25 ns thold 15 5 UP/DN CP 10 thold 15 5 CE CP 10 thold 15 Maximum clock pulse frequency 5 10 15 January 1995 fmax 20 -40 ns 5 -15 ns 5 -10 ns 3 6 MHz 7 14 MHz 9 18 MHz 8 see also waveforms Figs 6 and 7 Philips Semiconductors Product specification HEF4516B MSI Binary up/down counter Fig.6 Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP. Fig.7 Waveforms showing minimum pulse width for PL and MR, recovery time for PL and MR and set-up and hold times for Pn to PL. January 1995 9 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Philips Semiconductors Binary up/down counter January 1995 10 Fig.8 Timing diagram. Product specification HEF4516B MSI