1
Data sheet acquired from Harris Semiconductor
SCHS187A
Features
• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• Typical Propagation Delay = 13ns at VCC = 5V,
CL = 15pF, TA = 25oC (Data to Output)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il≤1µA at VOL, VOH
Description
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are high
speed Octal Transparent Latches manufactured with silicon
gate CMOS technology. They possess the low power con-
sumption of standard CMOS integrated circuits, as well as the
ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the three-
state outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
is independent of the state of the output enable .
The ’HC533 and ’HCT533 are identical in function to the
’HC563 and CD74HCT563 but have different pinouts. The
’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;
the latter are non-inverting types.
Ordering Information
PART NUMBER TEMP. RANGE
(oC) PACKAGE
CD54HC533F3A -55 to 125 20 Ld CERDIP
CD74HC533E -55 to 125 20 Ld PDIP
CD54HCT533F3A -55 to 125 20 Ld CERDIP
CD74HCT533E -55 to 125 20 Ld PDIP
CD54HC563F3A -55 to 125 20 Ld CERDIP
CD74HC563E -55 to 125 20 Ld PDIP
CD74HCT563E -55 to 125 20 Ld PDIP
CD74HCT563M -55 to 125 20 Ld SOIC
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number are available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.
January 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2000, Texas Instruments Incorporated
CD54/74HC533, CD54/74HCT533,
CD54/74HC563, CD74HCT563
High Speed CMOS Logic Octal Inverting
Transparent Latch, Three-State Outputs
[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
Speed
2
Pinouts
CD54HC533, CD54HCT533
(CERDIP)
CD74HC533, CD74HCT533
(PDIP, SOIC)
TOP VIEW
CD54HC563
(CERDIP)
CD74HC563, CD74HCT563
(PDIP, SOIC)
TOP VIEW
Functional Block Diagram
HC/HCT533
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
Q0
D0
D1
Q1
Q2
D3
D2
Q3
GND
VCC
D7
D6
Q6
Q7
Q5
D5
D4
Q4
LE 11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
OE
D0
D1
D2
D3
D4
D6
D5
D7
GND
VCC
Q1
Q2
Q3
Q0
Q4
Q5
Q6
Q7
LE
O0
D0
LE
OE
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
D
G
OD
G
OD
G
OD
G
OD
G
OD
G
OD
G
OD
G
O
TRUTH TABLE
OUTPUT ENABLE LATCH ENABLE DATA Q OUTPUT
LHHL
LHLH
LLlH
LLhL
HXXZ
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior
to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
6 4.5 - - 0.26 - 0.33 - 0.4 V
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
4
Three-State Leakage
Current -V
IL or
VIH VO =
VCC or
GND
6--±0.5 - ±5-±10 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-6 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
6 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC to
GND - 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Three-State Leakage
Current -V
IL or
VIH VO =
VCC or
GND
5.5 - - ±0.5 - ±5-±10 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆ICC VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
D0 - D7 0.15
LE 0.30
OE 0.55
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25oC.
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
5
Prerequisite For Switching Specifications
PARAMETER SYMBOL TEST
CONDITIONS VCC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
LE Pulse Width tW- 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
Set-up Time Data to LE tSU - 2 50 - - 65 - 75 - ns
4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns
Hold Time, Data to LE
(533) tH- 2 35 - - 45 - 55 - ns
4.5 7 - - 9 - 11 - ns
66--8-7-ns
Hold Time, Data to LE
(563) tH-24--4-4-ns
4.5 4 - - 4 - 4 - ns
64--4-4-ns
HCT TYPES
LE Pulse Width tw- 4.5 16 - - 20 - 24 - ns
Set-up Time Data to LE tw- 4.5 10 - - 13 - 15 - ns
Hold Time, Data to LE (533) tH- 4.5 8 - - 10 - 12 - ns
Hold Time, Data to LE (563) tH- 4.5 5 - - 5 - 5 - ns
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC-55oC TO
125oC
UNITSTYP MAX MAX MAX
HC TYPES
Propagation Delay,
Data to Qn
(HC533)
tPLH, tPHL CL= 50pF 2 - 165 205 250 ns
4.5 - 33 41 50 ns
6 - 28 35 43 ns
CL= 15pF 5 13 - - - ns
Propagation Delay,
Data to Qn
(HC563)
tPLH, tPHL CL= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns
6 - 26 33 38 ns
CL= 15pF 5 12 - - - ns
Propagation Delay,
LE to Qn
(HC533)
tPLH, tPHL CL= 50pF 2 - 175 220 265 ns
4.5 - 35 44 53 ns
6 - 30 37 45 ns
CL= 15pF 5 14 - - - ns
Propagation Delay,
LE to Qn
(HC563)
tPLH, tPHL CL= 50pF 2 - 165 205 250 ns
4.5 - 33 41 50 ns
6 - 28 35 43 ns
CL= 15pF 5 13 - - - ns
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
6
Enable Times
(HC533) tPZH, tPZL CL= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns
6 - 26 33 38 ns
CL= 15pF 5 12 - - - ns
Disable Times
(HC533) tPHZ, tPLZ CL= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns
6 - 26 33 38 ns
CL= 15pF 5 12 - - - ns
Enable and Disable Times
(HC563) tPZH, tPZL,
tPHZ, tPLZ CL= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns
6 - 26 33 38 ns
CL= 15pF 5 12 - - - ns
Input Capacitance CI---1010 10pF
Three-State Output
Capacitance CO---2020 20pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD - 5 42 - - - pF
HCT TYPES
Propagation Delay,
Data to Qn
(HC/HCT533)
tPLH, tPHL CL= 50pF 4.5 - 34 43 51 ns
CL= 15pF 5 14 - - - ns
Propagation Delay,
Data to Qn
(HC/HCT563)
tPLH, tPHL CL= 50pF 4.5 - 30 38 45 ns
CL= 15pF 5 12 - - - ns
Propagation Delay,
LE to Qn
(HC/HCT533)
tPLH, tPHL CL= 50pF 4.5 - 38 48 57 ns
CL= 15pF 5 16 - - - ns
Propagation Delay,
LE to Qn
(HC/HCT563)
tPZL, tPZH CL= 50pF 4.5 - 35 44 53 ns
CL= 15pF 5 14 - - - ns
Enable Times
(HC/HCT533) tPLZ, tPZH CL= 50pF 4.5 - 35 44 53 ns
CL= 15pF 5 14 - - - ns
Disable Times
(HC/HCT533) tTLH, tTHL CL= 50pF 4.5 - 30 38 45 ns
CL= 15pF 5 12 - - - ns
Enable and Disable Times
(HC/HCT563) tPZH, tPZL,
tPHZ, tPLZ CL= 50pF 4.5 - 35 44 53 ns
CL= 15pF 5 14 - - - ns
Input Capacitance CI---1010 10pF
Power Dissipation
Capacitance
(Notes 5, 6)
CPD - 5 42 - - - pF
NOTES:
5. CPD is used to determine the no-load dynamic power consumption, per latch.
6. PD (total power per latch) = CPD VCC2 fi + Σ CLVCC2 fo where fi = Input Frequency, fo = Output Frequency, CL = Output Load
Capacitance, VCC = Supply Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC-55oC TO
125oC
UNITSTYP MAX MAX MAX
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
7
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
8
FIGURE 7. HC THREE-STATE PROPAGATION DELAY
WAVEFORM FIGURE 8. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
Test Circuits and Waveforms
(Continued)
50% 10%
90%
GND
VCC
10%
90% 50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
0.3
2.7
GND
3V
10%
90%
1.3V
1.3V
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED OUTPUTS
DISABLED OUTPUTS
ENABLED
tr6ns
tPZH
tPHZ
tPZL
tPLZ
6ns tf
1.3
IC WITH
THREE-
STATE
OUTPUT
OTHER
INPUTS
TIED HIGH
OR LOW
OUTPUT
DISABLE
VCC FOR tPLZ AND tPZL
GND FOR tPHZ AND tPZH
OUTPUT
RL = 1kΩ
CL
50pF
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
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Copyright 2000, Texas Instruments Incorporated
