SI8241BB-B-IS1R - Silicon Labs

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si824x

CLASS D AUDIO DRIVER WITH PRECISION D EAD-TIME GENERATOR

Features

Applications

Description

The Si824x isolated driver family combines two isolated drivers in a single

package. The Si8241/44 are high-side/low-side drivers specifically targeted at

high-power (>30 W) audio applications. Versions with peak output currents of

0.5 A (Si8241) and 4.0 A (Si8244) are available. All drivers operate with a

maximum supply voltage of 24 V.

Based on Silicon Labs' proprietary isolation technology, the Si824x audio drivers

incorporate input-to-output and output-to-output isolation, which enables level-

translation of signals without additional external circuits as well as use of bipolar

supply voltage up to ±750 V. The Si824x audio drivers feature an integrated dead-

time generator that provides highly precise control for achieving optimal THD.

These products also have overlap protection that safeguards against shoot-

through current damage. The CMOS-based design also provides robust immunity

from latch-up and high-voltage transients. The extremely low propagation delays

enable faster modulation frequencies for an enhanced audio experience. The TTL

level compatible inputs with >400 mV hysteresis are available in PWM input

configuration; other options include UVLO levels of 8 V or 10 V. These products

are available in narrow body SOIC packages.

Functional Block Diagram

0.5 A peak output (Si8241)

4.0 A peak output (Si8244)

PWM input

High-precision linear programmable

dead-time generator

0.4ns to 1µs

High latchup immunity >100 V/ns

Up to 1500 Vrms output-output

isolation, supply voltage of ±750 V

Input to output isolation for low noise

(up to 2500 V)

Up to 8 MHz operation

Wide operating rang e

–40 to +125 °C

Transient immunity >45 kV/µs

RoHS-compliant

SOIC-16 narrow body

Class D audio amplifiers

GNDI

VDDI

PWM VDDA

VOA

GNDA

VOB

VDDB

GNDB

DISABLE

UVLO

Isolation

Programmable Dead

Time, Contr ol Gating

Si8241/44

Patents Pending

Ordering Information:

See page 26.

Pin Assignments

PWM

VDDI

GNDI

DISABLE

VDDI

VDDA

VOA

GNDA

VDDB

VOB

GNDB

Si8241/44

SO IC-16 (Narrow )

Si824x

2 Preliminary Rev. 0.3

Si824x

Preliminary Rev. 0.3 3

TABLE OF CONTENTS

Section Page

1. Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1. Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.1. Typical Performance Characteristics (0.5 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.2. Typical Performance Characteristics (4.0 Amp) . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.3. Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . . . . . . . .18

3.4. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.5. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.6. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.7. Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.8. Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . . . . . . . . . .22

4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.1. Class D Digital Audio Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

9. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9.1. Si824x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .29

9.2. Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . .29

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Si824x

4 Preliminary Rev. 0.3

1. Top-Level Block Diagram

Figure 1. Si8241/44 Single-Input High-Side/Low-Side Isolated Drivers

Si8241/44

UVLO

GNDI

VDDI

PWM VDDA

VOA

GNDA

VOB

VDDI

ISOLATION

VDDI VDDB

GNDB

DISABLE

ISOLATION

UVLO

DT CONTROL

OVERLAP

PROTECTION

LPWM

Si824x

Preliminary Rev. 0.3 5

2. Electrical Specifications

Table 1. Electrical Characteristics1

4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C

Parameter Symbol Test Conditions Min Typ Max Units

DC Spec ifications

Input-Side Power Supply

Voltage VDDI 4.5 — 5.5 V

Driver Supply Voltage VDDA, VDDB Voltage between VDDA and

GNDA, and VDDB and GNDB

(See “6. Ordering Guide” ) 6.5 — 24 V

Input Supply Quiescent

Current IDDI(Q) Si8241/44 — 2 3 mA

Output Supply Quiescent

Current IDDA(Q),

IDDB(Q) Current per channel — — 3.0 mA

Input Supply Active Current IDDI PWM freq = 500 kHz — 2.5 — mA

Output Supply Active Current IDDO PWM freq = 500 kHz — 3.6 — mA

Input Pin Leakage Current IPWM –10 — +10 µA dc

Input Pin Leakage Current IDISABLE –10 — +10 µA dc

Logic High Input Threshold VIH 2.0 — — V

Logic Low Input Threshold VIL — — 0.8 V

Input Hysteresis VIHYST 400 450 — mV

Logic High Output Voltage VOAH,

VOBH IOA, IOB = –1 mA (VDDA

/VDDB)

— 0.04 ——V

Logic Low Output Voltage VOAL, VOBL IOA, IOB = 1 mA — — 0.04 V

Output Short-Circuit Pulsed

Sink Current IOA(SCL),

IOB(SCL) Si8241, Figure 2 — 0.5 — A

Si8244, Figure 2 — 4.0 — A

Output Short-Circuit Pulsed

Source Current IOA(SCH),

IOB(SCH) Si8241, Figure 3 — 0.25 — A

Si8244, Figure 3 — 2.0 — A

Output Sink Resistance RON(SINK) Si8241 — 5.0 — 

Si8244 — 1.0 — 

Output Source Resistance RON(SOURCE) Si8241 — 15 — 

Si8244 — 2.7 — 

Notes:

1. VDDA = VDDB = 12 V for 8 V UVLO and 10 V UVLO devices.

2. The largest RDT resistor that can be used is 220 k.

Si824x

6 Preliminary Rev. 0.3

VDDI Undervoltage Threshold VDDIUV+ VDDI rising 3.60 4.0 4.45 V

VDDI Undervoltage Threshold VDDIUV– VDDI falling 3.30 3.70 4.15 V

VDDI Lockout Hysteresis VDDIHYS —250—mV

VDDA, VDDB Undervoltage

Threshold VDDAUV+,

VDDBUV+ VDDA, VDDB rising

8V Threshold See Figure 35 on page 22. 7.50 8.60 9.40 V

10 V Threshold See Figure 36 on page 22. 9.60 11.1 12.2 V

VDDA, VDDB Undervoltage

Threshold VDDAUV–,

VDDBUV– VDDA, VDDB falling

8V Threshold See Figure 35 on page 22. 7.20 8.10 8.70 V

10 V Threshold See Figure 36 on page 22. 9.40 10.1 10.9 V

VDDA, VDDB

Lockout Hystere sis VDDAHYS,

VDDBHYS UVLO volt age = 8 V — 600 — mV

VDDA, VDDB

Lockout Hystere sis VDDAHYS,

VDDBHYS UVLO voltage = 10 V — 1000 — mV

AC Spec ifications

Minimum Pulse Width — 10 — ns

Propagation Delay tPHL, tPLH CL = 1 nF — 25 60 ns

Pulse Width Distortion

|tPLH - tPHL|PWD — 1.0 5.60 ns

Programmed Dead Time2DT See Figures 37 and 38 0.4 — 1000 ns

Output Rise and Fall Time tR,tFCL= 1 nF (Si8241) — — 20 ns

CL= 1 nF (Si8244) — — 12 ns

Shutdown Time from

Disable True tSD ——60

Restart Time from

Disable False tRESTART ——60

Device Start-up Time tSTART Time from VDD_ = VDD_UV+

to VOA, VOB = VIA, VIB —57µs

Common Mode

Transient Immunity CMTI VIA, VIB, PWM = VDDI or 0 V

VCM = 1500 V (see Figure 4) 25 45 — kV/µs

Table 1. Electrical Characteristics1 (Continued)

4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C

Parameter Symbol Test Conditions Min Typ Max Units

Notes:

1. VDDA = VDDB = 12 V for 8 V UVLO and 10 V UVLO devices.

2. The largest RDT resistor that can be used is 220 k.

Si824x

Preliminary Rev. 0.3 7

2.1. Test Circuits

Figures 2 and 3 depict sink current an d so ur ce curr en t tes t c ircu its.

Figure 2. IOL Sink Current Test Circuit

Figure 3. IOH Source Current Test Circuit

INPUT

1 µF 100 µF

RSNS

0.1

Si824x

1 µF

CER 10 µF

VDD A = VD DB = 15 V

IN OUT

VSS

VDD

SCHOTTKY

50 ns

200 ns

Measure

I NPUT W AVEFO RM

GND

VDDI

8 V +

INPUT

1 µF 100 µF

RSNS

0.1

Si824x

1 µF

CER 10 µF

VDD A = VD DB = 15 V

IN OUT

VSS

VDD

50 ns

200 ns

Measure

I NPUT WAVEFO RM

GND

VDDI

SCHOTTKY

VDDI

5.5 V +

Si824x

8 Preliminary Rev. 0.3

Figure 4. Common Mode Transient Immunity Test Circuit

Table 2. Regulatory Information*

CSA

The Si824x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.

61010-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.

60950-1: Up to 300 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.

VDE

The Si824x is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.

60747-5-2: Up to 560 Vpeak for basic insulation working voltage.

The Si824x is certified under UL1577 component recognition program. For more details, see File E257455.

Rated up to 2500 VRMS isolation voltage for basic protection.

*Note: Regulatory Certifications apply to 2.5 kVRMS rated devices, which are production tested to 3.0 kVRMS for 1 sec.

For more information, see "6.Ordering Guide " on page 26.

Oscilloscope

Isolated

Supply

VDDA

VOA

GNDA

12V

Supply

High Voltage

Surge Generator

VcmSurge

Output

100k

High Voltage

Differen tial

Probe

VDDB

VOB

GNDB

GNDI

VDDI

INPUT

DISABLE

InputSignal

Switch

Input

Output

Isolated

Ground

Si824x

Preliminary Rev. 0.3 9

Table 3. Insulation and Safety-Related Specifications

Parameter Symbol Test Condition

Value

Unit

NBSOIC-16

2.5 kVRMS

Nominal Air Gap

(Clearance)1L(1O1) 4.01 mm

Nominal External Tracking (Creep age)1L(1O2) 4.01 mm

Minimum Internal Gap

(Internal Clearance) 0.011 mm

Trac king Resistance

(Proof Tracking Index) PTI IEC60112 600 V

Erosion Depth ED 0.019 mm

Resistance

(Input-Output)2RIO 1012 

Capacitance

(Input-Output)2CIO f=1MHz 1.4 pF

Input Capacitance3CI4.0 pF

Notes:

1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Pa ckage Outline:

16-Pin Narrow Body SOIC” . VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16.

UL does not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance

and creepage limits as 3.9 mm minimum for the NB SOIC 16.

2. To determine resistance and capacitance, the Si824x is converted into a 2-terminal device. Pins 1–8 are shorted

together to form the first terminal and pins 9–16 are shorted together to form the second terminal. The parameters are

then measured between these two terminals.

3. Measured from input pin to ground.

Table 4. IEC 60664-1 (VDE 0884 Part 2) Ratings

Parameter Test Conditions Specification

NB SOIC-16

Basic Isolation Group Material Group I

Installation Classification

Rated Mains Vo ltages < 150 VRMS I-IV

Rated Mains Vo ltages < 300 VRMS I-III

Rated Mains Vo ltages < 400 VRMS I-II

Rated Mains Vo ltages < 600 VRMS I-II

Si824x

10 Preliminary Rev. 0.3

Table 5. IEC 60747-5-2 Insulation Characteristics*

Parameter Symbol Test Condition Characteristic Unit

NB SOIC-16

Maximum Working Insulation Voltage VIORM 560 V peak

Input to Output Test Voltage VPR

Method b1

(VIORM x1.875=V

PR,

100%

Production Te st, tm= 1 sec,

Partial Discharge < 5 pC)

1050 V peak

Transient Overvoltage VIOTM t = 60 sec 4000 V peak

Pollution Degree

(DIN VDE 0110, Table 1) 2

Insulation Resistance at TS,

VIO =500V RS>109

*Note: Maintenance of the safety data is ensured by protective circuits. The Si824x provides a climate class if ication of

40/125/21.

Table 6. IEC Safety Limiting Values1

Parameter Symbol Test Condition NB SOIC-16 Unit

Case Temperature TS150 °C

Safety Input Current IS

JA = 105 °C/W (NB SOIC-16),

VDDI =5.5V,

VDDA =V

DDB=24V,

TJ= 150 °C, TA=25°C

50 mA

Device Power Dissipation2PD1.2 W

Notes:

1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 5.

2. The Si82xx is tested with V DDI =5.5V, V

DDA =V

DDB =24V, T

J=150ºC, C

L= 100 pF, input 2 MHz 50% duty cycle

square wave.

Si824x

Preliminary Rev. 0.3 11

Figure 5. NB SOIC-16, Thermal Derating Curve, Dependence of Safety Limiting Values with Case

Temperature per DIN EN 60747-5-2

Table 7. Thermal Characteristics

Parameter Symbol NB

SOIC-16 Unit

IC Junction-to- Air

Thermal Resistance JA 105 °C/W

Table 8. Absolute Maximum Ratings1

Parameter Symbol Min Typ Max Units

Storage Temperature2TSTG –65 — +150 °C

Ambient Temperature under Bias TA–40 — +125 °C

Input-side Supply Voltage VDDI –0.6 — 6.0 V

Driver-side Supply Voltage VDDA, VDDB –0.6 — 30 V

Voltage on any Pin with respect to Ground VIN –0.5 — VDD + 0.5 V

Output Drive Current per Channel IO—— 10 mA

Lead Solder Temperature (10 sec) — — 260 °C

Latchup Immunity3—— 100 V/ns

Maximum Isolation (Input to Output) — — 2500 VRMS

Maximum Isolation (Output to Output) — — 1500 VRMS

Notes:

1. Permanent device damage may occur if the absolute maximum ratings are exceed ed. Fun ctional operation should be

restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

2. VDE certifies storage temperature fro m –4 0 to 150 °C.

3. Latchup immunity specification is for slew rate applied across GNDI and GND A or GNDB.

0 20015010050

Case Temperature (ºC)

Safety-Lim iting Current (mA )

VDDI = 5.5 V

VDDA, VDDB = 24 V

Si824x

12 Preliminary Rev. 0.3

3. Functional Description

The operation of an Si824x chan nel is analogou s to that of an opto coupler and gate driver, except an RF carrier is

modulated instead of light. This simple architecture provides a robust isolated data path and requires no special

considerations or initialization at start-up. A simplified block diagram for a single Si824x channel is shown in

Figure 6.

Figure 6. Simplified Channel Diagram

A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.

Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The

Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the

result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it

provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See

Figure 7 for more details.

Figure 7. Modulation Scheme

RF Oscillator

Modulator Demodulator

Semiconductor-

Based Isolation

Barrier

Transmitter Receiver

Dead

Time

Generator 0.5 to 4 A

peak

Gnd

VDD

Driver

Input Signal

Output Signal

Modulation Signal

Si824x

Preliminary Rev. 0.3 13

3.1. Typical Performance Characteristics (0.5 Amp)

The typical performance characteristics depicted in Figures 8 through 19 are for information purposes only. Refer

to Table 1 on page 5 for actual specification limits.

Figure 8. Rise/Fall Time vs. Supply Voltage

Figure 9. Propagation Delay vs. Supply Voltage

Figure 10. Supply Current vs. Supply Voltage

9 1215182124

Rise/Fall Time (ns)

VDDA Supply (V)

VDD=12V, 25°C

CL= 100 pF

Tfall

Trise

9 1215182124

Propagation Delay (ns)

VDDA Supply (V)

H-L

L-H

VDD=12V, 25°C

CL= 100 pF

1.5

2.5

3.5

9141924

VDDA Supply Current (mA)

VDDA Supply Voltage (V)

Duty Cyc le = 50%

= 0 pF

1 Channel Switching 1MHz

500kHz

100kHz

50 kHz

Si824x

14 Preliminary Rev. 0.3

Figure 11. Supply Current vs. Supply Voltage

Figure 12. Supply Current vs. Temperature

Figure 13. Rise/Fall Time vs. Load

Figure 14. Propagation Delay vs. Load

Figure 15. Propagation Delay vs. Temperature

Figure 16. Output Sink Current vs. Supply

Voltage

9141924

VDDA Supply Current (mA)

VDDA Supply Voltage (V)

Duty Cycle = 50%

CL= 100 pF

1 Channel Switching 1MHz

500kHz

100kHz

50 kHz

-50 0 50 100

Supply Current (mA)

Temperature (°C)

VDDA = 15V,

f = 250kHz, CL= 0 pF

Duty Cycle = 50%

2 Channels Switching

0.0 0.5 1.0 1.5 2.0

Rise/Fall Time (ns)

Load (nF)

VDD=12V, 25°C

Tfall

Trise

0.0 0.5 1.0 1.5 2.0

Propagation Delay (ns)

Load (nF)

VDD=12V, 25°C

H-L

L-H

-40 -20 0 20 40 60 80 100 120

Propagation Delay (ns)

Temperature (°C)

VDD=12V, Load = 200pF

H-L

L-H

10 12 14 16 18 20 22 24

Sink Current (A)

Supply Voltage (V)

VDD=12V, Vout=5V

Si824x

Preliminary Rev. 0.3 15

Figure 17. Output Source Current vs. Supply

Voltage

Figure 18. Output Sink Current vs. Temperature

Figure 19. Output Source Current vs.

Temperature

2.25

2.5

2.75

3.25

3.5

3.75

10 15 20 25

Source Current (A)

Supply Voltage (V)

VDD=12V, Vout=VDD-5V

4.25

4.5

4.75

5.25

5.5

5.75

6.25

6.5

6.75

-40 -10 20 50 80 110

Sink Current (A)

Temperature (°C)

VDD=12V, Vout=5V

2.25

2.5

2.75

3.25

3.5

-40 -10 20 50 80 110

Source Current (A)

Temperature (°C)

VDD=12V, Vout=VDD-5V

Si824x

16 Preliminary Rev. 0.3

3.2. Typical Performance Characteristics (4.0 Amp)

The typical performance characteristics depicted in Figures 20 through 31 are for information purposes only. Refer

to Table 1 on page 5 for actual specification limits.

Figure 20. Rise/Fall Time vs. Supply Voltage

Figure 21. Propagation Delay vs. Supply

Voltage

Figure 22. Supply Current vs. Supply Voltage

Figure 23. Supply Current vs. Supply Voltage

Figure 24. Supply Current vs. Temperature

Figure 25. Rise/Fall Time vs. Load

9 1215182124

Rise/Fall Time (ns)

VDDA Supply (V)

VDD=12V, 25°C

= 100 pF

Tfall

Trise

9 1215182124

Propagation Delay (ns)

VDDA Supply (V)

H-L

L-H

VDD=12V, 25°C

CL= 100 pF

9 141924

VDDA Supply Current (mA)

VDDA Supply Voltage (V)

Duty Cyc le = 50%

CL= 0 pF

1 Channel Switching 1MHz

500kHz

100kHz

50 kHz

9141924

VDDA Supply Current (mA)

VDDA Supply Voltage (V)

Duty Cyc le = 50%

CL= 100 pF

1 Channel Switching

1MHz

500kHz

100kHz

50 kHz

-50 0 50 100

Supply Current (mA)

Temperature (°C)

VDDA = 15V,

f = 250kHz, CL= 0 pF

Duty Cycle = 50%

2 Channels Switching

012345678910

Rise/Fall Time (ns)

Load (nF)

VDD=12V, 25°C

Tfall

Trise

Si824x

Preliminary Rev. 0.3 17

Figure 26. Propagation Delay vs. Load

Figure 27. Propagation Delay vs. Temperature

Figure 28. Output Sink Current vs. Supply

Voltage

Figure 29. Output Source Current vs. Supply

Voltage

Figure 30. Output Sink Current vs. Temperature

Figure 31. Output Source Current vs.

Temperature

012345678910

Propagation Delay (ns)

Load (nF)

VDD=12V, 25°C

H-L

L-H

-40 -20 0 20 40 60 80 100 120

Propagation Delay (ns)

Temperature (°C)

VDD=12V, Load = 200pF

H-L

L-H

10 12 14 16 18 20 22 24

Sink Current (A)

Supply Voltage (V)

VDD=12V, Vout=5V

2.25

2.5

2.75

3.25

3.5

3.75

10 15 20 25

Source Current (A)

Supply Voltage (V)

VDD=12V, Vout=VDD-5V

4.25

4.5

4.75

5.25

5.5

5.75

6.25

6.5

6.75

-40 -10 20 50 80 110

Sink Current (A)

Temperature (°C)

VDD=12V, Vout=5V

2.25

2.5

2.75

3.25

3.5

-40 -10 20 50 80 110

Source Current (A)

Temperature (°C)

VDD=12V, Vout=VDD-5V

Si824x

18 Preliminary Rev. 0.3

3.3. Family Overview and Logic Operation During Startup

The Si824x family of isolated drivers consists of high-side, low-side, and dual driver configurations.

3.3.1. Products

Table 9 shows the configuration and functional overview for each product in this family.

3.3.2. Device Behavior

Table 10 contains truth tables for the Si8241/4 families.

Table 9. Si824x Family Overview

Part Number Configuration UVLO Voltage Programmable

Dead Time Inputs Peak Output

Current (A)

Si8241 High-Side/Low-Side 8 V/10 V PWM 0.5

Si8244 High-Side/Low-Side 8 V/10 V PWM 4.0

Table 10. Si824x Family Truth Table*

Si8241/4 (PWM Input High-Side/Low-Side) Truth Table

PWM Input VDDI State Disable Output Notes

VOA VOB

H Powered L H L Output transition occurs after internal dead time

expires.

L Powered L L H Output transition occurs after internal dead time

expires.

X Unpowered X L L Output returns to input state within 7 µs of VDDI

power restoration.

X Powered H L L Device is disabled.

*Note: This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see

"3.7.2.Undervoltage Lockout" on page 21 for more information.

Si824x

Preliminary Rev. 0.3 19

3.4. Power Supply Connections

Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these

supplies must be placed as close to the VDD and GND pins of the Si824x as possible. The optimum values for

these capacitors depend on load current and the distance between the chip and the regulator that powers it. Low

effective series resistance (ESR) capacitors, such as Tantalum, are recommended.

3.5. Power Dissipation Considerations

Proper system design must assure that the Si8 24x operates within safe ther mal limits across the entire load range.

The Si824x total power dissipation is the sum of the power dissipated by bias supply current, internal switching

losses, and power delivered to the load. Equation 1 shows total Si824x power dissipation. In a non-overlapping

system, such as a high-side/low-side driver, n = 1.

Equation 1.

The maximum power dissipation allowable for the Si824x is a function of the package thermal resistance, ambient

temperature, and maximum allowable junction temperature, as shown in Equation 2:

Equation 2.

Substituting values for PDmax T

jmax, TA, and ja into Equation 2 results in a maximum allowable total power

dissipation of 1.19 W. Maximum allowable load is found by substituting this limit and the appropriate datasheet

values from Table 1 on page 5 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and

Equation 4 (4.0 A driver), both of which assume VDDI = 5 V and VDDA = VDDB = 18 V.

Equation 3.

Equation 4.

PDVDDIIDDI 2V

DDOIQOUT CintVDDO2F+2n CLVDDO2F++

where:

PD is the total Si824x device power dissipation (W)

IDDI is the input-side maximum bias current (3 mA)

IQOUT is the driver die maximum bias current (2.5 mA)

Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)

VDDI is the input-side VDD supply voltage (4.5 to 5.5 V)

VDDO is the driver-side supply vol tage (10 to 24 V)

F is the switching frequency (Hz)

n is the overlap constant (max value = 2)

PDmax Tjmax TA

–

ja

---------------------------

where:

PDmax = Maximum Si824x power dissipation (W)

Tjmax = Si824x maximum junction temperature (150 °C)

TA = Ambient temperature (°C)

ja = Si824x junction-to-air thermal resistance (105 °C/W)

F = Si824x switching frequency (Hz)



CL(MAX) 1.4 10 3–



-------------------------- 7.5–10 11–

=

CL(MAX) 1.4 10 3–



-------------------------- 3.7–10 10–

=

Si824x

20 Preliminary Rev. 0.3

Equation 1 and Equation 2 are graphed in Figure 32 where the points along the load line represent the package

dissipation-limited value of CL for the corresponding switching frequency.

Figure 32. Max Load vs. Switching Frequency

Figure 33. Switching Frequency vs. Load Current

2,000

4,000

6,000

8,000

10,000

12,000

14,000

16,000

100

150

200

250

300

350

400

450

500

550

600

650

700

Frequency (K hz)

Max Loa d (pF)

0.5A D river (pF)

4A D river (pF)

Ta = 25 °C

0 200 400 600 800 1000

VDDA Supply Current (mA)

Switching Frequency (kHz)

VDD=15V, 25°C

= 1000pF

= 500pF

CL= 200pF

Si824x

Preliminary Rev. 0.3 21

3.6. Layout Considerations

It is most important to minimize ringing in the drive path and noise on the Si824x VDD lines. Care must be taken to

minimize parasitic inductance in these paths by locating the Si824x as close to the device it is driving as possible.

In addition, the VDD supply and ground trace paths must be kept short. For this reason, the use of power and

ground planes is highly recommended. A split ground plane system having separate ground and VDD planes for

power devices and small signal components provides th e best overall noise performance.

3.7. Undervoltage Lockout Operation

Device behavior during start-up, normal operation and shutdown is shown in Figure 34, where UVLO+ and UVLO-

are the positive-going and negative-going thresholds respectively. Note that outputs VOA and VOB default low

when input side powe r supply (VDDI) is not present.

3.7.1. Device Startup

Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period

tSTART. Following this, the outputs follow the states of inputs VIA and VIB.

3.7.2. Undervoltage Lockout

Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or

when VDD is below its specified operating circuits range. The input (control) side, Driver A and Driver B, each have

their own undervoltage lockout monitors.

The Si824x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver

outputs, VOA and VOB, remain low when the input side of the Si824x is in UVLO and their respective VDD supply

(VDDA, VDDB) is within tolerance. Each driver output can enter or exit UVLO independently. For example, VOA

unconditionally enters UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above

VDDAUV+.

Figure 34. Device Behavior during Normal Operation and Shutdown

PWM

VOA

DISABLE

VDDI

UVLO-

VDDA

tSTART tSTART tSTART tSD tRESTART tPHL tPLH

UVLO+

UVLO-

UVLO+

tSD

VDDHYS

Si824x

22 Preliminary Rev. 0.3

3.7.3. Undervoltage Lockout (UVLO)

The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Referring to Figures 35

and 36, upon power up , the Si82 4x is maint ained in UVLO until VDD r ises a bove VDDUV+. During power down, th e

Si824x enters UVLO when VDD falls below the UVLO threshold plus hysteresis (i.e., VDD < VDDUV+ – VDDHYS).

Figure 35. Si824x UVLO Response (8 V) Figure 36. Si824x UVLO Response (10 V)

3.7.4. Control Inputs

PWM inputs are high-tr ue, TTL level-co mpatible logic inputs. VOA is high and VOB is low when the PWM input is

high, and VOA is low and VOB is high when the PWM input is low.

3.7.5. Disable Input

When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of input.

Device operation terminates within tSD after DISABLE = VIH and resumes within tRESTART after DISABLE = VIL.

The DISABLE input has no effect if VDDI is below its UVLO level (i.e. VOA, VOB remain low). The DISABLE input

is typically connected to external protection circuitry to unconditionally halt dr iver operation in the event of a fault.

6.0

10.5

VDDUV+ (Typ)

Output Voltage (VO)

6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0

Supply Voltage (VDD - VSS) ( V )

8.5

10.5

VDDUV+ (Typ)

Output Voltage (VO)

9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5

Supply Voltage (VDD - VSS) (V)

Si824x

Preliminary Rev. 0.3 23

3.8. Programmable Dead Time and Overlap Protection

All high-side/low-side drivers (Si8241/4) include programmable overlap protection to prevent outputs VOA and

VOB from being high at the same time. These devices also include programmable dead time, which adds a user-

programmable delay between transitions of VOA and VOB. When enabled, dead time is present on all transitions,

even after overlap recovery. The amount of dead time delay (DT) is programmed by a single resistor (RDT)

connected from the DT input to ground per Equation 5. Minimum dead time (approximately 400 ps) can be

achieved by connecting the DT pin to VDDI. Note that dead time accuracy is limited by the resistor’s (RDT)

tolerance and te mpera ture co efficient. See Figures 37 and 38 fo r add itio nal information about d ead time ope ra tion.

Equation 5.

Figure 37. Dead T ime vs.Resistance (RDT)

Figure 38. Dead Time vs.Temperature

DT 10 RDT

where: 

DT dead time (ns)

and

RDT dead time programming resistor (k=



100

200

300

400

500

600

700

800

900

1000

0 20 40 60 80 100

Dead-time (ns)

Dead-time Resistance (k::)

100

-40 -20 0 20 40 60 80 100 120

Dead-time (ns)

Temperature (°C)

RDT = 4k

RDT = 10k

RDT = 3k

RDT = 5k

RDT = 6k

RDT = 2k

RDT = 1k

RDT =0

Si824x

24 Preliminary Rev. 0.3

4. Applications

The following examples illustrate typical circuit configurations using the Si824x.

4.1. Class D Digital Audio Driver

Figures 39 an d 40 show the Si8241/4 con trolled by a single PWM signal. Supply can be unipolar (0 to 1500 V) or

bipolar (± 750 V).

Figure 39. Si824x in Half-Bridge Audio Application

Figure 40. Si824x in Half-Bridge Audio Application

D1 and CB form a convention al bootstrap circuit that allows VOA to operate as a high -side drive r for Q1, which h as

a maximum drain volt age of 1500 V. VOB is connected as a conventional low-side driver. Note that the inpu t side of

the Si824x requires VDD in the range of 4.5 to 5.5 V, while the VDDA and VDDB output side supplies must be

between 6.5 and 24 V with respect to their respective grounds. The boot-strap start up time will depend on the CB

cap chosen. VDD2 is usually the same as VDDB. Also note that the bypass capacitors on the Si824x should be

located as close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors be

used to reduce high frequency noise and maximize performance. The D1 diod e sho uld be a fast -rec over y diode; it

should be able to withstand the maximum high voltage (e.g. 1500 V) and be low-loss. See “AN486: High-Side

Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems” for more details in selecting the bootstrap

cap (CB) and diode (D1).

Si8241/4

GNDI

VDDI

PWM

VDDA

VOA

GNDA

VOB

VDDI

VDDB

GNDB

DISABLE

RDT

CONTROLLER

1uF

PWMOUT

I/O

VDDB

10uF

VDD2

1 µF

1500 V max

Si8241/4

GNDI

VDDI

PWM

VDDA

VOA

GNDA

VOB

VDDI

VDDB

GNDB

DISABLE

RDT

CONTROLLER

1uF

PWMOUT

I/O

VDDB

10uF

VDD2

1 µF

+750 V max

-750 V max

Si824x

Preliminary Rev. 0.3 25

5. Pin Descriptions

Table 11. Si8241/44 PWM Input HS/LS Isolated Driver (SOIC-16)

Pin Name Description

1 PWM PWM input.

2 NC No conn ec tio n.

3 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.

4 GNDI Input-side ground terminal.

5 DISABLE Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It is

strongly recommended that this input be connected to external logic level to avoid erroneous

operation due to capacitive noise coupling.

6 DT Dead time programming input. The value of the resistor connected from DT to ground sets the

dead time between output transitions of VOA and VOB. Defaults to 1 ns dead time when con-

nected to VDDI or left open (see "3.8.Programmable Dead Time and Overlap Protection" on

page 2 3).

7 NC No conn ec tio n.

8 VDDI Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.

9 GNDB Ground terminal for Driver B.

10 VOB Driver B output (low-side driver).

11 VDDB Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.

12 NC No connection.

13 NC No connection.

14 GNDA Ground terminal for Driver A.

15 VOA Driver A output (high-side driver).

16 VDDA Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.

PWM

VDDI

GNDI

DISABLE

VDDI

VDDA

VOA

GNDA

VDDB

VOB

GNDB

Si8241/44

SO IC-16 (Narrow )

Si824x

26 Preliminary Rev. 0.3

6. Ordering Guide

The currently available OPNs are listed in Table 12.

Table 12. Ordering Part Numbers*

Ordering Part

Number (OPN) Input Type Package Drive

Strength Output UVLO

Voltage

Isolation

Rating

(Input to

Output)

Si8241BB-B-IS1 PWM NB SOIC-16 0.5 A

High-Side/Low-Side

2.5 kVrms

Si8241CB-B-IS1 PWM NB SOIC-16 10 V

Si8244BB-C-IS1 PWM NB SOIC-16 4A 8V

Si8244CB-C-IS1 PWM NB SOIC-16 10 V

*Note: All packages are RoHS-compliant.

Moisture sensitivity level is MSL3 for narrow-body SOIC-16 packages with peak reflow temperatures of 260 °C

according to the JEDEC industry standard classifications and peak sold er temperatures. Tape and reel options are

specified by adding an “R” suffix to the ordering part number. “Si” and “SI” are used interchangeably.

Si824x

Preliminary Rev. 0.3 27

7. Package Outline: 16-Pin Narrow Body SOIC

Figure 41 illustrates the package details for the Si824x in a 16-pin narrow-body SOIC (SO-16). Table 13 lists the

values for the dimensions shown in the illustration.

Figure 41. 16-pin Small Outline Integrated Circuit (SOIC) Package

Table 13. Package Diagram Dimensions

Dimension Min Max Dimension Min Max

A — 1.75 L 0.40 1.27

A1 0.10 0.25 L2 0.25 BSC

A2 1.25 — h 0.25 0.50

b0.31 0.51 θ0° 8°

c 0.17 0.25 aaa 0.10

D 9.90 BSC bbb 0.20

E 6.00 BSC ccc 0.10

E1 3.90 BSC ddd 0.25

e 1.27 BSC

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC So lid State Outline MS-012, Variation AC.

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si824x

28 Preliminary Rev. 0.3

8. Land Pattern: 16-Pin Narrow Body SOIC

Figure 42 illustrates the recommended land pattern details for the Si824x in a 16-pin narrow-body SOIC. Table 14

lists the values for the dimensions shown in the illustration.

Figure 42. 16-Pin Narrow Body SOIC PCB Land Pattern

Table 14. 16-Pin Narrow Body SOIC Land Pattern Dimensions

Dimension Feature (mm)

C1 Pad Column Spacing 5.40

E Pad Row Pitch 1.27

X1 Pad Width 0.60

Y1 Pad Length 1.55

Notes:

1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N

for Density Level B (Median Land Protrusion).

2. All feature sizes shown are at Maximum Material Condition (MMC) and a card

fabrication tolerance of 0.05 mm is assumed.

Si824x

Preliminary Rev. 0.3 29

9. To p Marking: 16-Pin Narrow Body SOIC

9.1. Si824x Top Marking (16-Pin Narrow Body SOIC)

9.2. Top Marking Explanation (16-Pin Narrow Body SOIC)

Line 1 Marking:

Base Part Number

Ordering Options

See Ordering Guid e fo r more

information.

Si824 = ISOdriver product series

Y = Peak output current

1=0.5A

4=4.0A

U = UVLO level

B=8V; C=10V

V = Isolation rating

B=2.5kV

Line 2 Marking:

YY = Year

WW = Workweek Assigned by the Asse m bly Hous e. Corr es po n ds to the

year and workweek of the mold date.

TTTTTT = Mfg Code Manufacturing Cod e from Assembly Purchase Order

form.

Si824YUV

YYWWTTTTTT

Si824x

30 Preliminary Rev. 0.3

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2

Deleted Table 3.

Added Tables 2 through 7.

Added Figure 5.

Updated common-mode transient immunity

specification throughout.

Revision 0.2 to Revision 0.3

Updated Figu re s 2 an d 3 on page 7.

Added Figure 4 on page 8.

Updated Table 1 2 on page 26.

Si824x

Preliminary Rev. 0.3 31

NOTES:

Si824x

32 Preliminary Rev. 0.3

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

Patent Notice

Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-

intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed fea-

tures or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warran-

ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any

liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intend-

ed to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized

application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.