Features
•Permanent and reversible software write protection for the first-half of the array
– Software procedure to verify write protect status
•Hardware write protection for the entire array
•Low-voltage and standard-voltage operation
–1.7 (V
CC = 1.7V to 5.5V)
•Internally organized 256 x 8
•Two-wire serial interface
•Schmitt trigger, filtered inputs for noise suppression
•Bidirectional data transfer protocol
•100kHz (1.7V) and 400kHz (2.7V and 5.0V) compatibility
•16-byte page write modes
•Partial page writes are allowed
•Self-timed write cycle (5ms max)
•High-reliability
– Endurance: 1 million write cycles
– Data retention: 100 years
•8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball
dBGA2 packages
•Die sales: wafer form, tape and reel, and bumped wafers
Description
The Atmel® AT34C02C provides 2048 bits of serial electrically-erasable and programmable
read only memory (EEPROM) organized as 256 words of eight bits each. The first-half of
the device incorporates a permanent and a reversible software write protection feature
while hardware write protection for the entire array is available via an external pin. Once the
permanent software write protection is enabled, by sending a special command to the
device, it cannot be reversed. However, the reversible software write protection is enabled
and can be reversed by sending a special command. The hardware write protection is con-
trolled with the WP pin and can be used to protect the entire array, whether or not the
software write protection has been enabled. This allows the user to protect none, first-half,
or all of the array depending on the application. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operations are
essential. The AT34C02C is available in space saving 8-lead JEDEC SOIC, 8-lead Ultra Thin
Mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-
wire serial interface. It is available in 1.7V (1.7V to 5.5V).
Two-wire Serial
Electrically-erasable
and Programmable
Read Only Memory
with Permanent
and Reversible
Software Write
Protect
2K (256 x 8)
Atmel AT34C02C
5185E–SEEPR–3/11
8-lead TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-ball dBGA2
Bottom View
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
8
7
6
5
8-lead Ultra Thin Mini-MAP
(MLP 2x3) Bottom View
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-lead SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
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Atmel AT34C02C
Table 0-1. Pin configurations
1. Absolute maximum ratings*
Figure 1-1. Block diagram
Pin Name Function
A0 - A2 Address inputs
SDA Serial data
SCL Serial clock input
WP Write protect
Operating temperature . . . . . . . . . . . . . . –55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only
and functional operation of the device at these
or any other conditions beyond those indicated
in the operational sections of this specification
is not implied. Exposure to absolute maximum
rating conditions for extended periods may
affect device reliability.
Storage temperature . . . . . . . . . . . . . . . . –65°C to +150°C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . . . . .–1.0V to +7.0V
Maximum operating voltage . . . . . . . . . . . . . . . . . . . . 6.25V
DC output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.0mA
DOUT/ACK
LOGIC
DOUT
DIN
A0
SDA
GND
A1
SCL
VCC
A2
Y DEC
DATA WORD
ADDR/COUNTER
SERIAL
CONTROL
LOGIC
START
STOP
LOGIC
DEVICE
ADDRESS
COMPARATOR
SERIAL MUX
EEPROM
EN
COMP
INCLOAD
LOAD
R/W
H.V. PUMP/TIMING
DATA RECOVERY
X DEC
WP
WRITE PROTECT
CIRCUITRY
SOFTWARE WRITE
PROTECTED AREA
(00H - 7FH)
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Atmel AT34C02C
2. Pin description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-
ORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired
(directly to GND or to Vcc) for compatibility with other Atmel AT24Cxx devices. When the pins are hardwired, as many as
eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device
Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are
left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10k or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is
connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using
10k or less.
Table 2-1. Atmel AT34C02C write protection modes
Table 2-2. Pin capacitance(1)
Note: 1. This parameter is characterized and is not 100% tested
WP pin status
Permanent write protect
register
Reversible write protect
register Part of the array write protected
VCC – – Full array (2K)
GND or floating Not programmed Not programmed Normal read/write
GND or floating Programmed – First-half of array
(1K: 00H - 7FH)
GND or floating – Programmed First-half of array
(1K: 00H - 7FH)
Applicable over recommended operating range from TA = 25C, f = 100 kHz, VCC = +1.7V
Symbol Test condition Max Units Conditions
CI/O Input/output capacitance (SDA) 8 pF VI/O = 0V
CIN Input capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
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Atmel AT34C02C
Table 2-3. DC characteristics
Note: 1. VIL min and VIH max are reference only and are not tested
Table 2-4. AC characteristics
Note: 1. This parameter is characterized and is not 100% tested.
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.7V to +5.5V, (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC Supply voltage 1.7 5.5 V
ICC Supply current VCC = 5.0V READ at 100kHz 0.4 1.0 mA
ICC Supply current VCC = 5.0V WRITE at 100kHz 2.0 3.0 mA
ISB1 Standby current VCC = 1.7V VIN = VCC or VSS 0.6 3.0 μA
ISB2 Standby current VCC = 3.6V VIN = VCC or VSS 1.6 4.0 μA
ISB3 Standby current VCC = 5.5V VIN = VCC or VSS 8.0 18.0 μA
ILI Input leakage current VIN = VCC or VSS 0.10 3.0 μA
ILO Output leakage current VOUT = VCC or VSS 0.05 3.0 μA
VIL Input low level(1) –0.6 VCC x 0.3 V
VIH Input high level(1) VCC x 0.7 VCC + 0.5 V
VOL2 Output low level VCC = 3.0V IOL = 2.1mA 0.4 V
VOL1 Output low level VCC = 1.7V IOL = 0.15mA 0.2 V
Applicable over recommended operating range from TAI = –40C to +85C, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and
100pF (unless otherwise noted)
Symbol Parameter
1.7V 2.7V, 5.0V
UnitsMin Max Min Max
fSCL Clock frequency, SCL 100 400 kHz
tLOW Clock pulse width low 4.7 1.2 μs
tHIGH Clock pulse width high 4.0 0.6 μs
tINoise suppression time(1) 100 50 ns
tAA Clock low to data out valid 0.1 4.5 0.1 0.9 μs
tBUF
Time the bus must be free before a new
transmission can start(1) 4.7 1.2 μs
tHD.STA Start hold time 4.0 0.6 μs
tSU.STA Start set-up time 4.7 0.6 μs
tHD.DAT Data in hold time 0 0 μs
tSU.DAT Data In set-up time 200 100 ns
tRInputs rise time(1) 1.0 0.3 μs
tFInputs fall time(1) 300 300 ns
tSU.STO Stop set-up time 4.7 0.6 μs
tDH Data out hold time 100 50 ns
tWR Write cycle time 5 5 ms
Endurance(1) 25C, page mode 1M 1M Write
cycles
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Atmel AT34C02C
3. Memory organization
Atmel AT34C02C, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each. Random word
addressing requires a 8-bit data word address.
4. Device operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (see Figure 4-3 on page 6). Data changes during SCL high periods will indicate
a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 4-4 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 4-4 on page 6).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The Atmel AT34C02C features a low-power standby mode which is enabled:
•Upon power-up or
•After the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any Two-wire part can be reset by
following these steps:
•Clock up to nine cycles
•Look for SDA high in each cycle while SCL is high and then
•Create a start condition.
Figure 4-1. Bus timing SCL: Serial clock SDA: Serial data I/O
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Atmel AT34C02C
Figure 4-2. Write cycle timing SCL: Serial clock SDA: Serial data I/O
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
Figure 4-3. Data validity
Figure 4-4. Start and stop condition
twr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
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Atmel AT34C02C
Figure 4-5. Output acknowledge
5. Device addressing
The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or
write operation (see Figure 8-1 on page 12).
The device address word consists of a mandatory one-zero sequence for the first four most-significant bits (1010) for
normal read and write operations and 0110 for writing to the write protect register.
The next three bits are the A2, A1, and A0 device address bits for the Atmel AT34C02C EEPROM. These three bits must
compare to their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and
a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a
standby state. The device will not acknowledge if the write protect register has been programmed and the control code is
0110.
6. Write operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit
data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a
microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-
timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not
respond until the write is complete (see Figure 8-2 on page 12).
The device will acknowledge a write command, but not write the data, if the software or hardware write protection has
been enabled. The write cycle time must be observed even when the write protection is enabled.
PAGE WRITE: The 2K device is capable of 16-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data
word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit
up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller
must terminate the page write sequence with a stop condition (see Figure 8-3 on page 12).
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5185E–SEEPR–3/11
Atmel AT34C02C
The data word address lower four bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than
sixteen data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same
page.
The device will acknowledge a write command, but not write the data, if the software or hardware write protection has
been enabled. The write cycle time must be observed even when the write protection is enabled.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the read or write sequence to continue.
7. Write protection
The software write protection, once enabled, write protects only the first-half of the array (00H - 7FH) while the hardware
write protection, via the WP pin, is used to protect the entire array.
PERMANENT SOFTWARE WRITE PROTECTION: The software write protection is enabled by sending a command,
similar to a normal write command, to the device which programs the permanent write protect register. This must be done
with the WP pin low. The write protect register is programmed by sending a write command with the device address of
0110 instead of 1010 with the address and data bit being don’t cares (see Figure 7-1 on page 8). Once the software
write protection has been enabled, the device will no longer acknowledge the 0110 control byte. The software write
protection cannot be reversed even if the device is powered down. The write cycle time must be observed.
REVERSIBLE SOFTWARE WRITE PROTECTION: The reversible software write protection is enabled by sending a
command, similar to a normal write command, to the device which programs the reversible write protect register. This
must be done with the WP pin low. The write protect register is programmed by sending a write command 01100010
with pins A2 and A1 tied to ground or don't connect and pin A0 connected to VHV (see Figure 7-2). The reversible write
protection can be reversed by sending a command 01100110 with pin A2 tied to ground or no connect, pin A1 tied to VCC
and pin A0 tied to VHV (see Figure 7-3).
HARDWARE WRITE PROTECTION: The WP pin can be connected to VCC, GND, or left floating. Connecting the WP pin to
VCC will write protect the entire array, regardless of whether or not the software write protection has been enabled. The
software write protection register cannot be programmed when the WP pin is connected to VCC. If the WP pin is connected
to GND or left floating, the write protection mode is determined by the status of the software write protect register.
Figure 7-1. Setting permanent write protect register (PSWP)
S
T
A
R
T
S
T
O
P
SDA LINE
WORD
ADDRESS DATA
CONTROL
BYTE
A
C
K
0 1 1 0 A2 A1 A0 0
A
C
K
A
C
K
= Don't Care
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Atmel AT34C02C
Figure 7-2. Setting reversible write protect register (RSWP)
Figure 7-3. Clearing reversible write protect register (RSWP)
Table 7-1. Write protection
Table 7-2. VHV
Note: VHV - VCC > 4.8V
Pin Preamble RW
Command A2A1 A0 B7B6B5B4B3B2B1B0
Set PSWP A2 A1 A0 0 1 1 0 A2 A1 A0 0
Set RSWP 00VHV01100010
Clear RSWP 01VHV01100110
Min Max Units
VHV 7 10 V
S
T
A
R
T
S
T
O
P
SDA LINE
WORD
ADDRESS DATA
CONTROL
BYTE
A
C
K
011 0 0
A
C
K
A
C
K
100
= Don't Care
S
T
A
R
T
S
T
O
P
SDA LINE
WORD
ADDRESS DATA
CONTROL
BYTE
A
C
K
011 0 0
A
C
K
A
C
K
101
= Don't Care
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Atmel AT34C02C
Table 7-3. WP connected to GND or floating
WP connected to GND or floating
Command R/W bit
Permanent write
protect register
PSWP
Reversible write
protect register
RSWP
Acknowledgment
from device Action from device
1010 R X X ACK
1010 W Programmed X ACK Can write to second Half (80H - FFH) only
1010 W X Programmed ACK Can write to second Half (80H - FFH) only
1010 W Not programmed Not programmed ACK Can write to full array
Read PSWP R Programmed X No ACK STOP - Indicates permanent write protect register is
programmed
Read PSWP R Not programmed X ACK Read out data don't care. Indicates PSWP register is not
programmed
Set PSWP W Programmed X No ACK STOP - Indicates permanent write protect register is
programmed
Set PSWP W Not programmed X ACK Program permanent write protect register
(irreversible)
Read RSWP R X Programmed No ACK STOP - Indicates reversible write protect register is
programmed
Read RSWP R X Not programmed ACK Read out data don't care. Indicates RSWP register is not
programmed
Set RSWP W X Programmed No ACK STOP - Indicates reversible write protect register is
programmed
Set RSWP W X Not programmed ACK Program reversible write protect register (reversible)
Clear RSWP W Programmed X No ACK STOP - Indicates permanent write protect register is
programmed
Clear RSWP W Not programmed X ACK Clear (unprogram) reversible write protect register
(reversible)
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Atmel AT34C02C
Table 7-4. WP connected to Vcc
8. Read operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are three read operations:
•Current address read
•Random address read
•Sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first
page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. To end the command, the microcontroller does not respond with an input
zero but does generate a following stop condition (see Figure 8-4 on page 13).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another start condition. The microcontroller now initiates a current address read by sending a device address with
the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. To end
the command, the microcontroller does not respond with a zero but does generate a following stop condition (see Figure
8-5 on page 13).
WP connected to Vcc
Command R/W bit
Permanent write
protect register
PSWP
Reversible write
protect register
RSWP
Acknowledgment
from device Action from device
1010 R X X ACK Read array
1010 W X X ACK Device write protect
Read PSWP R Programmed X No ACK STOP - Indicates permanent write protect register is
programmed
Read PSWP R Not programmed X ACK Read out data don't care. Indicates PSWP register is not
programmed
Set PSWP W Programmed X No ACK STOP - Indicates permanent write protect register is
programmed
Set PSWP W Not programmed X ACK Cannot program write protect registers
Read RSWP R X Programmed No ACK STOP - Indicates reversible write protect register is
programmed
Read RSWP R X Not programmed ACK Read out data don't care. Indicates RSWP register is not
programmed
Set RSWP W X Programmed No ACK STOP - Indicates reversible write protect register is
programmed
Set RSWP W X Not programmed ACK Cannot program write protect registers
Clear RSWP W Programmed X No ACK STOP - Indicates permanent write protect register is
programmed
Clear RSWP W Not programmed X ACK Cannot write to write protect registers
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Atmel AT34C02C
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge,
it will continue to increment the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read
operation is terminated when the microcontroller does not respond with a zero but does generate a following stop
condition (see Figure 8-6 on page 13).
PERMANENT WRITE PROTECT REGISTER (PSWP) STATUS: To find out if the register has been programmed,
the same procedure is used as to program the register except that the R/W bit is set to one. If the device sends
an acknowledge, then the permanent write protect register has not been programmed. Otherwise, it has been
programmed and the device is permanently write protected at the first half of the array.
Table 8-1. PSWP status
REVERSIBLE WRITE PROTECT REGISTER(RSWP) STATUS: To find out if the register has been programmed,
the same procedure is used as to program the register except that the R/W bit is set to one. If the sends an
device acknowledge, then the reversible write protect register has not been programmed. Otherwise, it has
been programmed and the device is write protected (reversible) at the first half of the array.
Figure 8-1. Device address
Figure 8-2. Byte write
Figure 8-3. Page write
Pin Preamble RW
Command A2A1 A0 B7B6B5B4B3B2B1B0
Read PSWP A2 A1 A0 0 1 1 0 A2 A1 A0 1
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Atmel AT34C02C
Figure 8-4. Current address read
Figure 8-5. Random read
Figure 8-6. Sequential read
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Atmel AT34C02C
9. Atmel AT34C02C ordering information
Notes: 1. “-B” denotes bulk
2. “-T” denotes tape and reel. SOIC = 4K per reel; TSSOP, Ultra Thin Mini MAP and dBGA2 = 5K per reel.
Atmel ordering code Package Operation range
AT34C02CN-SH-B(1) (NiPdAu lead finish) 8S1
Lead-free/Halogen-free/
Industrial temperature
(–40C to 85C)
AT34C02CN-SH-T(2)(NiPdAu lead finish) 8S1
AT34C02C-TH-B(1) (NiPdAu lead finish) 8A2
AT34C02C-TH-T(2) (NiPdAu lead finish) 8A2
AT34C02CY6-YH-T(2)(NiPdAu lead finish) 8Y6
AT34C02CU3-UU-T(2) 8U3-1
Package type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline package (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline package (TSSOP)
8Y6 8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3mm)
8U3-1 8-ball, die Ball Grid Array package (dBGA2)
Options
–1.7 Low voltage (1.7V to 5.5V)
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Atmel AT34C02C
10. Part markings
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
DRAWING NO. REV. TITLE
Lot Number
AAAAAAA = ATMEL Wafer Lot Number
Voltages
1: 1.7v min
Grade/Lead Finish Material
U: Industrial/Matt Tin
H: Industrial/NiPdAu
ATMEL Truncation
AT: ATMEL
ATM: ATMEL
ATML: ATMEL
Catalog Number: AT34C02C Catalog Truncation: 34C
3 Rows of 8 Characters
AAAAAAAA
34C1
ATMLHYWW
8 lead SOIC
2 Rows/Top & Bottom
8 lead TSSOP
34C 1
HYWW
8 lead UDFN -
3 Rows of 3 Characters
34C
H1@
YXX
2.0x3.0mm
Date Codes
Y = Year M = Month WW = Work Week of Assembly
0: 2010 4: 2014 A: January 02: Week 2
1: 2011 5: 2015 B: February 04: Week 4
2: 2012 6: 2016 “ ” “ ” “ ”
3: 2013 7: 2017 L: December 52: Week 52
Location of Assembly
@ = Location of Assembly
Trace Code
XX = Trace Code (ATMEL Lot Numbers to Correspond to Code)
(e.g. XX: AA, AB...YZ, ZZ)
PIN 1
4/5 Top-7/7 Bottom Characters
2 Rows of 4 Characters
1.5x2.0mm
8-ball VFBGA -
PIN 1
34CU
YMXX
AAAAAAA
LOA Bottom
Top
34C02CSM A
3/17/11
34C02CSM, AT34C02C Standard Marking Information
for Package Offering
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Atmel AT34C02C
11. Packaging Information
8S1 – JEDEC SOIC
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
ØØ 0° – 8°
ØØ
EE
11
NN
TOP VIEWTOP VIEW
CC
E1E1
END VIEW
AA
bb
LL
A1A1
ee
DD
SIDE VIEWSIDE VIEW
8S1 F
5/19/10
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC) SWB
17
5185E–SEEPR–3/11
Atmel AT34C02C
8A2 – TSSOP
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25mm (0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 E
5/19/10
8A2, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
18
5185E–SEEPR–3/11
Atmel AT34C02C
8Y6 – Mini-MAP
19
5185E–SEEPR–3/11
Atmel AT34C02C
8U3-1 – dBGA2
Package Drawing Contact:
packagedrawings@atmel.com
DRAWING NO. REV. TITLE GPC
8U3-1 D
07/14/10
8U3-1, 8-ball, 1.50 x 2.00 mm Body,
0.50 pitch, VFBGA Package (dBGA2) GXU
COMMON DIMENSIONS
(Unit of Measure - mm)
SYMBOL MIN NOM MAX NOTE
A 0.73 0.79 0.85
A1 0.09 0.14 0.19
A2 0.40 0.45 0.50
b 0.20 0.25 0.30 2
D 1.50 BSC
E 2.0 BSC
e 0.50 BSC
e1 0.25 REF
d 1.00 BSC
d1 0.25 REF
1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
Notes:
A2
SIDE VIEW
A
PIN 1 BALL PAD CORNER
TOP VIEW
E
D
A1
5. b
8 SOLDER BALLS
BOTTOM VIEW
(d1)
d
4
32
(e1)
6
e
5
7
PIN 1 BALL PAD CORNER
1
8
20
5185E–SEEPR–3/11
Atmel AT34C02C
12. Revision history
Doc. rev. Date Comments
5185E 03/2011 Replaced part markings to single page part markings
Updated template
5185D 01/2008 Removed ‘preliminary’ status
5185C 08/2007 Updated to new template
Added package marking tables
5185B 03/2007 Implemented revision history
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